; -------------------------------------------------------------------------------- ; @Title: 476IBM On-Chip Peripherals ; @Props: Released ; @Author: BAN ; @Changelog: 2019-05-30 BAN ; @Manufacturer: IBM - IBM Deutschland GmbH ; @Doc: 476fpe-chip.pdf (Rev. 1.0, 2012-05-24) ; 476fpe_core_docs.html ; @Core: PPC476 ; @Chip: PPC476FPE ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: per476ibm.per 10617 2019-05-30 11:57:37Z kwitkowski $ ; Known Problems: ; Module Register Description ; -------------------------------------------------------------------------------- ; L2C L2CDCRAI, L2CDCRDI L2C_DCRBASEADDR[0:23] is not accessible: omitted ; whole module since those registers are crucial ; MPIC Module base address conflict information (either ; constant value as in 476fpe-chip.pdf or ; dependent on GCF0.BAS as in MPIC documentation) ; PLB6PLB4 I_DCR_ABUSIN is not accessible ; PLB4PLB6 I_DCR_ABUSIN is not accessible ; PLB4ARB Assumed docs mentioned in chapter 4.11.4 are ; wrong since they refer to PLB6. Module omitted ; PCIEXG2UTL Could not find indication of current status ; (endpoint/root complex) ; PCIEXG2CFG PM_, MSI_, MSIX_, EC_, VPD_BASEADDR not found ; PCIEXGPL4DDR I_CFG_DCR_BASE signal is not accessible ; SPR Conflict addresses for ICU (tab 5-4 vs tab A-1) ; PPC476FP Missing base address ; PCIEXG2PIPEPCS04 Missing base address ; WRAP1_T12_HS06GPF04L Missing base address ; PCIEXG2UTL Missing base address ; PCIEXG2CFG Missing base address ; PCIe Wrappers Missing base address config 16. 8. tree "MCG (Main Clock Generator)" width 9. group.long (dcr:0x80000700)++0x03 line.long 0x00 "CTL,MCG Control" bitfld.long 0x00 31. " MCSC ,Main clock switch control" "I_SYS_REF_CLK,CLK_PLL_PPC_A" bitfld.long 0x00 30. " DCR ,CLK_PPC to CLK_DCR ratio" "8 to 1,16 to 1" bitfld.long 0x00 28.--29. " L2 ,CLK_PPC to CLK_L2 ratio" "2 to 1,3 to 1,4 to 1,4 to 1" bitfld.long 0x00 26.--27. " PLB4 ,CLK_PLB6 to CLK_PLB4 ratio" "4 to 1,3 to 1,2 to 1,2 to 1" newline bitfld.long 0x00 24.--25. " PLB42 ,CLK_PLB6 to CLK_PLB42 ratio" "4 to 1,3 to 1,2 to 1,2 to 1" bitfld.long 0x00 23. " OPB ,CLK_PLB4 to CLK_OPB ratio" "2 to 1,3 to 1" hexmask.long.byte 0x00 16.--22. 1. " UART ,UART clock divider" bitfld.long 0x00 15. " TIMER ,PowerPC 476FP timer clock select" "I_SYS_REF_CLK,CLK_PLL_PPC_B" newline bitfld.long 0x00 13.--14. " ZCNTL ,ZCNTL clock select" "I_SYS_REF_CLK,CLK_DCR,CLK_OPB,CLK_OPB" bitfld.long 0x00 8.--12. " SCRTCH ,Scratch pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. " MCGKEY ,MCG control key" rgroup.long (dcr:0x80000700+0x01)++0x03 line.long 0x00 "STAT,MCG Status" bitfld.long 0x00 30. " DCR ,CLK_PPC to CLK_DCR ratio" "8 to 1,16 to 1" bitfld.long 0x00 28.--29. " L2 ,CLK_PPC to CLK_L2 ratio" "2 to 1,3 to 1,4 to 1,4 to 1" bitfld.long 0x00 26.--27. " PLB4 ,CLK_PLB6 to CLK_PLB4 ratio" "4 to 1,3 to 1,2 to 1,2 to 1" bitfld.long 0x00 24.--25. " PLB42 ,CLK_PLB6 to CLK_PLB42 ratio" "4 to 1,3 to 1,2 to 1,2 to 1" newline bitfld.long 0x00 23. " OPB ,CLK_PLB4 to CLK_OPB ratio" "2 to 1,3 to 1" bitfld.long 0x00 22. " SYSPLL ,Main system PLL lock" "-,Locked" bitfld.long 0x00 21. " DDRPLL ,DDR PLL lock" "-,Locked" tree "MP PLL" group.long (dcr:0x80000700+0x2)++0x03 line.long 0x00 "MPCTL,Main PLL Control" bitfld.long 0x00 26.--30. " PREDIV[4:0] ,Reference clock divide ratio" "/1,/16,/17,/30,/13,/18,/7,/31,/14,/11,/19,/21,/27,/8,/23,/32,/15,/29,/12,/6,/10,/20,/26,/22,/28,/5,/9,/25,/4,/24,/3,/2" bitfld.long 0x00 24.--25. " RANGEA[6:5] ,PLLOUTA prescaler divide ratio" "/1,/2,,/4" bitfld.long 0x00 19.--23. " RANGEA[4:0] ,PLLOUTA divide ratio" "/1,/2,/28,/27,/22,/21,/30,/29,/24,/23,/12,/11,/16,/15,/32,/31,/26,/25,/20,/19,/10,/9,/14,/13,/18,/17,/8,/7,/6,/5,/4,/3" bitfld.long 0x00 12.--16. " RANGEB[4:0] ,PLLOUTB divide ratio" "/1,/2,/28,/27,/22,/21,/30,/29,/24,/23,/12,/11,/16,/15,/32,/31,/26,/25,/20,/19,/10,/9,/14,/13,/18,/17,/8,/7,/6,/5,/4,/3" newline bitfld.long 0x00 9.--10. " MULTIN[9:8] ,Feedback prescaler divide ratio" "/1,/2,/3,/4" hexmask.long.byte 0x00 1.--8. 1. " MULTIN[7:0] ,Feedback clock driver integer divide ratio" bitfld.long 0x00 0. " RESET ,Main PLL reset" "-,Reset" group.long (dcr:0x80000700+0x4)++0x03 line.long 0x00 "MPTUNE1,Main PLL Tune 1" hexmask.long 0x00 0.--31. 1. " LFTUNE[40:9] ,Loop filter tuning bits [40:9]" group.long (dcr:0x80000700+0x4+0x01)++0x03 line.long 0x00 "MPTUNE2,Main PLL Tune 2" hexmask.long.word 0x00 23.--31. 1. " LFTUNE[8:0] ,Loop filter tuning bits [8:0]" bitfld.long 0x00 21. " LCKSEL[0] ,Lock indicator sensitivity" "Default,As LOCKTUNE" hexmask.long.byte 0x00 0.--7. 1. " FFSLEW ,Feedback divisor slew rate" group.long (dcr:0x80000700+0x4+0x02)++0x03 line.long 0x00 "MPTUNE3,Main PLL Tune 3" bitfld.long 0x00 16.--18. " LKTUNE[2:0] ,Lock indicator tuning bits [2:0]" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--15. " FFTUNE[15:10] ,Loop filter tuning bits [15:10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " FFTUNE[9] ,Fast DCO select" "0,1" bitfld.long 0x00 8. " FFTUNE[8] ,Slow DCO select" "0,1" newline bitfld.long 0x00 7. " FFTUNE[7] ,Loop filter tuning bit [7]" "0,1" bitfld.long 0x00 6. " FFTUNE[6] ,DCO mode enable bypass" "-,Bypass" bitfld.long 0x00 5. " FFTUNE[5] ,Change RANGE(A,B) on the fly" "0,1" bitfld.long 0x00 4. " FFTUNE[4] ,Output clock control frame stop enable" "-,Enabled" newline bitfld.long 0x00 0.--3. " FFTUNE[3:0] ,Loop filter tuning bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "DP PLL" group.long (dcr:0x80000700+0x3)++0x03 line.long 0x00 "DPCTL,DDR PLL Control" bitfld.long 0x00 26.--30. " PREDIV[4:0] ,Reference clock divide ratio" "/1,/16,/17,/30,/13,/18,/7,/31,/14,/11,/19,/21,/27,/8,/23,/32,/15,/29,/12,/6,/10,/20,/26,/22,/28,/5,/9,/25,/4,/24,/3,/2" bitfld.long 0x00 24.--25. " RANGEA[6:5] ,PLLOUTA prescaler divide ratio" "/1,/2,,/4" bitfld.long 0x00 19.--23. " RANGEA[4:0] ,PLLOUTA divide ratio" "/1,/2,/28,/27,/22,/21,/30,/29,/24,/23,/12,/11,/16,/15,/32,/31,/26,/25,/20,/19,/10,/9,/14,/13,/18,/17,/8,/7,/6,/5,/4,/3" bitfld.long 0x00 12.--16. " RANGEB[4:0] ,PLLOUTB divide ratio" "/1,/2,/28,/27,/22,/21,/30,/29,/24,/23,/12,/11,/16,/15,/32,/31,/26,/25,/20,/19,/10,/9,/14,/13,/18,/17,/8,/7,/6,/5,/4,/3" newline bitfld.long 0x00 9.--10. " MULTIN[9:8] ,Feedback prescaler divide ratio" "/1,/2,/3,/4" hexmask.long.byte 0x00 1.--8. 1. " MULTIN[7:0] ,Feedback clock driver integer divide ratio" bitfld.long 0x00 0. " RESET ,Main PLL reset" "-,Reset" group.long (dcr:0x80000700+0x7)++0x03 line.long 0x00 "DPTUNE1,DDR PLL Tune 1" hexmask.long 0x00 0.--31. 1. " LFTUNE[40:9] ,Loop filter tuning bits [40:9]" group.long (dcr:0x80000700+0x7+0x01)++0x03 line.long 0x00 "DPTUNE2,DDR PLL Tune 2" hexmask.long.word 0x00 23.--31. 1. " LFTUNE[8:0] ,Loop filter tuning bits [8:0]" bitfld.long 0x00 21. " LCKSEL[0] ,Lock indicator sensitivity" "Default,As LOCKTUNE" bitfld.long 0x00 20. " STCLKB ,PLLOUTB output clock disable" "No,Yes" textfld " " hexmask.long.byte 0x00 0.--7. 1. " FFSLEW ,Feedback divisor slew rate" group.long (dcr:0x80000700+0x7+0x02)++0x03 line.long 0x00 "DPTUNE3,DDR PLL Tune 3" bitfld.long 0x00 16.--18. " LKTUNE[2:0] ,Lock indicator tuning bits [2:0]" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--15. " FFTUNE[15:10] ,Loop filter tuning bits [15:10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " FFTUNE[9] ,Fast DCO select" "0,1" bitfld.long 0x00 8. " FFTUNE[8] ,Slow DCO select" "0,1" newline bitfld.long 0x00 7. " FFTUNE[7] ,Loop filter tuning bit [7]" "0,1" bitfld.long 0x00 6. " FFTUNE[6] ,DCO mode enable bypass" "-,Bypass" bitfld.long 0x00 5. " FFTUNE[5] ,Change RANGE(A,B) on the fly" "0,1" bitfld.long 0x00 4. " FFTUNE[4] ,Output clock control frame stop enable" "-,Enabled" newline bitfld.long 0x00 0.--3. " FFTUNE[3:0] ,Loop filter tuning bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end newline rgroup.long (dcr:0x80000700+0xA)++0x03 line.long 0x00 "ECID0,Electronic Chip Identification 0 - Bits [255:224]" rgroup.long (dcr:0x80000700+0xB)++0x03 line.long 0x00 "ECID1,Electronic Chip Identification 1 - Bits [223:192]" rgroup.long (dcr:0x80000700+0xC)++0x03 line.long 0x00 "ECID2,Electronic Chip Identification 2 - Bits [191:160]" rgroup.long (dcr:0x80000700+0xD)++0x03 line.long 0x00 "ECID3,Electronic Chip Identification 3 - Bits [159:128]" rgroup.long (dcr:0x80000700+0xE)++0x03 line.long 0x00 "ECID4,Electronic Chip Identification 4 - Bits [127:96]" rgroup.long (dcr:0x80000700+0xF)++0x03 line.long 0x00 "ECID5,Electronic Chip Identification 5 - Bits [95:64]" rgroup.long (dcr:0x80000700+0x10)++0x03 line.long 0x00 "ECID6,Electronic Chip Identification 6 - Bits [63:32]" rgroup.long (dcr:0x80000700+0x11)++0x03 line.long 0x00 "ECID7,Electronic Chip Identification 7 - Bits [31:0]" width 0x0B tree.end tree "RSM (Reset And Sleep Mode)" width 8. if ((per.l(dcr:0x80000800+0x01)&0xC0000000)==0x00) rgroup.long (dcr:0x80000800)++0x03 line.long 0x00 "PPCOPT,PowerPC Option" hexmask.long.word 0x00 22.--31. 1. " ERPN0 ,Extended real page number control 0" bitfld.long 0x00 21. " END0 ,Endian control 0" "0,1" bitfld.long 0x00 17.--20. " USER0 ,User storage attribute control 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 6.--15. 1. " ERPN1 ,Extended real page number control 1" bitfld.long 0x00 5. " END1 ,Endian control 1" "0,1" bitfld.long 0x00 1.--4. " USER1 ,User storage attribute control 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif ((per.l(dcr:0x80000800+0x01)&0xC0000000)==0x80000000) group.long (dcr:0x80000800)++0x03 line.long 0x00 "PPCOPT,PowerPC Option" hexmask.long.word 0x00 22.--31. 1. " ERPN0 ,Extended real page number control 0" bitfld.long 0x00 21. " END0 ,Endian control 0" "0,1" bitfld.long 0x00 17.--20. " USER0 ,User storage attribute control 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 6.--15. 1. " ERPN1 ,Extended real page number control 1" rbitfld.long 0x00 5. " END1 ,Endian control 1" "0,1" rbitfld.long 0x00 1.--4. " USER1 ,User storage attribute control 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif ((per.l(dcr:0x80000800+0x01)&0xC0000000)==0x40000000) group.long (dcr:0x80000800)++0x03 line.long 0x00 "PPCOPT,PowerPC Option" hexmask.long.word 0x00 22.--31. 1. " ERPN0 ,Extended real page number control 0" rbitfld.long 0x00 21. " END0 ,Endian control 0" "0,1" rbitfld.long 0x00 17.--20. " USER0 ,User storage attribute control 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 6.--15. 1. " ERPN1 ,Extended real page number control 1" bitfld.long 0x00 5. " END1 ,Endian control 1" "0,1" bitfld.long 0x00 1.--4. " USER1 ,User storage attribute control 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (dcr:0x80000800)++0x03 line.long 0x00 "PPCOPT,PowerPC Option" hexmask.long.word 0x00 22.--31. 1. " ERPN0 ,Extended real page number control 0" bitfld.long 0x00 21. " END0 ,Endian control 0" "0,1" bitfld.long 0x00 17.--20. " USER0 ,User storage attribute control 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 6.--15. 1. " ERPN1 ,Extended real page number control 1" bitfld.long 0x00 5. " END1 ,Endian control 1" "0,1" bitfld.long 0x00 1.--4. " USER1 ,User storage attribute control 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (dcr:0x80000800+0x01)++0x03 line.long 0x00 "PLRPM,PowerPC And L2 Reset And Power Management" bitfld.long 0x00 31. " PPCRST[0] ,PowerPC 0 reset" "-,Reset" bitfld.long 0x00 30. " PPCRST[1] ,PowerPC 1 reset" "-,Reset" bitfld.long 0x00 29. " PPCDIS[0] ,PowerPC 0 clock disable" "No,Yes" bitfld.long 0x00 28. " PPCDIS[1] ,PowerPC 1 clock disable" "No,Yes" newline bitfld.long 0x00 27. " L2RST[0] ,L2 0 reset" "-,Reset" bitfld.long 0x00 26. " L2RST[1] ,L2 1 reset" "-,Reset" bitfld.long 0x00 25. " L2RSTN ,Allow L2 cache reset" "-,Allowed" bitfld.long 0x00 24. " PPCL2[0] ,PowerPC 0 and L2 0 reset" "-,Reset" newline bitfld.long 0x00 23. " PPCL2[1] ,PowerPC 1 and L2 1 reset" "-,Reset" bitfld.long 0x00 22. " PME ,Power management feature enable" "-,Enabled" bitfld.long 0x00 21. " PPCWU[0] ,PowerPC 0 wake up" "-,Wake up" bitfld.long 0x00 20. " PPCWU[1] ,PowerPC 1 wake up" "-,Wake up" newline bitfld.long 0x00 19. " PPCSLP[0] ,PowerPC 0 sleep status" "-,Sleep" bitfld.long 0x00 18. " PPCSLP[1] ,PowerPC 1 sleep status" "-,Sleep" bitfld.long 0x00 17. " ITCDHE[0] ,PowerPC 0 instruction trace complete debug halt enable" "-,Enabled" bitfld.long 0x00 16. " ITCDHE[1] ,PowerPC 1 instruction trace complete debug halt enable" "-,Enabled" newline bitfld.long 0x00 15. " LTCDHE[0] ,PowerPC 0 login trace complete debug halt enable" "-,Enabled" bitfld.long 0x00 14. " LTCDHE[1] ,PowerPC 1 login trace complete debug halt enable" "-,Enabled" bitfld.long 0x00 13. " L2CNTL[0] ,PowerPC 0 CPM_L2CCLKEN" "0,1" bitfld.long 0x00 12. " L2CNTL[1] ,PowerPC 0 CPM_L2CPLBCLKEN" "0,1" newline bitfld.long 0x00 11. " L2CNTL[2] ,PowerPC 0 CPM_L2CDCRCLKEN" "0,1" bitfld.long 0x00 10. " L2CNTL[3] ,PowerPC 1 CPM_L2CCLKEN" "0,1" bitfld.long 0x00 9. " L2CNTL[4] ,PowerPC 1 CPM_L2CPLBCLKEN" "0,1" bitfld.long 0x00 8. " L2CNTL[5] ,PowerPC 1 CPM_L2CDCRCLKEN" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. " MRGKEY ,MRG control key" group.long (dcr:0x80000800+0x02)++0x03 line.long 0x00 "RH,Reset History" bitfld.long 0x00 31. " CORCPU[0] ,PowerPC 0 CPU reset because of processor request" "No,Yes" bitfld.long 0x00 30. " CORCPU[1] ,PowerPC 1 CPU reset because of processor request" "No,Yes" bitfld.long 0x00 29. " CORDCR[0] ,PowerPC 0 CPU reset because of DCR write" "No,Yes" bitfld.long 0x00 28. " CORDCR[1] ,PowerPC 1 CPU reset because of DCR write" "No,Yes" newline eventfld.long 0x00 27. " CHPCPU[0] ,PowerPC 0 CPU reset because of CPU request" "No,Yes" eventfld.long 0x00 26. " CHPCPU[1] ,PowerPC 1 CPU reset because of CPU request" "No,Yes" eventfld.long 0x00 25. " SYSPIN ,System reset because of I_HRST pull down" "No,Yes" eventfld.long 0x00 24. " SYSCPU[0] ,PowerPC 0 system reset because of CPU request" "No,Yes" newline eventfld.long 0x00 23. " SYSCPU[1] ,PowerPC 1 system reset because of CPU request" "No,Yes" group.long (dcr:0x80000800+0x03)++0x03 line.long 0x00 "SR0,Soft Reset 0" bitfld.long 0x00 31. " PP0IPR ,PLB6 bus reset" "-,Reset" bitfld.long 0x00 30. " MM0SR ,MPIC core reset" "-,Reset" bitfld.long 0x00 29. " II0IR ,ITRACE core reset" "-,Reset" bitfld.long 0x00 28. " LL0IR ,LTRACE0 core reset" "-,Reset" newline bitfld.long 0x00 27. " LL1IR ,LTRACE1 core reset" "-,Reset" bitfld.long 0x00 26. " DDIDR ,DMA core DCR clock domain reset" "-,Reset" bitfld.long 0x00 25. " DDIPR ,DMA core PLB6 clock domain reset" "-,Reset" bitfld.long 0x00 24. " DWDIR ,DDR controller reset" "-,Reset" newline bitfld.long 0x00 23. " DDRAI ,DDR3PHYCFG/DDR3PHYDFICNTL/ZCNTL reset" "-,Reset" bitfld.long 0x00 22. " PB4IP ,PLB6-to-PLB4 bridge core PLB6 clock domain reset" "-,Reset" bitfld.long 0x00 21. " PB4ISP ,PLB6-to-PLB4 bridge core PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 20. " PB4ID ,PLB6-to-PLB4 bridge core DCR clock domain reset" "-,Reset" newline bitfld.long 0x00 19. " PB42IP ,PLB6-to-PLB4 bridge core 2 DCR clock domain reset" "-,Reset" bitfld.long 0x00 18. " PB42IS ,PLB6-to-PLB4 bridge core 2 PLB6 clock domain reset" "-,Reset" bitfld.long 0x00 17. " PBI42D ,PLB6-to-PLB4 bridge core 2 PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 16. " PB6IP ,PLB4-to-PLB6 bridge core PLB6 clock domain reset" "-,Reset" newline bitfld.long 0x00 15. " PB6ISP ,PLB4-to-PLB6 bridge core PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 14. " PB6ID ,PLB4-to-PLB6 bridge core DCR clock domain reset" "-,Reset" bitfld.long 0x00 13. " PB62IP ,PLB4-to-PLB6 bridge core 2 PLB6 clock domain reset" "-,Reset" bitfld.long 0x00 12. " PB62IS ,PLB4-to-PLB6 bridge core 2 PLB4 clock domain reset" "-,Reset" newline bitfld.long 0x00 11. " PB62ID ,PLB4-to-PLB6 bridge core 2 DCR clock domain reset" "-,Reset" bitfld.long 0x00 10. " PPSPR ,PLB4 arbiter core PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 9. " PPSPR ,PLB4 arbiter core 2 PLB 4 clock domain reset" "-,Reset" bitfld.long 0x00 8. " PPIR ,PLB4-to_OPB bridge core reset" "-,Reset" newline bitfld.long 0x00 7. " IIRST ,IIC400 core reset" "-,Reset" bitfld.long 0x00 6. " UUM ,UART16750 core reset" "-,Reset" bitfld.long 0x00 5. " GGGC ,GPIO core reset" "-,Reset" bitfld.long 0x00 4. " EEIER ,EBCO core reset" "-,Reset" newline bitfld.long 0x00 3. " OERNO ,O_EBC_RESET_N output" "High,Low" group.long (dcr:0x80000800+0x04)++0x03 line.long 0x00 "SR1,Soft reset 1" bitfld.long 0x00 31. " RRRRB ,RC_BUS core RCBUS clock domain reset" "-,Reset" bitfld.long 0x00 30. " PPH1 ,PCIEXG2PIPEPCS04 core RCBUS clock domain reset" "-,Reset" bitfld.long 0x00 29. " PPP0 ,HS06GPF04L PHY RCBUS clock domain reset" "-,Reset" bitfld.long 0x00 28. " PPP1 ,PCIEXG2PIPEPCS04 core 2 RCBUS clock domain reset" "-,Reset" newline bitfld.long 0x00 27. " PPP2 ,HS06GPF04L PHY 2 RCBUS clock domain reset" "-,Reset" bitfld.long 0x00 26. " PPP3 ,PCIEXG2PIPEPCS04 core lane 3 support reset" "-,Reset" bitfld.long 0x00 25. " WTHPH ,HS06GPF04L core support block reset" "-,Reset" bitfld.long 0x00 24. " PP2H2 ,PCIEXG2PIPEPCS04 core 2 entire core reset" "-,Reset" newline bitfld.long 0x00 23. " PP2P0 ,PCIEXG2PIPEPCS04 core 2 lane 0 support reset" "-,Reset" bitfld.long 0x00 22. " PP2P1 ,PCIEXG2PIPEPCS04 core 2 lane 1 support reset" "-,Reset" bitfld.long 0x00 21. " PP2P2 ,PCIEXG2PIPEPCS04 core 2 lane 2 support reset" "-,Reset" bitfld.long 0x00 20. " PP2P3 ,PCIEXG2PIPEPCS04 core 2 lane 3 support reset" "-,Reset" newline bitfld.long 0x00 19. " WTHP2H ,HS06GPF04L core 2 support block reset" "-,Reset" bitfld.long 0x00 18. " P4M0IP ,PCIEXG2WRAPP2P MAC0 PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 17. " P4M0SR ,PCIEXG2WRAPP2P MAC0 PCLK clock domain reset" "-,Reset" bitfld.long 0x00 16. " P4M0SH ,PCIEXG2WRAPP2P MAC0 PCLK clock domain reset" "-,Reset" newline bitfld.long 0x00 15. " P4M1IP ,PCIEXG2WRAPP2P MAC1 PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 14. " P4M1SR ,PCIEXG2WRAPP2P MAC1 PCLK clock domain reset" "-,Reset" bitfld.long 0x00 13. " P4M1SH ,PCIEXG2WRAPP2P MAC1 PCLK clock domain reset" "-,Reset" bitfld.long 0x00 12. " P2M0IP ,PCIEXG2WRAPP2P 2 MAC0 PLB4 clock domain reset" "-,Reset" newline bitfld.long 0x00 11. " P2M0SR ,PCIEXG2WRAPP2P 2 MAC0 MCIF clock domain reset" "-,Reset" bitfld.long 0x00 10. " P2M0SH ,PCIEXG2WRAPP2P 2 MAC0 PCLK clock domain reset" "-,Reset" bitfld.long 0x00 9. " P2M1IP ,PCIEXG2WRAPP2P 2 MAC1 PLB4 clock domain reset" "-,Reset" bitfld.long 0x00 8. " P2M1SR ,PCIEXG2WRAPP2P 2 MAC1 MCIF clock domain reset" "-,Reset" newline bitfld.long 0x00 7. " P2M1SH ,PCIEXG2WRAPP2P 2 MAC1 PCLK clock domain reset" "-,Reset" bitfld.long 0x00 3.--4. " LTR0DBMUX ,LTRACE0 debug bus multiplexer control" "0,1,2,3" bitfld.long 0x00 1.--2. " LTR1DBMUX ,LTRACE1 debug bus multiplexer control" "0,1,2,3" bitfld.long 0x00 0. " P6NSZCD ,PPC/L2C on PLB6 segments cachebility disable" "No,Yes" width 0x0B tree.end tree "CCTL (PowerPC 476FPE Control Registers)" width 8. group.long (dcr:0x80000800+0x05)++0x03 line.long 0x00 "PMACTL,PMA Control" bitfld.long 0x00 31. " APLLN ,PCIe 0 PLL A enable" "-,Enabled" bitfld.long 0x00 30. " APCLK ,PCIe 0 PCLK divider" "Normal,/8" newline bitfld.long 0x00 27.--29. " ADV ,PCIe 0 PLL A reference clock multiplier" ",,x24,x32,x40,x50,x80,x100" bitfld.long 0x00 26. " APLRF ,PCIe PLL 0 A reference clock source" ",External" bitfld.long 0x00 23.--25. " BDIV ,PCIe 0 PLL B reference clock multiplier" ",,x24,x32,x40,x50,x80,x100" bitfld.long 0x00 22. " BPLRF ,PCIe 0 PLL B reference clock source" ",External" newline bitfld.long 0x00 21. " SRFN ,PCIe 0 bandgap circuit reference voltage output enable" "-,Enabled" bitfld.long 0x00 20. " SRFDS ,PCIe 0 internal PLL A/B reference clock output disable" "No,Yes" bitfld.long 0x00 19. " SRFRG ,PCIe 0 reference clock input range" "60-120 MHz,>120 MHz" bitfld.long 0x00 18. " SRFTR ,PCIe 0 external reference clock input termination" "-,Terminated" newline bitfld.long 0x00 15. " 2APLLN ,PCIe 1 PLL A enable" "-,Enabled" bitfld.long 0x00 14. " 2APCLK ,PCIe 1 PCLK divider" "Normal,/8" newline bitfld.long 0x00 11.--13. " 2ADV ,PCIe 1 PLL A reference clock multiplier" ",,x24,x32,x40,x50,x80,x100" bitfld.long 0x00 10. " 2APLRF ,PCIe 1 PLL A reference clock source" ",External" bitfld.long 0x00 7.--9. " 2BDIV ,PCIe 1 PLL B reference clock multiplier" ",,x24,x32,x40,x50,x80,x100" bitfld.long 0x00 6. " 2BPLRF ,PCIe 1 PLL B reference clock source" ",External" newline bitfld.long 0x00 5. " 2SRFN ,PCIe 1 bandgap circuit reference voltage output enable" "-,Enabled" bitfld.long 0x00 4. " 2SRFDS ,PCIe 1 internal PLL A/B reference clock input disable" "No,Yes" bitfld.long 0x00 3. " 2SRFRG ,PCIe 1 reference clock input range" "60-120 MHz,>120 MHz" bitfld.long 0x00 2. " 2SRFTR ,PCIe 1 external reference clock input termination" "-,Terminated" group.long (dcr:0x80000800+0x06)++0x03 line.long 0x00 "PCSCTL,PCS Control" bitfld.long 0x00 30.--31. " PTWTH ,PCIe 0 bifurcation support" "No bifurcation,2:1,?..." bitfld.long 0x00 29. " VRWTH ,PCIe 0 data width during rate change" ",Variable" bitfld.long 0x00 28. " L2PLN ,PCIe 0 PLL operation" "Off/On,Always On" bitfld.long 0x00 27. " 2BYTE ,PCIe 0 internal data path" "8 bit,16 bit" newline bitfld.long 0x00 26. " RSTMD ,PCIe 0 logical OR of incoming RESET_N signals enable" "-,Enabled" bitfld.long 0x00 25. " 0CTDS ,PCIe 0 PIPE 0 PCS elastic buffer clock tolerance compensation disable" "No,Yes" bitfld.long 0x00 24. " 2CTDS ,PCIe 0 PIPE 2 PCS elastic buffer clock tolerance compensation disable" "No,Yes" newline bitfld.long 0x00 23. " 0ATPL ,PCIe 0 PIPE 0 PCS lane A output invert" "-,Inverted" bitfld.long 0x00 22. " 0BTPL ,PCIe 0 PIPE 0 PCS lane B output invert" "-,Inverted" bitfld.long 0x00 21. " 0CTPL ,PCIe 0 PIPE 0 PCS lane C output invert" "-,Inverted" bitfld.long 0x00 20. " 0DTPL ,PCIe 0 PIPE 0 PCS lane D output invert" "-,Inverted" newline bitfld.long 0x00 19. " 2ATPL ,PCIe 0 PIPE 2 PCS lane A output invert" "-,Inverted" bitfld.long 0x00 18. " 2BTPL ,PCIe 0 PIPE 2 PCS lane B output invert" "-,Inverted" bitfld.long 0x00 17. " 0TSWN ,PCIe 0 PIPE 0 PCS transmitter swing mode" "Full swing,Half swing" bitfld.long 0x00 16. " 2TSWN ,PCIe 0 PIPE 2 PCS transmitter swing mode" "Full swing,Half swing" newline bitfld.long 0x00 14.--15. " 2PTWTH ,PCIe 1 bifurcation support" "No bifurcation,2:1,?..." bitfld.long 0x00 13. " 2VRWTH ,PCIe 1 data width during rate change" ",Variable" bitfld.long 0x00 12. " 2L2PLN ,PCIe 1 PLL operation" "Off/On,Always On" bitfld.long 0x00 11. " 22BYTE ,PCIe 1 internal data path" "8 bit,16 bit" newline bitfld.long 0x00 10. " 2RSTMD ,PCIe 1 logical OR of incoming RESET_N signals enable" "-,Enabled" bitfld.long 0x00 9. " 20CTDS ,PCIe 1 PIPE 0 PCS elastic buffer clock tolerance compensation disable" "No,Yes" bitfld.long 0x00 8. " 22CTDS ,PCIe 1 PIPE 2 PCS elastic buffer clock tolerance compensation disable" "No,Yes" newline bitfld.long 0x00 7. " 20ATPL ,PCIe 1 PIPE 0 PCS lane A output invert" "-,Inverted" bitfld.long 0x00 6. " 20BTPL ,PCIe 1 PIPE 0 PCS lane B output invert" "-,Inverted" bitfld.long 0x00 5. " 20CTPL ,PCIe 1 PIPE 0 PCS lane C output invert" "-,Inverted" bitfld.long 0x00 4. " 20DTPL ,PCIe 1 PIPE 0 PCS lane D output invert" "-,Inverted" newline bitfld.long 0x00 3. " 22ATPL ,PCIe 1 PIPE 2 PCS lane A output invert" "-,Inverted" bitfld.long 0x00 2. " 22BTPL ,PCIe 1 PIPE 2 PCS lane B output invert" "-,Inverted" bitfld.long 0x00 1. " 20TSWN ,PCIe 1 PIPE 0 PCS transmitter swing mode" "Full swing,Half swing" bitfld.long 0x00 0. " 22TSWN ,PCIe 1 PIPE 2 PCS transmitter swing mode" "Full swing,Half swing" group.long (dcr:0x80000800+0x07)++0x03 line.long 0x00 "PCO0,PCS Control And Observation PCIe 0" bitfld.long 0x00 29.--31. " SSEL ,Pseudo random bit stream source" "x^7+x^6+1,x^23+x^18+1,x^31+x^28+1,Static register,2^12 bytes CEI CID,2^16 bytes CEI CID,2^24 bytes CEI CID,2^28 bytes CEI CID" bitfld.long 0x00 28. " ASENRX ,Lane A pseudo random bit stream checker enable" "-,Enabled" rbitfld.long 0x00 27. " ASSYNC ,Lane A pseudo random bit stream lock status" "-,Locked" bitfld.long 0x00 26. " ASRST ,Lane A pseudo random bit stream result reset" "-,Reset" newline rbitfld.long 0x00 25. " ASERRH ,Lane A pseudo random bit stream error status" "-,Error" bitfld.long 0x00 24. " ASENTX ,Lane A pseudo random bit stream generator enable" "-,Enabled" bitfld.long 0x00 23. " ALPOPN ,Lane A pseudo random bit stream serial loopback enable" "-,Enabled" bitfld.long 0x00 22. " ALPBK ,Lane A parallel loopback enable" "-,Enabled" newline bitfld.long 0x00 21. " BSENRX ,Lane B pseudo random bit stream checker enable" "-,Enabled" rbitfld.long 0x00 20. " BSSYNC ,Lane B pseudo random bit stream lock status" "-,Locked" bitfld.long 0x00 19. " BSRST ,Lane B pseudo random bit stream result reset" "-,Reset" rbitfld.long 0x00 18. " BSERRH ,Lane B pseudo random bit stream error status" "-,Error" newline bitfld.long 0x00 17. " BSENTX ,Lane B pseudo random bit stream generator enable" "-,Enabled" bitfld.long 0x00 16. " BLPOPN ,Lane B pseudo random bit stream serial loopback enable" "-,Enabled" bitfld.long 0x00 15. " BLPBK ,Lane B parallel loopback enable" "-,Enabled" bitfld.long 0x00 14. " CSENRX ,Lane C pseudo random bit stream checker enable" "-,Enabled" newline rbitfld.long 0x00 13. " CSSYNC ,Lane C pseudo random bit stream lock status" "-,Locked" bitfld.long 0x00 12. " CSRST ,Lane C pseudo random bit stream result reset" "-,Reset" rbitfld.long 0x00 11. " CSERRH ,Lane C pseudo random bit stream error status" "-,Error" bitfld.long 0x00 10. " CSENTX ,Lane C pseudo random bit stream generator enable" "-,Enabled" newline bitfld.long 0x00 9. " CLPOPN ,Lane C pseudo random bit stream serial loopback enable" "-,Enabled" bitfld.long 0x00 8. " CLPBK ,Lane C parallel loopback enable" "-,Enabled" bitfld.long 0x00 7. " DSENRX ,Lane D pseudo random bit stream checker enable" "-,Enabled" rbitfld.long 0x00 6. " DSSYNC ,Lane D pseudo random bit stream lock status" "-,Locked" newline bitfld.long 0x00 5. " DSRST ,Lane D pseudo random bit stream result reset" "-,Reset" rbitfld.long 0x00 4. " DSERRH ,Lane D pseudo random bit stream error status" "-,Error" bitfld.long 0x00 3. " DSENTX ,Lane D pseudo random bit stream generator enable" "-,Enabled" bitfld.long 0x00 2. " DLPOPN ,Lane D pseudo random bit stream serial loopback enable" "-,Enabled" newline bitfld.long 0x00 1. " DLPBK ,Lane D parallel loopback enable" "-,Enabled" bitfld.long 0x00 0. " SCRTCH ,Scratch pad" "0,1" group.long (dcr:0x80000800+0x08)++0x03 line.long 0x00 "PCO1,PCS Control And Observation PCIe 1" bitfld.long 0x00 29.--31. " 2SSEL ,Pseudo random bit stream source" "x^7+x^6+1,x^23+x^18+1,x^31+x^28+1,Static register,2^12 bytes CEI CID,2^16 bytes CEI CID,2^24 bytes CEI CID,2^28 bytes CEI CID" bitfld.long 0x00 28. " 2ASENRX ,Lane A pseudo random bit stream checker enable" "-,Enabled" rbitfld.long 0x00 27. " 2ASSYNC ,Lane A pseudo random bit stream lock status" "-,Locked" bitfld.long 0x00 26. " 2ASRST ,Lane A pseudo random bit stream result reset" "-,Reset" newline rbitfld.long 0x00 25. " 2ASERRH ,Lane A pseudo random bit stream error status" "-,Error" bitfld.long 0x00 24. " 2ASENTX ,Lane A pseudo random bit stream generator enable" "-,Enabled" bitfld.long 0x00 23. " 2ALPOPN ,Lane A pseudo random bit stream serial loopback enable" "-,Enabled" bitfld.long 0x00 22. " 2ALPBK ,Lane A parallel loopback enable" "-,Enabled" newline bitfld.long 0x00 21. " 2BSENRX ,Lane B pseudo random bit stream checker enable" "-,Enabled" rbitfld.long 0x00 20. " 2BSSYNC ,Lane B pseudo random bit stream lock status" "-,Locked" bitfld.long 0x00 19. " 2BSRST ,Lane B pseudo random bit stream result reset" "-,Reset" rbitfld.long 0x00 18. " 2BSERRH ,Lane B pseudo random bit stream error status" "-,Error" newline bitfld.long 0x00 17. " 2BSENTX ,Lane B pseudo random bit stream generator enable" "-,Enabled" bitfld.long 0x00 16. " 2BLPOPN ,Lane B pseudo random bit stream serial loopback enable" "-,Enabled" bitfld.long 0x00 15. " 2BLPBK ,Lane B parallel loopback enable" "-,Enabled" bitfld.long 0x00 14. " 2CSENRX ,Lane C pseudo random bit stream checker enable" "-,Enabled" newline rbitfld.long 0x00 13. " 2CSSYNC ,Lane C pseudo random bit stream lock status" "-,Locked" bitfld.long 0x00 12. " 2CSRST ,Lane C pseudo random bit stream result reset" "-,Reset" rbitfld.long 0x00 11. " 2CSERRH ,Lane C pseudo random bit stream error status" "-,Error" bitfld.long 0x00 10. " 2CSENTX ,Lane C pseudo random bit stream generator enable" "-,Enabled" newline bitfld.long 0x00 9. " 2CLPOPN ,Lane C pseudo random bit stream serial loopback enable" "-,Enabled" bitfld.long 0x00 8. " 2CLPBK ,Lane C parallel loopback enable" "-,Enabled" bitfld.long 0x00 7. " 2DSENRX ,Lane D pseudo random bit stream checker enable" "-,Enabled" rbitfld.long 0x00 6. " 2DSSYNC ,Lane D pseudo random bit stream lock status" "-,Locked" newline bitfld.long 0x00 5. " 2DSRST ,Lane D pseudo random bit stream result reset" "-,Reset" rbitfld.long 0x00 4. " 2DSERRH ,Lane D pseudo random bit stream error status" "-,Error" bitfld.long 0x00 3. " 2DSENTX ,Lane D pseudo random bit stream generator enable" "-,Enabled" bitfld.long 0x00 2. " 2DLPOPN ,Lane D pseudo random bit stream serial loopback enable" "-,Enabled" newline bitfld.long 0x00 1. " 2DLPBK ,Lane D parallel loopback enable" "-,Enabled" newline group.long (dcr:0x80000800+0x09)++0x03 line.long 0x00 "MCO0,Miscellaneous Control And Observation 0" bitfld.long 0x00 31. " EBCCLKEN ,O_EBC_CLK output tristate enable" "-,Enabled" bitfld.long 0x00 30. " SPEED ,I2C speed" "High speed,Standard/Fast" bitfld.long 0x00 29. " DRIVER ,I2C driver type" "Standard/Push-pull,Open drain" bitfld.long 0x00 27.--28. " RISCTR ,RISCTrace external output control" "Normal,PowerPC[0],PowerPC[1],?..." newline bitfld.long 0x00 26. " 6DLYRD ,PLB6 to PLB4 bridge 1 slave interface transfer mode" "Address ACK,Delayed read" bitfld.long 0x00 25. " 62DLYRD ,PLB6 to PLB4 bridge 2 slave interface transfer mode" "Address ACK,Delayed read" bitfld.long 0x00 24. " ADRBPR ,DDR3 interface address signal control" "Default,?..." newline bitfld.long 0x00 23. " CS[0] ,DDR3 interface CS 0 control" "Default,?..." bitfld.long 0x00 22. " CS[1] ,DDR3 interface CS 1 control" "Default,?..." bitfld.long 0x00 21. " CS[2] ,DDR3 interface CS 2 control" "Default,?..." bitfld.long 0x00 20. " CS[3] ,DDR3 interface CS 3 control" "Default,?..." newline bitfld.long 0x00 19. " ODT[0] ,DDR3 interface ODT 0 control" "Default,?..." bitfld.long 0x00 18. " ODT[1] ,DDR3 interface ODT 1 control" "Default,?..." bitfld.long 0x00 17. " ODT[2] ,DDR3 interface ODT 2 control" "Default,?..." bitfld.long 0x00 16. " ODT[3] ,DDR3 interface ODT 3 control" "Default,?..." newline bitfld.long 0x00 15. " CLKDSN[0] ,DDR3 interface clock 0 negative edge control" "Default,?..." bitfld.long 0x00 14. " CLKDSN[1] ,DDR3 interface clock 1 negative edge control" "Default,?..." bitfld.long 0x00 13. " CLKDSN[2] ,DDR3 interface clock 2 negative edge control" "Default,?..." bitfld.long 0x00 12. " CLKDSN[3] ,DDR3 interface clock 3 negative edge control" "Default,?..." newline bitfld.long 0x00 11. " CLKDS[0] ,DDR3 interface clock 0 positive edge control" "Default,?..." bitfld.long 0x00 10. " CLKDS[1] ,DDR3 interface clock 1 positive edge control" "Default,?..." bitfld.long 0x00 9. " CLKDS[2] ,DDR3 interface clock 2 positive edge control" "Default,?..." bitfld.long 0x00 8. " CLKDS[3] ,DDR3 interface clock 3 positive edge control" "Default,?..." newline bitfld.long 0x00 7. " CKE[0] ,DDR3 interface CKE 0 control" "Default,?..." bitfld.long 0x00 6. " CKE[1] ,DDR3 interface CKE 1 control" "Default,?..." bitfld.long 0x00 5. " CKE[2] ,DDR3 interface CKE 2 control" "Default,?..." bitfld.long 0x00 4. " CKE[3] ,DDR3 interface CKE 3 control" "Default,?..." newline bitfld.long 0x00 3. " RESET ,DDR3 interface reset control" "Default,?..." bitfld.long 0x00 2. " WE ,DDR3 interface WE signal control" "Default,?..." bitfld.long 0x00 1. " CAS ,DDR3 interface CAS signal control" "Default,?..." bitfld.long 0x00 0. " RAS ,DDR3 interface RAS signal control" "Default,?..." group.long (dcr:0x80000800+0x0A)++0x03 line.long 0x00 "MCO1,Miscellaneous Control And Observation 1" bitfld.long 0x00 31. " CS[0] ,DDR3 interface CS 0 control" ",Default" bitfld.long 0x00 30. " CS[1] ,DDR3 interface CS 1 control" ",Default" bitfld.long 0x00 29. " CS[2] ,DDR3 interface CS 2 control" ",Default" bitfld.long 0x00 28. " CS[3] ,DDR3 interface CS 3 control" ",Default" newline bitfld.long 0x00 27. " RESET ,DDR3 interface RESET control" ",Default" bitfld.long 0x00 26. " WE ,DDR3 interface WE control" ",Default" bitfld.long 0x00 25. " CAS ,DDR3 interface CAS control" ",Default" bitfld.long 0x00 24. " RAS ,DDR interface RAS control" ",Default" newline bitfld.long 0x00 23. " OTHERS ,DDR3 interface active high control" ",Default" hexmask.long.word 0x00 11.--22. 1. " CLKMDI ,CLK mode" rbitfld.long 0x00 1. " WRLVL ,WRLVL value" "0,1" rbitfld.long 0x00 0. " RDLVL ,RDLVL value" "0,1" group.long (dcr:0x80000800+0x0B)++0x03 line.long 0x00 "DPIOC,DDR3 PHY I/O Control" bitfld.long 0x00 31. " AZEN ,ZCNTL sleep/permit operations for address signals" "Sleep,Permit" bitfld.long 0x00 30. " DZEN ,ZCNTL sleep/permit operations for data signals" "Sleep,Permit" bitfld.long 0x00 29. " TZEN ,ZCNTL sleep/permit operations for termination signals" "Sleep,Permit" bitfld.long 0x00 28. " AC1N ,I/O buffers impedance control" "0,1" newline bitfld.long 0x00 27. " AC2N ,I/O buffers impedance control" "0,1" bitfld.long 0x00 26. " DC1N ,I/O buffers impedance control" "0,1" bitfld.long 0x00 25. " DC2N ,I/O buffers impedance control" "0,1" bitfld.long 0x00 24. " AC12N ,I/O buffers voltage control" "0,1" newline bitfld.long 0x00 23. " ACSLWN ,I/O buffers slew rate control" "0,1" bitfld.long 0x00 22. " DDSLW ,DQ I/O buffers slew rate control" "0,1" bitfld.long 0x00 21. " DDSSLW ,DQS1 I/O buffers slew rate control" "0,1" bitfld.long 0x00 20. " DM1512 ,I/O buffers voltage control" "0,1" newline bitfld.long 0x00 19. " DDVRF[0] ,DQ I/O buffers VREF trimmer control" "0,1" bitfld.long 0x00 18. " DDVRF[1] ,DQ I/O buffers VREF trimmer control" "0,1" bitfld.long 0x00 17. " DDVRF[2] ,DQ I/O buffers VREF trimmer control" "0,1" bitfld.long 0x00 16. " DDVRF[3] ,DQ I/O buffers VREF trimmer control" "0,1" newline bitfld.long 0x00 15. " VRFOE ,VREF OE (output enable)" "-,Enabled" bitfld.long 0x00 14. " VRFD1 ,VREF D1" "0,1" bitfld.long 0x00 13. " VRFD2 ,VREF D2" "0,1" bitfld.long 0x00 12. " VRFD3 ,VREF D3" "0,1" newline bitfld.long 0x00 11. " VRFD4 ,VREF D4" "0,1" bitfld.long 0x00 10. " VRFDSN ,VREF DSIGN" "0,1" bitfld.long 0x00 9. " MCVREF ,VREF MCVREF" "0,1" group.long (dcr:0x80000800+0x0C)++0x03 line.long 0x00 "DPC,DDR3 PHY Control" bitfld.long 0x00 27. " ADRDLY[0] ,Use DELAYLONG for CLKGATE 0 delay" "No,Yes" bitfld.long 0x00 26. " ADRDLY[1] ,Use DELAYLONG for CLKGATE 1 delay" "No,Yes" bitfld.long 0x00 25. " ADRDLY[2] ,Use DELAYLONG for CLKGATE 2 delay" "No,Yes" bitfld.long 0x00 24. " ADRENE ,DDR3 interface rank 3 CS/clock drivers On" "Off,On" newline bitfld.long 0x00 23. " ADREND ,DDR3 interface rank 2 CS/clock drivers On" "Off,On" bitfld.long 0x00 22. " ADRENC ,DDR3 interface rank 1 CS/clock drivers On" "Off,On" bitfld.long 0x00 21. " ADRENB ,DDR3 interface rank 0 CS/clock drivers On" "Off,On" bitfld.long 0x00 20. " ADRENA ,DDR3 interface address/command drivers On" "Off,On" newline bitfld.long 0x00 17.--19. " RNKVAL ,Rank override value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13.--16. " DLYVAL ,Initial delay value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--12. " PHYOFF ,PHYOFF value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " DATLAT ,Fixed read latency" "-,Fixed" newline bitfld.long 0x00 6.--8. " RDPTR ,FIFO margin (setup-hold)" "4-0,0-0,0-4,1-3,2-2,3-1,2-2,3-1" bitfld.long 0x00 5. " RNKOVR ,Value loaded into RANK_OVERRIDE" "Not used,RANK_OVERRIDE_VALUE" bitfld.long 0x00 4. " INIDLA ,Initialization delay" "No delay,DLYVAL" bitfld.long 0x00 3. " DESKEW ,Run RDDLY DESKEW during read calibration" "No,Yes" newline bitfld.long 0x00 2. " CENTER ,Run RDDLY readeye DQS centring" "No,Yes" bitfld.long 0x00 1. " RESET ,Latches reset" "-,Reset" bitfld.long 0x00 0. " RUN ,FSM calibration" "Default,?..." width 0x0B tree.end tree.open "PCIe (PCIe Support Module)" tree "PCIe 0 4x0" width 8. group.long (dcr:0x80001000+0x0)++0x03 line.long 0x00 "PCIE00,PCIe Support Register 00" group.long (dcr:0x80001000+0x1)++0x03 line.long 0x00 "PCIE01,PCIe Support Register 01" group.long (dcr:0x80001000+0x2)++0x03 line.long 0x00 "PCIE02,PCIe Support Register 02" group.long (dcr:0x80001000+0x03)++0x03 line.long 0x00 "PCIE03,PCIe Support Register 03" bitfld.long 0x00 31. " REQ ,Generate 1 cycle pulse" "-,Generated" bitfld.long 0x00 30. " TYPE ,Transaction type" "MSI write,INT-x message" bitfld.long 0x00 27.--29. " TC ,MSI transaction traffic class" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--26. " FUNC ,Device function number responsible for interrupt request setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 22. " REQACK ,Interrupt generation request/Interrupt request acknowledge" "Acknowledged,Requested" bitfld.long 0x00 21. " INTXST ,INTx legacy interrupt status" "0,1" bitfld.long 0x00 20. " LKDWNN ,Link down reset mechanism enable" "-,Enabled" bitfld.long 0x00 19. " AUXPWA ,Auxiliary power available" "-,Available" newline bitfld.long 0x00 18. " AUXPWD ,Auxiliary power detected" "-,Detected" bitfld.long 0x00 17. " ATNBTN ,Attention button pressed" "-,Pressed" bitfld.long 0x00 16. " PWRFLT ,Power fault detected" "-,Detected" bitfld.long 0x00 15. " MRLSNC ,Mechanical retention latch sensor state change" "0,1" newline bitfld.long 0x00 14. " SLTDCT ,Presence detect state change" "0,1" bitfld.long 0x00 13. " PWRCTL ,Command completed" "-,Completed" bitfld.long 0x00 12. " MRLSNS ,Mechanical retention latch sensor state" "0,1" bitfld.long 0x00 11. " SLTDST ,Presence detect state" "0,1" newline bitfld.long 0x00 10. " ELMST ,Electromechanical interlock status" "0,1" rbitfld.long 0x00 9. " VFMSE ,Virtual function memory space enable" "-,Enabled" rbitfld.long 0x00 8. " PMEN ,Auxiliary power PM enable" "-,Enabled" rbitfld.long 0x00 7. " SERR ,PCIe system error" "-,Error" newline rbitfld.long 0x00 3.--6. " DATSEL ,Data select for PM data register from PMCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " VCACTV ,VC0 flow control negotiation complete" "-,Completed" rbitfld.long 0x00 1. " SRVFEN ,Physical function 0 virtual functions enable" "-,Enabled" rbitfld.long 0x00 0. " ARICAP ,Alternative routing interpretation (ARI) function numbering support" "-,Supported" if ((per.l(dcr:0x80001000+0x03)&0x02)==0x02) group.long (dcr:0x80001000+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" hexmask.long.word 0x00 0.--15. 1. " CFGVFS ,Number of VFs enabled for PF0" else group.long (dcr:0x80001000+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" endif group.long (dcr:0x80001000+0x5)++0x03 line.long 0x00 "PCIE05,PCIe Support Register 05" rgroup.long (dcr:0x80001000+0x6)++0x03 line.long 0x00 "PCIE06,PCIe Support Register 06" group.long (dcr:0x80001000+0x7)++0x03 line.long 0x00 "PCIE07,PCIe Support Register 07" group.long (dcr:0x80001000+0x8)++0x03 line.long 0x00 "PCIE08,PCIe Support Register 08" group.long (dcr:0x80001000+0x9)++0x03 line.long 0x00 "PCIE09,PCIe Support Register 09" group.long (dcr:0x80001000+0xA)++0x03 line.long 0x00 "PCIE0A,PCIe Support Register 0A" group.long (dcr:0x80001000+0xB)++0x03 line.long 0x00 "PCIE0B,PCIe Support Register 0B" group.long (dcr:0x80001000+0xC)++0x03 line.long 0x00 "PCIE0C,PCIe Support Register 0C" group.long (dcr:0x80001000+0x0D)++0x03 line.long 0x00 "PCIE0D,PCIe Support Register 0D" hexmask.long.word 0x00 16.--31. 1. " DEVICEID ,VFs device ID" bitfld.long 0x00 12.--15. " VFBAR0 ,VF base address register 0 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " VFVAR1 ,VF base address register 1 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " VFBAR2 ,VF base address register 2 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " INTXDS ,INTx legacy interrupt disable" "No,Yes" group.long (dcr:0x80001000+0x0E)++0x03 line.long 0x00 "PCIE0E,PCIe Support Register 0E" bitfld.long 0x00 28.--31. " VFBAR3 ,VF base address register 3 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " VFBAR4 ,VF base address register 4 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " VFBAR5 ,VF base address register 5 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 7.--19. 1. " BUFSIZ ,Replay buffer size" newline bitfld.long 0x00 4.--6. " RDSIZE ,Maximum outbound PCIe read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 2.--3. " PCINPT ,Maximum number of outbound non-posted transaction outstanding on PCIe" "4 transactions,8 transactions,16 transactions,32 transactions" bitfld.long 0x00 0.--1. " GBINPT ,Maximum number of inbound non-posted transactions outstanding on GBIF" "4 transactions,8 transactions,16 transactions,32 transactions" rgroup.long (dcr:0x80001000+0x0F)++0x03 line.long 0x00 "PCIE0F,PCIe Support Register 0F" group.long (dcr:0x80001000+0x10)++0x03 line.long 0x00 "PCIE10,PCIe Support Register 10" group.long (dcr:0x80001000+0x11)++0x03 line.long 0x00 "PCIE11,PCIe Support Register 11" bitfld.long 0x00 31. " VCTMSK ,MSI vector masking capable" "-,Capable" bitfld.long 0x00 30. " FNCMSK ,MSI-X function mask" "0,1" hexmask.long 0x00 0.--29. 0x01 " MSGADD ,MSI lower address bits" rgroup.long (dcr:0x80001000+0x12)++0x03 line.long 0x00 "PCIE12,PCIe Support Register 12" rgroup.long (dcr:0x80001000+0x13)++0x03 line.long 0x00 "PCIE13,PCIe Support Register 13" hexmask.long.word 0x00 23.--31. 1. " MSIEN ,MSI enable status" hexmask.long.word 0x00 14.--22. 1. " MSIXEN ,MSI-X enable status" bitfld.long 0x00 11.--13. " MSGEN ,MSI multiple messages enable status" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 2.--10. 1. " EPBUS ,Endpoint mode: PCI bus master enable" bitfld.long 0x00 1. " RCBUS ,Root port mode: PCI bus master enable" "-,Enabled" bitfld.long 0x00 0. " SLTWK ,Slow wake indication" "0,1" rgroup.long (dcr:0x80001000+0x14)++0x03 line.long 0x00 "PCIE14,PCIe Support Register 14" hexmask.long.word 0x00 16.--31. 1. " MSGDAT ,MSI-X message data" hexmask.long.word 0x00 7.--15. 1. " FLR ,Function level reset request" bitfld.long 0x00 6. " SLTINT ,Slot interrupt" "-,Interrupt" bitfld.long 0x00 4.--5. " ATNIND ,Attention indicator" "0,1,2,3" newline bitfld.long 0x00 2.--3. " PWRIND ,Power indicator" "0,1,2,3" bitfld.long 0x00 1. " PWRCTL ,Power control" "0,1" bitfld.long 0x00 0. " ELMTOG ,Electromechanical interlock toggle" "0,1" group.long (dcr:0x80001000+0x15)++0x03 line.long 0x00 "PCIE15,PCIe Support Register 15" group.long (dcr:0x80001000+0x16)++0x03 line.long 0x00 "PCIE16,PCIe Support Register 16" group.long (dcr:0x80001000+0x17)++0x03 line.long 0x00 "PCIE17,PCIe Support Register 17" bitfld.long 0x00 29.--31. " RDSIZE ,Maximum supported inbound GBIF read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 26.--28. " WRSIZE ,Maximum supported inbound GBIF write request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 25. " DISCON ,Inbound discontinuous writes enable" "-,Enabled" bitfld.long 0x00 22.--24. " OUTPDT ,VSs Outbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" newline bitfld.long 0x00 19.--21. " INPDT ,VSs inbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" bitfld.long 0x00 18. " INITEN ,Buffer allocation registers initialization with SYS_LINK_INIT_* enable" "-,Enabled" bitfld.long 0x00 12.--17. " RXPH0 ,Initial number of inbound posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " RXNPH0 ,Initial number of inbound non-posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " GBIFTG ,Initial number of inbound GBIF read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(dcr:0x80001000+0x18)&0x400)==0x00) group.long (dcr:0x80001000+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" hexmask.long.word 0x00 1.--9. 1. " FLR ,FLR acknowledge" bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" else group.long (dcr:0x80001000+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" textfld " " bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" endif group.long (dcr:0x80001000+0x19)++0x03 line.long 0x00 "PCIE19,PCIe Support Register 19" bitfld.long 0x00 31. " IDLERR ,Assert TXELECIDLE to PHY on uncorrectable error in transmit data" "-,Asserted" newline bitfld.long 0x00 30. " BLKTRN ,Block ACK/NAK TX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 29. " BLKRCV ,Block ACK/NAK RX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 28. " CMD ,Error injection command" "0,1" bitfld.long 0x00 22.--27. " TYPE ,Error injection command type" ",TX B/B encoding error,,,,,,,,,,,,,,,,TX LCRC error,,Force Detection of DLPE,Force detection of FCPE,,Force detection of replay timeout error,Force detection replay roll-over,Force bad TLP detection,Force bad DLLP detection,,,,,,,,Inject TX datapath parity/ECC error,Inject RX datapath parity/ECC error,Inject control arrays parity error,Inject TX poisoned TLP,Inject RX poisoned TLP,TX ECRC error,Force detection of completion timeout,Force detection of completer abort status,Force detection of unsupported request status,Force detection of unexpected completion,Force detection of receiver overflow,Force detection of malformed TLP,Force detection of unsupported request error,Force detection of RX ECRC error,,,Inject configuration registers parity error,?..." newline rbitfld.long 0x00 21. " CMDDNE ,AL_EI_CMD pulsed" "Asserted,Pulsed" rbitfld.long 0x00 20. " WDTCFG ,Remote component is capable of link width up configuration" "-,Capable" rbitfld.long 0x00 19. " WDTCHG ,SYS_CHANGELINKWIDTH asserted" "-,Asserted" newline rbitfld.long 0x00 18. " WDTDIS ,Hardware autonomous link width up configuration capability disable" "No,Yes" rbitfld.long 0x00 17. " BAREN ,ROM region enabled by application" "0,1" bitfld.long 0x00 16. " ASYNC ,SYS_ASYNC_STABLE value" "0,1" hexmask.long.word 0x00 0.--15. 1. " FRCDCT ,Receiver detect result" group.long (dcr:0x80001000+0x20)++0x03 line.long 0x00 "PCIE1A,PCIe Support Register 1A" bitfld.long 0x00 31. " DISDET ,Link bring up sequence disable" "No,Yes" bitfld.long 0x00 30. " FRCDET ,Receiver detect results from PHY override by SYS_FORCEDETECTRESULTS" "-,Overridden" bitfld.long 0x00 24.--29. " TRGLKW ,Target link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " CHGLKW ,Link width change initialization" "-,Initialized" newline bitfld.long 0x00 22. " IMMISC ,Master hold requested" "-,Requested" bitfld.long 0x00 21. " ISMISC ,Slave hold requested" "-,Requested" rbitfld.long 0x00 20. " OSMISC ,PCIEXGPL4DDR slave idle" "-,Idle" rbitfld.long 0x00 19. " OMMISC ,PCIEXGPL4DDR master idle" "-,Idle" newline rbitfld.long 0x00 18. " RDACT ,Outbound GBIF read transaction in process" "-,In process" rbitfld.long 0x00 17. " WRACT ,Outbound GBIF write transaction in process" "-,In process" rbitfld.long 0x00 16. " REGACT ,Outbound GBIF registers transaction in process" "-,In process" width 0x0B tree.end tree "PCIe 0 2x0" width 8. group.long (dcr:0x80001100+0x0)++0x03 line.long 0x00 "PCIE00,PCIe Support Register 00" group.long (dcr:0x80001100+0x1)++0x03 line.long 0x00 "PCIE01,PCIe Support Register 01" group.long (dcr:0x80001100+0x2)++0x03 line.long 0x00 "PCIE02,PCIe Support Register 02" group.long (dcr:0x80001100+0x03)++0x03 line.long 0x00 "PCIE03,PCIe Support Register 03" bitfld.long 0x00 31. " REQ ,Generate 1 cycle pulse" "-,Generated" bitfld.long 0x00 30. " TYPE ,Transaction type" "MSI write,INT-x message" bitfld.long 0x00 27.--29. " TC ,MSI transaction traffic class" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--26. " FUNC ,Device function number responsible for interrupt request setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 22. " REQACK ,Interrupt generation request/Interrupt request acknowledge" "Acknowledged,Requested" bitfld.long 0x00 21. " INTXST ,INTx legacy interrupt status" "0,1" bitfld.long 0x00 20. " LKDWNN ,Link down reset mechanism enable" "-,Enabled" bitfld.long 0x00 19. " AUXPWA ,Auxiliary power available" "-,Available" newline bitfld.long 0x00 18. " AUXPWD ,Auxiliary power detected" "-,Detected" bitfld.long 0x00 17. " ATNBTN ,Attention button pressed" "-,Pressed" bitfld.long 0x00 16. " PWRFLT ,Power fault detected" "-,Detected" bitfld.long 0x00 15. " MRLSNC ,Mechanical retention latch sensor state change" "0,1" newline bitfld.long 0x00 14. " SLTDCT ,Presence detect state change" "0,1" bitfld.long 0x00 13. " PWRCTL ,Command completed" "-,Completed" bitfld.long 0x00 12. " MRLSNS ,Mechanical retention latch sensor state" "0,1" bitfld.long 0x00 11. " SLTDST ,Presence detect state" "0,1" newline bitfld.long 0x00 10. " ELMST ,Electromechanical interlock status" "0,1" rbitfld.long 0x00 9. " VFMSE ,Virtual function memory space enable" "-,Enabled" rbitfld.long 0x00 8. " PMEN ,Auxiliary power PM enable" "-,Enabled" rbitfld.long 0x00 7. " SERR ,PCIe system error" "-,Error" newline rbitfld.long 0x00 3.--6. " DATSEL ,Data select for PM data register from PMCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " VCACTV ,VC0 flow control negotiation complete" "-,Completed" rbitfld.long 0x00 1. " SRVFEN ,Physical function 0 virtual functions enable" "-,Enabled" rbitfld.long 0x00 0. " ARICAP ,Alternative routing interpretation (ARI) function numbering support" "-,Supported" if ((per.l(dcr:0x80001100+0x03)&0x02)==0x02) group.long (dcr:0x80001100+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" hexmask.long.word 0x00 0.--15. 1. " CFGVFS ,Number of VFs enabled for PF0" else group.long (dcr:0x80001100+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" endif group.long (dcr:0x80001100+0x5)++0x03 line.long 0x00 "PCIE05,PCIe Support Register 05" rgroup.long (dcr:0x80001100+0x6)++0x03 line.long 0x00 "PCIE06,PCIe Support Register 06" group.long (dcr:0x80001100+0x7)++0x03 line.long 0x00 "PCIE07,PCIe Support Register 07" group.long (dcr:0x80001100+0x8)++0x03 line.long 0x00 "PCIE08,PCIe Support Register 08" group.long (dcr:0x80001100+0x9)++0x03 line.long 0x00 "PCIE09,PCIe Support Register 09" group.long (dcr:0x80001100+0xA)++0x03 line.long 0x00 "PCIE0A,PCIe Support Register 0A" group.long (dcr:0x80001100+0xB)++0x03 line.long 0x00 "PCIE0B,PCIe Support Register 0B" group.long (dcr:0x80001100+0xC)++0x03 line.long 0x00 "PCIE0C,PCIe Support Register 0C" group.long (dcr:0x80001100+0x0D)++0x03 line.long 0x00 "PCIE0D,PCIe Support Register 0D" hexmask.long.word 0x00 16.--31. 1. " DEVICEID ,VFs device ID" bitfld.long 0x00 12.--15. " VFBAR0 ,VF base address register 0 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " VFVAR1 ,VF base address register 1 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " VFBAR2 ,VF base address register 2 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " INTXDS ,INTx legacy interrupt disable" "No,Yes" group.long (dcr:0x80001100+0x0E)++0x03 line.long 0x00 "PCIE0E,PCIe Support Register 0E" bitfld.long 0x00 28.--31. " VFBAR3 ,VF base address register 3 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " VFBAR4 ,VF base address register 4 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " VFBAR5 ,VF base address register 5 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 7.--19. 1. " BUFSIZ ,Replay buffer size" newline bitfld.long 0x00 4.--6. " RDSIZE ,Maximum outbound PCIe read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 2.--3. " PCINPT ,Maximum number of outbound non-posted transaction outstanding on PCIe" "4 transactions,8 transactions,16 transactions,32 transactions" bitfld.long 0x00 0.--1. " GBINPT ,Maximum number of inbound non-posted transactions outstanding on GBIF" "4 transactions,8 transactions,16 transactions,32 transactions" rgroup.long (dcr:0x80001100+0x0F)++0x03 line.long 0x00 "PCIE0F,PCIe Support Register 0F" group.long (dcr:0x80001100+0x10)++0x03 line.long 0x00 "PCIE10,PCIe Support Register 10" group.long (dcr:0x80001100+0x11)++0x03 line.long 0x00 "PCIE11,PCIe Support Register 11" bitfld.long 0x00 31. " VCTMSK ,MSI vector masking capable" "-,Capable" bitfld.long 0x00 30. " FNCMSK ,MSI-X function mask" "0,1" hexmask.long 0x00 0.--29. 0x01 " MSGADD ,MSI lower address bits" rgroup.long (dcr:0x80001100+0x12)++0x03 line.long 0x00 "PCIE12,PCIe Support Register 12" rgroup.long (dcr:0x80001100+0x13)++0x03 line.long 0x00 "PCIE13,PCIe Support Register 13" hexmask.long.word 0x00 23.--31. 1. " MSIEN ,MSI enable status" hexmask.long.word 0x00 14.--22. 1. " MSIXEN ,MSI-X enable status" bitfld.long 0x00 11.--13. " MSGEN ,MSI multiple messages enable status" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 2.--10. 1. " EPBUS ,Endpoint mode: PCI bus master enable" bitfld.long 0x00 1. " RCBUS ,Root port mode: PCI bus master enable" "-,Enabled" bitfld.long 0x00 0. " SLTWK ,Slow wake indication" "0,1" rgroup.long (dcr:0x80001100+0x14)++0x03 line.long 0x00 "PCIE14,PCIe Support Register 14" hexmask.long.word 0x00 16.--31. 1. " MSGDAT ,MSI-X message data" hexmask.long.word 0x00 7.--15. 1. " FLR ,Function level reset request" bitfld.long 0x00 6. " SLTINT ,Slot interrupt" "-,Interrupt" bitfld.long 0x00 4.--5. " ATNIND ,Attention indicator" "0,1,2,3" newline bitfld.long 0x00 2.--3. " PWRIND ,Power indicator" "0,1,2,3" bitfld.long 0x00 1. " PWRCTL ,Power control" "0,1" bitfld.long 0x00 0. " ELMTOG ,Electromechanical interlock toggle" "0,1" group.long (dcr:0x80001100+0x15)++0x03 line.long 0x00 "PCIE15,PCIe Support Register 15" group.long (dcr:0x80001100+0x16)++0x03 line.long 0x00 "PCIE16,PCIe Support Register 16" group.long (dcr:0x80001100+0x17)++0x03 line.long 0x00 "PCIE17,PCIe Support Register 17" bitfld.long 0x00 29.--31. " RDSIZE ,Maximum supported inbound GBIF read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 26.--28. " WRSIZE ,Maximum supported inbound GBIF write request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 25. " DISCON ,Inbound discontinuous writes enable" "-,Enabled" bitfld.long 0x00 22.--24. " OUTPDT ,VSs Outbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" newline bitfld.long 0x00 19.--21. " INPDT ,VSs inbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" bitfld.long 0x00 18. " INITEN ,Buffer allocation registers initialization with SYS_LINK_INIT_* enable" "-,Enabled" bitfld.long 0x00 12.--17. " RXPH0 ,Initial number of inbound posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " RXNPH0 ,Initial number of inbound non-posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " GBIFTG ,Initial number of inbound GBIF read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(dcr:0x80001100+0x18)&0x400)==0x00) group.long (dcr:0x80001100+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" hexmask.long.word 0x00 1.--9. 1. " FLR ,FLR acknowledge" bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" else group.long (dcr:0x80001100+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" textfld " " bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" endif group.long (dcr:0x80001100+0x19)++0x03 line.long 0x00 "PCIE19,PCIe Support Register 19" bitfld.long 0x00 31. " IDLERR ,Assert TXELECIDLE to PHY on uncorrectable error in transmit data" "-,Asserted" newline bitfld.long 0x00 30. " BLKTRN ,Block ACK/NAK TX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 29. " BLKRCV ,Block ACK/NAK RX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 28. " CMD ,Error injection command" "0,1" bitfld.long 0x00 22.--27. " TYPE ,Error injection command type" ",TX B/B encoding error,,,,,,,,,,,,,,,,TX LCRC error,,Force Detection of DLPE,Force detection of FCPE,,Force detection of replay timeout error,Force detection replay roll-over,Force bad TLP detection,Force bad DLLP detection,,,,,,,,Inject TX datapath parity/ECC error,Inject RX datapath parity/ECC error,Inject control arrays parity error,Inject TX poisoned TLP,Inject RX poisoned TLP,TX ECRC error,Force detection of completion timeout,Force detection of completer abort status,Force detection of unsupported request status,Force detection of unexpected completion,Force detection of receiver overflow,Force detection of malformed TLP,Force detection of unsupported request error,Force detection of RX ECRC error,,,Inject configuration registers parity error,?..." newline rbitfld.long 0x00 21. " CMDDNE ,AL_EI_CMD pulsed" "Asserted,Pulsed" rbitfld.long 0x00 20. " WDTCFG ,Remote component is capable of link width up configuration" "-,Capable" rbitfld.long 0x00 19. " WDTCHG ,SYS_CHANGELINKWIDTH asserted" "-,Asserted" newline rbitfld.long 0x00 18. " WDTDIS ,Hardware autonomous link width up configuration capability disable" "No,Yes" rbitfld.long 0x00 17. " BAREN ,ROM region enabled by application" "0,1" bitfld.long 0x00 16. " ASYNC ,SYS_ASYNC_STABLE value" "0,1" hexmask.long.word 0x00 0.--15. 1. " FRCDCT ,Receiver detect result" group.long (dcr:0x80001100+0x20)++0x03 line.long 0x00 "PCIE1A,PCIe Support Register 1A" bitfld.long 0x00 31. " DISDET ,Link bring up sequence disable" "No,Yes" bitfld.long 0x00 30. " FRCDET ,Receiver detect results from PHY override by SYS_FORCEDETECTRESULTS" "-,Overridden" bitfld.long 0x00 24.--29. " TRGLKW ,Target link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " CHGLKW ,Link width change initialization" "-,Initialized" newline bitfld.long 0x00 22. " IMMISC ,Master hold requested" "-,Requested" bitfld.long 0x00 21. " ISMISC ,Slave hold requested" "-,Requested" rbitfld.long 0x00 20. " OSMISC ,PCIEXGPL4DDR slave idle" "-,Idle" rbitfld.long 0x00 19. " OMMISC ,PCIEXGPL4DDR master idle" "-,Idle" newline rbitfld.long 0x00 18. " RDACT ,Outbound GBIF read transaction in process" "-,In process" rbitfld.long 0x00 17. " WRACT ,Outbound GBIF write transaction in process" "-,In process" rbitfld.long 0x00 16. " REGACT ,Outbound GBIF registers transaction in process" "-,In process" width 0x0B tree.end tree "PCIe 1 4x1" width 8. group.long (dcr:0x80001200+0x0)++0x03 line.long 0x00 "PCIE00,PCIe Support Register 00" group.long (dcr:0x80001200+0x1)++0x03 line.long 0x00 "PCIE01,PCIe Support Register 01" group.long (dcr:0x80001200+0x2)++0x03 line.long 0x00 "PCIE02,PCIe Support Register 02" group.long (dcr:0x80001200+0x03)++0x03 line.long 0x00 "PCIE03,PCIe Support Register 03" bitfld.long 0x00 31. " REQ ,Generate 1 cycle pulse" "-,Generated" bitfld.long 0x00 30. " TYPE ,Transaction type" "MSI write,INT-x message" bitfld.long 0x00 27.--29. " TC ,MSI transaction traffic class" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--26. " FUNC ,Device function number responsible for interrupt request setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 22. " REQACK ,Interrupt generation request/Interrupt request acknowledge" "Acknowledged,Requested" bitfld.long 0x00 21. " INTXST ,INTx legacy interrupt status" "0,1" bitfld.long 0x00 20. " LKDWNN ,Link down reset mechanism enable" "-,Enabled" bitfld.long 0x00 19. " AUXPWA ,Auxiliary power available" "-,Available" newline bitfld.long 0x00 18. " AUXPWD ,Auxiliary power detected" "-,Detected" bitfld.long 0x00 17. " ATNBTN ,Attention button pressed" "-,Pressed" bitfld.long 0x00 16. " PWRFLT ,Power fault detected" "-,Detected" bitfld.long 0x00 15. " MRLSNC ,Mechanical retention latch sensor state change" "0,1" newline bitfld.long 0x00 14. " SLTDCT ,Presence detect state change" "0,1" bitfld.long 0x00 13. " PWRCTL ,Command completed" "-,Completed" bitfld.long 0x00 12. " MRLSNS ,Mechanical retention latch sensor state" "0,1" bitfld.long 0x00 11. " SLTDST ,Presence detect state" "0,1" newline bitfld.long 0x00 10. " ELMST ,Electromechanical interlock status" "0,1" rbitfld.long 0x00 9. " VFMSE ,Virtual function memory space enable" "-,Enabled" rbitfld.long 0x00 8. " PMEN ,Auxiliary power PM enable" "-,Enabled" rbitfld.long 0x00 7. " SERR ,PCIe system error" "-,Error" newline rbitfld.long 0x00 3.--6. " DATSEL ,Data select for PM data register from PMCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " VCACTV ,VC0 flow control negotiation complete" "-,Completed" rbitfld.long 0x00 1. " SRVFEN ,Physical function 0 virtual functions enable" "-,Enabled" rbitfld.long 0x00 0. " ARICAP ,Alternative routing interpretation (ARI) function numbering support" "-,Supported" if ((per.l(dcr:0x80001200+0x03)&0x02)==0x02) group.long (dcr:0x80001200+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" hexmask.long.word 0x00 0.--15. 1. " CFGVFS ,Number of VFs enabled for PF0" else group.long (dcr:0x80001200+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" endif group.long (dcr:0x80001200+0x5)++0x03 line.long 0x00 "PCIE05,PCIe Support Register 05" rgroup.long (dcr:0x80001200+0x6)++0x03 line.long 0x00 "PCIE06,PCIe Support Register 06" group.long (dcr:0x80001200+0x7)++0x03 line.long 0x00 "PCIE07,PCIe Support Register 07" group.long (dcr:0x80001200+0x8)++0x03 line.long 0x00 "PCIE08,PCIe Support Register 08" group.long (dcr:0x80001200+0x9)++0x03 line.long 0x00 "PCIE09,PCIe Support Register 09" group.long (dcr:0x80001200+0xA)++0x03 line.long 0x00 "PCIE0A,PCIe Support Register 0A" group.long (dcr:0x80001200+0xB)++0x03 line.long 0x00 "PCIE0B,PCIe Support Register 0B" group.long (dcr:0x80001200+0xC)++0x03 line.long 0x00 "PCIE0C,PCIe Support Register 0C" group.long (dcr:0x80001200+0x0D)++0x03 line.long 0x00 "PCIE0D,PCIe Support Register 0D" hexmask.long.word 0x00 16.--31. 1. " DEVICEID ,VFs device ID" bitfld.long 0x00 12.--15. " VFBAR0 ,VF base address register 0 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " VFVAR1 ,VF base address register 1 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " VFBAR2 ,VF base address register 2 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " INTXDS ,INTx legacy interrupt disable" "No,Yes" group.long (dcr:0x80001200+0x0E)++0x03 line.long 0x00 "PCIE0E,PCIe Support Register 0E" bitfld.long 0x00 28.--31. " VFBAR3 ,VF base address register 3 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " VFBAR4 ,VF base address register 4 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " VFBAR5 ,VF base address register 5 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 7.--19. 1. " BUFSIZ ,Replay buffer size" newline bitfld.long 0x00 4.--6. " RDSIZE ,Maximum outbound PCIe read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 2.--3. " PCINPT ,Maximum number of outbound non-posted transaction outstanding on PCIe" "4 transactions,8 transactions,16 transactions,32 transactions" bitfld.long 0x00 0.--1. " GBINPT ,Maximum number of inbound non-posted transactions outstanding on GBIF" "4 transactions,8 transactions,16 transactions,32 transactions" rgroup.long (dcr:0x80001200+0x0F)++0x03 line.long 0x00 "PCIE0F,PCIe Support Register 0F" group.long (dcr:0x80001200+0x10)++0x03 line.long 0x00 "PCIE10,PCIe Support Register 10" group.long (dcr:0x80001200+0x11)++0x03 line.long 0x00 "PCIE11,PCIe Support Register 11" bitfld.long 0x00 31. " VCTMSK ,MSI vector masking capable" "-,Capable" bitfld.long 0x00 30. " FNCMSK ,MSI-X function mask" "0,1" hexmask.long 0x00 0.--29. 0x01 " MSGADD ,MSI lower address bits" rgroup.long (dcr:0x80001200+0x12)++0x03 line.long 0x00 "PCIE12,PCIe Support Register 12" rgroup.long (dcr:0x80001200+0x13)++0x03 line.long 0x00 "PCIE13,PCIe Support Register 13" hexmask.long.word 0x00 23.--31. 1. " MSIEN ,MSI enable status" hexmask.long.word 0x00 14.--22. 1. " MSIXEN ,MSI-X enable status" bitfld.long 0x00 11.--13. " MSGEN ,MSI multiple messages enable status" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 2.--10. 1. " EPBUS ,Endpoint mode: PCI bus master enable" bitfld.long 0x00 1. " RCBUS ,Root port mode: PCI bus master enable" "-,Enabled" bitfld.long 0x00 0. " SLTWK ,Slow wake indication" "0,1" rgroup.long (dcr:0x80001200+0x14)++0x03 line.long 0x00 "PCIE14,PCIe Support Register 14" hexmask.long.word 0x00 16.--31. 1. " MSGDAT ,MSI-X message data" hexmask.long.word 0x00 7.--15. 1. " FLR ,Function level reset request" bitfld.long 0x00 6. " SLTINT ,Slot interrupt" "-,Interrupt" bitfld.long 0x00 4.--5. " ATNIND ,Attention indicator" "0,1,2,3" newline bitfld.long 0x00 2.--3. " PWRIND ,Power indicator" "0,1,2,3" bitfld.long 0x00 1. " PWRCTL ,Power control" "0,1" bitfld.long 0x00 0. " ELMTOG ,Electromechanical interlock toggle" "0,1" group.long (dcr:0x80001200+0x15)++0x03 line.long 0x00 "PCIE15,PCIe Support Register 15" group.long (dcr:0x80001200+0x16)++0x03 line.long 0x00 "PCIE16,PCIe Support Register 16" group.long (dcr:0x80001200+0x17)++0x03 line.long 0x00 "PCIE17,PCIe Support Register 17" bitfld.long 0x00 29.--31. " RDSIZE ,Maximum supported inbound GBIF read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 26.--28. " WRSIZE ,Maximum supported inbound GBIF write request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 25. " DISCON ,Inbound discontinuous writes enable" "-,Enabled" bitfld.long 0x00 22.--24. " OUTPDT ,VSs Outbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" newline bitfld.long 0x00 19.--21. " INPDT ,VSs inbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" bitfld.long 0x00 18. " INITEN ,Buffer allocation registers initialization with SYS_LINK_INIT_* enable" "-,Enabled" bitfld.long 0x00 12.--17. " RXPH0 ,Initial number of inbound posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " RXNPH0 ,Initial number of inbound non-posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " GBIFTG ,Initial number of inbound GBIF read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(dcr:0x80001200+0x18)&0x400)==0x00) group.long (dcr:0x80001200+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" hexmask.long.word 0x00 1.--9. 1. " FLR ,FLR acknowledge" bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" else group.long (dcr:0x80001200+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" textfld " " bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" endif group.long (dcr:0x80001200+0x19)++0x03 line.long 0x00 "PCIE19,PCIe Support Register 19" bitfld.long 0x00 31. " IDLERR ,Assert TXELECIDLE to PHY on uncorrectable error in transmit data" "-,Asserted" newline bitfld.long 0x00 30. " BLKTRN ,Block ACK/NAK TX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 29. " BLKRCV ,Block ACK/NAK RX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 28. " CMD ,Error injection command" "0,1" bitfld.long 0x00 22.--27. " TYPE ,Error injection command type" ",TX B/B encoding error,,,,,,,,,,,,,,,,TX LCRC error,,Force Detection of DLPE,Force detection of FCPE,,Force detection of replay timeout error,Force detection replay roll-over,Force bad TLP detection,Force bad DLLP detection,,,,,,,,Inject TX datapath parity/ECC error,Inject RX datapath parity/ECC error,Inject control arrays parity error,Inject TX poisoned TLP,Inject RX poisoned TLP,TX ECRC error,Force detection of completion timeout,Force detection of completer abort status,Force detection of unsupported request status,Force detection of unexpected completion,Force detection of receiver overflow,Force detection of malformed TLP,Force detection of unsupported request error,Force detection of RX ECRC error,,,Inject configuration registers parity error,?..." newline rbitfld.long 0x00 21. " CMDDNE ,AL_EI_CMD pulsed" "Asserted,Pulsed" rbitfld.long 0x00 20. " WDTCFG ,Remote component is capable of link width up configuration" "-,Capable" rbitfld.long 0x00 19. " WDTCHG ,SYS_CHANGELINKWIDTH asserted" "-,Asserted" newline rbitfld.long 0x00 18. " WDTDIS ,Hardware autonomous link width up configuration capability disable" "No,Yes" rbitfld.long 0x00 17. " BAREN ,ROM region enabled by application" "0,1" bitfld.long 0x00 16. " ASYNC ,SYS_ASYNC_STABLE value" "0,1" hexmask.long.word 0x00 0.--15. 1. " FRCDCT ,Receiver detect result" group.long (dcr:0x80001200+0x20)++0x03 line.long 0x00 "PCIE1A,PCIe Support Register 1A" bitfld.long 0x00 31. " DISDET ,Link bring up sequence disable" "No,Yes" bitfld.long 0x00 30. " FRCDET ,Receiver detect results from PHY override by SYS_FORCEDETECTRESULTS" "-,Overridden" bitfld.long 0x00 24.--29. " TRGLKW ,Target link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " CHGLKW ,Link width change initialization" "-,Initialized" newline bitfld.long 0x00 22. " IMMISC ,Master hold requested" "-,Requested" bitfld.long 0x00 21. " ISMISC ,Slave hold requested" "-,Requested" rbitfld.long 0x00 20. " OSMISC ,PCIEXGPL4DDR slave idle" "-,Idle" rbitfld.long 0x00 19. " OMMISC ,PCIEXGPL4DDR master idle" "-,Idle" newline rbitfld.long 0x00 18. " RDACT ,Outbound GBIF read transaction in process" "-,In process" rbitfld.long 0x00 17. " WRACT ,Outbound GBIF write transaction in process" "-,In process" rbitfld.long 0x00 16. " REGACT ,Outbound GBIF registers transaction in process" "-,In process" width 0x0B tree.end tree "PCIe 1 2x1" width 8. group.long (dcr:0x80001300+0x0)++0x03 line.long 0x00 "PCIE00,PCIe Support Register 00" group.long (dcr:0x80001300+0x1)++0x03 line.long 0x00 "PCIE01,PCIe Support Register 01" group.long (dcr:0x80001300+0x2)++0x03 line.long 0x00 "PCIE02,PCIe Support Register 02" group.long (dcr:0x80001300+0x03)++0x03 line.long 0x00 "PCIE03,PCIe Support Register 03" bitfld.long 0x00 31. " REQ ,Generate 1 cycle pulse" "-,Generated" bitfld.long 0x00 30. " TYPE ,Transaction type" "MSI write,INT-x message" bitfld.long 0x00 27.--29. " TC ,MSI transaction traffic class" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--26. " FUNC ,Device function number responsible for interrupt request setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 22. " REQACK ,Interrupt generation request/Interrupt request acknowledge" "Acknowledged,Requested" bitfld.long 0x00 21. " INTXST ,INTx legacy interrupt status" "0,1" bitfld.long 0x00 20. " LKDWNN ,Link down reset mechanism enable" "-,Enabled" bitfld.long 0x00 19. " AUXPWA ,Auxiliary power available" "-,Available" newline bitfld.long 0x00 18. " AUXPWD ,Auxiliary power detected" "-,Detected" bitfld.long 0x00 17. " ATNBTN ,Attention button pressed" "-,Pressed" bitfld.long 0x00 16. " PWRFLT ,Power fault detected" "-,Detected" bitfld.long 0x00 15. " MRLSNC ,Mechanical retention latch sensor state change" "0,1" newline bitfld.long 0x00 14. " SLTDCT ,Presence detect state change" "0,1" bitfld.long 0x00 13. " PWRCTL ,Command completed" "-,Completed" bitfld.long 0x00 12. " MRLSNS ,Mechanical retention latch sensor state" "0,1" bitfld.long 0x00 11. " SLTDST ,Presence detect state" "0,1" newline bitfld.long 0x00 10. " ELMST ,Electromechanical interlock status" "0,1" rbitfld.long 0x00 9. " VFMSE ,Virtual function memory space enable" "-,Enabled" rbitfld.long 0x00 8. " PMEN ,Auxiliary power PM enable" "-,Enabled" rbitfld.long 0x00 7. " SERR ,PCIe system error" "-,Error" newline rbitfld.long 0x00 3.--6. " DATSEL ,Data select for PM data register from PMCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 2. " VCACTV ,VC0 flow control negotiation complete" "-,Completed" rbitfld.long 0x00 1. " SRVFEN ,Physical function 0 virtual functions enable" "-,Enabled" rbitfld.long 0x00 0. " ARICAP ,Alternative routing interpretation (ARI) function numbering support" "-,Supported" if ((per.l(dcr:0x80001300+0x03)&0x02)==0x02) group.long (dcr:0x80001300+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" hexmask.long.word 0x00 0.--15. 1. " CFGVFS ,Number of VFs enabled for PF0" else group.long (dcr:0x80001300+0x04)++0x03 line.long 0x00 "PCIE04,PCIe Support Register 04" hexmask.long.word 0x00 16.--31. 1. " SYSVFS ,Total number of supported VFs" endif group.long (dcr:0x80001300+0x5)++0x03 line.long 0x00 "PCIE05,PCIe Support Register 05" rgroup.long (dcr:0x80001300+0x6)++0x03 line.long 0x00 "PCIE06,PCIe Support Register 06" group.long (dcr:0x80001300+0x7)++0x03 line.long 0x00 "PCIE07,PCIe Support Register 07" group.long (dcr:0x80001300+0x8)++0x03 line.long 0x00 "PCIE08,PCIe Support Register 08" group.long (dcr:0x80001300+0x9)++0x03 line.long 0x00 "PCIE09,PCIe Support Register 09" group.long (dcr:0x80001300+0xA)++0x03 line.long 0x00 "PCIE0A,PCIe Support Register 0A" group.long (dcr:0x80001300+0xB)++0x03 line.long 0x00 "PCIE0B,PCIe Support Register 0B" group.long (dcr:0x80001300+0xC)++0x03 line.long 0x00 "PCIE0C,PCIe Support Register 0C" group.long (dcr:0x80001300+0x0D)++0x03 line.long 0x00 "PCIE0D,PCIe Support Register 0D" hexmask.long.word 0x00 16.--31. 1. " DEVICEID ,VFs device ID" bitfld.long 0x00 12.--15. " VFBAR0 ,VF base address register 0 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " VFVAR1 ,VF base address register 1 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " VFBAR2 ,VF base address register 2 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " INTXDS ,INTx legacy interrupt disable" "No,Yes" group.long (dcr:0x80001300+0x0E)++0x03 line.long 0x00 "PCIE0E,PCIe Support Register 0E" bitfld.long 0x00 28.--31. " VFBAR3 ,VF base address register 3 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " VFBAR4 ,VF base address register 4 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " VFBAR5 ,VF base address register 5 type input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 7.--19. 1. " BUFSIZ ,Replay buffer size" newline bitfld.long 0x00 4.--6. " RDSIZE ,Maximum outbound PCIe read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 2.--3. " PCINPT ,Maximum number of outbound non-posted transaction outstanding on PCIe" "4 transactions,8 transactions,16 transactions,32 transactions" bitfld.long 0x00 0.--1. " GBINPT ,Maximum number of inbound non-posted transactions outstanding on GBIF" "4 transactions,8 transactions,16 transactions,32 transactions" rgroup.long (dcr:0x80001300+0x0F)++0x03 line.long 0x00 "PCIE0F,PCIe Support Register 0F" group.long (dcr:0x80001300+0x10)++0x03 line.long 0x00 "PCIE10,PCIe Support Register 10" group.long (dcr:0x80001300+0x11)++0x03 line.long 0x00 "PCIE11,PCIe Support Register 11" bitfld.long 0x00 31. " VCTMSK ,MSI vector masking capable" "-,Capable" bitfld.long 0x00 30. " FNCMSK ,MSI-X function mask" "0,1" hexmask.long 0x00 0.--29. 0x01 " MSGADD ,MSI lower address bits" rgroup.long (dcr:0x80001300+0x12)++0x03 line.long 0x00 "PCIE12,PCIe Support Register 12" rgroup.long (dcr:0x80001300+0x13)++0x03 line.long 0x00 "PCIE13,PCIe Support Register 13" hexmask.long.word 0x00 23.--31. 1. " MSIEN ,MSI enable status" hexmask.long.word 0x00 14.--22. 1. " MSIXEN ,MSI-X enable status" bitfld.long 0x00 11.--13. " MSGEN ,MSI multiple messages enable status" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 2.--10. 1. " EPBUS ,Endpoint mode: PCI bus master enable" bitfld.long 0x00 1. " RCBUS ,Root port mode: PCI bus master enable" "-,Enabled" bitfld.long 0x00 0. " SLTWK ,Slow wake indication" "0,1" rgroup.long (dcr:0x80001300+0x14)++0x03 line.long 0x00 "PCIE14,PCIe Support Register 14" hexmask.long.word 0x00 16.--31. 1. " MSGDAT ,MSI-X message data" hexmask.long.word 0x00 7.--15. 1. " FLR ,Function level reset request" bitfld.long 0x00 6. " SLTINT ,Slot interrupt" "-,Interrupt" bitfld.long 0x00 4.--5. " ATNIND ,Attention indicator" "0,1,2,3" newline bitfld.long 0x00 2.--3. " PWRIND ,Power indicator" "0,1,2,3" bitfld.long 0x00 1. " PWRCTL ,Power control" "0,1" bitfld.long 0x00 0. " ELMTOG ,Electromechanical interlock toggle" "0,1" group.long (dcr:0x80001300+0x15)++0x03 line.long 0x00 "PCIE15,PCIe Support Register 15" group.long (dcr:0x80001300+0x16)++0x03 line.long 0x00 "PCIE16,PCIe Support Register 16" group.long (dcr:0x80001300+0x17)++0x03 line.long 0x00 "PCIE17,PCIe Support Register 17" bitfld.long 0x00 29.--31. " RDSIZE ,Maximum supported inbound GBIF read request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 26.--28. " WRSIZE ,Maximum supported inbound GBIF write request size" "128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." bitfld.long 0x00 25. " DISCON ,Inbound discontinuous writes enable" "-,Enabled" bitfld.long 0x00 22.--24. " OUTPDT ,VSs Outbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" newline bitfld.long 0x00 19.--21. " INPDT ,VSs inbound posted data buffer size" "0.5 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB" bitfld.long 0x00 18. " INITEN ,Buffer allocation registers initialization with SYS_LINK_INIT_* enable" "-,Enabled" bitfld.long 0x00 12.--17. " RXPH0 ,Initial number of inbound posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " RXNPH0 ,Initial number of inbound non-posted header credits allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " GBIFTG ,Initial number of inbound GBIF read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l(dcr:0x80001300+0x18)&0x400)==0x00) group.long (dcr:0x80001300+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" hexmask.long.word 0x00 1.--9. 1. " FLR ,FLR acknowledge" bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" else group.long (dcr:0x80001300+0x18)++0x03 line.long 0x00 "PCIE18,PCIe Support Register 18" hexmask.long.byte 0x00 24.--31. 1. " RXPD0 ,Initial number of inbound posted data credits allocated to VC0" hexmask.long.byte 0x00 17.--23. 1. " TXPD0 ,Initial size of inbound posted data buffer tags allocated to VC0" bitfld.long 0x00 11.--16. " PCITAG ,Initial number of outbound PCI read tags allocated to VC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. " TYPE1 ,System header type 1" "Endpoint,Root complex" textfld " " bitfld.long 0x00 0. " FRCERR ,Replay buffer read port data error" "-,Error" endif group.long (dcr:0x80001300+0x19)++0x03 line.long 0x00 "PCIE19,PCIe Support Register 19" bitfld.long 0x00 31. " IDLERR ,Assert TXELECIDLE to PHY on uncorrectable error in transmit data" "-,Asserted" newline bitfld.long 0x00 30. " BLKTRN ,Block ACK/NAK TX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 29. " BLKRCV ,Block ACK/NAK RX DLLPS error injection command" "-,Blocked" bitfld.long 0x00 28. " CMD ,Error injection command" "0,1" bitfld.long 0x00 22.--27. " TYPE ,Error injection command type" ",TX B/B encoding error,,,,,,,,,,,,,,,,TX LCRC error,,Force Detection of DLPE,Force detection of FCPE,,Force detection of replay timeout error,Force detection replay roll-over,Force bad TLP detection,Force bad DLLP detection,,,,,,,,Inject TX datapath parity/ECC error,Inject RX datapath parity/ECC error,Inject control arrays parity error,Inject TX poisoned TLP,Inject RX poisoned TLP,TX ECRC error,Force detection of completion timeout,Force detection of completer abort status,Force detection of unsupported request status,Force detection of unexpected completion,Force detection of receiver overflow,Force detection of malformed TLP,Force detection of unsupported request error,Force detection of RX ECRC error,,,Inject configuration registers parity error,?..." newline rbitfld.long 0x00 21. " CMDDNE ,AL_EI_CMD pulsed" "Asserted,Pulsed" rbitfld.long 0x00 20. " WDTCFG ,Remote component is capable of link width up configuration" "-,Capable" rbitfld.long 0x00 19. " WDTCHG ,SYS_CHANGELINKWIDTH asserted" "-,Asserted" newline rbitfld.long 0x00 18. " WDTDIS ,Hardware autonomous link width up configuration capability disable" "No,Yes" rbitfld.long 0x00 17. " BAREN ,ROM region enabled by application" "0,1" bitfld.long 0x00 16. " ASYNC ,SYS_ASYNC_STABLE value" "0,1" hexmask.long.word 0x00 0.--15. 1. " FRCDCT ,Receiver detect result" group.long (dcr:0x80001300+0x20)++0x03 line.long 0x00 "PCIE1A,PCIe Support Register 1A" bitfld.long 0x00 31. " DISDET ,Link bring up sequence disable" "No,Yes" bitfld.long 0x00 30. " FRCDET ,Receiver detect results from PHY override by SYS_FORCEDETECTRESULTS" "-,Overridden" bitfld.long 0x00 24.--29. " TRGLKW ,Target link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " CHGLKW ,Link width change initialization" "-,Initialized" newline bitfld.long 0x00 22. " IMMISC ,Master hold requested" "-,Requested" bitfld.long 0x00 21. " ISMISC ,Slave hold requested" "-,Requested" rbitfld.long 0x00 20. " OSMISC ,PCIEXGPL4DDR slave idle" "-,Idle" rbitfld.long 0x00 19. " OMMISC ,PCIEXGPL4DDR master idle" "-,Idle" newline rbitfld.long 0x00 18. " RDACT ,Outbound GBIF read transaction in process" "-,In process" rbitfld.long 0x00 17. " WRACT ,Outbound GBIF write transaction in process" "-,In process" rbitfld.long 0x00 16. " REGACT ,Outbound GBIF registers transaction in process" "-,In process" width 0x0B tree.end tree.end tree "DCRRC (DCR To RCBUS Converter Module)" width 8. group.long (dcr:0x80000D00)++0x03 line.long 0x00 "ADDR,Address Register" group.long (dcr:0x80000D00+0x01)++0x03 line.long 0x00 "MSKDAT,Data Register For Read And Masked Writes" hexmask.long.word 0x00 16.--31. 1. " MASKS ,Mask" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data" group.long (dcr:0x80000D00+0x02)++0x03 line.long 0x00 "DAT,Data Register For Read And Regular Writes" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data" width 0x0B tree.end tree "ITRACE (Instruction Trace)" width 6. group.long (dcr:0x80000400)++0x03 line.long 0x00 "TC,Instruction Trace Control" bitfld.long 0x00 31. " ITE ,Instruction trace enable" "-,Enabled" bitfld.long 0x00 29.--30. " ITCT ,Instruction trace condition type" "On/Off via ITE,Single state: cond1,Two state: timeout enabled,Two state: timeout disabled" bitfld.long 0x00 28. " ITTM ,Instruction trace trigger mode" "Stop,Bank" bitfld.long 0x00 24.--27. " SS ,Trace source selection" "None,,,,PowerPC[1],PowerPC[1],PowerPC[1],PowerPC[1],,PowerPC[0],PowerPC[0],PowerPC[0],PowerPC[0]/PowerPC[1],PowerPC[0]/PowerPC[1],PowerPC[0]/PowerPC[1],PowerPC[0]/PowerPC[1]" newline bitfld.long 0x00 23. " ITIM ,Instruction trace interrupt mask" "0,1" bitfld.long 0x00 21. " ITPD ,eDRAM power down" "No,Yes" if ((per.l(dcr:0x80000400)&0x10000000)==0x10000000) group.long (dcr:0x80000400+0x01)++0x03 line.long 0x00 "TS,Instruction Trace Status" bitfld.long 0x00 31. " ITR ,Instruction trace running" "-,Running" bitfld.long 0x00 30. " ITT ,Instruction trace terminated" "-,Terminated" bitfld.long 0x00 29. " ITA1W ,Instruction trace address 1 wrapped" "-,Wrapped" newline bitfld.long 0x00 28. " ITA2W ,Instruction trace address 2 wrapped" "-,Wrapped" bitfld.long 0x00 27. " ITLBU ,Last buffer used" "BUF1,BUF2" bitfld.long 0x00 26. " ITTOO ,Timeout" "-,Timeout" else group.long (dcr:0x80000400+0x01)++0x03 line.long 0x00 "TS,Instruction Trace Status" bitfld.long 0x00 31. " ITR ,Instruction trace running" "-,Running" bitfld.long 0x00 30. " ITT ,Instruction trace terminated" "-,Terminated" bitfld.long 0x00 29. " ITA1W ,Instruction trace address 1 wrapped" "-,Wrapped" newline bitfld.long 0x00 28. " ITA2W ,Instruction trace address 2 wrapped" "-,Wrapped" textfld " " bitfld.long 0x00 26. " ITTOO ,Timeout" "-,Timeout" endif rgroup.long (dcr:0x80000400+0x02)++0x03 line.long 0x00 "TLA1,Instruction Trace Last Address 1" rgroup.long (dcr:0x80000400+0x03)++0x03 line.long 0x00 "TLA2,Instruction Trace Last Address 2" group.long (dcr:0x80000400+0x04)++0x03 line.long 0x00 "WCNT,Instruction Trace Window" group.long (dcr:0x80000400+0x05)++0x03 line.long 0x00 "CTO,Instruction Trace Condition Timeout" group.long (dcr:0x80000400+0x06)++0x03 line.long 0x00 "C1MH,Instruction Trace Cond1 MaskH" bitfld.long 0x00 31. " EE0 ,Logical AND with external event 0" "0,1" bitfld.long 0x00 30. " EE1 ,Logical AND with external event 1" "0,1" hexmask.long.word 0x00 16.--29. 1. " TET0 ,Logical AND with PowerPC[0] TriggerEventType[0:13] bus" hexmask.long.word 0x00 0.--13. 1. " TET1 ,Logical AND with PowerPC[1] TriggerEventType[0:13] bus" group.long (dcr:0x80000400+0x08)++0x03 line.long 0x00 "C2MH,Instruction Trace Cond2 MaskH" bitfld.long 0x00 31. " EE0 ,Logical AND with external event 0" "0,1" bitfld.long 0x00 30. " EE1 ,Logical AND with external event 1" "0,1" hexmask.long.word 0x00 16.--29. 1. " TET0 ,Logical AND with PowerPC[0] TriggerEventType[0:13] bus" hexmask.long.word 0x00 0.--13. 1. " TET1 ,Logical AND with PowerPC[1] TriggerEventType[0:13] bus" group.long (dcr:0x80000400+0x0A)++0x03 line.long 0x00 "ITAI,Instruction Trace Array Indirect" group.long (dcr:0x80000400+0x0B)++0x03 line.long 0x00 "ITAD,Instruction Trace Array Data" width 0x0B tree.end tree.open "LTRACE (Logic Trace)" tree "LTRACE0" width 7. group.long (dcr:0x80000500)++0x03 line.long 0x00 "TC,Logic Trace Control" bitfld.long 0x00 31. " LTE ,Logic trace enable" "-,Enabled" bitfld.long 0x00 29.--30. " LTCT ,Logic trace condition type" ",Single state,Two state: timeout enabled,Two state: timeout disabled" bitfld.long 0x00 28. " LTTM ,Logic trace trigger mode" "Stop,Bank" bitfld.long 0x00 27. " LTCM ,Logic trace compression mode" "No compression,Compression" newline bitfld.long 0x00 24.--26. " COND1OR ,Cond1 condition composition" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " COND2OR ,Cond2 condition composition" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " COND3OR ,Cond3 condition composition" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " LAPD ,Logic array power down" "No,Yes" newline bitfld.long 0x00 15. " C1IN[0] ,Cond1 CondComp1 input invert" "-,Inverted" bitfld.long 0x00 14. " C1IN[1] ,Cond1 CondComp2 input invert" "-,Inverted" bitfld.long 0x00 13. " C1IN[2] ,Cond1 CondComp3 input invert" "-,Inverted" bitfld.long 0x00 12. " C1IN[3] ,Cond1 logical OR output as Cond1 invert" "-,Inverted" newline bitfld.long 0x00 11. " C2IN[0] ,Cond2 CondComp1 input invert" "-,Inverted" bitfld.long 0x00 10. " C2IN[1] ,Cond2 CondComp2 input invert" "-,Inverted" bitfld.long 0x00 9. " C2IN[2] ,Cond2 CondComp3 input invert" "-,Inverted" bitfld.long 0x00 8. " C2IN[3] ,Cond2 logical OR output as Cond2 invert" "-,Inverted" newline bitfld.long 0x00 7. " C3IN[0] ,Cond3 CondComp1 input invert" "-,Inverted" bitfld.long 0x00 6. " C3IN[1] ,Cond3 CondComp2 input invert" "-,Inverted" bitfld.long 0x00 5. " C3IN[2] ,Cond3 CondComp3 input invert" "-,Inverted" bitfld.long 0x00 4. " C3IN[3] ,Cond3 logical OR output as Cond3 invert" "-,Inverted" newline bitfld.long 0x00 1. " LTCSM ,Logic trace complete as stop" "No,Yes" bitfld.long 0x00 0. " LTCEN ,Logic trace complete enable" "-,Enabled" if ((per.l(dcr:0x80000500)&0x10000000)==0x10000000) group.long (dcr:0x80000500+0x01)++0x03 line.long 0x00 "TS,Logic Trace Status" bitfld.long 0x00 31. " LTR ,Logic trace running" "-,Running" bitfld.long 0x00 30. " LTC ,Logic trace terminated" "-,Terminated" bitfld.long 0x00 29. " LTA1W ,Logic trace address 1 wrapped" "-,Wrapped" newline bitfld.long 0x00 28. " LTA21 ,Logic trace address 2 wrapped" "-,Wrapped" bitfld.long 0x00 27. " LBU ,Last buffer used" "BUF1,BUF2" bitfld.long 0x00 26. " TO ,Timeout" "-,Timeout" else group.long (dcr:0x80000500+0x01)++0x03 line.long 0x00 "TS,Logic Trace Status" bitfld.long 0x00 31. " LTR ,Logic trace running" "-,Running" bitfld.long 0x00 30. " LTC ,Logic trace terminated" "-,Terminated" bitfld.long 0x00 29. " LTA1W ,Logic trace address 1 wrapped" "-,Wrapped" newline bitfld.long 0x00 28. " LTA21 ,Logic trace address 2 wrapped" "-,Wrapped" textfld " " bitfld.long 0x00 26. " TO ,Timeout" "-,Timeout" endif rgroup.long (dcr:0x80000500+0x02)++0x03 line.long 0x00 "LA1,Logic Trace Last Address 1" rgroup.long (dcr:0x80000500+0x03)++0x03 line.long 0x00 "LA2,Logic Trace Last Address 2" group.long (dcr:0x80000500+0x04)++0x03 line.long 0x00 "WC,Logic Trace Window Count" group.long (dcr:0x80000500+0x05)++0x03 line.long 0x00 "CT,Logic Trace Condition Timeout" group.long (dcr:0x80000500+0x6)++0x03 line.long 0x00 "CC1PH,Logic Trace CondComp1 PolarityH" group.long (dcr:0x80000500+0x6+0x01)++0x03 line.long 0x00 "CC1PL,Logic Trace CondComp1 PolarityL" group.long (dcr:0x80000500+0x6+0x02)++0x03 line.long 0x00 "CC1MH,Logic Trace CondComp1 MaskH" group.long (dcr:0x80000500+0x6+0x03)++0x03 line.long 0x00 "CC1ML,Logic Trace CondComp1 MaskL" group.long (dcr:0x80000500+0xA)++0x03 line.long 0x00 "CC2PH,Logic Trace CondComp2 PolarityH" group.long (dcr:0x80000500+0xA+0x01)++0x03 line.long 0x00 "CC2PL,Logic Trace CondComp2 PolarityL" group.long (dcr:0x80000500+0xA+0x02)++0x03 line.long 0x00 "CC2MH,Logic Trace CondComp2 MaskH" group.long (dcr:0x80000500+0xA+0x03)++0x03 line.long 0x00 "CC2ML,Logic Trace CondComp2 MaskL" group.long (dcr:0x80000500+0xE)++0x03 line.long 0x00 "CC3PH,Logic Trace CondComp3 PolarityH" group.long (dcr:0x80000500+0xE+0x01)++0x03 line.long 0x00 "CC3PL,Logic Trace CondComp3 PolarityL" group.long (dcr:0x80000500+0xE+0x02)++0x03 line.long 0x00 "CC3MH,Logic Trace CondComp3 MaskH" group.long (dcr:0x80000500+0xE+0x03)++0x03 line.long 0x00 "CC3ML,Logic Trace CondComp3 MaskL" group.long (dcr:0x80000500+0x12)++0x03 line.long 0x00 "CMH,Logic Trace Compression MaskH" group.long (dcr:0x80000500+0x13)++0x03 line.long 0x00 "CML,Logic Trace Compression MaskL" group.long (dcr:0x80000500+0x14)++0x03 line.long 0x00 "AI,Logic Trace Array Indirect" bitfld.long 0x00 30.--31. " LTAI ,Data bits to read" "[0:31],[32:63],[64:71],?..." hexmask.long.byte 0x00 0.--7. 0x01 " INADR ,Read/write indirect address" group.long (dcr:0x80000500+0x15)++0x03 line.long 0x00 "LTAD,Logic Trace Array Data" width 0x0B tree.end tree "LTRACE1" width 7. group.long (dcr:0x80000600)++0x03 line.long 0x00 "TC,Logic Trace Control" bitfld.long 0x00 31. " LTE ,Logic trace enable" "-,Enabled" bitfld.long 0x00 29.--30. " LTCT ,Logic trace condition type" ",Single state,Two state: timeout enabled,Two state: timeout disabled" bitfld.long 0x00 28. " LTTM ,Logic trace trigger mode" "Stop,Bank" bitfld.long 0x00 27. " LTCM ,Logic trace compression mode" "No compression,Compression" newline bitfld.long 0x00 24.--26. " COND1OR ,Cond1 condition composition" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " COND2OR ,Cond2 condition composition" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " COND3OR ,Cond3 condition composition" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " LAPD ,Logic array power down" "No,Yes" newline bitfld.long 0x00 15. " C1IN[0] ,Cond1 CondComp1 input invert" "-,Inverted" bitfld.long 0x00 14. " C1IN[1] ,Cond1 CondComp2 input invert" "-,Inverted" bitfld.long 0x00 13. " C1IN[2] ,Cond1 CondComp3 input invert" "-,Inverted" bitfld.long 0x00 12. " C1IN[3] ,Cond1 logical OR output as Cond1 invert" "-,Inverted" newline bitfld.long 0x00 11. " C2IN[0] ,Cond2 CondComp1 input invert" "-,Inverted" bitfld.long 0x00 10. " C2IN[1] ,Cond2 CondComp2 input invert" "-,Inverted" bitfld.long 0x00 9. " C2IN[2] ,Cond2 CondComp3 input invert" "-,Inverted" bitfld.long 0x00 8. " C2IN[3] ,Cond2 logical OR output as Cond2 invert" "-,Inverted" newline bitfld.long 0x00 7. " C3IN[0] ,Cond3 CondComp1 input invert" "-,Inverted" bitfld.long 0x00 6. " C3IN[1] ,Cond3 CondComp2 input invert" "-,Inverted" bitfld.long 0x00 5. " C3IN[2] ,Cond3 CondComp3 input invert" "-,Inverted" bitfld.long 0x00 4. " C3IN[3] ,Cond3 logical OR output as Cond3 invert" "-,Inverted" newline bitfld.long 0x00 1. " LTCSM ,Logic trace complete as stop" "No,Yes" bitfld.long 0x00 0. " LTCEN ,Logic trace complete enable" "-,Enabled" if ((per.l(dcr:0x80000600)&0x10000000)==0x10000000) group.long (dcr:0x80000600+0x01)++0x03 line.long 0x00 "TS,Logic Trace Status" bitfld.long 0x00 31. " LTR ,Logic trace running" "-,Running" bitfld.long 0x00 30. " LTC ,Logic trace terminated" "-,Terminated" bitfld.long 0x00 29. " LTA1W ,Logic trace address 1 wrapped" "-,Wrapped" newline bitfld.long 0x00 28. " LTA21 ,Logic trace address 2 wrapped" "-,Wrapped" bitfld.long 0x00 27. " LBU ,Last buffer used" "BUF1,BUF2" bitfld.long 0x00 26. " TO ,Timeout" "-,Timeout" else group.long (dcr:0x80000600+0x01)++0x03 line.long 0x00 "TS,Logic Trace Status" bitfld.long 0x00 31. " LTR ,Logic trace running" "-,Running" bitfld.long 0x00 30. " LTC ,Logic trace terminated" "-,Terminated" bitfld.long 0x00 29. " LTA1W ,Logic trace address 1 wrapped" "-,Wrapped" newline bitfld.long 0x00 28. " LTA21 ,Logic trace address 2 wrapped" "-,Wrapped" textfld " " bitfld.long 0x00 26. " TO ,Timeout" "-,Timeout" endif rgroup.long (dcr:0x80000600+0x02)++0x03 line.long 0x00 "LA1,Logic Trace Last Address 1" rgroup.long (dcr:0x80000600+0x03)++0x03 line.long 0x00 "LA2,Logic Trace Last Address 2" group.long (dcr:0x80000600+0x04)++0x03 line.long 0x00 "WC,Logic Trace Window Count" group.long (dcr:0x80000600+0x05)++0x03 line.long 0x00 "CT,Logic Trace Condition Timeout" group.long (dcr:0x80000600+0x6)++0x03 line.long 0x00 "CC1PH,Logic Trace CondComp1 PolarityH" group.long (dcr:0x80000600+0x6+0x01)++0x03 line.long 0x00 "CC1PL,Logic Trace CondComp1 PolarityL" group.long (dcr:0x80000600+0x6+0x02)++0x03 line.long 0x00 "CC1MH,Logic Trace CondComp1 MaskH" group.long (dcr:0x80000600+0x6+0x03)++0x03 line.long 0x00 "CC1ML,Logic Trace CondComp1 MaskL" group.long (dcr:0x80000600+0xA)++0x03 line.long 0x00 "CC2PH,Logic Trace CondComp2 PolarityH" group.long (dcr:0x80000600+0xA+0x01)++0x03 line.long 0x00 "CC2PL,Logic Trace CondComp2 PolarityL" group.long (dcr:0x80000600+0xA+0x02)++0x03 line.long 0x00 "CC2MH,Logic Trace CondComp2 MaskH" group.long (dcr:0x80000600+0xA+0x03)++0x03 line.long 0x00 "CC2ML,Logic Trace CondComp2 MaskL" group.long (dcr:0x80000600+0xE)++0x03 line.long 0x00 "CC3PH,Logic Trace CondComp3 PolarityH" group.long (dcr:0x80000600+0xE+0x01)++0x03 line.long 0x00 "CC3PL,Logic Trace CondComp3 PolarityL" group.long (dcr:0x80000600+0xE+0x02)++0x03 line.long 0x00 "CC3MH,Logic Trace CondComp3 MaskH" group.long (dcr:0x80000600+0xE+0x03)++0x03 line.long 0x00 "CC3ML,Logic Trace CondComp3 MaskL" group.long (dcr:0x80000600+0x12)++0x03 line.long 0x00 "CMH,Logic Trace Compression MaskH" group.long (dcr:0x80000600+0x13)++0x03 line.long 0x00 "CML,Logic Trace Compression MaskL" group.long (dcr:0x80000600+0x14)++0x03 line.long 0x00 "AI,Logic Trace Array Indirect" bitfld.long 0x00 30.--31. " LTAI ,Data bits to read" "[0:31],[32:63],[64:71],?..." hexmask.long.byte 0x00 0.--7. 0x01 " INADR ,Read/write indirect address" group.long (dcr:0x80000600+0x15)++0x03 line.long 0x00 "LTAD,Logic Trace Array Data" width 0x0B tree.end tree.end ; tree "PPC476FP (Embedded PowerPC)" ; %include 476ibm/spr.ph spr:0x00 ; tree.end tree "P6BC (PLB6 Bus Controller)" width 14. group.long (dcr:0x80000100)++0x03 line.long 0x00 "CR0,Control Register" bitfld.long 0x00 31. " DSBS ,Disable segment boot strap" "No,Yes" bitfld.long 0x00 30. " MASK_MSRSP ,MSRSP mask" "0,1" bitfld.long 0x00 29. " MASK_SRSNZ ,SRSNZ mask" "0,1" group.long (dcr:0x80000100+0x01)++0x03 line.long 0x00 "PRI,Master Priority Register" bitfld.long 0x00 31. " M0P ,Master 0 priority level" "Low,High" bitfld.long 0x00 30. " M1P ,Master 1 priority level" "Low,High" bitfld.long 0x00 29. " M2P ,Master 2 priority level" "Low,High" bitfld.long 0x00 28. " M3P ,Master 3 priority level" "Low,High" newline bitfld.long 0x00 27. " M4P ,Master 4 priority level" "Low,High" bitfld.long 0x00 26. " M5P ,Master 5 priority level" "Low,High" bitfld.long 0x00 25. " M6P ,Master 6 priority level" "Low,High" bitfld.long 0x00 24. " M7P ,Master 7 priority level" "Low,High" newline bitfld.long 0x00 23. " M8P ,Master 8 priority level" "Low,High" bitfld.long 0x00 22. " M9P ,Master 9 priority level" "Low,High" bitfld.long 0x00 21. " M10P ,Master 10 priority level" "Low,High" bitfld.long 0x00 20. " M11P ,Master 11 priority level" "Low,High" newline bitfld.long 0x00 19. " M12P ,Master 12 priority level" "Low,High" bitfld.long 0x00 18. " M13P ,Master 13 priority level" "Low,High" bitfld.long 0x00 17. " M14P ,Master 14 priority level" "Low,High" bitfld.long 0x00 16. " M15P ,Master 15 priority level" "Low,High" rgroup.byte (dcr:0x80000100+0x02)++0x00 line.byte 0x00 "TSNOOP,TSNOOP Register" bitfld.byte 0x00 4.--7. " TSNOOP ,Bus controller TSNOOP clock count" ",,,,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,?..." group.long (dcr:0x80000100+0x03)++0x03 line.long 0x00 "PAAM_WIN_EXT,PAAM Window Extension Register" bitfld.long 0x00 30.--31. " PAAM_WIN_EXT ,Bus controller PAAM window extension" ",1 clock,2 clocks,3 clocks" group.long (dcr:0x80000100+0x4)++0x03 line.long 0x00 "SGD1,Segment Decode Register 1" hexmask.long 0x00 4.--31. 0x10 " SGD1 ,Segment 1 start address" group.long (dcr:0x80000100+0x5)++0x03 line.long 0x00 "SGD2,Segment Decode Register 2" hexmask.long 0x00 4.--31. 0x10 " SGD2 ,Segment 2 start address" group.long (dcr:0x80000100+0x6)++0x03 line.long 0x00 "SGD3,Segment Decode Register 3" hexmask.long 0x00 4.--31. 0x10 " SGD3 ,Segment 3 start address" group.long (dcr:0x80000100+0x7)++0x03 line.long 0x00 "SGD4,Segment Decode Register 4" hexmask.long 0x00 4.--31. 0x10 " SGD4 ,Segment 4 start address" group.long (dcr:0x80000100+0x8)++0x03 line.long 0x00 "SGD5,Segment Decode Register 5" hexmask.long 0x00 4.--31. 0x10 " SGD5 ,Segment 5 start address" group.long (dcr:0x80000100+0x9)++0x03 line.long 0x00 "SGD6,Segment Decode Register 6" hexmask.long 0x00 4.--31. 0x10 " SGD6 ,Segment 6 start address" group.long (dcr:0x80000100+0xA)++0x03 line.long 0x00 "SGD7,Segment Decode Register 7" hexmask.long 0x00 4.--31. 0x10 " SGD7 ,Segment 7 start address" newline if ((per.l(dcr:0x80000100+0x0B)&0xE0000000)==0xE0000000) group.long (dcr:0x80000100+0x0B)++0x03 line.long 0x00 "ERR,Error Register" bitfld.long 0x00 31. " NSRSP ,No slave response per segment" "No,Yes" bitfld.long 0x00 30. " MSRSP ,Multiple slave response per segment" "No,Yes" bitfld.long 0x00 29. " SRSNZ ,Snoopable request to segment other than zero" "No,Yes" newline bitfld.long 0x00 24.--27. " SREMID ,Slave response error master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19.--23. " SREMT ,Slave response error MTAG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " SRERD ,Slave response error read" "-,Error" bitfld.long 0x00 15.--17. " SEGID ,Slave response error read" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14. " SPVAL[0] ,Slave 0 responded to the same address" "No,Yes" bitfld.long 0x00 13. " [1] ,Slave 1 responded to the same address" "No,Yes" bitfld.long 0x00 12. " [2] ,Slave 2 responded to the same address" "No,Yes" bitfld.long 0x00 11. " [3] ,Slave 3 responded to the same address" "No,Yes" else group.long (dcr:0x80000100+0x0B)++0x03 line.long 0x00 "ERR,Error Register" bitfld.long 0x00 31. " NSRSP ,No slave response per segment" "No,Yes" bitfld.long 0x00 30. " MSRSP ,Multiple slave response per segment" "No,Yes" bitfld.long 0x00 29. " SRSNZ ,Snoopable request to segment other than zero" "No,Yes" newline newline bitfld.long 0x00 14. " SPVAL[0] ,Slave 0 responded to the same address" "No,Yes" bitfld.long 0x00 13. " [1] ,Slave 1 responded to the same address" "No,Yes" bitfld.long 0x00 12. " [2] ,Slave 2 responded to the same address" "No,Yes" bitfld.long 0x00 11. " [3] ,Slave 3 responded to the same address" "No,Yes" endif group.long (dcr:0x80000100+0x0C)++0x03 line.long 0x00 "MSRSP,Multiple Slaves Responded Register" eventfld.long 0x00 31. " S0_MSRSP[0] ,Segment 0 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 30. " [1] ,Segment 0 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 29. " [2] ,Segment 0 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 28. " [3] ,Segment 0 slave 3 multiple slaves" "No,Yes" newline eventfld.long 0x00 27. " S1_MSRSP[0] ,Segment 1 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 26. " [1] ,Segment 1 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 25. " [2] ,Segment 1 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 24. " [3] ,Segment 1 slave 3 multiple slaves" "No,Yes" newline eventfld.long 0x00 23. " S2_MSRSP[0] ,Segment 2 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 22. " [1] ,Segment 2 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 21. " [2] ,Segment 2 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 20. " [3] ,Segment 2 slave 3 multiple slaves" "No,Yes" newline eventfld.long 0x00 19. " S3_MSRSP[0] ,Segment 3 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 18. " [1] ,Segment 3 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 17. " [2] ,Segment 3 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 16. " [3] ,Segment 3 slave 3 multiple slaves" "No,Yes" newline eventfld.long 0x00 15. " S4_MSRSP[0] ,Segment 4 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 14. " [1] ,Segment 4 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 13. " [2] ,Segment 4 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 12. " [3] ,Segment 4 slave 3 multiple slaves" "No,Yes" newline eventfld.long 0x00 11. " S5_MSRSP[0] ,Segment 5 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 10. " [1] ,Segment 5 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 9. " [2] ,Segment 5 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 8. " [3] ,Segment 5 slave 3 multiple slaves" "No,Yes" newline eventfld.long 0x00 7. " S6_MSRSP[0] ,Segment 6 slave 0 multiple slaves" "No,Yes" eventfld.long 0x00 6. " [1] ,Segment 6 slave 1 multiple slaves" "No,Yes" eventfld.long 0x00 5. " [2] ,Segment 6 slave 2 multiple slaves" "No,Yes" eventfld.long 0x00 4. " [3] ,Segment 6 slave 3 multiple slaves" "No,Yes" group.long (dcr:0x80000100+0x0D)++0x03 line.long 0x00 "HCPP,Hang Count Pulse Period Register" hexmask.long 0x00 0.--25. 1. " HCCP ,Clock count pulse interval" group.long (dcr:0x80000100+0x0E)++0x03 line.long 0x00 "HD,Hang Detected Status Register" eventfld.long 0x00 31. " HD[0] ,Master 0 hang detected" "-,Detected" eventfld.long 0x00 30. " [1] ,Master 1 hang detected" "-,Detected" eventfld.long 0x00 29. " [2] ,Master 2 hang detected" "-,Detected" eventfld.long 0x00 28. " [3] ,Master 3 hang detected" "-,Detected" newline eventfld.long 0x00 27. " [4] ,Master 4 hang detected" "-,Detected" eventfld.long 0x00 26. " [5] ,Master 5 hang detected" "-,Detected" eventfld.long 0x00 25. " [6] ,Master 6 hang detected" "-,Detected" eventfld.long 0x00 24. " [7] ,Master 7 hang detected" "-,Detected" newline eventfld.long 0x00 23. " [8] ,Master 8 hang detected" "-,Detected" eventfld.long 0x00 22. " [9] ,Master 9 hang detected" "-,Detected" eventfld.long 0x00 21. " [10] ,Master 10 hang detected" "-,Detected" eventfld.long 0x00 20. " [11] ,Master 11 hang detected" "-,Detected" newline eventfld.long 0x00 19. " [12] ,Master 12 hang detected" "-,Detected" eventfld.long 0x00 18. " [13] ,Master 13 hang detected" "-,Detected" eventfld.long 0x00 17. " [14] ,Master 14 hang detected" "-,Detected" eventfld.long 0x00 16. " [15] ,Master 15 hang detected" "-,Detected" group.long (dcr:0x80000100+0x0F)++0x03 line.long 0x00 "QD,Quiesce Status" eventfld.long 0x00 31. " QD[0] ,Master 0 quiesce detected" "-,Detected" eventfld.long 0x00 30. " [1] ,Master 1 quiesce detected" "-,Detected" eventfld.long 0x00 29. " [2] ,Master 2 quiesce detected" "-,Detected" eventfld.long 0x00 28. " [3] ,Master 3 quiesce detected" "-,Detected" newline eventfld.long 0x00 27. " [4] ,Master 4 quiesce detected" "-,Detected" eventfld.long 0x00 26. " [5] ,Master 5 quiesce detected" "-,Detected" eventfld.long 0x00 25. " [6] ,Master 6 quiesce detected" "-,Detected" eventfld.long 0x00 24. " [7] ,Master 7 quiesce detected" "-,Detected" newline eventfld.long 0x00 23. " [8] ,Master 8 quiesce detected" "-,Detected" eventfld.long 0x00 22. " [9] ,Master 9 quiesce detected" "-,Detected" eventfld.long 0x00 21. " [10] ,Master 10 quiesce detected" "-,Detected" eventfld.long 0x00 20. " [11] ,Master 11 quiesce detected" "-,Detected" newline eventfld.long 0x00 19. " [12] ,Master 12 quiesce detected" "-,Detected" eventfld.long 0x00 18. " [13] ,Master 13 quiesce detected" "-,Detected" eventfld.long 0x00 17. " [14] ,Master 14 quiesce detected" "-,Detected" eventfld.long 0x00 16. " [15] ,Master 15 quiesce detected" "-,Detected" group.long (dcr:0x80000100+0x10)++0x03 line.long 0x00 "SHD,System Hung Detected Status Register" eventfld.long 0x00 31. " SHD[0] ,Master 0 system hung detected" "-,Detected" eventfld.long 0x00 30. " [1] ,Master 1 system hung detected" "-,Detected" eventfld.long 0x00 29. " [2] ,Master 2 system hung detected" "-,Detected" eventfld.long 0x00 28. " [3] ,Master 3 system hung detected" "-,Detected" newline eventfld.long 0x00 27. " [4] ,Master 4 system hung detected" "-,Detected" eventfld.long 0x00 26. " [5] ,Master 5 system hung detected" "-,Detected" eventfld.long 0x00 25. " [6] ,Master 6 system hung detected" "-,Detected" eventfld.long 0x00 24. " [7] ,Master 7 system hung detected" "-,Detected" newline eventfld.long 0x00 23. " [8] ,Master 8 system hung detected" "-,Detected" eventfld.long 0x00 22. " [9] ,Master 9 system hung detected" "-,Detected" eventfld.long 0x00 21. " [10] ,Master 10 system hung detected" "-,Detected" eventfld.long 0x00 20. " [11] ,Master 11 system hung detected" "-,Detected" newline eventfld.long 0x00 19. " [12] ,Master 12 system hung detected" "-,Detected" eventfld.long 0x00 18. " [13] ,Master 13 system hung detected" "-,Detected" eventfld.long 0x00 17. " [14] ,Master 14 system hung detected" "-,Detected" eventfld.long 0x00 16. " [15] ,Master 15 system hung detected" "-,Detected" rgroup.long (dcr:0x80000100+0x11)++0x03 line.long 0x00 "REVID,CoreConnect Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VNUMB ,Version number" hexmask.long.byte 0x00 0.--7. 1. " RVNUMB ,Revision number" width 0x0B tree.end tree "DCRARB4M (Device Control Register Arbiter)" width 7. group.long dcr:0x80000900++0x03 line.long 0x00 "TADDR,Translation Address Register" hexmask.long 0x00 1.--31. 0x01 " TADR ,Translation address" bitfld.long 0x00 0. " TP ,Privileged mode translation" "-,Privileged" group.long (dcr:0x80000900+0x01)++0x03 line.long 0x00 "MADDR,Match Address Register" hexmask.long 0x00 1.--31. 0x01 " MADR ,Match address" bitfld.long 0x00 0. " MP ,Privileged mode match" "-,Privileged" group.long (dcr:0x80000900+0x02)++0x03 line.long 0x00 "MASK,Match/Translation Address Mask Register" hexmask.long 0x00 1.--31. 0x01 " AMSK ,Address match mask" bitfld.long 0x00 0. " PMSK ,Privileged mode mask" "-,Privileged" group.long (dcr:0x80000900+0x03)++0x03 line.long 0x00 "DACR,DCR Arbiter Control Register" bitfld.long 0x00 31. " DPM ,DCR arbiter priority mode" "As DACR.DPO,Fair arbitration" bitfld.long 0x00 30. " LP ,DCR shared bus legacy protect" "-,Protected" bitfld.long 0x00 24.--25. " DPO ,DCR arbiter master priority order" "0 > 1 > 2 > 3,1 > 2 > 3 > 0,2 > 3 > 0 > 1,3 > 0 > 1 > 2" bitfld.long 0x00 4.--9. " TOCNT[0:5] ,Timeout counter control" "No timeout,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240,256,272,288,304,320,336,352,368,384,400,416,432,448,464,480,496,512,528,544,560,576,592,608,624,640,656,672,688,704,720,736,752,768,784,800,816,832,848,864,880,896,912,928,944,960,976,992,1008" if ((per.l(dcr:0x80000900+0x04)&0x80000000)==0x80000000) group.long (dcr:0x80000900+0x04)++0x03 line.long 0x00 "DAESR,DCR Arbiter Error Status Register" eventfld.long 0x00 31. " EV ,DCR arbiter error valid" "-,Error" bitfld.long 0x00 30. " TE ,Timeout error" "-,Error" newline bitfld.long 0x00 29. " LPE ,Legacy protect error" "-,Error" bitfld.long 0x00 24.--27. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " RW ,Read/Write indicator" "Write,Read" bitfld.long 0x00 22. " PT ,Privileged transfer" "Unprivileged,Privileged" newline bitfld.long 0x00 3. " M0E ,Master 0 error" "-,Error" bitfld.long 0x00 2. " M1E ,Master 1 error" "-,Error" bitfld.long 0x00 1. " M2E ,Master 2 error" "-,Error" bitfld.long 0x00 0. " M3E ,Master 3 error" "-,Error" rgroup.long (dcr:0x80000900+0x05)++0x03 line.long 0x00 "DAEAR,DCR Arbiter Error Address Capture Register" else group.long (dcr:0x80000900+0x04)++0x03 line.long 0x00 "DAESR,DCR Arbiter Error Status Register" eventfld.long 0x00 31. " EV ,DCR arbiter error valid" "-,Error" newline newline bitfld.long 0x00 3. " M0E ,Master 0 error" "-,Error" bitfld.long 0x00 2. " M1E ,Master 1 error" "-,Error" bitfld.long 0x00 1. " M2E ,Master 2 error" "-,Error" bitfld.long 0x00 0. " M3E ,Master 3 error" "-,Error" hgroup.long (dcr:0x80000900+0x05)++0x03 hide.long 0x00 "DAEAR,DCR Arbiter Error Address Capture Register" endif group.long (dcr:0x80000900+0x06)++0x03 line.long 0x00 "DASMR,DCR Semaphore Register" bitfld.long 0x00 31. " SV ,Semaphore valid" "-,Valid" bitfld.long 0x00 0.--3. " SMID ,Current semaphore owner master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (dcr:0x80000900+0x07)++0x03 line.long 0x00 "REVID,Core Revision ID" hexmask.long.word 0x00 8.--19. 1. " RN ,Revision number" hexmask.long.byte 0x00 0.--7. 1. " BRN ,Branch revision number" width 0x0B tree.end tree "MPIC128 (Multiprocessor Interrupt Controller)" width 8. tree "Interrupt Source Configuration Registers" group.long (dcr:0xFFC00000+0x10000)++0x03 line.long 0x00 "VP0 ,Vector/Priority Register 0 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10000+0x10)++0x03 line.long 0x00 "DST0 ,Destination Register 0 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10020)++0x03 line.long 0x00 "VP1 ,Vector/Priority Register 1 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10020+0x10)++0x03 line.long 0x00 "DST1 ,Destination Register 1 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10040)++0x03 line.long 0x00 "VP2 ,Vector/Priority Register 2 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10040+0x10)++0x03 line.long 0x00 "DST2 ,Destination Register 2 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10060)++0x03 line.long 0x00 "VP3 ,Vector/Priority Register 3 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10060+0x10)++0x03 line.long 0x00 "DST3 ,Destination Register 3 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10080)++0x03 line.long 0x00 "VP4 ,Vector/Priority Register 4 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10080+0x10)++0x03 line.long 0x00 "DST4 ,Destination Register 4 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x100A0)++0x03 line.long 0x00 "VP5 ,Vector/Priority Register 5 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x100A0+0x10)++0x03 line.long 0x00 "DST5 ,Destination Register 5 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x100C0)++0x03 line.long 0x00 "VP6 ,Vector/Priority Register 6 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x100C0+0x10)++0x03 line.long 0x00 "DST6 ,Destination Register 6 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x100E0)++0x03 line.long 0x00 "VP7 ,Vector/Priority Register 7 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x100E0+0x10)++0x03 line.long 0x00 "DST7 ,Destination Register 7 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10100)++0x03 line.long 0x00 "VP8 ,Vector/Priority Register 8 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10100+0x10)++0x03 line.long 0x00 "DST8 ,Destination Register 8 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10120)++0x03 line.long 0x00 "VP9 ,Vector/Priority Register 9 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10120+0x10)++0x03 line.long 0x00 "DST9 ,Destination Register 9 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10140)++0x03 line.long 0x00 "VP10 ,Vector/Priority Register 10 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10140+0x10)++0x03 line.long 0x00 "DST10 ,Destination Register 10 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10160)++0x03 line.long 0x00 "VP11 ,Vector/Priority Register 11 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10160+0x10)++0x03 line.long 0x00 "DST11 ,Destination Register 11 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10180)++0x03 line.long 0x00 "VP12 ,Vector/Priority Register 12 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10180+0x10)++0x03 line.long 0x00 "DST12 ,Destination Register 12 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x101A0)++0x03 line.long 0x00 "VP13 ,Vector/Priority Register 13 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x101A0+0x10)++0x03 line.long 0x00 "DST13 ,Destination Register 13 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x101C0)++0x03 line.long 0x00 "VP14 ,Vector/Priority Register 14 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x101C0+0x10)++0x03 line.long 0x00 "DST14 ,Destination Register 14 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x101E0)++0x03 line.long 0x00 "VP15 ,Vector/Priority Register 15 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x101E0+0x10)++0x03 line.long 0x00 "DST15 ,Destination Register 15 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10200)++0x03 line.long 0x00 "VP16 ,Vector/Priority Register 16 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10200+0x10)++0x03 line.long 0x00 "DST16 ,Destination Register 16 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10220)++0x03 line.long 0x00 "VP17 ,Vector/Priority Register 17 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10220+0x10)++0x03 line.long 0x00 "DST17 ,Destination Register 17 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10240)++0x03 line.long 0x00 "VP18 ,Vector/Priority Register 18 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10240+0x10)++0x03 line.long 0x00 "DST18 ,Destination Register 18 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10260)++0x03 line.long 0x00 "VP19 ,Vector/Priority Register 19 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10260+0x10)++0x03 line.long 0x00 "DST19 ,Destination Register 19 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10280)++0x03 line.long 0x00 "VP20 ,Vector/Priority Register 20 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10280+0x10)++0x03 line.long 0x00 "DST20 ,Destination Register 20 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x102A0)++0x03 line.long 0x00 "VP21 ,Vector/Priority Register 21 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x102A0+0x10)++0x03 line.long 0x00 "DST21 ,Destination Register 21 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x102C0)++0x03 line.long 0x00 "VP22 ,Vector/Priority Register 22 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x102C0+0x10)++0x03 line.long 0x00 "DST22 ,Destination Register 22 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x102E0)++0x03 line.long 0x00 "VP23 ,Vector/Priority Register 23 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x102E0+0x10)++0x03 line.long 0x00 "DST23 ,Destination Register 23 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10300)++0x03 line.long 0x00 "VP24 ,Vector/Priority Register 24 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10300+0x10)++0x03 line.long 0x00 "DST24 ,Destination Register 24 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10320)++0x03 line.long 0x00 "VP25 ,Vector/Priority Register 25 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10320+0x10)++0x03 line.long 0x00 "DST25 ,Destination Register 25 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10340)++0x03 line.long 0x00 "VP26 ,Vector/Priority Register 26 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10340+0x10)++0x03 line.long 0x00 "DST26 ,Destination Register 26 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10360)++0x03 line.long 0x00 "VP27 ,Vector/Priority Register 27 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10360+0x10)++0x03 line.long 0x00 "DST27 ,Destination Register 27 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10380)++0x03 line.long 0x00 "VP28 ,Vector/Priority Register 28 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10380+0x10)++0x03 line.long 0x00 "DST28 ,Destination Register 28 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x103A0)++0x03 line.long 0x00 "VP29 ,Vector/Priority Register 29 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x103A0+0x10)++0x03 line.long 0x00 "DST29 ,Destination Register 29 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x103C0)++0x03 line.long 0x00 "VP30 ,Vector/Priority Register 30 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x103C0+0x10)++0x03 line.long 0x00 "DST30 ,Destination Register 30 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x103E0)++0x03 line.long 0x00 "VP31 ,Vector/Priority Register 31 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x103E0+0x10)++0x03 line.long 0x00 "DST31 ,Destination Register 31 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10400)++0x03 line.long 0x00 "VP32 ,Vector/Priority Register 32 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10400+0x10)++0x03 line.long 0x00 "DST32 ,Destination Register 32 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10420)++0x03 line.long 0x00 "VP33 ,Vector/Priority Register 33 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10420+0x10)++0x03 line.long 0x00 "DST33 ,Destination Register 33 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10440)++0x03 line.long 0x00 "VP34 ,Vector/Priority Register 34 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10440+0x10)++0x03 line.long 0x00 "DST34 ,Destination Register 34 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10460)++0x03 line.long 0x00 "VP35 ,Vector/Priority Register 35 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10460+0x10)++0x03 line.long 0x00 "DST35 ,Destination Register 35 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10480)++0x03 line.long 0x00 "VP36 ,Vector/Priority Register 36 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10480+0x10)++0x03 line.long 0x00 "DST36 ,Destination Register 36 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x104A0)++0x03 line.long 0x00 "VP37 ,Vector/Priority Register 37 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x104A0+0x10)++0x03 line.long 0x00 "DST37 ,Destination Register 37 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x104C0)++0x03 line.long 0x00 "VP38 ,Vector/Priority Register 38 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x104C0+0x10)++0x03 line.long 0x00 "DST38 ,Destination Register 38 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x104E0)++0x03 line.long 0x00 "VP39 ,Vector/Priority Register 39 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x104E0+0x10)++0x03 line.long 0x00 "DST39 ,Destination Register 39 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10500)++0x03 line.long 0x00 "VP40 ,Vector/Priority Register 40 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10500+0x10)++0x03 line.long 0x00 "DST40 ,Destination Register 40 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10520)++0x03 line.long 0x00 "VP41 ,Vector/Priority Register 41 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10520+0x10)++0x03 line.long 0x00 "DST41 ,Destination Register 41 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10540)++0x03 line.long 0x00 "VP42 ,Vector/Priority Register 42 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10540+0x10)++0x03 line.long 0x00 "DST42 ,Destination Register 42 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10560)++0x03 line.long 0x00 "VP43 ,Vector/Priority Register 43 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10560+0x10)++0x03 line.long 0x00 "DST43 ,Destination Register 43 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10580)++0x03 line.long 0x00 "VP44 ,Vector/Priority Register 44 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10580+0x10)++0x03 line.long 0x00 "DST44 ,Destination Register 44 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x105A0)++0x03 line.long 0x00 "VP45 ,Vector/Priority Register 45 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x105A0+0x10)++0x03 line.long 0x00 "DST45 ,Destination Register 45 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x105C0)++0x03 line.long 0x00 "VP46 ,Vector/Priority Register 46 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x105C0+0x10)++0x03 line.long 0x00 "DST46 ,Destination Register 46 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x105E0)++0x03 line.long 0x00 "VP47 ,Vector/Priority Register 47 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x105E0+0x10)++0x03 line.long 0x00 "DST47 ,Destination Register 47 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10600)++0x03 line.long 0x00 "VP48 ,Vector/Priority Register 48 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10600+0x10)++0x03 line.long 0x00 "DST48 ,Destination Register 48 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10620)++0x03 line.long 0x00 "VP49 ,Vector/Priority Register 49 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10620+0x10)++0x03 line.long 0x00 "DST49 ,Destination Register 49 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10640)++0x03 line.long 0x00 "VP50 ,Vector/Priority Register 50 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10640+0x10)++0x03 line.long 0x00 "DST50 ,Destination Register 50 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10660)++0x03 line.long 0x00 "VP51 ,Vector/Priority Register 51 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10660+0x10)++0x03 line.long 0x00 "DST51 ,Destination Register 51 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10680)++0x03 line.long 0x00 "VP52 ,Vector/Priority Register 52 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10680+0x10)++0x03 line.long 0x00 "DST52 ,Destination Register 52 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x106A0)++0x03 line.long 0x00 "VP53 ,Vector/Priority Register 53 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x106A0+0x10)++0x03 line.long 0x00 "DST53 ,Destination Register 53 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x106C0)++0x03 line.long 0x00 "VP54 ,Vector/Priority Register 54 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x106C0+0x10)++0x03 line.long 0x00 "DST54 ,Destination Register 54 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x106E0)++0x03 line.long 0x00 "VP55 ,Vector/Priority Register 55 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x106E0+0x10)++0x03 line.long 0x00 "DST55 ,Destination Register 55 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10700)++0x03 line.long 0x00 "VP56 ,Vector/Priority Register 56 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10700+0x10)++0x03 line.long 0x00 "DST56 ,Destination Register 56 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10720)++0x03 line.long 0x00 "VP57 ,Vector/Priority Register 57 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10720+0x10)++0x03 line.long 0x00 "DST57 ,Destination Register 57 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10740)++0x03 line.long 0x00 "VP58 ,Vector/Priority Register 58 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10740+0x10)++0x03 line.long 0x00 "DST58 ,Destination Register 58 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10760)++0x03 line.long 0x00 "VP59 ,Vector/Priority Register 59 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10760+0x10)++0x03 line.long 0x00 "DST59 ,Destination Register 59 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10780)++0x03 line.long 0x00 "VP60 ,Vector/Priority Register 60 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10780+0x10)++0x03 line.long 0x00 "DST60 ,Destination Register 60 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x107A0)++0x03 line.long 0x00 "VP61 ,Vector/Priority Register 61 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x107A0+0x10)++0x03 line.long 0x00 "DST61 ,Destination Register 61 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x107C0)++0x03 line.long 0x00 "VP62 ,Vector/Priority Register 62 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x107C0+0x10)++0x03 line.long 0x00 "DST62 ,Destination Register 62 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x107E0)++0x03 line.long 0x00 "VP63 ,Vector/Priority Register 63 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x107E0+0x10)++0x03 line.long 0x00 "DST63 ,Destination Register 63 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10800)++0x03 line.long 0x00 "VP64 ,Vector/Priority Register 64 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10800+0x10)++0x03 line.long 0x00 "DST64 ,Destination Register 64 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10820)++0x03 line.long 0x00 "VP65 ,Vector/Priority Register 65 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10820+0x10)++0x03 line.long 0x00 "DST65 ,Destination Register 65 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10840)++0x03 line.long 0x00 "VP66 ,Vector/Priority Register 66 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10840+0x10)++0x03 line.long 0x00 "DST66 ,Destination Register 66 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10860)++0x03 line.long 0x00 "VP67 ,Vector/Priority Register 67 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10860+0x10)++0x03 line.long 0x00 "DST67 ,Destination Register 67 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10880)++0x03 line.long 0x00 "VP68 ,Vector/Priority Register 68 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10880+0x10)++0x03 line.long 0x00 "DST68 ,Destination Register 68 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x108A0)++0x03 line.long 0x00 "VP69 ,Vector/Priority Register 69 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x108A0+0x10)++0x03 line.long 0x00 "DST69 ,Destination Register 69 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x108C0)++0x03 line.long 0x00 "VP70 ,Vector/Priority Register 70 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x108C0+0x10)++0x03 line.long 0x00 "DST70 ,Destination Register 70 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x108E0)++0x03 line.long 0x00 "VP71 ,Vector/Priority Register 71 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x108E0+0x10)++0x03 line.long 0x00 "DST71 ,Destination Register 71 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10900)++0x03 line.long 0x00 "VP72 ,Vector/Priority Register 72 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10900+0x10)++0x03 line.long 0x00 "DST72 ,Destination Register 72 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10920)++0x03 line.long 0x00 "VP73 ,Vector/Priority Register 73 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10920+0x10)++0x03 line.long 0x00 "DST73 ,Destination Register 73 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10940)++0x03 line.long 0x00 "VP74 ,Vector/Priority Register 74 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10940+0x10)++0x03 line.long 0x00 "DST74 ,Destination Register 74 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10960)++0x03 line.long 0x00 "VP75 ,Vector/Priority Register 75 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10960+0x10)++0x03 line.long 0x00 "DST75 ,Destination Register 75 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10980)++0x03 line.long 0x00 "VP76 ,Vector/Priority Register 76 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10980+0x10)++0x03 line.long 0x00 "DST76 ,Destination Register 76 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x109A0)++0x03 line.long 0x00 "VP77 ,Vector/Priority Register 77 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x109A0+0x10)++0x03 line.long 0x00 "DST77 ,Destination Register 77 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x109C0)++0x03 line.long 0x00 "VP78 ,Vector/Priority Register 78 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x109C0+0x10)++0x03 line.long 0x00 "DST78 ,Destination Register 78 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x109E0)++0x03 line.long 0x00 "VP79 ,Vector/Priority Register 79 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x109E0+0x10)++0x03 line.long 0x00 "DST79 ,Destination Register 79 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10A00)++0x03 line.long 0x00 "VP80 ,Vector/Priority Register 80 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10A00+0x10)++0x03 line.long 0x00 "DST80 ,Destination Register 80 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10A20)++0x03 line.long 0x00 "VP81 ,Vector/Priority Register 81 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10A20+0x10)++0x03 line.long 0x00 "DST81 ,Destination Register 81 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10A40)++0x03 line.long 0x00 "VP82 ,Vector/Priority Register 82 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10A40+0x10)++0x03 line.long 0x00 "DST82 ,Destination Register 82 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10A60)++0x03 line.long 0x00 "VP83 ,Vector/Priority Register 83 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10A60+0x10)++0x03 line.long 0x00 "DST83 ,Destination Register 83 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10A80)++0x03 line.long 0x00 "VP84 ,Vector/Priority Register 84 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10A80+0x10)++0x03 line.long 0x00 "DST84 ,Destination Register 84 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10AA0)++0x03 line.long 0x00 "VP85 ,Vector/Priority Register 85 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10AA0+0x10)++0x03 line.long 0x00 "DST85 ,Destination Register 85 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10AC0)++0x03 line.long 0x00 "VP86 ,Vector/Priority Register 86 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10AC0+0x10)++0x03 line.long 0x00 "DST86 ,Destination Register 86 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10AE0)++0x03 line.long 0x00 "VP87 ,Vector/Priority Register 87 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10AE0+0x10)++0x03 line.long 0x00 "DST87 ,Destination Register 87 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10B00)++0x03 line.long 0x00 "VP88 ,Vector/Priority Register 88 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10B00+0x10)++0x03 line.long 0x00 "DST88 ,Destination Register 88 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10B20)++0x03 line.long 0x00 "VP89 ,Vector/Priority Register 89 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10B20+0x10)++0x03 line.long 0x00 "DST89 ,Destination Register 89 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10B40)++0x03 line.long 0x00 "VP90 ,Vector/Priority Register 90 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10B40+0x10)++0x03 line.long 0x00 "DST90 ,Destination Register 90 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10B60)++0x03 line.long 0x00 "VP91 ,Vector/Priority Register 91 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10B60+0x10)++0x03 line.long 0x00 "DST91 ,Destination Register 91 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10B80)++0x03 line.long 0x00 "VP92 ,Vector/Priority Register 92 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10B80+0x10)++0x03 line.long 0x00 "DST92 ,Destination Register 92 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10BA0)++0x03 line.long 0x00 "VP93 ,Vector/Priority Register 93 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10BA0+0x10)++0x03 line.long 0x00 "DST93 ,Destination Register 93 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10BC0)++0x03 line.long 0x00 "VP94 ,Vector/Priority Register 94 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10BC0+0x10)++0x03 line.long 0x00 "DST94 ,Destination Register 94 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10BE0)++0x03 line.long 0x00 "VP95 ,Vector/Priority Register 95 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10BE0+0x10)++0x03 line.long 0x00 "DST95 ,Destination Register 95 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10C00)++0x03 line.long 0x00 "VP96 ,Vector/Priority Register 96 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10C00+0x10)++0x03 line.long 0x00 "DST96 ,Destination Register 96 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10C20)++0x03 line.long 0x00 "VP97 ,Vector/Priority Register 97 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10C20+0x10)++0x03 line.long 0x00 "DST97 ,Destination Register 97 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10C40)++0x03 line.long 0x00 "VP98 ,Vector/Priority Register 98 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10C40+0x10)++0x03 line.long 0x00 "DST98 ,Destination Register 98 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10C60)++0x03 line.long 0x00 "VP99 ,Vector/Priority Register 99 " bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10C60+0x10)++0x03 line.long 0x00 "DST99 ,Destination Register 99 " bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10C80)++0x03 line.long 0x00 "VP100,Vector/Priority Register 100" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10C80+0x10)++0x03 line.long 0x00 "DST100,Destination Register 100" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10CA0)++0x03 line.long 0x00 "VP101,Vector/Priority Register 101" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10CA0+0x10)++0x03 line.long 0x00 "DST101,Destination Register 101" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10CC0)++0x03 line.long 0x00 "VP102,Vector/Priority Register 102" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10CC0+0x10)++0x03 line.long 0x00 "DST102,Destination Register 102" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10CE0)++0x03 line.long 0x00 "VP103,Vector/Priority Register 103" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10CE0+0x10)++0x03 line.long 0x00 "DST103,Destination Register 103" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10D00)++0x03 line.long 0x00 "VP104,Vector/Priority Register 104" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10D00+0x10)++0x03 line.long 0x00 "DST104,Destination Register 104" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10D20)++0x03 line.long 0x00 "VP105,Vector/Priority Register 105" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10D20+0x10)++0x03 line.long 0x00 "DST105,Destination Register 105" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10D40)++0x03 line.long 0x00 "VP106,Vector/Priority Register 106" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10D40+0x10)++0x03 line.long 0x00 "DST106,Destination Register 106" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10D60)++0x03 line.long 0x00 "VP107,Vector/Priority Register 107" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10D60+0x10)++0x03 line.long 0x00 "DST107,Destination Register 107" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10D80)++0x03 line.long 0x00 "VP108,Vector/Priority Register 108" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10D80+0x10)++0x03 line.long 0x00 "DST108,Destination Register 108" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10DA0)++0x03 line.long 0x00 "VP109,Vector/Priority Register 109" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10DA0+0x10)++0x03 line.long 0x00 "DST109,Destination Register 109" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10DC0)++0x03 line.long 0x00 "VP110,Vector/Priority Register 110" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10DC0+0x10)++0x03 line.long 0x00 "DST110,Destination Register 110" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10DE0)++0x03 line.long 0x00 "VP111,Vector/Priority Register 111" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10DE0+0x10)++0x03 line.long 0x00 "DST111,Destination Register 111" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10E00)++0x03 line.long 0x00 "VP112,Vector/Priority Register 112" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10E00+0x10)++0x03 line.long 0x00 "DST112,Destination Register 112" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10E20)++0x03 line.long 0x00 "VP113,Vector/Priority Register 113" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10E20+0x10)++0x03 line.long 0x00 "DST113,Destination Register 113" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10E40)++0x03 line.long 0x00 "VP114,Vector/Priority Register 114" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10E40+0x10)++0x03 line.long 0x00 "DST114,Destination Register 114" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10E60)++0x03 line.long 0x00 "VP115,Vector/Priority Register 115" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10E60+0x10)++0x03 line.long 0x00 "DST115,Destination Register 115" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10E80)++0x03 line.long 0x00 "VP116,Vector/Priority Register 116" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10E80+0x10)++0x03 line.long 0x00 "DST116,Destination Register 116" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10EA0)++0x03 line.long 0x00 "VP117,Vector/Priority Register 117" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10EA0+0x10)++0x03 line.long 0x00 "DST117,Destination Register 117" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10EC0)++0x03 line.long 0x00 "VP118,Vector/Priority Register 118" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10EC0+0x10)++0x03 line.long 0x00 "DST118,Destination Register 118" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10EE0)++0x03 line.long 0x00 "VP119,Vector/Priority Register 119" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10EE0+0x10)++0x03 line.long 0x00 "DST119,Destination Register 119" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10F00)++0x03 line.long 0x00 "VP120,Vector/Priority Register 120" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10F00+0x10)++0x03 line.long 0x00 "DST120,Destination Register 120" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10F20)++0x03 line.long 0x00 "VP121,Vector/Priority Register 121" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10F20+0x10)++0x03 line.long 0x00 "DST121,Destination Register 121" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10F40)++0x03 line.long 0x00 "VP122,Vector/Priority Register 122" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10F40+0x10)++0x03 line.long 0x00 "DST122,Destination Register 122" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10F60)++0x03 line.long 0x00 "VP123,Vector/Priority Register 123" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10F60+0x10)++0x03 line.long 0x00 "DST123,Destination Register 123" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10F80)++0x03 line.long 0x00 "VP124,Vector/Priority Register 124" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10F80+0x10)++0x03 line.long 0x00 "DST124,Destination Register 124" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10FA0)++0x03 line.long 0x00 "VP125,Vector/Priority Register 125" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10FA0+0x10)++0x03 line.long 0x00 "DST125,Destination Register 125" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10FC0)++0x03 line.long 0x00 "VP126,Vector/Priority Register 126" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10FC0+0x10)++0x03 line.long 0x00 "DST126,Destination Register 126" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" group.long (dcr:0xFFC00000+0x10FE0)++0x03 line.long 0x00 "VP127,Vector/Priority Register 127" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 23. " POL ,Polarity select" "Low/Negative edge,High/Positive edge" bitfld.long 0x00 22. " S ,Sense select" "Edge,Level" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10FE0+0x10)++0x03 line.long 0x00 "DST127,Destination Register 127" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt source" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt source" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt source" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt source" "No,Yes" tree.end tree "Per Processor Registers" tree "P0" wsgroup.long (dcr:0xFFC00000+0x0+0x20040)++0x03 dcr:0xFFC00000 line.long 0x00 "IPID0,Inter Processor Interrupt Dispatch 0" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x0+0x20050)++0x03 line.long 0x00 "IPID1,Inter Processor Interrupt Dispatch 1" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x0+0x20060)++0x03 line.long 0x00 "IPID2,Inter Processor Interrupt Dispatch 2" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x0+0x20070)++0x03 line.long 0x00 "IPID3,Inter Processor Interrupt Dispatch 3" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" group.long (dcr:0xFFC00000+0x0+0x20080)++0x03 line.long 0x00 "CTP0,Current Task Priority Register 0" bitfld.long 0x00 0.--3. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" rgroup.long (dcr:0xFFC00000+0x0+0x20090)++0x03 line.long 0x00 "WAI0,Who Am I Register 0" bitfld.long 0x00 0.--1. " ID ,Processor ID" "0,1,2,3" hgroup.long (dcr:0xFFC00000+0x0+0x200A0)++0x03 hide.long 0x00 "NCIAR0,Non Critical Interrupt Acknowledge Register 0" in hgroup.long (dcr:0xFFC00000+0x0+0x200C0)++0x03 hide.long 0x00 "CIAR0,Critical Interrupt Acknowledge Register 0" in hgroup.long (dcr:0xFFC00000+0x0+0x200E0)++0x03 hide.long 0x00 "MCIAR0,Machine Check Interrupt Acknowledge Register 0" in group.long (dcr:0xFFC00000+0x0+0x200B0)++0x03 line.long 0x00 "NCEOI0,Non Critical End Of Interrupt Register 0" group.long (dcr:0xFFC00000+0x0+0x200D0)++0x03 line.long 0x00 "CEOI0,Critical End Of Interrupt Register 0" group.long (dcr:0xFFC00000+0x0+0x200F0)++0x03 line.long 0x00 "MCEOI0,Machine Check End Of Interrupt Register 0" tree.end tree "P1" wsgroup.long (dcr:0xFFC00000+0x1000+0x20040)++0x03 dcr:0xFFC00000 line.long 0x00 "IPID0,Inter Processor Interrupt Dispatch 0" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x1000+0x20050)++0x03 line.long 0x00 "IPID1,Inter Processor Interrupt Dispatch 1" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x1000+0x20060)++0x03 line.long 0x00 "IPID2,Inter Processor Interrupt Dispatch 2" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x1000+0x20070)++0x03 line.long 0x00 "IPID3,Inter Processor Interrupt Dispatch 3" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" group.long (dcr:0xFFC00000+0x1000+0x20080)++0x03 line.long 0x00 "CTP1,Current Task Priority Register 1" bitfld.long 0x00 0.--3. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" rgroup.long (dcr:0xFFC00000+0x1000+0x20090)++0x03 line.long 0x00 "WAI1,Who Am I Register 1" bitfld.long 0x00 0.--1. " ID ,Processor ID" "0,1,2,3" hgroup.long (dcr:0xFFC00000+0x1000+0x200A0)++0x03 hide.long 0x00 "NCIAR1,Non Critical Interrupt Acknowledge Register 1" in hgroup.long (dcr:0xFFC00000+0x1000+0x200C0)++0x03 hide.long 0x00 "CIAR1,Critical Interrupt Acknowledge Register 1" in hgroup.long (dcr:0xFFC00000+0x1000+0x200E0)++0x03 hide.long 0x00 "MCIAR1,Machine Check Interrupt Acknowledge Register 1" in group.long (dcr:0xFFC00000+0x1000+0x200B0)++0x03 line.long 0x00 "NCEOI1,Non Critical End Of Interrupt Register 1" group.long (dcr:0xFFC00000+0x1000+0x200D0)++0x03 line.long 0x00 "CEOI1,Critical End Of Interrupt Register 1" group.long (dcr:0xFFC00000+0x1000+0x200F0)++0x03 line.long 0x00 "MCEOI1,Machine Check End Of Interrupt Register 1" tree.end tree "P2" wsgroup.long (dcr:0xFFC00000+0x2000+0x20040)++0x03 dcr:0xFFC00000 line.long 0x00 "IPID0,Inter Processor Interrupt Dispatch 0" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x2000+0x20050)++0x03 line.long 0x00 "IPID1,Inter Processor Interrupt Dispatch 1" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x2000+0x20060)++0x03 line.long 0x00 "IPID2,Inter Processor Interrupt Dispatch 2" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x2000+0x20070)++0x03 line.long 0x00 "IPID3,Inter Processor Interrupt Dispatch 3" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" group.long (dcr:0xFFC00000+0x2000+0x20080)++0x03 line.long 0x00 "CTP2,Current Task Priority Register 2" bitfld.long 0x00 0.--3. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" rgroup.long (dcr:0xFFC00000+0x2000+0x20090)++0x03 line.long 0x00 "WAI2,Who Am I Register 2" bitfld.long 0x00 0.--1. " ID ,Processor ID" "0,1,2,3" hgroup.long (dcr:0xFFC00000+0x2000+0x200A0)++0x03 hide.long 0x00 "NCIAR2,Non Critical Interrupt Acknowledge Register 2" in hgroup.long (dcr:0xFFC00000+0x2000+0x200C0)++0x03 hide.long 0x00 "CIAR2,Critical Interrupt Acknowledge Register 2" in hgroup.long (dcr:0xFFC00000+0x2000+0x200E0)++0x03 hide.long 0x00 "MCIAR2,Machine Check Interrupt Acknowledge Register 2" in group.long (dcr:0xFFC00000+0x2000+0x200B0)++0x03 line.long 0x00 "NCEOI2,Non Critical End Of Interrupt Register 2" group.long (dcr:0xFFC00000+0x2000+0x200D0)++0x03 line.long 0x00 "CEOI2,Critical End Of Interrupt Register 2" group.long (dcr:0xFFC00000+0x2000+0x200F0)++0x03 line.long 0x00 "MCEOI2,Machine Check End Of Interrupt Register 2" tree.end tree "P3" wsgroup.long (dcr:0xFFC00000+0x3000+0x20040)++0x03 dcr:0xFFC00000 line.long 0x00 "IPID0,Inter Processor Interrupt Dispatch 0" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x3000+0x20050)++0x03 line.long 0x00 "IPID1,Inter Processor Interrupt Dispatch 1" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x3000+0x20060)++0x03 line.long 0x00 "IPID2,Inter Processor Interrupt Dispatch 2" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" wgroup.long (dcr:0xFFC00000+0x3000+0x20070)++0x03 line.long 0x00 "IPID3,Inter Processor Interrupt Dispatch 3" bitfld.long 0x00 3. " P3 ,Processor 3 interrupt request" "-,Interrupt" bitfld.long 0x00 2. " P2 ,Processor 2 interrupt request" "-,Interrupt" bitfld.long 0x00 1. " P1 ,Processor 1 interrupt request" "-,Interrupt" bitfld.long 0x00 0. " P0 ,Processor 0 interrupt request" "-,Interrupt" group.long (dcr:0xFFC00000+0x3000+0x20080)++0x03 line.long 0x00 "CTP3,Current Task Priority Register 3" bitfld.long 0x00 0.--3. " PRI ,Interrupt priority level" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" rgroup.long (dcr:0xFFC00000+0x3000+0x20090)++0x03 line.long 0x00 "WAI3,Who Am I Register 3" bitfld.long 0x00 0.--1. " ID ,Processor ID" "0,1,2,3" hgroup.long (dcr:0xFFC00000+0x3000+0x200A0)++0x03 hide.long 0x00 "NCIAR3,Non Critical Interrupt Acknowledge Register 3" in hgroup.long (dcr:0xFFC00000+0x3000+0x200C0)++0x03 hide.long 0x00 "CIAR3,Critical Interrupt Acknowledge Register 3" in hgroup.long (dcr:0xFFC00000+0x3000+0x200E0)++0x03 hide.long 0x00 "MCIAR3,Machine Check Interrupt Acknowledge Register 3" in group.long (dcr:0xFFC00000+0x3000+0x200B0)++0x03 line.long 0x00 "NCEOI3,Non Critical End Of Interrupt Register 3" group.long (dcr:0xFFC00000+0x3000+0x200D0)++0x03 line.long 0x00 "CEOI3,Critical End Of Interrupt Register 3" group.long (dcr:0xFFC00000+0x3000+0x200F0)++0x03 line.long 0x00 "MCEOI3,Machine Check End Of Interrupt Register 3" tree.end tree.end tree "Global Registers" rgroup.long (dcr:0xFFC00000+0x1000)++0x03 line.long 0x00 "FRG0,Feature Reporting Register 0" hexmask.long.word 0x00 16.--26. 1. " IRQ ,Highest supported IRQ number" bitfld.long 0x00 8.--12. " CPU ,Highest physical supported CPU number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. " VER ,Version ID" group.long (dcr:0xFFC00000+0x1020)++0x03 line.long 0x00 "GCF0,Global Configuration Register 0" bitfld.long 0x00 30. " R ,MPIC reset" "-,Reset" bitfld.long 0x00 29. " P ,Pass through enable" "-,Enabled" bitfld.long 0x00 0.--3. " BAS ,Base address relocation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0xFFC00000+0x1040)++0x03 line.long 0x00 "VITC,Vendor Interrupt Type COnfiguration Register" bitfld.long 0x00 8.--12. " MCB ,Machine check border (lower)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0.--4. " CRB ,Critical interrupt border (lower)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.long (dcr:0xFFC00000+0x1050)++0x03 line.long 0x00 "VRID,Vendor Raw Interrupt Debug Register" hexmask.long.tbyte 0x00 12.--31. 1. " IPB ,Interrupt pending register section" bitfld.long 0x00 0.--2. " GRP ,Interrupt group" "0,1,2,3,4,5,6,7" rgroup.long (dcr:0xFFC00000+0x1070)++0x03 line.long 0x00 "REVID,Vendor Soft Core Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " RN ,Revision number" hexmask.long.byte 0x00 0.--7. 1. " BRN ,Branch number" rgroup.long (dcr:0xFFC00000+0x1080)++0x03 line.long 0x00 "VIR0,Vendor Identification Register 0" hexmask.long.byte 0x00 16.--23. 1. " STP ,Silicon stepping" hexmask.long.byte 0x00 8.--15. 1. " DEV ,Device ID" hexmask.long.byte 0x00 0.--7. 1. " VID ,Vendor ID" group.long (dcr:0xFFC00000+0x1090)++0x03 line.long 0x00 "PINI,Processor Initialization Register" bitfld.long 0x00 3. " P3 ,Processor 3 INIT line activate" "-,Activated" bitfld.long 0x00 2. " P2 ,Processor 2 INIT line activate" "-,Activated" bitfld.long 0x00 1. " P1 ,Processor 1 INIT line activate" "-,Activated" bitfld.long 0x00 0. " P0 ,Processor 0 INIT line activate" "-,Activated" group.long (dcr:0xFFC00000+0x10A0)++0x03 line.long 0x00 "IVP0,IPI Vector/Priority Register 0" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10B0)++0x03 line.long 0x00 "IVP1,IPI Vector/Priority Register 1" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10C0)++0x03 line.long 0x00 "IVP2,IPI Vector/Priority Register 2" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10D0)++0x03 line.long 0x00 "IVP3,IPI Vector/Priority Register 3" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x10E0)++0x03 line.long 0x00 "SPV,Spurious Vector Register" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" tree "Global Timer Registers" group.long (dcr:0xFFC00000+0x10F0)++0x03 line.long 0x00 "TFR,Timer Frequency Reporting Register" tree "Timer 0" rgroup.long (dcr:0xFFC00000+0x1100)++0x03 line.long 0x00 "TCC0,Timer 0 Current Count Register" bitfld.long 0x00 31. " T ,Toggled upon CC reaching zero" "0,1" hexmask.long 0x00 0.--30. 1. " CC ,Current count" group.long (dcr:0xFFC00000+0x1100+0x10)++0x03 line.long 0x00 "TBC0,Timer 0 Base Count Register" bitfld.long 0x00 31. " CI ,Count inhibit" "Reloaded,Inhibited" hexmask.long 0x00 0.--30. 1. " BC ,Base count" group.long (dcr:0xFFC00000+0x1100+0x20)++0x03 line.long 0x00 "TVP0,Timer dcr:0xFFC00000 Vector/Priority Register" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x1100+0x30)++0x03 line.long 0x00 "TDST0,Timer 0 Destination Register" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt destination" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt destination" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt destination" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt destination" "No,Yes" tree.end tree "Timer 1" rgroup.long (dcr:0xFFC00000+0x1140)++0x03 line.long 0x00 "TCC1,Timer 1 Current Count Register" bitfld.long 0x00 31. " T ,Toggled upon CC reaching zero" "0,1" hexmask.long 0x00 0.--30. 1. " CC ,Current count" group.long (dcr:0xFFC00000+0x1140+0x10)++0x03 line.long 0x00 "TBC1,Timer 1 Base Count Register" bitfld.long 0x00 31. " CI ,Count inhibit" "Reloaded,Inhibited" hexmask.long 0x00 0.--30. 1. " BC ,Base count" group.long (dcr:0xFFC00000+0x1140+0x20)++0x03 line.long 0x00 "TVP1,Timer dcr:0xFFC00000 Vector/Priority Register" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x1140+0x30)++0x03 line.long 0x00 "TDST1,Timer 1 Destination Register" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt destination" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt destination" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt destination" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt destination" "No,Yes" tree.end tree "Timer 2" rgroup.long (dcr:0xFFC00000+0x1180)++0x03 line.long 0x00 "TCC2,Timer 2 Current Count Register" bitfld.long 0x00 31. " T ,Toggled upon CC reaching zero" "0,1" hexmask.long 0x00 0.--30. 1. " CC ,Current count" group.long (dcr:0xFFC00000+0x1180+0x10)++0x03 line.long 0x00 "TBC2,Timer 2 Base Count Register" bitfld.long 0x00 31. " CI ,Count inhibit" "Reloaded,Inhibited" hexmask.long 0x00 0.--30. 1. " BC ,Base count" group.long (dcr:0xFFC00000+0x1180+0x20)++0x03 line.long 0x00 "TVP2,Timer dcr:0xFFC00000 Vector/Priority Register" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x1180+0x30)++0x03 line.long 0x00 "TDST2,Timer 2 Destination Register" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt destination" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt destination" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt destination" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt destination" "No,Yes" tree.end tree "Timer 3" rgroup.long (dcr:0xFFC00000+0x11C0)++0x03 line.long 0x00 "TCC3,Timer 3 Current Count Register" bitfld.long 0x00 31. " T ,Toggled upon CC reaching zero" "0,1" hexmask.long 0x00 0.--30. 1. " CC ,Current count" group.long (dcr:0xFFC00000+0x11C0+0x10)++0x03 line.long 0x00 "TBC3,Timer 3 Base Count Register" bitfld.long 0x00 31. " CI ,Count inhibit" "Reloaded,Inhibited" hexmask.long 0x00 0.--30. 1. " BC ,Base count" group.long (dcr:0xFFC00000+0x11C0+0x20)++0x03 line.long 0x00 "TVP3,Timer dcr:0xFFC00000 Vector/Priority Register" bitfld.long 0x00 31. " MSK ,Disable interrupts" "No,Yes" rbitfld.long 0x00 30. " ACT ,VP/DST registers active" "-,Active" bitfld.long 0x00 16.--19. " PRI ,Interrupt priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" hexmask.long.byte 0x00 0.--7. 1. " VEC ,Interrupt vector" group.long (dcr:0xFFC00000+0x11C0+0x30)++0x03 line.long 0x00 "TDST3,Timer 3 Destination Register" bitfld.long 0x00 3. " P3 ,Processor 3 as interrupt destination" "No,Yes" bitfld.long 0x00 2. " P2 ,Processor 2 as interrupt destination" "No,Yes" bitfld.long 0x00 1. " P1 ,Processor 1 as interrupt destination" "No,Yes" bitfld.long 0x00 0. " P0 ,Processor 0 as interrupt destination" "No,Yes" tree.end tree.end tree.end width 0x0B tree.end tree.open "DDR3MCPLB6 (DDR3 Memory Controller)" tree "PLB6" width 10. group.long (dcr:0x80010000+0x00)++0x03 line.long 0x00 "BESR,Bus Error Syndrome Register" bitfld.long 0x00 31. " MXRW ,Operation causing error" "Write,Read" bitfld.long 0x00 26.--30. " MXID ,PLB master ID of instance with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--25. " MTAG ,PLB MTag of instance with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 17.--20. " BUFFERID ,Buffer ID of instance with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " MXET1[0] ,Address decode miss" "-,Missed" bitfld.long 0x00 14. " MXET1[1] ,Address or byte enable parity error" "-,Error" bitfld.long 0x00 13. " MXET1[2] ,PLB write data error" "-,Error" bitfld.long 0x00 12. " MXET1[3] ,MCIF read data error" "-,Error" bitfld.long 0x00 11. " MXET1[4] ,MCIF read parity error" "-,Error" newline bitfld.long 0x00 8. " MXET2[0] ,PLB write parity error" "-,Error" bitfld.long 0x00 7. " MXET2[1] ,MCIF write parity error" "-,Error" bitfld.long 0x00 6. " MXET2[2] ,MCIF write RMW error" "-,Error" bitfld.long 0x00 0.--3. " MXET3 ,Diagnostic type 3 detection" "No flags,Write,Read,,MCIFII,,,,Decode,?..." wgroup.long (dcr:0x80010000+0x01)++0x03 line.long 0x00 "BESR_SET,Bus Error Syndrome Register Set" bitfld.long 0x00 31. " MXRW ,Operation causing error" "Write,Read" bitfld.long 0x00 26.--30. " MXID ,PLB master ID of instance with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--25. " MTAG ,PLB MTag of instance with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 17.--20. " BUFFERID ,Buffer ID of instance with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " MXET1[0] ,Address decode miss" "-,Missed" bitfld.long 0x00 14. " MXET1[1] ,Address or byte enable parity error" "-,Error" bitfld.long 0x00 13. " MXET1[2] ,PLB write data error" "-,Error" bitfld.long 0x00 12. " MXET1[3] ,MCIF read data error" "-,Error" bitfld.long 0x00 11. " MXET1[4] ,MCIF read parity error" "-,Error" newline bitfld.long 0x00 8. " MXET2[0] ,PLB write parity error" "-,Error" bitfld.long 0x00 7. " MXET2[1] ,MCIF write parity error" "-,Error" bitfld.long 0x00 6. " MXET2[2] ,MCIF write RMW error" "-,Error" bitfld.long 0x00 0.--3. " MXET3 ,Diagnostic type 3 detection" "No flags,Write,Read,,MCIFII,,,,Decode,?..." rgroup.long (dcr:0x80010000+0x02)++0x03 line.long 0x00 "BEARL,Bus Error Lower Address Register" rgroup.long (dcr:0x80010000+0x03)++0x03 line.long 0x00 "BEARU,Bus Error Upper Address Register" newline group.long (dcr:0x80010000+0x04)++0x03 line.long 0x00 "INTR_EN,Interrupt Enable" bitfld.long 0x00 31. " ERROR_ENA[0] ,BESR 16 error log enable" "-,Enabled" bitfld.long 0x00 30. " [1] ,BESR 17 error log enable" "-,Enabled" bitfld.long 0x00 29. " [2] ,BESR 18 error log enable" "-,Enabled" bitfld.long 0x00 28. " [3] ,BESR 19 error log enable" "-,Enabled" newline bitfld.long 0x00 27. " [4] ,BESR 20 error log enable" "-,Enabled" bitfld.long 0x00 26. " [5] ,BESR 21 error log enable" "-,Enabled" bitfld.long 0x00 25. " [6] ,BESR 22 error log enable" "-,Enabled" bitfld.long 0x00 24. " [7] ,BESR 23 error log enable" "-,Enabled" newline bitfld.long 0x00 23. " [8] ,BESR 24 error log enable" "-,Enabled" bitfld.long 0x00 22. " [9] ,BESR 25 error log enable" "-,Enabled" bitfld.long 0x00 21. " [10] ,BESR 26 error log enable" "-,Enabled" bitfld.long 0x00 20. " [11] ,BESR 27 error log enable" "-,Enabled" newline bitfld.long 0x00 19. " [12] ,BESR 28 error log enable" "-,Enabled" bitfld.long 0x00 18. " [13] ,BESR 29 error log enable" "-,Enabled" bitfld.long 0x00 17. " [14] ,BESR 30 error log enable" "-,Enabled" bitfld.long 0x00 16. " [15] ,BESR 31 error log enable" "-,Enabled" newline bitfld.long 0x00 15. " INTERRUPT_ENA[0] ,BESR 16 interrupt enable" "-,Enabled" bitfld.long 0x00 14. " [1] ,BESR 17 interrupt enable" "-,Enabled" bitfld.long 0x00 13. " [2] ,BESR 18 interrupt enable" "-,Enabled" bitfld.long 0x00 12. " [3] ,BESR 19 interrupt enable" "-,Enabled" newline bitfld.long 0x00 11. " [4] ,BESR 20 interrupt enable" "-,Enabled" bitfld.long 0x00 10. " [5] ,BESR 21 interrupt enable" "-,Enabled" bitfld.long 0x00 9. " [6] ,BESR 22 interrupt enable" "-,Enabled" bitfld.long 0x00 8. " [7] ,BESR 23 interrupt enable" "-,Enabled" newline bitfld.long 0x00 7. " [8] ,BESR 24 interrupt enable" "-,Enabled" bitfld.long 0x00 6. " [9] ,BESR 25 interrupt enable" "-,Enabled" bitfld.long 0x00 5. " [10] ,BESR 26 interrupt enable" "-,Enabled" bitfld.long 0x00 4. " [11] ,BESR 27 interrupt enable" "-,Enabled" newline bitfld.long 0x00 3. " [12] ,BESR 28 interrupt enable" "-,Enabled" bitfld.long 0x00 2. " [13] ,BESR 29 interrupt enable" "-,Enabled" bitfld.long 0x00 1. " [14] ,BESR 30 interrupt enable" "-,Enabled" bitfld.long 0x00 0. " [15] ,BESR 31 interrupt enable" "-,Enabled" group.long (dcr:0x80010000+0x07)++0x03 line.long 0x00 "PLBASYNC,PLB Asynchronous Options" bitfld.long 0x00 31. " PLBGTMCIF ,PLB greater than MCIF" "Less,Greater" bitfld.long 0x00 30. " PLBEQMCIF ,PLB equal MCIF" "-,Equal" bitfld.long 0x00 24.--27. " PLB6NUM ,Number of PLB6 clock cycles interval override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " MCIFNUM ,Number of MCIF clock cycles interval override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. " WRDONE_TUNE ,Number of WRDONE clock cycles interval override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " WRRDY_TUNE ,Number of WRRDY clock cycles interval override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RDRDY_TUNE ,Number of RDRDY clock cycles interval override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80010000+0x08)++0x03 line.long 0x00 "PLBORD,PLB Bridge Order Options" bitfld.long 0x00 31. " RAW ,PLB read around write enable" "-,Enabled" bitfld.long 0x00 28.--30. " THRESHOLD ,Read around write threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " IT_OOO ,MCIFII intra thread out of order read data return enable" "-,Enabled" bitfld.long 0x00 13.--14. " TOM ,MCIFII transaction order mode" "Strict in order,Partial out of order,,Full out of order" group.long (dcr:0x80010000+0x09)++0x03 line.long 0x00 "PLBCFG,PLB Configuration Register" bitfld.long 0x00 31. " NON_COHERENT ,Coherency" "Coherent,Non coherent" bitfld.long 0x00 27.--30. " TSNOOP ,Tsnoop value" ",,,,4,5,6,7,8,?..." group.long (dcr:0x80010000+0x10)++0x03 line.long 0x00 "PUABA,PLB Upper Address Base Address Register" hexmask.long 0x00 6.--31. 0x01 " PUABA ,PLB upper address bus base address" group.long (dcr:0x80010000+0x11)++0x03 line.long 0x00 "MR0CF,Memory Rank 0 Configuration" hexmask.long.word 0x00 17.--31. 0x02 " M_BA ,Memory base address" bitfld.long 0x00 12.--15. " M_SZ ,Memory size" ",,,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,?..." bitfld.long 0x00 0. " M_RE ,Memory rank enable" "-,Enabled" group.long (dcr:0x80010000+0x12)++0x03 line.long 0x00 "MR1CF,Memory Rank 1 Configuration" hexmask.long.word 0x00 17.--31. 0x02 " M_BA ,Memory base address" bitfld.long 0x00 12.--15. " M_SZ ,Memory size" ",,,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,?..." bitfld.long 0x00 0. " M_RE ,Memory rank enable" "-,Enabled" group.long (dcr:0x80010000+0x13)++0x03 line.long 0x00 "MR2CF,Memory Rank 2 Configuration" hexmask.long.word 0x00 17.--31. 0x02 " M_BA ,Memory base address" bitfld.long 0x00 12.--15. " M_SZ ,Memory size" ",,,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,?..." bitfld.long 0x00 0. " M_RE ,Memory rank enable" "-,Enabled" group.long (dcr:0x80010000+0x14)++0x03 line.long 0x00 "MR3CF,Memory Rank 3 Configuration" hexmask.long.word 0x00 17.--31. 0x02 " M_BA ,Memory base address" bitfld.long 0x00 12.--15. " M_SZ ,Memory size" ",,,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,32 GB,64 GB,?..." bitfld.long 0x00 0. " M_RE ,Memory rank enable" "-,Enabled" rgroup.long (dcr:0x80010000+0x20)++0x03 line.long 0x00 "STATUS,Bridge Status" bitfld.long 0x00 31. " IDLE ,Core idle status" "Busy,Idle" rgroup.long (dcr:0x80010000+0x21)++0x03 line.long 0x00 "RID,Revision ID Register" hexmask.long 0x00 0.--31. 1. " RID ,Revision ID" width 0x0B tree.end tree "MCIF" width 16. rgroup.long (dcr:0x80020000+0x10)++0x03 line.long 0x00 "MCSTAT,Memory Controller Status" bitfld.long 0x00 31. " INIT_COMPLETE ,Memory initialization sequencer complete" "-,Completed" bitfld.long 0x00 30. " SELF_REF_MODE ,SDRAM in self refresh mode" "No,Yes" newline bitfld.long 0x00 29. " IDLE ,Memory controller idle" "Busy,Idle" bitfld.long 0x00 28. " DFI_INIT_COMPLETE ,DFI initialization complete" "-,Completed" group.long (dcr:0x80020000+0x20)++0x03 line.long 0x00 "MCOPT1,Memory Controller Options 1" bitfld.long 0x00 30. " DM_DISABLE ,Data mask disable" "-,Yes" bitfld.long 0x00 28.--29. " ECC_CHK ,Memory data ECC error checking mode" "None,Generation + correction,Generation,Generation + correction + reporting" newline bitfld.long 0x00 27. " RDIMM ,Registered DIMM enable" "-,Enabled" bitfld.long 0x00 25.--26. " PMUM ,Page management unit mode" "Close,Auto close,Open,?..." newline bitfld.long 0x00 24. " WIDTH ,DDR DRAM data width" "32/40 bit,64/72 bit" bitfld.long 0x00 22. " UIOS ,Unused IO state" "Read: Hi-Z - Write: driven,Always Hi-Z" newline bitfld.long 0x00 20. " ZQCL_EN ,ZQCL command on exit from self refresh enable" "-,Enabled" bitfld.long 0x00 18. " WD_DLY ,MCIF write data request to return delay" "1 cycle,2 cycles" newline bitfld.long 0x00 16.--17. " QDEPTH ,Command queue depth" ",,4 commands,?..." bitfld.long 0x00 15. " RWOO ,Out of order reads and writes enable" "-,Enabled" newline bitfld.long 0x00 14. " WOOO ,Out of order writes enable" "-,Enabled" bitfld.long 0x00 13. " DCCO ,All out of order operations disable" "-,Yes" newline bitfld.long 0x00 12. " DEF_REF ,Deferred refresh enable" "-,Enabled" group.long (dcr:0x80020000+0x21)++0x03 line.long 0x00 "MCOPT2,Memory Controller Options 2" bitfld.long 0x00 31. " SELF_REF_EN ,Self refresh entry and exit control" "Exit,Enter" bitfld.long 0x00 30. " XSR_PREVENT ,Exit self refresh prevent" "-,Prevented" newline bitfld.long 0x00 29. " INIT_START ,Initialization start trigger and status" "Idle,Started" bitfld.long 0x00 28. " MC_ENABLE ,SDRAM memory controller enable" "-,Enabled" newline bitfld.long 0x00 27. " CLK_DISABLE[0] ,O_DFI_DRAM_CLK_DISABLE[0] activate" "-,Activated" bitfld.long 0x00 26. " CLK_DISABLE[1] ,O_DFI_DRAM_CLK_DISABLE[1] activate" "-,Activated" newline bitfld.long 0x00 25. " CLK_DISABLE[2] ,O_DFI_DRAM_CLK_DISABLE[2] activate" "-,Activated" bitfld.long 0x00 24. " CLK_DISABLE[3] ,O_DFI_DRAM_CLK_DISABLE[3] activate" "-,Activated" newline bitfld.long 0x00 23. " RESET_RANK[0] ,O_DFI_RESET_N[0] activate" "Activated,-" bitfld.long 0x00 22. " RESET_RANK[1] ,O_DFI_RESET_N[1] activate" "Activated,-" newline bitfld.long 0x00 21. " RESET_RANK[2] ,O_DFI_RESET_N[2] activate" "Activated,-" bitfld.long 0x00 20. " RESET_RANK[3] ,O_DFI_RESET_N[3] activate" "Activated,-" newline bitfld.long 0x00 17. " CKE_OE ,CKE output enable" "-,Enabled" bitfld.long 0x00 16. " RESET_OE ,RESET_N output enable" "-,Enabled" newline group.long (dcr:0x80020000+0x30)++0x03 line.long 0x00 "IOCNTL,I/O Pin Control" bitfld.long 0x00 31. " IO_CONTROL[0] ,O_PHY_IO_CONTROL[31] output" "Low,High" bitfld.long 0x00 30. " [1] ,O_PHY_IO_CONTROL[30] output" "Low,High" bitfld.long 0x00 29. " [2] ,O_PHY_IO_CONTROL[29] output" "Low,High" bitfld.long 0x00 28. " [3] ,O_PHY_IO_CONTROL[28] output" "Low,High" newline bitfld.long 0x00 27. " [4] ,O_PHY_IO_CONTROL[27] output" "Low,High" bitfld.long 0x00 26. " [5] ,O_PHY_IO_CONTROL[26] output" "Low,High" bitfld.long 0x00 25. " [6] ,O_PHY_IO_CONTROL[25] output" "Low,High" bitfld.long 0x00 24. " [7] ,O_PHY_IO_CONTROL[24] output" "Low,High" newline bitfld.long 0x00 23. " [8] ,O_PHY_IO_CONTROL[23] output" "Low,High" bitfld.long 0x00 22. " [9] ,O_PHY_IO_CONTROL[22] output" "Low,High" bitfld.long 0x00 21. " [10] ,O_PHY_IO_CONTROL[21] output" "Low,High" bitfld.long 0x00 20. " [11] ,O_PHY_IO_CONTROL[20] output" "Low,High" newline bitfld.long 0x00 19. " [12] ,O_PHY_IO_CONTROL[19] output" "Low,High" bitfld.long 0x00 18. " [13] ,O_PHY_IO_CONTROL[18] output" "Low,High" bitfld.long 0x00 17. " [14] ,O_PHY_IO_CONTROL[17] output" "Low,High" bitfld.long 0x00 16. " [15] ,O_PHY_IO_CONTROL[16] output" "Low,High" newline bitfld.long 0x00 15. " [16] ,O_PHY_IO_CONTROL[15] output" "Low,High" bitfld.long 0x00 14. " [17] ,O_PHY_IO_CONTROL[14] output" "Low,High" bitfld.long 0x00 13. " [18] ,O_PHY_IO_CONTROL[13] output" "Low,High" bitfld.long 0x00 12. " [19] ,O_PHY_IO_CONTROL[12] output" "Low,High" newline bitfld.long 0x00 11. " [20] ,O_PHY_IO_CONTROL[11] output" "Low,High" bitfld.long 0x00 10. " [21] ,O_PHY_IO_CONTROL[10] output" "Low,High" bitfld.long 0x00 9. " [22] ,O_PHY_IO_CONTROL[9] output" "Low,High" bitfld.long 0x00 8. " [23] ,O_PHY_IO_CONTROL[8] output" "Low,High" newline bitfld.long 0x00 7. " [24] ,O_PHY_IO_CONTROL[7] output" "Low,High" bitfld.long 0x00 6. " [25] ,O_PHY_IO_CONTROL[6] output" "Low,High" bitfld.long 0x00 5. " [26] ,O_PHY_IO_CONTROL[5] output" "Low,High" bitfld.long 0x00 4. " [27] ,O_PHY_IO_CONTROL[4] output" "Low,High" newline bitfld.long 0x00 3. " [28] ,O_PHY_IO_CONTROL[3] output" "Low,High" bitfld.long 0x00 2. " [29] ,O_PHY_IO_CONTROL[2] output" "Low,High" bitfld.long 0x00 1. " [30] ,O_PHY_IO_CONTROL[1] output" "Low,High" bitfld.long 0x00 0. " [31] ,O_PHY_IO_CONTROL[0] output" "Low,High" group.long (dcr:0x80020000+0x31)++0x03 line.long 0x00 "PHYCNTL,PHY Control" bitfld.long 0x00 31. " PHY_CNTL[0] ,O_PHY_CONTROL[31] output" "Low,High" bitfld.long 0x00 30. " [1] ,O_PHY_CONTROL[30] output" "Low,High" bitfld.long 0x00 29. " [2] ,O_PHY_CONTROL[29] output" "Low,High" bitfld.long 0x00 28. " [3] ,O_PHY_CONTROL[28] output" "Low,High" newline bitfld.long 0x00 27. " [4] ,O_PHY_CONTROL[27] output" "Low,High" bitfld.long 0x00 26. " [5] ,O_PHY_CONTROL[26] output" "Low,High" bitfld.long 0x00 25. " [6] ,O_PHY_CONTROL[25] output" "Low,High" bitfld.long 0x00 24. " [7] ,O_PHY_CONTROL[24] output" "Low,High" newline bitfld.long 0x00 23. " [8] ,O_PHY_CONTROL[23] output" "Low,High" bitfld.long 0x00 22. " [9] ,O_PHY_CONTROL[22] output" "Low,High" bitfld.long 0x00 21. " [10] ,O_PHY_CONTROL[21] output" "Low,High" bitfld.long 0x00 20. " [11] ,O_PHY_CONTROL[20] output" "Low,High" newline bitfld.long 0x00 19. " [12] ,O_PHY_CONTROL[19] output" "Low,High" bitfld.long 0x00 18. " [13] ,O_PHY_CONTROL[18] output" "Low,High" bitfld.long 0x00 17. " [14] ,O_PHY_CONTROL[17] output" "Low,High" bitfld.long 0x00 16. " [15] ,O_PHY_CONTROL[16] output" "Low,High" newline bitfld.long 0x00 15. " [16] ,O_PHY_CONTROL[15] output" "Low,High" bitfld.long 0x00 14. " [17] ,O_PHY_CONTROL[14] output" "Low,High" bitfld.long 0x00 13. " [18] ,O_PHY_CONTROL[13] output" "Low,High" bitfld.long 0x00 12. " [19] ,O_PHY_CONTROL[12] output" "Low,High" newline bitfld.long 0x00 11. " [20] ,O_PHY_CONTROL[11] output" "Low,High" bitfld.long 0x00 10. " [21] ,O_PHY_CONTROL[10] output" "Low,High" bitfld.long 0x00 9. " [22] ,O_PHY_CONTROL[9] output" "Low,High" bitfld.long 0x00 8. " [23] ,O_PHY_CONTROL[8] output" "Low,High" newline bitfld.long 0x00 7. " [24] ,O_PHY_CONTROL[7] output" "Low,High" bitfld.long 0x00 6. " [25] ,O_PHY_CONTROL[6] output" "Low,High" bitfld.long 0x00 5. " [26] ,O_PHY_CONTROL[5] output" "Low,High" bitfld.long 0x00 4. " [27] ,O_PHY_CONTROL[4] output" "Low,High" newline bitfld.long 0x00 3. " [28] ,O_PHY_CONTROL[3] output" "Low,High" bitfld.long 0x00 2. " [29] ,O_PHY_CONTROL[2] output" "Low,High" bitfld.long 0x00 1. " [30] ,O_PHY_CONTROL[1] output" "Low,High" bitfld.long 0x00 0. " [31] ,O_PHY_CONTROL[0] output" "Low,High" rgroup.long (dcr:0x80020000+0x32)++0x03 line.long 0x00 "PHYSTAT,PHY Status" bitfld.long 0x00 31. " PHY_STATUS[0] ,I_PHY_STATUS[31] input" "Low,High" bitfld.long 0x00 30. " [1] ,I_PHY_STATUS[30] input" "Low,High" bitfld.long 0x00 29. " [2] ,I_PHY_STATUS[29] input" "Low,High" bitfld.long 0x00 28. " [3] ,I_PHY_STATUS[28] input" "Low,High" newline bitfld.long 0x00 27. " [4] ,I_PHY_STATUS[27] input" "Low,High" bitfld.long 0x00 26. " [5] ,I_PHY_STATUS[26] input" "Low,High" bitfld.long 0x00 25. " [6] ,I_PHY_STATUS[25] input" "Low,High" bitfld.long 0x00 24. " [7] ,I_PHY_STATUS[24] input" "Low,High" newline bitfld.long 0x00 23. " [8] ,I_PHY_STATUS[23] input" "Low,High" bitfld.long 0x00 22. " [9] ,I_PHY_STATUS[22] input" "Low,High" bitfld.long 0x00 21. " [10] ,I_PHY_STATUS[21] input" "Low,High" bitfld.long 0x00 20. " [11] ,I_PHY_STATUS[20] input" "Low,High" newline bitfld.long 0x00 19. " [12] ,I_PHY_STATUS[19] input" "Low,High" bitfld.long 0x00 18. " [13] ,I_PHY_STATUS[18] input" "Low,High" bitfld.long 0x00 17. " [14] ,I_PHY_STATUS[17] input" "Low,High" bitfld.long 0x00 16. " [15] ,I_PHY_STATUS[16] input" "Low,High" newline bitfld.long 0x00 15. " [16] ,I_PHY_STATUS[15] input" "Low,High" bitfld.long 0x00 14. " [17] ,I_PHY_STATUS[14] input" "Low,High" bitfld.long 0x00 13. " [18] ,I_PHY_STATUS[13] input" "Low,High" bitfld.long 0x00 12. " [19] ,I_PHY_STATUS[12] input" "Low,High" newline bitfld.long 0x00 11. " [20] ,I_PHY_STATUS[11] input" "Low,High" bitfld.long 0x00 10. " [21] ,I_PHY_STATUS[10] input" "Low,High" bitfld.long 0x00 9. " [22] ,I_PHY_STATUS[9] input" "Low,High" bitfld.long 0x00 8. " [23] ,I_PHY_STATUS[8] input" "Low,High" newline bitfld.long 0x00 7. " [24] ,I_PHY_STATUS[7] input" "Low,High" bitfld.long 0x00 6. " [25] ,I_PHY_STATUS[6] input" "Low,High" bitfld.long 0x00 5. " [26] ,I_PHY_STATUS[5] input" "Low,High" bitfld.long 0x00 4. " [27] ,I_PHY_STATUS[4] input" "Low,High" newline bitfld.long 0x00 3. " [28] ,I_PHY_STATUS[3] input" "Low,High" bitfld.long 0x00 2. " [29] ,I_PHY_STATUS[2] input" "Low,High" bitfld.long 0x00 1. " [30] ,I_PHY_STATUS[1] input" "Low,High" bitfld.long 0x00 0. " [31] ,I_PHY_STATUS[0] input" "Low,High" group.long (dcr:0x80020000+0x33)++0x03 line.long 0x00 "PHYMASK,PHY Status Interrupt Mask" bitfld.long 0x00 31. " PHY_MASK[0] ,PHY_STATUS[0] interrupt mask" "0,1" bitfld.long 0x00 30. " [1] ,PHY_STATUS[1] interrupt mask" "0,1" bitfld.long 0x00 29. " [2] ,PHY_STATUS[2] interrupt mask" "0,1" bitfld.long 0x00 28. " [3] ,PHY_STATUS[3] interrupt mask" "0,1" newline bitfld.long 0x00 27. " [4] ,PHY_STATUS[4] interrupt mask" "0,1" bitfld.long 0x00 26. " [5] ,PHY_STATUS[5] interrupt mask" "0,1" bitfld.long 0x00 25. " [6] ,PHY_STATUS[6] interrupt mask" "0,1" bitfld.long 0x00 24. " [7] ,PHY_STATUS[7] interrupt mask" "0,1" newline bitfld.long 0x00 23. " [8] ,PHY_STATUS[8] interrupt mask" "0,1" bitfld.long 0x00 22. " [9] ,PHY_STATUS[9] interrupt mask" "0,1" bitfld.long 0x00 21. " [10] ,PHY_STATUS[10] interrupt mask" "0,1" bitfld.long 0x00 20. " [11] ,PHY_STATUS[11] interrupt mask" "0,1" newline bitfld.long 0x00 19. " [12] ,PHY_STATUS[12] interrupt mask" "0,1" bitfld.long 0x00 18. " [13] ,PHY_STATUS[13] interrupt mask" "0,1" bitfld.long 0x00 17. " [14] ,PHY_STATUS[14] interrupt mask" "0,1" bitfld.long 0x00 16. " [15] ,PHY_STATUS[15] interrupt mask" "0,1" newline bitfld.long 0x00 15. " [16] ,PHY_STATUS[16] interrupt mask" "0,1" bitfld.long 0x00 14. " [17] ,PHY_STATUS[17] interrupt mask" "0,1" bitfld.long 0x00 13. " [18] ,PHY_STATUS[18] interrupt mask" "0,1" bitfld.long 0x00 12. " [19] ,PHY_STATUS[19] interrupt mask" "0,1" newline bitfld.long 0x00 11. " [20] ,PHY_STATUS[20] interrupt mask" "0,1" bitfld.long 0x00 10. " [21] ,PHY_STATUS[21] interrupt mask" "0,1" bitfld.long 0x00 9. " [22] ,PHY_STATUS[22] interrupt mask" "0,1" bitfld.long 0x00 8. " [23] ,PHY_STATUS[23] interrupt mask" "0,1" newline bitfld.long 0x00 7. " [24] ,PHY_STATUS[24] interrupt mask" "0,1" bitfld.long 0x00 6. " [25] ,PHY_STATUS[25] interrupt mask" "0,1" bitfld.long 0x00 5. " [26] ,PHY_STATUS[26] interrupt mask" "0,1" bitfld.long 0x00 4. " [27] ,PHY_STATUS[27] interrupt mask" "0,1" newline bitfld.long 0x00 3. " [28] ,PHY_STATUS[28] interrupt mask" "0,1" bitfld.long 0x00 2. " [29] ,PHY_STATUS[29] interrupt mask" "0,1" bitfld.long 0x00 1. " [30] ,PHY_STATUS[30] interrupt mask" "0,1" bitfld.long 0x00 0. " [31] ,PHY_STATUS[31] interrupt mask" "0,1" newline group.long (dcr:0x80020000+0x40)++0x03 line.long 0x00 "CFGR0,Memory Rank 0 Configuration" bitfld.long 0x00 8.--11. " ADDR_MODE ,Addressing mode" ",,Mode 2 - Nx10,Mode 3 - Nx11,Mode 4 - Nx12,?..." bitfld.long 0x00 4. " MIRROR ,Address mirroring enable" "-,Enabled" bitfld.long 0x00 0. " RANK_ENABLE ,Memory rank enable" "-,Enabled" group.long (dcr:0x80020000+0x41)++0x03 line.long 0x00 "CFGR1,Memory Rank 1 Configuration" bitfld.long 0x00 8.--11. " ADDR_MODE ,Addressing mode" ",,Mode 2 - Nx10,Mode 3 - Nx11,Mode 4 - Nx12,?..." bitfld.long 0x00 4. " MIRROR ,Address mirroring enable" "-,Enabled" bitfld.long 0x00 0. " RANK_ENABLE ,Memory rank enable" "-,Enabled" group.long (dcr:0x80020000+0x42)++0x03 line.long 0x00 "CFGR2,Memory Rank 2 Configuration" bitfld.long 0x00 8.--11. " ADDR_MODE ,Addressing mode" ",,Mode 2 - Nx10,Mode 3 - Nx11,Mode 4 - Nx12,?..." bitfld.long 0x00 4. " MIRROR ,Address mirroring enable" "-,Enabled" bitfld.long 0x00 0. " RANK_ENABLE ,Memory rank enable" "-,Enabled" group.long (dcr:0x80020000+0x43)++0x03 line.long 0x00 "CFGR3,Memory Rank 3 Configuration" bitfld.long 0x00 8.--11. " ADDR_MODE ,Addressing mode" ",,Mode 2 - Nx10,Mode 3 - Nx11,Mode 4 - Nx12,?..." bitfld.long 0x00 4. " MIRROR ,Address mirroring enable" "-,Enabled" bitfld.long 0x00 0. " RANK_ENABLE ,Memory rank enable" "-,Enabled" newline group.long (dcr:0x80020000+0x50)++0x03 line.long 0x00 "INITSEQ0,SDRAM Initialization Sequence 0" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x50+0x01)++0x03 line.long 0x00 "INITCMD0,SDRAM Initialization Command 0" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x52)++0x03 line.long 0x00 "INITSEQ1,SDRAM Initialization Sequence 1" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x52+0x01)++0x03 line.long 0x00 "INITCMD1,SDRAM Initialization Command 1" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x54)++0x03 line.long 0x00 "INITSEQ2,SDRAM Initialization Sequence 2" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x54+0x01)++0x03 line.long 0x00 "INITCMD2,SDRAM Initialization Command 2" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x56)++0x03 line.long 0x00 "INITSEQ3,SDRAM Initialization Sequence 3" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x56+0x01)++0x03 line.long 0x00 "INITCMD3,SDRAM Initialization Command 3" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x58)++0x03 line.long 0x00 "INITSEQ4,SDRAM Initialization Sequence 4" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x58+0x01)++0x03 line.long 0x00 "INITCMD4,SDRAM Initialization Command 4" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x5A)++0x03 line.long 0x00 "INITSEQ5,SDRAM Initialization Sequence 5" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x5A+0x01)++0x03 line.long 0x00 "INITCMD5,SDRAM Initialization Command 5" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x5C)++0x03 line.long 0x00 "INITSEQ6,SDRAM Initialization Sequence 6" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x5C+0x01)++0x03 line.long 0x00 "INITCMD6,SDRAM Initialization Command 6" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x5E)++0x03 line.long 0x00 "INITSEQ7,SDRAM Initialization Sequence 7" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x5E+0x01)++0x03 line.long 0x00 "INITCMD7,SDRAM Initialization Command 7" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x60)++0x03 line.long 0x00 "INITSEQ8,SDRAM Initialization Sequence 8" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x60+0x01)++0x03 line.long 0x00 "INITCMD8,SDRAM Initialization Command 8" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x62)++0x03 line.long 0x00 "INITSEQ9,SDRAM Initialization Sequence 9" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x62+0x01)++0x03 line.long 0x00 "INITCMD9,SDRAM Initialization Command 9" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x64)++0x03 line.long 0x00 "INITSEQ10,SDRAM Initialization Sequence 10" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x64+0x01)++0x03 line.long 0x00 "INITCMD10,SDRAM Initialization Command 10" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x66)++0x03 line.long 0x00 "INITSEQ11,SDRAM Initialization Sequence 11" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x66+0x01)++0x03 line.long 0x00 "INITCMD11,SDRAM Initialization Command 11" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x68)++0x03 line.long 0x00 "INITSEQ12,SDRAM Initialization Sequence 12" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x68+0x01)++0x03 line.long 0x00 "INITCMD12,SDRAM Initialization Command 12" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x6A)++0x03 line.long 0x00 "INITSEQ13,SDRAM Initialization Sequence 13" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x6A+0x01)++0x03 line.long 0x00 "INITCMD13,SDRAM Initialization Command 13" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x6C)++0x03 line.long 0x00 "INITSEQ14,SDRAM Initialization Sequence 14" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x6C+0x01)++0x03 line.long 0x00 "INITCMD14,SDRAM Initialization Command 14" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" group.long (dcr:0x80020000+0x6E)++0x03 line.long 0x00 "INITSEQ15,SDRAM Initialization Sequence 15" bitfld.long 0x00 31. " ENABLE ,Command enable" "-,Enabled" hexmask.long.word 0x00 16.--27. 1. " WAIT ,Minimum wait clock cycles" bitfld.long 0x00 0.--3. " RANK ,Initialization rank select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x80020000+0x6E+0x01)++0x03 line.long 0x00 "INITCMD15,SDRAM Initialization Command 15" bitfld.long 0x00 29.--31. " CMD ,Initialization command" "Drive low,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high,Drive high" bitfld.long 0x00 20.--22. " BANK ,Initialization bank address" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 0x01 " ADDR ,Initialization memory address" newline group.long (dcr:0x80020000+0x80)++0x03 line.long 0x00 "SDTR0,SDRAM Timing Register 0" hexmask.long.word 0x00 16.--31. 1. " T_REFI ,Periodic refresh interval" hexmask.long.word 0x00 0.--11. 1. " T_RFC_XPR ,Delay between consecutive refresh and refresh/activate command" group.long (dcr:0x80020000+0x81)++0x03 line.long 0x00 "SDTR1,SDRAM Timing Register 1" bitfld.long 0x00 31. " T_LEADOFF ,Command leadoff enable" "Single cycle,Two cycle" bitfld.long 0x00 30. " ODT_DELAY ,ODT activation delay" "Same cycle,Cycle after" bitfld.long 0x00 29. " ODT_WIDTH ,ODT width" "4/6 cycles,5/7 cycles" newline bitfld.long 0x00 24.--27. " T_WTRO ,Write to read bus turnaround delay" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..." bitfld.long 0x00 16.--19. " T_RTWO ,Read to write bus turnaround delay" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..." bitfld.long 0x00 8.--11. " T_WTWO ,Write to write rank switch delay" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..." bitfld.long 0x00 0.--3. " T_RTRO ,Read to read rank switch delay" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..." group.long (dcr:0x80020000+0x82)++0x03 line.long 0x00 "SDTR2,SDRAM Timing Register 2" bitfld.long 0x00 24.--27. " T_RCD ,Activate to read/write command delay" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 16.--19. " T_RP ,Precharge command period" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 8.--13. " T_RC ,Activate to activate/auto refresh time" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,?..." bitfld.long 0x00 0.--5. " T_RAS ,Activate to precharge time" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,?..." group.long (dcr:0x80020000+0x83)++0x03 line.long 0x00 "SDTR3,SDRAM Timing Register 3" bitfld.long 0x00 24.--27. " T_WTR ,Internal write to internal read delay" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 16.--19. " T_RTP ,Internal read command to precharge delay" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 8.--11. " T_RRD ,Activate to activate delay" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" hexmask.long.byte 0x00 0.--7. 1. " T_XSDLL ,Exit self refresh and DLL lock delay" group.long (dcr:0x80020000+0x84)++0x03 line.long 0x00 "SDTR4,SDRAM Timing Register 4" bitfld.long 0x00 24.--29. " T_RDDATA_EN ,PHY read data enable delay" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,?..." bitfld.long 0x00 16.--20. " T_SYS_RDLAT ,System read latency" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles" bitfld.long 0x00 8.--10. " T_CCD ,CAS to CAS command delay" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x00 0.--4. " T_MOD ,Mode register set command update delay" ",1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles" group.long (dcr:0x80020000+0x90)++0x03 line.long 0x00 "SMR0,Shadow SDRAM Mode Register 0" bitfld.long 0x00 12. " PPD ,Precharge power down" "Slow exit,Fast exit" bitfld.long 0x00 9.--11. " WR ,Auto precharge write recovery time" ",5 cycles,6 cycles,7 cycles,8 cycles,10 cycles,12 cycles,?..." bitfld.long 0x00 3. " RBT ,Read burst type" "Sequential,?..." newline bitfld.long 0x00 2. 4.--6. " CL ,CAS latency" ",12 cycles,5 cycles,13 cycles,6 cycles,14 cycles,7 cycles,15 cycles,8 cycles,16 cycles,9 cycles,,10 cycles,,11 cycles,?..." bitfld.long 0x00 0.--1. " BL ,Burst length" "BL8 fixed,BC4/BL8 on the fly,BC4 fixed,?..." group.long (dcr:0x80020000+0x91)++0x03 line.long 0x00 "SMR1,Shadow SDRAM Mode Register 1" bitfld.long 0x00 12. " QOFF ,Output buffer disable" "-,Yes" bitfld.long 0x00 11. " TDQS ,TDQS enable" "-,Enabled" bitfld.long 0x00 9. 6. 2. " RTT_NOM ,Memory device signal termination control" "Disabled,/4 Ohm,/2 Ohm,/6 Ohm,/12 Ohm,/8 Ohm,?..." newline bitfld.long 0x00 7. " WR_LEVEL ,Write leveling enable" "-,Enabled" bitfld.long 0x00 5. 1. " DIC ,Driver impedance control" "0,1,2,3" bitfld.long 0x00 3.--4. " AL ,Additive latency in cycles" "Disabled,CL-1,CL-2,?..." bitfld.long 0x00 0. " DLL ,DLL enable" "-,Enabled" group.long (dcr:0x80020000+0x92)++0x03 line.long 0x00 "SMR2,Shadow SDRAM Mode Register 2" bitfld.long 0x00 9.--10. " RTT_WR ,RTT for write operations" "Dynamic ODT off,RZQ/4,RZQ/2,?..." bitfld.long 0x00 7. " SRT ,Self refresh temperature range" "Normal,Extended" bitfld.long 0x00 6. " ASR ,Auto self refresh" "Manual,Auto" newline bitfld.long 0x00 3.--5. " CWL ,CAS write latency" "5 clocks,6 clocks,7 clocks,8 clocks,?..." bitfld.long 0x00 0.--2. " PASR ,Partial array self refresh" "0,1,2,3,4,5,6,7" group.long (dcr:0x80020000+0x93)++0x03 line.long 0x00 "SMR3,Shadow SDRAM Mode Register 3" bitfld.long 0x00 2. " MPR ,MPR operation" "Normal,Dataflow from MPR" bitfld.long 0x00 0.--1. " MPRLOC ,MPR location" "Predefined,?..." group.long (dcr:0x80020000+0xA0)++0x03 line.long 0x00 "ODTR0,Memory On Die Termination Control 0" bitfld.long 0x00 31. " RK3W ,Enable ODT0 with rank 3 write" "No,Yes" bitfld.long 0x00 30. " RK3R ,Enable ODT0 with rank 3 read" "No,Yes" bitfld.long 0x00 29. " RK2W ,Enable ODT0 with rank 2 write" "No,Yes" bitfld.long 0x00 28. " RK2R ,Enable ODT0 with rank 2 read" "No,Yes" newline bitfld.long 0x00 27. " RK1W ,Enable ODT0 with rank 1 write" "No,Yes" bitfld.long 0x00 26. " RK1R ,Enable ODT0 with rank 1 read" "No,Yes" bitfld.long 0x00 25. " RK0W ,Enable ODT0 with rank 0 write" "No,Yes" bitfld.long 0x00 24. " RK0R ,Enable ODT0 with rank 0 read" "No,?..." group.long (dcr:0x80020000+0xA1)++0x03 line.long 0x00 "ODTR1,Memory On Die Termination Control 1" bitfld.long 0x00 31. " RK3W ,Enable ODT1 with rank 3 write" "No,Yes" bitfld.long 0x00 30. " RK3R ,Enable ODT1 with rank 3 read" "No,Yes" bitfld.long 0x00 29. " RK2W ,Enable ODT1 with rank 2 write" "No,Yes" bitfld.long 0x00 28. " RK2R ,Enable ODT1 with rank 2 read" "No,Yes" newline bitfld.long 0x00 27. " RK1W ,Enable ODT1 with rank 1 write" "No,Yes" bitfld.long 0x00 26. " RK1R ,Enable ODT1 with rank 1 read" "No,?..." bitfld.long 0x00 25. " RK0W ,Enable ODT1 with rank 0 write" "No,Yes" bitfld.long 0x00 24. " RK0R ,Enable ODT1 with rank 0 read" "No,Yes" group.long (dcr:0x80020000+0xA2)++0x03 line.long 0x00 "ODTR2,Memory On Die Termination Control 2" bitfld.long 0x00 31. " RK3W ,Enable ODT2 with rank 3 write" "No,Yes" bitfld.long 0x00 30. " RK3R ,Enable ODT2 with rank 3 read" "No,Yes" bitfld.long 0x00 29. " RK2W ,Enable ODT2 with rank 2 write" "No,Yes" bitfld.long 0x00 28. " RK2R ,Enable ODT2 with rank 2 read" "No,?..." newline bitfld.long 0x00 27. " RK1W ,Enable ODT2 with rank 1 write" "No,Yes" bitfld.long 0x00 26. " RK1R ,Enable ODT2 with rank 1 read" "No,Yes" bitfld.long 0x00 25. " RK0W ,Enable ODT2 with rank 0 write" "No,Yes" bitfld.long 0x00 24. " RK0R ,Enable ODT2 with rank 0 read" "No,Yes" group.long (dcr:0x80020000+0xA3)++0x03 line.long 0x00 "ODTR3,Memory On Die Termination Control 3" bitfld.long 0x00 31. " RK3W ,Enable ODT3 with rank 3 write" "No,Yes" bitfld.long 0x00 30. " RK3R ,Enable ODT3 with rank 3 read" "No,?..." bitfld.long 0x00 29. " RK2W ,Enable ODT3 with rank 2 write" "No,Yes" bitfld.long 0x00 28. " RK2R ,Enable ODT3 with rank 2 read" "No,Yes" newline bitfld.long 0x00 27. " RK1W ,Enable ODT3 with rank 1 write" "No,Yes" bitfld.long 0x00 26. " RK1R ,Enable ODT3 with rank 1 read" "No,Yes" bitfld.long 0x00 25. " RK0W ,Enable ODT3 with rank 0 write" "No,Yes" bitfld.long 0x00 24. " RK0R ,Enable ODT3 with rank 0 read" "No,Yes" group.long (dcr:0x80020000+0xC0)++0x03 line.long 0x00 "CALCNTL,Calibration Control Register" bitfld.long 0x00 31. " CPC ,Clock period calibration state machine enable" "-,Enabled" bitfld.long 0x00 30. " WRLVL ,Write leveling state machine enable" "-,Enabled" bitfld.long 0x00 29. " GTLVL ,Read gate leveling state machine enable" "-,Enabled" bitfld.long 0x00 28. " RDLVL ,Read data leveling state machine enable" "-,Enabled" newline bitfld.long 0x00 27. " CAL_RANK_EN[3] ,Rank 3 for calibration enable" "-,Enabled" bitfld.long 0x00 26. " CAL_RANK_EN[2] ,Rank 2 for calibration enable" "-,Enabled" bitfld.long 0x00 25. " CAL_RANK_EN[1] ,Rank 1 for calibration enable" "-,Enabled" bitfld.long 0x00 24. " CAL_RANK_EN[0] ,Rank 0 for calibration enable" "-,Enabled" newline bitfld.long 0x00 20. " RL_EDGE ,Read leveling read DQS edge" "Against rising,Against falling" bitfld.long 0x00 17. " ZQCAL_EN ,Periodic ZQ calibration during refresh interval enable" "-,Enabled" bitfld.long 0x00 16. " RTCAL_EN ,Periodic runtime read and CPC calibration during refresh intervals enable" "-,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ZQCAL_CNT ,ZQ calibration interval refresh count" newline hexmask.long.byte 0x00 0.--7. 1. " RTCAL_CNT ,Runtime calibration interval refresh count" newline group.long (dcr:0x80020000+0xC1)++0x03 line.long 0x00 "CALSTAT,Calibration Status Register" bitfld.long 0x00 29. " CPC_BUSY ,Clock period calibration busy" "-,Busy" bitfld.long 0x00 28. " CPC_DONE ,Clock period calibration complete" "-,Completed" bitfld.long 0x00 24. " CPC_ERR ,Clock period calibration routine timeout" "-,Timeout" newline bitfld.long 0x00 21. " WRLVL_BUSY ,Write leveling calibration busy" "-,Busy" bitfld.long 0x00 20. " WRLVL_DONE ,Write leveling complete" "-,Completed" newline bitfld.long 0x00 19. " WRLVL_ERR[3] ,Rank 3 write leveling timeout" "-,Timeout" bitfld.long 0x00 18. " WRLVL_ERR[2] ,Rank 2 write leveling timeout" "-,Timeout" bitfld.long 0x00 17. " WRLVL_ERR[1] ,Rank 1 write leveling timeout" "-,Timeout" bitfld.long 0x00 16. " WRLVL_ERR[0] ,Rank 0 write leveling timeout" "-,Timeout" newline bitfld.long 0x00 13. " GTLVL_BUSY ,Read gate leveling calibration busy" "-,Busy" bitfld.long 0x00 12. " GTLVL_DONE ,Read gate leveling complete" "-,Completed" newline bitfld.long 0x00 11. " GTLVL_ERR[3] ,Rank 3 read gate leveling timeout" "-,Timeout" bitfld.long 0x00 10. " GTLVL_ERR[2] ,Rank 2 read gate leveling timeout" "-,Timeout" bitfld.long 0x00 9. " GTLVL_ERR[1] ,Rank 1 read gate leveling timeout" "-,Timeout" bitfld.long 0x00 8. " GTLVL_ERR[0] ,Rank 0 read gate leveling timeout" "-,Timeout" newline bitfld.long 0x00 5. " RDLVL_BUSY ,Read leveling calibration busy" "-,Busy" bitfld.long 0x00 4. " RDLVL_DONE ,Read data leveling complete" "-,Completed" newline bitfld.long 0x00 3. " RDLVL_ERR[3] ,Rank 3 read leveling timeout" "-,Timeout" bitfld.long 0x00 2. " RDLVL_ERR[2] ,Rank 2 read leveling timeout" "-,Timeout" bitfld.long 0x00 1. " RDLVL_ERR[1] ,Rank 1 read leveling timeout" "-,Timeout" bitfld.long 0x00 0. " RDLVL_ERR[0] ,Rank 0 read leveling timeout" "-,Timeout" group.long (dcr:0x80020000+0xC2)++0x03 line.long 0x00 "T_CTRLUPD,DFI Control Update Timers" hexmask.long.word 0x00 16.--31. 1. " T_CTRLUPD_MIN ,DFI_CTRLUPD_REQ minimum assertion time" hexmask.long.word 0x00 0.--15. 1. " T_CTRLUPD_MAX ,DFI_CTRLUPD_REQ maximum assertion time" group.long (dcr:0x80020000+0xC4)++0x03 line.long 0x00 "T_WRLVL,DFI Write Leveling Timers" group.long (dcr:0x80020000+0xC5)++0x03 line.long 0x00 "WRLVL_DLY,DFI Write Leveling State Machine Delays" hexmask.long.byte 0x00 16.--23. 1. " T_WRLVL_EN ,Delay between write and activation" hexmask.long.byte 0x00 0.--7. 1. " T_WRLVL_WW ,Delay between two writes" group.long (dcr:0x80020000+0xC8)++0x03 line.long 0x00 "T_RDLVL,DFI Read Leveling Timers" group.long (dcr:0x80020000+0xC9)++0x03 line.long 0x00 "RDLVL_DLY,DFI Read Leveling State Machine Delays" hexmask.long.word 0x00 16.--27. 1. " T_RDLVL_EN ,Delay between activation and first read" hexmask.long.word 0x00 0.--11. 1. " T_RDLVL_RR ,Delay between two reads" group.long (dcr:0x80020000+0xEC)++0x03 line.long 0x00 "ECCERR_SET/CLR,ECC Error Status Register Set/Clear" setclrfld.long 0x00 31. 0x02<<2 31. 0x00 31. " B0CE ,Byte lane 0 correctable error" "-,Error" setclrfld.long 0x00 30. 0x02<<2 30. 0x00 30. " B1CE ,Byte lane 1 correctable error" "-,Error" setclrfld.long 0x00 29. 0x02<<2 29. 0x00 29. " B2CE ,Byte lane 2 correctable error" "-,Error" setclrfld.long 0x00 28. 0x02<<2 28. 0x00 28. " B3CE ,Byte lane 3 correctable error" "-,Error" newline setclrfld.long 0x00 27. 0x02<<2 27. 0x00 27. " B4CE ,Byte lane 4 correctable error" "-,Error" setclrfld.long 0x00 26. 0x02<<2 26. 0x00 26. " B5CE ,Byte lane 5 correctable error" "-,Error" setclrfld.long 0x00 25. 0x02<<2 25. 0x00 25. " B6CE ,Byte lane 6 correctable error" "-,Error" setclrfld.long 0x00 24. 0x02<<2 24. 0x00 24. " B7CE ,Byte lane 7 correctable error" "-,Error" newline setclrfld.long 0x00 23. 0x02<<2 23. 0x00 23. " B8CE ,Byte lane 8 correctable error" "-,Error" setclrfld.long 0x00 22. 0x02<<2 22. 0x00 22. " B9CE ,Byte lane 9 correctable error" "-,Error" setclrfld.long 0x00 21. 0x02<<2 21. 0x00 21. " B10CE ,Byte lane 10 correctable error" "-,Error" setclrfld.long 0x00 20. 0x02<<2 20. 0x00 20. " B11CE ,Byte lane 11 correctable error" "-,Error" newline setclrfld.long 0x00 19. 0x02<<2 19. 0x00 19. " B12CE ,Byte lane 12 correctable error" "-,Error" setclrfld.long 0x00 18. 0x02<<2 18. 0x00 18. " B13CE ,Byte lane 13 correctable error" "-,Error" setclrfld.long 0x00 17. 0x02<<2 17. 0x00 17. " B14CE ,Byte lane 14 correctable error" "-,Error" setclrfld.long 0x00 16. 0x02<<2 16. 0x00 16. " B15CE ,Byte lane 15 correctable error" "-,Error" newline setclrfld.long 0x00 15. 0x02<<2 15. 0x00 15. " CHKBITERR[1] ,O_M_RD_DATA[0:63] check byte error" "-,Error" setclrfld.long 0x00 14. 0x02<<2 14. 0x00 14. " CHKBITERR[0] ,O_M_RD_DATA[64:127] check byte error" "-,Error" setclrfld.long 0x00 13. 0x02<<2 13. 0x00 13. " CE ,Correctable error" "-,Error" setclrfld.long 0x00 12. 0x02<<2 12. 0x00 12. " UE ,Uncorrectable error" "-,Error" newline setclrfld.long 0x00 11. 0x02<<2 11. 0x00 11. " RNK3ERR ,Rank 3 error" "-,Error" setclrfld.long 0x00 10. 0x02<<2 10. 0x00 10. " RNK2ERR ,Rank 2 error" "-,Error" setclrfld.long 0x00 9. 0x02<<2 9. 0x00 9. " RNK1ERR ,Rank 1 error" "-,Error" setclrfld.long 0x00 8. 0x02<<2 8. 0x00 8. " RNK0ERR ,Rank 0 error" "-,Error" width 0x0B tree.end tree.end tree "DDR3 PHY" width 29. endian.le tree "DDR3PHYDFICNTL Registers" group.word (dcr:0x80030000+0xD000)++0x01 line.word 0x00 "DFICNTL_CONFIG_REG,DFI Configuration/Latency Register" bitfld.word 0x00 10. " DME ,Data mask enable" "-,Enabled" bitfld.word 0x00 5.--9. " WL ,Write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--4. " RL ,Read latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xD001)++0x01 line.word 0x00 "DFICNTL_CPC_CNTL,DFI CPC Update And Control Register" bitfld.word 0x00 8. " ITC ,Initial training complete" "-,Completed" bitfld.word 0x00 7. " PIC ,PHY initialization complete" "-,Completed" bitfld.word 0x00 6. " PUIE ,PHY update interface enable" "-,Enabled" bitfld.word 0x00 4.--5. " CUI ,CPC update interval" "Update every event,Update every 3rd event,Update every 5th event,Update every 9th event" newline bitfld.word 0x00 2.--3. " UI ,Update interval" "Update every request,Update every 4th request,Update every 16th request,Update every 64th request" bitfld.word 0x00 1. " ACUE ,Auto CPC update enable" "-,Enabled" bitfld.word 0x00 0. " CUR ,CPC update request" "-,Update" newline group.word (dcr:0x80030000+0xD002)++0x01 line.word 0x00 "DFICNTL_CPC_REQ_MASK_0,DFI CPC Request Mask 0" bitfld.word 0x00 15. " DQS1[6] ,DQS1 DP 6 periodic CPC update disable" "-,Yes" bitfld.word 0x00 14. " [5] ,DQS1 DP 5 periodic CPC update disable" "-,Yes" bitfld.word 0x00 13. " [4] ,DQS1 DP 4 periodic CPC update disable" "-,Yes" bitfld.word 0x00 12. " [3] ,DQS1 DP 3 periodic CPC update disable" "-,Yes" newline bitfld.word 0x00 11. " [2] ,DQS1 DP 2 periodic CPC update disable" "-,Yes" bitfld.word 0x00 10. " [1] ,DQS1 DP 1 periodic CPC update disable" "-,Yes" bitfld.word 0x00 9. " [0] ,DQS1 DP 0 periodic CPC update disable" "-,Yes" newline bitfld.word 0x00 8. " DQS0[8] ,DQS0 DP 8 periodic CPC update disable" "-,Yes" bitfld.word 0x00 7. " [7] ,DQS0 DP 7 periodic CPC update disable" "-,Yes" bitfld.word 0x00 6. " [6] ,DQS0 DP 6 periodic CPC update disable" "-,Yes" bitfld.word 0x00 5. " [5] ,DQS0 DP 5 periodic CPC update disable" "-,Yes" newline bitfld.word 0x00 4. " [4] ,DQS0 DP 4 periodic CPC update disable" "-,Yes" bitfld.word 0x00 3. " [3] ,DQS0 DP 3 periodic CPC update disable" "-,Yes" bitfld.word 0x00 2. " [2] ,DQS0 DP 2 periodic CPC update disable" "-,Yes" bitfld.word 0x00 1. " [1] ,DQS0 DP 1 periodic CPC update disable" "-,Yes" newline bitfld.word 0x00 0. " [0] ,DQS0 DP 0 periodic CPC update disable" "-,Yes" group.word (dcr:0x80030000+0xD003)++0x01 line.word 0x00 "DFICNTL_CPC_REQ_MASK_1,DFI CPC Request Mask 1" bitfld.word 0x00 5. " ADR[3] ,ADR3 periodic CPC update disable" "-,Yes" bitfld.word 0x00 4. " [2] ,ADR2 periodic CPC update disable" "-,Yes" bitfld.word 0x00 3. " [1] ,ADR1 periodic CPC update disable" "-,Yes" bitfld.word 0x00 2. " [0] ,ADR0 periodic CPC update disable" "-,Yes" newline bitfld.word 0x00 1. " DQS1[8] ,DQS1 DP 8 periodic CPC update disable" "-,Yes" bitfld.word 0x00 0. " DQS1[7] ,DQS1 DP 7 periodic CPC update disable" "-,Yes" rgroup.word (dcr:0x80030000+0xD004)++0x01 line.word 0x00 "DFICNTL_CPC_UPDATE_STATUS_0,DFI CPC Update Status 0" bitfld.word 0x00 15. " DQS1[6] ,DQS1 DP 6 CPC update status" "Error,Successful" bitfld.word 0x00 14. " [5] ,DQS1 DP 5 CPC update status" "Error,Successful" bitfld.word 0x00 13. " [4] ,DQS1 DP 4 CPC update status" "Error,Successful" bitfld.word 0x00 12. " [3] ,DQS1 DP 3 CPC update status" "Error,Successful" newline bitfld.word 0x00 11. " [2] ,DQS1 DP 2 CPC update status" "Error,Successful" bitfld.word 0x00 10. " [1] ,DQS1 DP 1 CPC update status" "Error,Successful" bitfld.word 0x00 9. " [0] ,DQS1 DP 0 CPC update status" "Error,Successful" newline bitfld.word 0x00 8. " DQS0[8] ,DQS0 DP 8 CPC update status" "Error,Successful" bitfld.word 0x00 7. " [7] ,DQS0 DP 7 CPC update status" "Error,Successful" bitfld.word 0x00 6. " [6] ,DQS0 DP 6 CPC update status" "Error,Successful" bitfld.word 0x00 5. " [5] ,DQS0 DP 5 CPC update status" "Error,Successful" newline bitfld.word 0x00 4. " [4] ,DQS0 DP 4 CPC update status" "Error,Successful" bitfld.word 0x00 3. " [3] ,DQS0 DP 3 CPC update status" "Error,Successful" bitfld.word 0x00 2. " [2] ,DQS0 DP 2 CPC update status" "Error,Successful" bitfld.word 0x00 1. " [1] ,DQS0 DP 1 CPC update status" "Error,Successful" newline bitfld.word 0x00 0. " [0] ,DQS0 DP 0 CPC update status" "Error,Successful" rgroup.word (dcr:0x80030000+0xD005)++0x01 line.word 0x00 "DFICNTL_CPC_UPDATE_STATUS_1,DFI CPC Update Status 1" bitfld.word 0x00 5. " ADR[3] ,ADR3 CPC update status" "Error,Successful" bitfld.word 0x00 4. " [2] ,ADR2 CPC update status" "Error,Successful" bitfld.word 0x00 3. " [1] ,ADR1 CPC update status" "Error,Successful" bitfld.word 0x00 2. " [0] ,ADR0 CPC update status" "Error,Successful" newline bitfld.word 0x00 1. " DQS1[8] ,DQS1 DP 8 CPC update status" "Error,Successful" bitfld.word 0x00 0. " DQS1[7] ,DQS1 DP 7 CPC update status" "Error,Successful" group.word (dcr:0x80030000+0xD006)++0x01 line.word 0x00 "DFICNTL_WL_DQS0_GROUP,DFI Write Level DQS0 Group Register" bitfld.word 0x00 8. " DQS0[8] ,DQS0 DP 8 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 7. " [7] ,DQS0 DP 7 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 6. " [6] ,DQS0 DP 6 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 5. " [5] ,DQS0 DP 5 write level cycle adjust enable" "-,Enabled" newline bitfld.word 0x00 4. " [4] ,DQS0 DP 4 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 3. " [3] ,DQS0 DP 3 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 2. " [2] ,DQS0 DP 2 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 1. " [1] ,DQS0 DP 1 write level cycle adjust enable" "-,Enabled" newline bitfld.word 0x00 0. " [0] ,DQS0 DP 0 write level cycle adjust enable" "-,Enabled" group.word (dcr:0x80030000+0xD007)++0x01 line.word 0x00 "DFICNTL_WL_DQS1_GROUP,DFI Write Level DQS1 Group Register" bitfld.word 0x00 8. " DQS1[8] ,DQS1 DP 8 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 7. " [7] ,DQS1 DP 7 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 6. " [6] ,DQS1 DP 6 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 5. " [5] ,DQS1 DP 5 write level cycle adjust enable" "-,Enabled" newline bitfld.word 0x00 4. " [4] ,DQS1 DP 4 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 3. " [3] ,DQS1 DP 3 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 2. " [2] ,DQS1 DP 2 write level cycle adjust enable" "-,Enabled" bitfld.word 0x00 1. " [1] ,DQS1 DP 1 write level cycle adjust enable" "-,Enabled" newline bitfld.word 0x00 0. " [0] ,DQS1 DP 0 write level cycle adjust enable" "-,Enabled" group.word (dcr:0x80030000+0xD008)++0x01 line.word 0x00 "DFICNTL_WL_CNTL,DFI Write Level Control Register" bitfld.word 0x00 3.--5. " WLCAR ,Write level cycle adjust rank" "0,1,2,3,4,5,6,7" bitfld.word 0x00 2. " WLDI ,Write level delay increment" "Decrement,Increment" bitfld.word 0x00 1. " WLCA ,Write level cycle adjust" "-,Adjusted" bitfld.word 0x00 0. " WLRE ,Write level request enable" "-,Enabled" group.word (dcr:0x80030000+0xD009)++0x01 line.word 0x00 "DFICNTL_RDL_CNTL,DFI Read level Control Register" bitfld.word 0x00 3. " RDE ,Runtime deskew enable" "-,Enabled" bitfld.word 0x00 2. " RRE ,Runtime readeye enable" "-,Enabled" bitfld.word 0x00 1. " IPDE ,Initial post deskew enable" "-,Enabled" bitfld.word 0x00 0. " IPDE ,Initial pre-deskew enable" "-,Enabled" tree.end tree "Address Command Delay Control Registers" tree "ADR 0" width 8. if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x0+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif group.word (dcr:0x80030000+0x0+0x8010)++0x01 line.word 0x00 "VCR0,VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." newline group.word (dcr:0x80030000+0x0+0xFF)++0x01 line.word 0x00 "CR,Configuration Register" bitfld.word 0x00 2. " COMPENSATION_TYPE_MEMCLK[1] ,MEMCLK DIMM1 compensation type" "PVT,Raw" bitfld.word 0x00 1. " COMPENSATION_TYPE_MEMCLK[0] ,MEMCLK DIMM0 compensation type" "PVT,Raw" bitfld.word 0x00 0. " COMPENSATION_TYPE ,Compensation type" "PVT,Raw" rgroup.word (dcr:0x80030000+0x0+0xF6)++0x01 line.word 0x00 "DCFR,Delay CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" width 0x0B tree.end tree "ADR 1" width 8. if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x100+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif group.word (dcr:0x80030000+0x100+0x8010)++0x01 line.word 0x00 "VCR0,VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." newline group.word (dcr:0x80030000+0x100+0xFF)++0x01 line.word 0x00 "CR,Configuration Register" bitfld.word 0x00 2. " COMPENSATION_TYPE_MEMCLK[1] ,MEMCLK DIMM1 compensation type" "PVT,Raw" bitfld.word 0x00 1. " COMPENSATION_TYPE_MEMCLK[0] ,MEMCLK DIMM0 compensation type" "PVT,Raw" bitfld.word 0x00 0. " COMPENSATION_TYPE ,Compensation type" "PVT,Raw" rgroup.word (dcr:0x80030000+0x100+0xF6)++0x01 line.word 0x00 "DCFR,Delay CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" width 0x0B tree.end tree "ADR 2" width 8. if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x200+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x200+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x200+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif group.word (dcr:0x80030000+0x200+0x8010)++0x01 line.word 0x00 "VCR0,VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." newline group.word (dcr:0x80030000+0x200+0xFF)++0x01 line.word 0x00 "CR,Configuration Register" bitfld.word 0x00 2. " COMPENSATION_TYPE_MEMCLK[1] ,MEMCLK DIMM1 compensation type" "PVT,Raw" bitfld.word 0x00 1. " COMPENSATION_TYPE_MEMCLK[0] ,MEMCLK DIMM0 compensation type" "PVT,Raw" bitfld.word 0x00 0. " COMPENSATION_TYPE ,Compensation type" "PVT,Raw" rgroup.word (dcr:0x80030000+0x200+0xF6)++0x01 line.word 0x00 "DCFR,Delay CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" width 0x0B tree.end tree "ADR 3" width 8. if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x0)++0x01 line.word 0x00 "BDSR0,Bit 0 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x1)++0x01 line.word 0x00 "BDSR1,Bit 1 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x2)++0x01 line.word 0x00 "BDSR2,Bit 2 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x3)++0x01 line.word 0x00 "BDSR3,Bit 3 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x4)++0x01 line.word 0x00 "BDSR4,Bit 4 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x5)++0x01 line.word 0x00 "BDSR5,Bit 5 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x6)++0x01 line.word 0x00 "BDSR6,Bit 6 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x7)++0x01 line.word 0x00 "BDSR7,Bit 7 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x8)++0x01 line.word 0x00 "BDSR8,Bit 8 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0x9)++0x01 line.word 0x00 "BDSR9,Bit 9 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0xA)++0x01 line.word 0x00 "BDSR10,Bit 10 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0xB)++0x01 line.word 0x00 "BDSR11,Bit 11 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0xC)++0x01 line.word 0x00 "BDSR12,Bit 12 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0xD)++0x01 line.word 0x00 "BDSR13,Bit 13 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0xE)++0x01 line.word 0x00 "BDSR14,Bit 14 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif if ((per.w.le(dcr:0x80030000+0x300+0xFF)&0x01)==0x00) group.word (dcr:0x80030000+0x300+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x300+0xF)++0x01 line.word 0x00 "BDSR15,Bit 15 Delay Settings Register" bitfld.word 0x00 7.--8. " DELAY_SETTING[8:7] ,Clock delay resolution" "0 degrees,90 degrees,180 degrees,270 degrees" hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif group.word (dcr:0x80030000+0x300+0x8010)++0x01 line.word 0x00 "VCR0,VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." newline group.word (dcr:0x80030000+0x300+0xFF)++0x01 line.word 0x00 "CR,Configuration Register" bitfld.word 0x00 2. " COMPENSATION_TYPE_MEMCLK[1] ,MEMCLK DIMM1 compensation type" "PVT,Raw" bitfld.word 0x00 1. " COMPENSATION_TYPE_MEMCLK[0] ,MEMCLK DIMM0 compensation type" "PVT,Raw" bitfld.word 0x00 0. " COMPENSATION_TYPE ,Compensation type" "PVT,Raw" rgroup.word (dcr:0x80030000+0x300+0xF6)++0x01 line.word 0x00 "DCFR,Delay CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" width 0x0B tree.end tree.end tree "Read Delay Control Registers" tree "Byte 0" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 1" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x20+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x20+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x20+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x20+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x20+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x20+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x20+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x20+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x20+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x20+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x20+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x20+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x20+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x20+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x20+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x20+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x20+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x20+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x20+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x20+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x20+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x20+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x20+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x20+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x20+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x20+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x20+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x20+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x20+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x20+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x20+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x20+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x20+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x20+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 2" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x40+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x40+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x40+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x40+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x40+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x40+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x40+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x40+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x40+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x40+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x40+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x40+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x40+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x40+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x40+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x40+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x40+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x40+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x40+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x40+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x40+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x40+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x40+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x40+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x40+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x40+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x40+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x40+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x40+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x40+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x40+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x40+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x40+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x40+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 3" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x60+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x60+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x60+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x60+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x60+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x60+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x60+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x60+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x60+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x60+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x60+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x60+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x60+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x60+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x60+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x60+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x60+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x60+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x60+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x60+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x60+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x60+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x60+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x60+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x60+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x60+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x60+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x60+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x60+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x60+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x60+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x60+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x60+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x60+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 4" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x80+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x80+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x80+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x80+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x80+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x80+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x80+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x80+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x80+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x80+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x80+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x80+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x80+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x80+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x80+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x80+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x80+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x80+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x80+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x80+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x80+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x80+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x80+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x80+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x80+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x80+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x80+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x80+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x80+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x80+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x80+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x80+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x80+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x80+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 5" width 14. tree "Rank 0" group.word (dcr:0x80030000+0xA0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0xA0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0xA0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0xA0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0xA0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0xA0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0xA0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0xA0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xA0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xA0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xA0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0xA0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0xA0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0xA0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0xA0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0xA0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0xA0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xA0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xA0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xA0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0xA0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xA0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xA0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xA0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0xA0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xA0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xA0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xA0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0xA0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xA0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xA0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xA0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xA0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0xA0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 6" width 14. tree "Rank 0" group.word (dcr:0x80030000+0xC0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0xC0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0xC0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0xC0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0xC0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0xC0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0xC0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0xC0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xC0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xC0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xC0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0xC0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0xC0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0xC0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0xC0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0xC0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0xC0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xC0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xC0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xC0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0xC0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xC0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xC0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xC0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0xC0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xC0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xC0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xC0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0xC0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xC0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xC0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xC0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xC0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0xC0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 7" width 14. tree "Rank 0" group.word (dcr:0x80030000+0xE0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0xE0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0xE0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0xE0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0xE0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0xE0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0xE0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0xE0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0xE0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0xE0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0xE0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0xE0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0xE0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0xE0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0xE0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0xE0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0xE0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xE0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xE0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xE0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0xE0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xE0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xE0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xE0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0xE0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xE0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xE0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xE0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0xE0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0xE0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0xE0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0xE0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0xE0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0xE0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 8" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x100+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x100+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x100+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x100+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x100+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x100+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x100+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x100+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x100+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x100+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x100+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x100+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x100+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x100+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x100+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x100+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x100+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x100+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x100+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x100+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x100+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x100+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x100+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x100+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x100+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x100+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x100+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x100+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x100+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x100+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x100+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x100+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x100+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x100+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 9" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x120+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x120+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x120+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x120+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x120+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x120+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x120+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x120+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x120+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x120+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x120+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x120+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x120+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x120+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x120+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x120+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x120+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x120+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x120+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x120+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x120+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x120+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x120+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x120+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x120+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x120+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x120+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x120+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x120+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x120+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x120+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x120+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x120+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x120+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 10" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x140+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x140+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x140+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x140+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x140+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x140+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x140+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x140+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x140+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x140+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x140+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x140+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x140+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x140+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x140+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x140+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x140+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x140+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x140+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x140+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x140+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x140+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x140+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x140+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x140+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x140+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x140+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x140+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x140+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x140+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x140+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x140+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x140+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x140+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 11" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x160+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x160+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x160+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x160+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x160+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x160+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x160+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x160+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x160+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x160+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x160+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x160+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x160+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x160+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x160+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x160+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x160+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x160+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x160+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x160+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x160+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x160+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x160+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x160+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x160+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x160+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x160+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x160+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x160+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x160+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x160+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x160+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x160+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x160+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 12" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x180+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x180+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x180+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x180+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x180+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x180+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x180+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x180+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x180+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x180+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x180+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x180+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x180+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x180+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x180+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x180+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x180+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x180+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x180+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x180+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x180+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x180+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x180+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x180+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x180+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x180+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x180+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x180+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x180+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x180+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x180+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x180+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x180+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x180+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 13" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x1A0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x1A0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x1A0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x1A0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x1A0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x1A0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x1A0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x1A0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1A0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1A0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1A0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x1A0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x1A0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x1A0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x1A0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x1A0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x1A0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1A0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1A0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1A0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x1A0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1A0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1A0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1A0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x1A0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1A0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1A0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1A0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x1A0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1A0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1A0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1A0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1A0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x1A0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 14" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x1C0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x1C0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x1C0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x1C0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x1C0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x1C0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x1C0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x1C0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1C0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1C0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1C0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x1C0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x1C0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x1C0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x1C0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x1C0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x1C0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1C0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1C0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1C0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x1C0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1C0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1C0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1C0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x1C0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1C0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1C0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1C0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x1C0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1C0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1C0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1C0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1C0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x1C0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree "Byte 15" width 14. tree "Rank 0" group.word (dcr:0x80030000+0x1E0+0x0+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x0+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x0+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0x0+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x0+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x0+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x1E0+0x200+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x200+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x200+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0x200+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x200+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x200+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x1E0+0x400+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x400+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x400+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0x400+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x400+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x400+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x1E0+0x600+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x600+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x600+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0x600+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x600+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x600+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x1E0+0x800+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x800+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x800+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0x800+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0x800+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0x800+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x1E0+0xA00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0xA00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0xA00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0xA00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0xA00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0xA00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x1E0+0xC00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0xC00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0xC00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0xC00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0xC00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0xC00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x1E0+0xE00+0x4000)++0x01 "Nibble 0" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0xE00+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0xE00+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" group.word (dcr:0x80030000+0x1E0+0xE00+0x10+0x4000)++0x01 "Nibble 1" line.word 0x00 "DBDSR,DQS Bits Delay Settings Register" hexmask.word.byte 0x00 0.--7. 1. " DQS_DELAY ,DQS delay" group.word (dcr:0x80030000+0x1E0+0xE00+0x10+0x4001)++0x01 line.word 0x00 "DBFDRR,DQS Bits FP Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " FP_DELAY ,Fail to passing point DQS delay" group.word (dcr:0x80030000+0x1E0+0xE00+0x10+0x4002)++0x01 line.word 0x00 "DBPDRR,DQS Bits PF Delay Result Register" hexmask.word.byte 0x00 0.--7. 1. " PF_DELAY ,Pass to fail point DQS delay" tree.end newline group.word (dcr:0x80030000+0x1E0+0x4003)++0x01 line.word 0x00 "CONFIG_0_REG,Configuration Register 0" bitfld.word 0x00 14. " INHIBIT_DQS_DELAY_UPDATE ,Delay update inhibit" "-,Inhibited" bitfld.word 0x00 12.--13. " DQS_CENTERING_BURST_WINDOW ,INIT and periodic read eye centring beats of data" "1-4,3-6,5-8,1-8" bitfld.word 0x00 9.--11. " RT_DELAY_WINDOW ,RT delay window" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8. " READ_EYE_CPC_DIV ,CPC_FRACTION for read eye centring divider" "/2,/4" newline bitfld.word 0x00 7. " CPC_FRACTION_LIMIT ,DQS/DQ delay limit" "-,Limited" bitfld.word 0x00 4.--6. " CPC_FRACTION_MARGIN ,CPC_FRACTION delay limit additional margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 3. " DESKEW_CPC_DIV ,CPC_FRACTION for deskew divider" "/2,/4" bitfld.word 0x00 2. " CONSEQ_PASS_MODE ,Consecutive pass mode value to use" "CONFIG_1_REG[4:0],Lower of: CONFIG_1_REG[4:0] or CPC fraction" newline bitfld.word 0x00 1. " DISABLE_BYTE ,Disable calibrations for this byte" "-,Yes" newline group.word (dcr:0x80030000+0x1E0+0x5003)++0x01 line.word 0x00 "CONFIG_1_REG,Configuration Register 1" bitfld.word 0x00 13. " STATE_101_SWITCH ,RDDLY prevent from entering 101 state" "-,Prevented" newline bitfld.word 0x00 12. " MPR[7] ,Rank 7 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 11. " [6] ,Rank 6 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 10. " [5] ,Rank 5 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 9. " [4] ,Rank 4 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 8. " [3] ,Rank 3 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 7. " [2] ,Rank 2 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 6. " [1] ,Rank 1 single bit MPR" "All DQ bits,Single bit" bitfld.word 0x00 5. " [0] ,Rank 0 single bit MPR" "All DQ bits,Single bit" newline bitfld.word 0x00 0.--4. " CONSEQ_PASS ,Consecutive passes required to determine fail to pass point in DQS centring" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1E0+0x4004)++0x01 line.word 0x00 "CER0,Compare Even Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 0 data compare value" group.word (dcr:0x80030000+0x1E0+0x4005)++0x01 line.word 0x00 "COR0,Compare Odd Register 0" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 1 data compare value" group.word (dcr:0x80030000+0x1E0+0x4006)++0x01 line.word 0x00 "CER1,Compare Even Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 2 data compare value" group.word (dcr:0x80030000+0x1E0+0x4007)++0x01 line.word 0x00 "COR1,Compare Odd Register 1" hexmask.word.byte 0x00 0.--7. 1. " COMPARE_VALUE ,Read eye algorithm cycle 3 data compare value" tree "Mapped Rank 0" group.word (dcr:0x80030000+0x1E0+0x0+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x0+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1E0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1E0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1E0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 1" group.word (dcr:0x80030000+0x1E0+0x200+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x200+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1E0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1E0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1E0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 2" group.word (dcr:0x80030000+0x1E0+0x400+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x400+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1E0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1E0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1E0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end tree "Mapped Rank 3" group.word (dcr:0x80030000+0x1E0+0x600+0x4008)++0x01 "DQ 0" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x01+0x4008)++0x01 "DQ 1" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x02+0x4008)++0x01 "DQ 2" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x03+0x4008)++0x01 "DQ 3" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x04+0x4008)++0x01 "DQ 4" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x05+0x4008)++0x01 "DQ 5" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x06+0x4008)++0x01 "DQ 6" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" group.word (dcr:0x80030000+0x1E0+0x600+0x07+0x4008)++0x01 "DQ 7" line.word 0x00 "DDR,DQ Delay Register" hexmask.word.byte 0x00 0.--6. 1. " DQ_DELAY ,DQ delay" rgroup.word (dcr:0x80030000+0x1E0+0x5000)++0x01 "Nibble 0" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" rgroup.word (dcr:0x80030000+0x1E0+0x10+0x5000)++0x01 "Nibble 1" line.word 0x00 "LDQSDR,Latest DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQS_DELAY ,Previous deskew algorithm run DQS delay value" newline rgroup.word (dcr:0x80030000+0x1E0+0x5001)++0x01 line.word 0x00 "LDQDR,Latest DQ Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQ_DQ_DELAY ,Previous DQ delay value" tree.end newline rgroup.word (dcr:0x80030000+0x1E0+0x5002)++0x01 line.word 0x00 "ER,Error Register" bitfld.word 0x00 3. " DQ_DELAY_OVERFLOW ,DQ delay overflow" "-,Overflow" bitfld.word 0x00 2. " NO_EYE_DETECTED ,Initial read eye not detected" "Detected,Not detected" bitfld.word 0x00 1. " READEYE_OVERFLOW ,Read eye overflow" "-,Overflow" bitfld.word 0x00 0. " DESKEW_OVERFLOW ,Deskew overflow" "-,Overflow" width 0x0B tree.end tree.end tree "Write Level Control Registers" tree "Byte 0" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x0+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x0+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x0+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x0+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x0+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x0+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x0+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 1" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x20+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x20+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x20+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x20+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x20+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x20+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x20+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x20+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x20+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x20+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x20+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x20+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 2" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x40+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x40+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x40+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x40+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x40+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x40+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x40+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x40+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x40+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x40+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x40+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x40+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 3" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x60+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x60+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x60+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x60+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x60+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x60+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x60+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x60+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x60+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x60+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x60+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x60+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 4" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x80+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x80+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x80+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x80+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x80+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x80+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x80+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x80+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x80+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x80+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x80+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x80+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 5" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xA0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xA0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xA0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xA0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0xA0+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0xA0+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0xA0+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0xA0+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0xA0+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0xA0+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0xA0+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 6" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xC0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xC0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xC0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xC0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0xC0+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0xC0+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0xC0+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0xC0+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0xC0+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0xC0+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0xC0+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 7" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0xE0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0xE0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0xE0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0xE0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0xE0+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0xE0+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0xE0+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0xE0+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0xE0+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0xE0+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0xE0+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 8" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x100+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x100+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x100+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x100+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x100+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x100+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x100+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x100+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x100+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x100+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x100+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x100+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 9" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x120+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x120+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x120+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x120+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x120+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x120+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x120+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x120+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x120+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x120+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x120+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x120+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 10" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x140+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x140+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x140+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x140+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x140+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x140+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x140+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x140+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x140+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x140+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x140+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x140+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 11" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x160+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x160+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x160+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x160+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x160+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x160+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x160+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x160+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x160+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x160+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x160+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x160+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 12" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x180+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x180+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x180+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x180+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x180+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x180+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x180+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x180+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x180+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x180+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x180+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x180+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 13" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1A0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1A0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x1A0+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x1A0+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x1A0+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x1A0+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x1A0+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x1A0+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x1A0+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end tree "Byte 14" width 11. tree "Mapped Rank 0" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x0+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x0+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 1" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x200+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x200+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 2" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x400+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x400+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end tree "Mapped Rank 3" tree "DQ0" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x600+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ1" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x01+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ2" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x02+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "DQ3" if ((per.w.le(dcr:0x80030000+0x1C0+0x2FFF)&0x01)==0x00) group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x2000)++0x01 "Nibble 0" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x10+0x2000)++0x01 "Nibble 1" line.word 0x00 "DQBDSR,DQ Bit Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" group.word (dcr:0x80030000+0x1C0+0x600+0x03+0x10+0x2004)++0x01 line.word 0x00 "DQSDSR,DQS Delay Setting Register" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree.end rgroup.word (dcr:0x80030000+0x1C0+0x200F)++0x01 "Nibble 0" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" rgroup.word (dcr:0x80030000+0x1C0+0x10+0x200F)++0x01 "Nibble 1" line.word 0x00 "LCFR,Level CPC Fraction Register" hexmask.word.byte 0x00 0.--6. 1. " CPC_FRACTION ,CPC fraction" newline rgroup.word (dcr:0x80030000+0x1C0+0x200E)++0x01 line.word 0x00 "LBSR1,Level Byte Status Register 1" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" hexmask.word 0x00 3.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" newline bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION ,Collision error" "-,Error" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND[1] ,High order nibble rising edge not found error" "-,Error" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND[0] ,Low order nibble rising edge not found error" "-,Error" rgroup.word (dcr:0x80030000+0x1C0+0x200D)++0x01 line.word 0x00 "LBSR2,Level Byte Status Register 2" bitfld.word 0x00 15. " SM_ACTIVE ,Write levelling state machine active" "-,Active" bitfld.word 0x00 13.--14. " DQ_NIBBLE_OR ,Memory clock samples per nibble" "0,1,2,3" bitfld.word 0x00 12. " ACTIVE_NIBBLE ,Active nibble" "0,1" newline hexmask.word 0x00 1.--11. 1. " WR_LVL_SM ,Write levelling state machine one hot state" bitfld.word 0x00 0. " ZERO_DETECTED ,Zero detected" "-,Detected" group.word (dcr:0x80030000+0x1C0+0x200C)++0x01 line.word 0x00 "LEMRB,Level Error Mask Register Byte" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x1C0+0x8400)++0x01 line.word 0x00 "LBVCR0,Level Byte VREG Control Register 0" bitfld.word 0x00 13.--14. " VREGCHDYN_O ,Loop gain" "0%,+15%,+30%,+45%" bitfld.word 0x00 5.--6. " VREGRANGE_O ,PFET transistor width" "1.5 V,1.35 V,,1.25 V" bitfld.word 0x00 0.--4. " VREGC_O ,VREGC voltage control" "0.793 V,0.807 V,0.821 V,0.835 V,0.850 V,0.866 V,0.882 V,0.898 V,0.915 V,0.933 V,0.952 V,0.971 V,0.992 V,1.013 V,1.035 V,1.058 V,1.082 V,1.107 V,1.133 V,1.161 V,1.190 V,1.221 V,?..." group.word (dcr:0x80030000+0x1C0+0x8403)++0x01 line.word 0x00 "LBVCR3,Level Byte VREG Control Register 3" bitfld.word 0x00 15. " ECOA0CSWITCH_O ,Delay line enable" "-,Enabled" width 0x0B tree.end width 11. tree "Mapped Rank 0" if ((per.w.le(dcr:0x80030000+0x2FFF)&0x01)==0x00) wgroup.word (dcr:0x80030000+0x0+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else wgroup.word (dcr:0x80030000+0x0+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "Mapped Rank 1" if ((per.w.le(dcr:0x80030000+0x2FFF)&0x01)==0x00) wgroup.word (dcr:0x80030000+0x200+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else wgroup.word (dcr:0x80030000+0x200+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "Mapped Rank 2" if ((per.w.le(dcr:0x80030000+0x2FFF)&0x01)==0x00) wgroup.word (dcr:0x80030000+0x400+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else wgroup.word (dcr:0x80030000+0x400+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end tree "Mapped Rank 3" if ((per.w.le(dcr:0x80030000+0x2FFF)&0x01)==0x00) wgroup.word (dcr:0x80030000+0x600+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else wgroup.word (dcr:0x80030000+0x600+0x3168)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif tree.end if ((per.w.le(dcr:0x80030000+0x2FFF)&0x01)==0x00) wgroup.word (dcr:0x80030000+0x3F88)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Ranks, Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." bitfld.word 0x00 2.--6. " DELAY_SETTING[6:2] ,Delay setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else wgroup.word (dcr:0x80030000+0x3F88)++0x01 line.word 0x00 "DQDQSDSBR,DQ/DQS Delay Setting Broadcast Register (All Ranks, Bytes, Nibbles And Bits)" bitfld.word 0x00 7.--10. " DELAY_SETTING[10:7] ,Clock delay resolution" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,?..." hexmask.word.byte 0x00 0.--6. 1. " DELAY_SETTING[6:0] ,Delay setting" endif hgroup.word (dcr:0x80030000+0x2FFE)++0x01 hide.word 0x00 "LER,Level Error Register" in group.word (dcr:0x80030000+0x3FFC)++0x01 line.word 0x00 "LEMBR,Level Error Mask Broadcast Register All Bytes" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" newline bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x2FFD)++0x01 line.word 0x00 "LEMR,Level Error Mask Register" bitfld.word 0x00 2. " ERROR_REG_WR_COLLISION_MASK ,Collision error mask" "0,1" newline bitfld.word 0x00 1. " ERROR_RISING_EDGE_NOT_FOUND_MASK[1] ,High order nibble rising edge not found error mask" "0,1" bitfld.word 0x00 0. " ERROR_RISING_EDGE_NOT_FOUND_MASK[0] ,Low order nibble rising edge not found error mask" "0,1" group.word (dcr:0x80030000+0x2FFF)++0x01 line.word 0x00 "LCR,Level Configuration Register" bitfld.word 0x00 15. " ENABLE_QUICK_DLYSHORTGATE_SHUTOFF ,Shut-off type" "Normal,Quick" bitfld.word 0x00 14. " HIGH_SWITCH_RATE_DQS ,DQS pulse type" "Single shot,Continuously switching" newline bitfld.word 0x00 10.--13. " TWLO_TWLOE_WAIT_COUNT ,t_WLO and t_WLOE DQ sample time" "0 clocks,4 clocks,8 clocks,12 clocks,16 clocks,20 clocks,24 clocks,28 clocks,32 clocks,36 clocks,40 clocks,44 clocks,48 clocks,52 clocks,56 clocks,60 clocks" bitfld.word 0x00 7. " ENHANCED_DIGITAL_FILTER ,Digital filter mode" "Normal,Enhanced" newline bitfld.word 0x00 3.--6. " MAX_DELAY_DELTA ,Maximum delay delta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 1.--2. " NUM_SAMPLES ,Samples number" "8 steps - 16 samples,4 steps - 32 samples,2 steps - 64 samples,1 step - 128 samples" newline bitfld.word 0x00 0. " COMPENSATION_TYPE ,Compensation type" "PVT,Raw" tree.end tree "Read Calibration Control Registers" width 13. tree "Byte 0" tree "Rank 0" group.word (dcr:0x80030000+0x0+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x0+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x0+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x0+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x0+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x0+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x0+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x0+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x0+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x0+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x0+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x0+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 1" tree "Rank 0" group.word (dcr:0x80030000+0x20+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x20+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x20+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x20+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x20+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x20+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x20+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x20+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x20+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x20+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x20+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x20+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x20+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 2" tree "Rank 0" group.word (dcr:0x80030000+0x40+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x40+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x40+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x40+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x40+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x40+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x40+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x40+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x40+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x40+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x40+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x40+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x40+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 3" tree "Rank 0" group.word (dcr:0x80030000+0x60+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x60+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x60+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x60+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x60+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x60+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x60+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x60+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x60+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x60+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x60+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x60+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x60+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 4" tree "Rank 0" group.word (dcr:0x80030000+0x80+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x80+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x80+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x80+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x80+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x80+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x80+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x80+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x80+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x80+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x80+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x80+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x80+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 5" tree "Rank 0" group.word (dcr:0x80030000+0xA0+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0xA0+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0xA0+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0xA0+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0xA0+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0xA0+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0xA0+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0xA0+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA0+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0xA0+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0xA0+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0xA0+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0xA0+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 6" tree "Rank 0" group.word (dcr:0x80030000+0xC0+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0xC0+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0xC0+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0xC0+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0xC0+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0xC0+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0xC0+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0xC0+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC0+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0xC0+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0xC0+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0xC0+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0xC0+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 7" tree "Rank 0" group.word (dcr:0x80030000+0xE0+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0xE0+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0xE0+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0xE0+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0xE0+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0xE0+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0xE0+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0xE0+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE0+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0xE0+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0xE0+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0xE0+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0xE0+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 8" tree "Rank 0" group.word (dcr:0x80030000+0x100+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x100+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x100+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x100+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x100+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x100+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x100+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x100+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x100+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x100+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x100+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x100+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x100+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 9" tree "Rank 0" group.word (dcr:0x80030000+0x120+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x120+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x120+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x120+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x120+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x120+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x120+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x120+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x120+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x120+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x120+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x120+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x120+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 10" tree "Rank 0" group.word (dcr:0x80030000+0x140+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x140+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x140+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x140+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x140+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x140+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x140+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x140+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x140+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x140+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x140+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x140+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x140+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 11" tree "Rank 0" group.word (dcr:0x80030000+0x160+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x160+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x160+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x160+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x160+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x160+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x160+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x160+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x160+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x160+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x160+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x160+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x160+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 12" tree "Rank 0" group.word (dcr:0x80030000+0x180+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x180+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x180+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x180+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x180+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x180+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x180+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x180+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x180+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x180+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x180+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x180+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x180+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 13" tree "Rank 0" group.word (dcr:0x80030000+0x1A0+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x1A0+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x1A0+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x1A0+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x1A0+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x1A0+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x1A0+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x1A0+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1A0+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x1A0+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x1A0+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x1A0+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x1A0+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Byte 14" tree "Rank 0" group.word (dcr:0x80030000+0x1C0+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" group.word (dcr:0x80030000+0x1C0+0x200+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0x200+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" group.word (dcr:0x80030000+0x1C0+0x400+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0x400+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" group.word (dcr:0x80030000+0x1C0+0x600+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0x600+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" group.word (dcr:0x80030000+0x1C0+0x800+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0x800+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" group.word (dcr:0x80030000+0x1C0+0xA00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0xA00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" group.word (dcr:0x80030000+0x1C0+0xC00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0xC00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" group.word (dcr:0x80030000+0x1C0+0xE00+0x6000)++0x01 "Nibble 0" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x1C0+0xE00+0x10+0x6000)++0x01 "Nibble 1" line.word 0x00 "DQSGDSR,DQS Gate Delay Setting Register" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end group.word (dcr:0x80030000+0x1C0+0x6001)++0x01 "Nibble 0" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x1C0+0x10+0x6001)++0x01 "Nibble 1" line.word 0x00 "DQSDR,DQS Delay Register" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" newline rgroup.word (dcr:0x80030000+0x1C0+0x6003)++0x01 line.word 0x00 "BSR,Byte Status Register" bitfld.word 0x00 15. " PREAMBLE_NOT_FOUND_ERROR[1] ,Nibble 1 DQS preamble not found error" "-,Error" bitfld.word 0x00 14. " PREAMBLE_NOT_FOUND_ERROR[0] ,Nibble 0 DQS preamble not found error" "-,Error" bitfld.word 0x00 12. " REG_WRITE_COLLISION_DETECTED ,Register write collision" "-,Collision" newline bitfld.word 0x00 11. " BUSY_ERROR_NIBBLE_1 ,Nibble 1 busy error" "-,Error" bitfld.word 0x00 10. " BUSY_ERROR_NIBBLE_0 ,Nibble 0 busy error" "-,Error" bitfld.word 0x00 0. " BUSY ,Byte level state machine busy" "-,Busy" group.word (dcr:0x80030000+0x1C0+0x6004)++0x01 line.word 0x00 "IE/MCTERMBR,Master Control IE/MCTERM Byte Register" bitfld.word 0x00 6. " MCTERM_DQS_1 ,MCTERM DQS 1 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 5. " IE_DQS_1 ,IE DQS static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 4. " MCTERM_DQS_0 ,MCTERM DQS 0 static override" "Dynamically controlled,Constantly enabled" newline bitfld.word 0x00 3. " IE_DQS_0 ,IE DQS 0 static override" "Dynamically controlled,Constantly enabled" bitfld.word 0x00 0.--2. " IE_MCTERM_OFFSET ,IE/MCTERM assertion offset" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" tree.end tree "Rank 0" wgroup.word (dcr:0x80030000+0x0+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x0+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 1" wgroup.word (dcr:0x80030000+0x200+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x200+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 2" wgroup.word (dcr:0x80030000+0x400+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x400+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 3" wgroup.word (dcr:0x80030000+0x600+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x600+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 4" wgroup.word (dcr:0x80030000+0x800+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x800+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 5" wgroup.word (dcr:0x80030000+0xA00+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xA00+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 6" wgroup.word (dcr:0x80030000+0xC00+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xC00+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end tree "Rank 7" wgroup.word (dcr:0x80030000+0xE00+0x71E0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Bytes And Bits Per Rank)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0xE00+0x6002)++0x01 line.word 0x00 "ORDR,Observed Rank Delay Register" bitfld.word 0x00 0.--3. " OBSERVED_RANK_DELAY ,Largest DQS_RANK_DELAY across all bytes and nibbles" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" tree.end rgroup.word (dcr:0x80030000+0x0+0x6FE7)++0x01 "Nibble 0" line.word 0x00 "DQSAR,DQS Active Register" bitfld.word 0x00 9. " DQSACTIVE[9] ,DPRDS byte lane 9 active read calibration enabled" "-,Enabled" bitfld.word 0x00 8. " [8] ,DPRDS byte lane 8 active read calibration enabled" "-,Enabled" bitfld.word 0x00 7. " [7] ,DPRDS byte lane 7 active read calibration enabled" "-,Enabled" bitfld.word 0x00 6. " [6] ,DPRDS byte lane 6 active read calibration enabled" "-,Enabled" bitfld.word 0x00 5. " [5] ,DPRDS byte lane 5 active read calibration enabled" "-,Enabled" newline bitfld.word 0x00 4. " [4] ,DPRDS byte lane 4 active read calibration enabled" "-,Enabled" bitfld.word 0x00 3. " [3] ,DPRDS byte lane 3 active read calibration enabled" "-,Enabled" bitfld.word 0x00 2. " [2] ,DPRDS byte lane 2 active read calibration enabled" "-,Enabled" bitfld.word 0x00 1. " [1] ,DPRDS byte lane 1 active read calibration enabled" "-,Enabled" bitfld.word 0x00 0. " [0] ,DPRDS byte lane 0 active read calibration enabled" "-,Enabled" rgroup.word (dcr:0x80030000+0x0+0x6FE8)++0x01 line.word 0x00 "DER,Data Error Register" bitfld.word 0x00 9. " DATAERROR[9] ,DPRDS byte lane 9 data integrity error" "-,Error" bitfld.word 0x00 8. " [8] ,DPRDS byte lane 8 data integrity error" "-,Error" bitfld.word 0x00 7. " [7] ,DPRDS byte lane 7 data integrity error" "-,Error" bitfld.word 0x00 6. " [6] ,DPRDS byte lane 6 data integrity error" "-,Error" bitfld.word 0x00 5. " [5] ,DPRDS byte lane 5 data integrity error" "-,Error" newline bitfld.word 0x00 4. " [4] ,DPRDS byte lane 4 data integrity error" "-,Error" bitfld.word 0x00 3. " [3] ,DPRDS byte lane 3 data integrity error" "-,Error" bitfld.word 0x00 2. " [2] ,DPRDS byte lane 2 data integrity error" "-,Error" bitfld.word 0x00 1. " [1] ,DPRDS byte lane 1 data integrity error" "-,Error" bitfld.word 0x00 0. " [0] ,DPRDS byte lane 0 data integrity error" "-,Error" rgroup.word (dcr:0x80030000+0x0+0x6FEC)++0x01 line.word 0x00 "PR,Preamble Register" bitfld.word 0x00 9. " PREAMBLE_DETECT[9] ,DP8 byte lane 8 preamble detected" "-,Detected" bitfld.word 0x00 8. " [8] ,DP8 byte lane 8 preamble detected" "-,Detected" bitfld.word 0x00 7. " [7] ,DP8 byte lane 7 preamble detected" "-,Detected" bitfld.word 0x00 6. " [6] ,DP8 byte lane 6 preamble detected" "-,Detected" bitfld.word 0x00 5. " [5] ,DP8 byte lane 5 preamble detected" "-,Detected" newline bitfld.word 0x00 4. " [4] ,DP8 byte lane 4 preamble detected" "-,Detected" bitfld.word 0x00 3. " [3] ,DP8 byte lane 3 preamble detected" "-,Detected" bitfld.word 0x00 2. " [2] ,DP8 byte lane 2 preamble detected" "-,Detected" bitfld.word 0x00 1. " [1] ,DP8 byte lane 1 preamble detected" "-,Detected" bitfld.word 0x00 0. " [0] ,DP8 byte lane 0 preamble detected" "-,Detected" rgroup.word (dcr:0x80030000+0x0+0x6FEA)++0x01 line.word 0x00 "DQSGR,DQS Group Register" bitfld.word 0x00 9. " MC_RC_DQS_GROUP[9] ,Byte lane 9 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 8. " [8] ,Byte lane 8 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 7. " [7] ,Byte lane 7 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 6. " [6] ,Byte lane 6 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 5. " [5] ,Byte lane 5 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" newline bitfld.word 0x00 4. " [4] ,Byte lane 4 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 3. " [3] ,Byte lane 3 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 2. " [2] ,Byte lane 2 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 1. " [1] ,Byte lane 1 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 0. " [0] ,Byte lane 0 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" rgroup.word (dcr:0x80030000+0x0+0x6FE5)++0x01 line.word 0x00 "BEDQSR,Byte Error DQS Register" bitfld.word 0x00 9. " BYTE_ERROR_DQS[9] ,Byte lane 9 read calibration error" "-,Error" bitfld.word 0x00 8. " [8] ,Byte lane 8 read calibration error" "-,Error" bitfld.word 0x00 7. " [7] ,Byte lane 7 read calibration error" "-,Error" bitfld.word 0x00 6. " [6] ,Byte lane 6 read calibration error" "-,Error" bitfld.word 0x00 5. " [5] ,Byte lane 5 read calibration error" "-,Error" newline bitfld.word 0x00 4. " [4] ,Byte lane 4 read calibration error" "-,Error" bitfld.word 0x00 3. " [3] ,Byte lane 3 read calibration error" "-,Error" bitfld.word 0x00 2. " [2] ,Byte lane 2 read calibration error" "-,Error" bitfld.word 0x00 1. " [1] ,Byte lane 1 read calibration error" "-,Error" bitfld.word 0x00 0. " [0] ,Byte lane 0 read calibration error" "-,Error" rgroup.word (dcr:0x80030000+0x10+0x6FE7)++0x01 "Nibble 1" line.word 0x00 "DQSAR,DQS Active Register" bitfld.word 0x00 9. " DQSACTIVE[9] ,DPRDS byte lane 9 active read calibration enabled" "-,Enabled" bitfld.word 0x00 8. " [8] ,DPRDS byte lane 8 active read calibration enabled" "-,Enabled" bitfld.word 0x00 7. " [7] ,DPRDS byte lane 7 active read calibration enabled" "-,Enabled" bitfld.word 0x00 6. " [6] ,DPRDS byte lane 6 active read calibration enabled" "-,Enabled" bitfld.word 0x00 5. " [5] ,DPRDS byte lane 5 active read calibration enabled" "-,Enabled" newline bitfld.word 0x00 4. " [4] ,DPRDS byte lane 4 active read calibration enabled" "-,Enabled" bitfld.word 0x00 3. " [3] ,DPRDS byte lane 3 active read calibration enabled" "-,Enabled" bitfld.word 0x00 2. " [2] ,DPRDS byte lane 2 active read calibration enabled" "-,Enabled" bitfld.word 0x00 1. " [1] ,DPRDS byte lane 1 active read calibration enabled" "-,Enabled" bitfld.word 0x00 0. " [0] ,DPRDS byte lane 0 active read calibration enabled" "-,Enabled" rgroup.word (dcr:0x80030000+0x10+0x6FE8)++0x01 line.word 0x00 "DER,Data Error Register" bitfld.word 0x00 9. " DATAERROR[9] ,DPRDS byte lane 9 data integrity error" "-,Error" bitfld.word 0x00 8. " [8] ,DPRDS byte lane 8 data integrity error" "-,Error" bitfld.word 0x00 7. " [7] ,DPRDS byte lane 7 data integrity error" "-,Error" bitfld.word 0x00 6. " [6] ,DPRDS byte lane 6 data integrity error" "-,Error" bitfld.word 0x00 5. " [5] ,DPRDS byte lane 5 data integrity error" "-,Error" newline bitfld.word 0x00 4. " [4] ,DPRDS byte lane 4 data integrity error" "-,Error" bitfld.word 0x00 3. " [3] ,DPRDS byte lane 3 data integrity error" "-,Error" bitfld.word 0x00 2. " [2] ,DPRDS byte lane 2 data integrity error" "-,Error" bitfld.word 0x00 1. " [1] ,DPRDS byte lane 1 data integrity error" "-,Error" bitfld.word 0x00 0. " [0] ,DPRDS byte lane 0 data integrity error" "-,Error" rgroup.word (dcr:0x80030000+0x10+0x6FEC)++0x01 line.word 0x00 "PR,Preamble Register" bitfld.word 0x00 9. " PREAMBLE_DETECT[9] ,DP8 byte lane 8 preamble detected" "-,Detected" bitfld.word 0x00 8. " [8] ,DP8 byte lane 8 preamble detected" "-,Detected" bitfld.word 0x00 7. " [7] ,DP8 byte lane 7 preamble detected" "-,Detected" bitfld.word 0x00 6. " [6] ,DP8 byte lane 6 preamble detected" "-,Detected" bitfld.word 0x00 5. " [5] ,DP8 byte lane 5 preamble detected" "-,Detected" newline bitfld.word 0x00 4. " [4] ,DP8 byte lane 4 preamble detected" "-,Detected" bitfld.word 0x00 3. " [3] ,DP8 byte lane 3 preamble detected" "-,Detected" bitfld.word 0x00 2. " [2] ,DP8 byte lane 2 preamble detected" "-,Detected" bitfld.word 0x00 1. " [1] ,DP8 byte lane 1 preamble detected" "-,Detected" bitfld.word 0x00 0. " [0] ,DP8 byte lane 0 preamble detected" "-,Detected" rgroup.word (dcr:0x80030000+0x10+0x6FEA)++0x01 line.word 0x00 "DQSGR,DQS Group Register" bitfld.word 0x00 9. " MC_RC_DQS_GROUP[9] ,Byte lane 9 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 8. " [8] ,Byte lane 8 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 7. " [7] ,Byte lane 7 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 6. " [6] ,Byte lane 6 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 5. " [5] ,Byte lane 5 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" newline bitfld.word 0x00 4. " [4] ,Byte lane 4 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 3. " [3] ,Byte lane 3 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 2. " [2] ,Byte lane 2 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 1. " [1] ,Byte lane 1 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" bitfld.word 0x00 0. " [0] ,Byte lane 0 nibble lane/DQS group for hardware assist algorithm enable" "-,Enabled" rgroup.word (dcr:0x80030000+0x10+0x6FE5)++0x01 line.word 0x00 "BEDQSR,Byte Error DQS Register" bitfld.word 0x00 9. " BYTE_ERROR_DQS[9] ,Byte lane 9 read calibration error" "-,Error" bitfld.word 0x00 8. " [8] ,Byte lane 8 read calibration error" "-,Error" bitfld.word 0x00 7. " [7] ,Byte lane 7 read calibration error" "-,Error" bitfld.word 0x00 6. " [6] ,Byte lane 6 read calibration error" "-,Error" bitfld.word 0x00 5. " [5] ,Byte lane 5 read calibration error" "-,Error" newline bitfld.word 0x00 4. " [4] ,Byte lane 4 read calibration error" "-,Error" bitfld.word 0x00 3. " [3] ,Byte lane 3 read calibration error" "-,Error" bitfld.word 0x00 2. " [2] ,Byte lane 2 read calibration error" "-,Error" bitfld.word 0x00 1. " [1] ,Byte lane 1 read calibration error" "-,Error" bitfld.word 0x00 0. " [0] ,Byte lane 0 read calibration error" "-,Error" newline wgroup.word (dcr:0x80030000+0x7FF0)++0x01 line.word 0x00 "DQSGDSRB,DQS Gate Delay Setting Register Broadcast (All Ranks, Bytes And Bits)" bitfld.word 0x00 0.--3. " DELAY_SETTING ,Delay between RD_EXPECTED and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" group.word (dcr:0x80030000+0x71E1)++0x01 line.word 0x00 "DQSDRB,DQS Delay Register Broadcast (All Bytes And Nibbles)" hexmask.word.byte 0x00 0.--7. 1. " DQSDELAY ,DQS delay override value" group.word (dcr:0x80030000+0x6FF9)++0x01 line.word 0x00 "RDDLYOR,RDDLY Override Register" bitfld.word 0x00 15. " JITTER_FILTER_ENABLE ,Jitter filter enable" "-,Enabled" bitfld.word 0x00 12.--14. " JITTER_FILTER_LOOP_COUNT ,N times loop counter" "8,16,24,32,40,48,56,64" bitfld.word 0x00 11. " USED_PORTS_NOT_REG ,DESKEW/DQSCENTERING use register/ports" "Register,Ports" bitfld.word 0x00 10. " DESKEW_ENABLE ,RDDLY deskew run during read calibration" "-,Enabled" newline bitfld.word 0x00 9. " DQSCENTERING_ENABLE ,RDDLY readeye DQS centring run during calibration" "-,Enabled" bitfld.word 0x00 8. " DATAINTEGRITY_ENABLE ,Full data integrity check enable" "-,Enabled" bitfld.word 0x00 7. " DQSDELAY_ENABLE ,DQS delay value" "Default,As CPC_FRACTION" hexmask.word.byte 0x00 0.--6. 1. " DQSDELAY_STEPSIZE ,DQS delay step size" group.word (dcr:0x80030000+0x6FFB)++0x01 line.word 0x00 "GDSR,Global Delay Setting Register" rbitfld.word 0x00 11.--14. " MAX_OBSERVED_RANK_DELAY ,Largest delay among DQS_GATE_RANK_DELAY" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" bitfld.word 0x00 7.--10. " MAX_RANK_DELAY ,Largest delay for DQS_GATE_RANK_DELAY" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" bitfld.word 0x00 3.--6. " DQS_GATE_GLOBAL_OFFSET ,Common delay between RD_EXPECTED_2X and DQS gating pulse start" "0,0.25,0.5,0.75,1,1.25,1.5,1.75,2,2.25,2.5,2.75,3,3.25,3.5,3.75" bitfld.word 0x00 0.--2. " RD_FIFO_DELAY ,RD FIFO delay" "0,1,2,3,4,5,6,7" group.word (dcr:0x80030000+0x6FFD)++0x01 line.word 0x00 "MR,Miscellaneous Register" bitfld.word 0x00 7.--9. " RC_ITERATION_COUNT ,Read calibration additional reads number" "3 reads,7 reads,11 reads,15 reads,19 reads,23 reads,27 reads,31 reads" bitfld.word 0x00 4.--6. " MC_RANK ,Last rank processed by RD_CALIBRATION_CNTL DQS_GATE" "0,1,2,3,4,5,6,7" hgroup.word (dcr:0x80030000+0x6FFE)++0x01 hide.word 0x00 "SR,Status Register" in newline if ((per.w.le(dcr:0x80030000+0x6FF6)&0x1000)==0x1000) group.word (dcr:0x80030000+0x6FFF)++0x01 line.word 0x00 "CR,Configuration Register" bitfld.word 0x00 15. " SEQ_DET_CS ,Sequence detector switch" "PREAMBLE_DETECT_MODE,PREAMBLE_DETECT_MODE or larger" bitfld.word 0x00 13.--14. " PREAMBLE_DETECT_MODE ,Preamble detect mode" "PDM-6,PDM-5,PDM-4,PDM-3" bitfld.word 0x00 12. " MODE_DEBUG_RCDQSGRP_ENABLE ,MC_RC_RANK and MC_RC_DQSGROUP control" "Hardware,Software" newline bitfld.word 0x00 11. " DQS_GATE_GUARDBAND_POLARITY ,DQS gate guardband polarity" "Subtract,Add" bitfld.word 0x00 8.--10. " DQS_GATE_GUARDBAND ,DQS gate guardband" "0,0.25,0.5,0.75,1,1.25,1.5,1.75" bitfld.word 0x00 1. " MODE[1] ,DQS_GATE_RANK_DELAY hardware enable" "-,Enabled" else group.word (dcr:0x80030000+0x6FFF)++0x01 line.word 0x00 "CR,Configuration Register" bitfld.word 0x00 15. " SEQ_DET_CS ,Sequence detector switch" "PREAMBLE_DETECT_MODE,PREAMBLE_DETECT_MODE or larger" bitfld.word 0x00 13.--14. " PREAMBLE_DETECT_MODE ,Preamble detect mode" ",,PDM-2,PDM-3" bitfld.word 0x00 12. " MODE_DEBUG_RCDQSGRP_ENABLE ,MC_RC_RANK and MC_RC_DQSGROUP control" "Hardware,Software" newline bitfld.word 0x00 11. " DQS_GATE_GUARDBAND_POLARITY ,DQS gate guardband polarity" "Subtract,Add" bitfld.word 0x00 8.--10. " DQS_GATE_GUARDBAND ,DQS gate guardband" "0,0.25,0.5,0.75,1,1.25,1.5,1.75" bitfld.word 0x00 1. " MODE[1] ,DQS_GATE_RANK_DELAY hardware enable" "-,Enabled" endif if ((per.w.le(dcr:0x80030000+0x6FF6)&0x40)==0x40) group.word (dcr:0x80030000+0x6FF6)++0x01 line.word 0x00 "CR1,Configuration Register 1" bitfld.word 0x00 14.--15. " PDTC ,Preamble detect timeshift control" "Always enabled,Dynamically enabled,,Always disabled" bitfld.word 0x00 13. " EDQSGDA ,DQS gate detect algorithm enable" "-,Enabled" bitfld.word 0x00 12. " EPDM ,Extended preamble detect mode enable" "-,Enabled" newline bitfld.word 0x00 11. " DQSRDOME ,DQS receiver DC offset master enable" "-,Enabled" bitfld.word 0x00 10. " DQSRDOS ,DQS receiver DC offset static" "Dynamically enabled,Always enabled" bitfld.word 0x00 7.--9. " DQSRDOV ,DQS receiver DC offset value" "80 mV,120 mV,160 mV,200 mV,?..." newline bitfld.word 0x00 6. " ROME ,Refine offset mode enable" "-,Enabled" bitfld.word 0x00 4.--5. " ROPDM ,Refine offset preamble detect mode" "PDM-6,PDM-5,PDM-4,PDM-3" bitfld.word 0x00 3. " ROP ,Refine offset polarity" "Subtract,Add" newline bitfld.word 0x00 0.--2. " RO ,Refine offset" "0,1,2,3,4,5,6,7" else group.word (dcr:0x80030000+0x6FF6)++0x01 line.word 0x00 "CR1,Configuration Register 1" bitfld.word 0x00 14.--15. " PDTC ,Preamble detect timeshift control" "Always enabled,Dynamically enabled,,Always disabled" bitfld.word 0x00 13. " EDQSGDA ,DQS gate detect algorithm enable" "-,Enabled" bitfld.word 0x00 12. " EPDM ,Extended preamble detect mode enable" "-,Enabled" newline bitfld.word 0x00 11. " DQSRDOME ,DQS receiver DC offset master enable" "-,Enabled" bitfld.word 0x00 10. " DQSRDOS ,DQS receiver DC offset static" "Dynamically enabled,Always enabled" bitfld.word 0x00 7.--9. " DQSRDOV ,DQS receiver DC offset value" "80 mV,120 mV,160 mV,200 mV,?..." newline bitfld.word 0x00 6. " ROME ,Refine offset mode enable" "-,Enabled" textfld " " bitfld.word 0x00 3. " ROP ,Refine offset polarity" "Subtract,Add" newline bitfld.word 0x00 0.--2. " RO ,Refine offset" "0,1,2,3,4,5,6,7" endif group.word (dcr:0x80030000+0x6FF3)++0x01 line.word 0x00 "CR2,Configuration Register 2" bitfld.word 0x00 6. " DPRMCPTF ,Disable phase rotor margin comparator polarity term fix" "No,Yes" bitfld.word 0x00 5. " IDQS1IX8M ,Ignore DQS1 in x8 mode" "-,Ignore" bitfld.word 0x00 4. " JFAE ,Jitter filter allpass enable" "-,Enabled" newline bitfld.word 0x00 3. " PRCE ,Phase rotor compare enable" "-,Enabled" bitfld.word 0x00 2. " PRMP ,Phase rotor margin polarity" "Subtract,Add" bitfld.word 0x00 0.--1. " PRM ,Phase rotor margin" "0x,0.25x,0.50x,0.75x" tree.end tree "Master Control Registers" width 7. group.word (dcr:0x80030000+0xEFF5)++0x01 line.word 0x00 "CPCCR,CPC Configuration Register" bitfld.word 0x00 0.--3. " CPC_CFGMODE ,CPC configuration mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.word (dcr:0x80030000+0xE005)++0x01 hide.word 0x00 "CPCER,CPC Error Register (ADR/CMD)" in tree "Byte 0" hgroup.word (dcr:0x80030000+0x0+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 1" hgroup.word (dcr:0x80030000+0x20+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 2" hgroup.word (dcr:0x80030000+0x40+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 3" hgroup.word (dcr:0x80030000+0x60+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 4" hgroup.word (dcr:0x80030000+0x80+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 5" hgroup.word (dcr:0x80030000+0xA0+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 6" hgroup.word (dcr:0x80030000+0xC0+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 7" hgroup.word (dcr:0x80030000+0xE0+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 8" hgroup.word (dcr:0x80030000+0x100+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 9" hgroup.word (dcr:0x80030000+0x120+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 10" hgroup.word (dcr:0x80030000+0x140+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 11" hgroup.word (dcr:0x80030000+0x160+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 12" hgroup.word (dcr:0x80030000+0x180+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 13" hgroup.word (dcr:0x80030000+0x1A0+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end tree "Byte 14" hgroup.word (dcr:0x80030000+0x1C0+0xE004)++0x01 hide.word 0x00 "CPCER,CPC Error Register (Byte)" in tree.end group.word (dcr:0x80030000+0xEFFD)++0x01 line.word 0x00 "CCR0,Control Configuration Register 0" bitfld.word 0x00 15. " UREG_DVDD_RNGE_1 ,Debug switch" "Normal,Add PFET strength" bitfld.word 0x00 14. " UREG_DVDD_RNGE_0 ,DVDD power supply range switch" "Normal,Add PFET strength" newline bitfld.word 0x00 12. " PREVENT_2_CYCLE_DELAY_SWITCHING ,Asynchronous delay switch" "Allowed,Prevented" bitfld.word 0x00 11. " PREVENT_RANK_DLY_SWITCH_WR ,Rank delay switch" "Allowed,Prevented" newline bitfld.word 0x00 9.--10. " RANK_MAP_MODE ,Write levelling and read per bit DQ deskew rank pair" "0/4 - 1/5 - 2/6 - 3/7,0/2 - 1/3 - 4/6 - 5/7,0/1 - 2/3 - 4/5 - 6/7,?..." bitfld.word 0x00 8. " RDCAL_PDM_456_AND_RL_EQ6 ,RDCAL_PDM_456_AND_RL_EQ6 value" "0,1" newline bitfld.word 0x00 7. " MEMORY_DEVICE_MODE[7] ,Rank 7 register bit location" "x4,x8" bitfld.word 0x00 6. " [6] ,Rank 6 register bit location" "x4,x8" newline bitfld.word 0x00 5. " [5] ,Rank 5 register bit location" "x4,x8" bitfld.word 0x00 4. " [4] ,Rank 4 register bit location" "x4,x8" newline bitfld.word 0x00 3. " [3] ,Rank 3 register bit location" "x4,x8" bitfld.word 0x00 2. " [2] ,Rank 2 register bit location" "x4,x8" newline bitfld.word 0x00 1. " [1] ,Rank 1 register bit location" "x4,x8" bitfld.word 0x00 0. " [0] ,Rank 0 register bit location" "x4,x8" group.word (dcr:0x80030000+0xEFFC)++0x01 line.word 0x00 "CCR1,Control Configuration Register 1" bitfld.word 0x00 15. " ALLOW_RD_FIFO_AUTO_RESET ,RD FIFO auto reset pointers on rank switch prevent" "Allowed,Prevented" bitfld.word 0x00 14. " RANK_OVERRIDE ,Rank override" "-,Override" newline bitfld.word 0x00 11.--13. " RANK_OVERRIDE_VALUE ,Rank override value" "0,1,2,3,4,5,6,7" bitfld.word 0x00 9.--10. " RD_N_CYCLE_GAP ,RD cycle gap" "2 cycles,2.5 cycle,3 cycles,?..." newline bitfld.word 0x00 7.--8. " DQS1_ENABLEMODE ,DQS1 enable mode" "Coincident mode,Quarter ahead/Quarter behind,Quarter ahead/Half behind,?..." bitfld.word 0x00 6. " DQS1_COREMODE ,DQS1 core mode" "DCPIN as DQ,DCPIN as DQS" newline bitfld.word 0x00 4.--5. " DQS0_ENABLEMODE ,DQS0 enable mode" "Coincident mode,Quarter ahead/Quarter behind,Quarter ahead/Half behind,?..." bitfld.word 0x00 3. " DQS0_COREMODE ,DQS0 core mode" "DCPIN as DQ,DCPIN as DQS" newline bitfld.word 0x00 1.--2. " DQ_ENABLEMODE ,DQ enable mode" "Coincident mode,Quarter ahead/Quarter behind,Quarter ahead/Half behind,?..." bitfld.word 0x00 0. " DQ_COREMODE ,DQ core mode" "DCPIN as DQ,DCPIN as DQS" group.word (dcr:0x80030000+0xEFF4)++0x01 line.word 0x00 "CCR5,Control Configuration Register 5" bitfld.word 0x00 1.--3. " VREF_ALT_REF_SELECT[3:1] ,VREF alternate reference select" "VDD based,VDD based,VDD based,VDD based,1.5 V,1.35 V,,1.2 V" group.word (dcr:0x80030000+0xEFFE)++0x01 line.word 0x00 "EMR,Error Mask Register" bitfld.word 0x00 4. " RD_CAL_ERROR_MASK ,Read calibration algorithm error" "-,Error" bitfld.word 0x00 3. " WR_LVL_ERROR_MASK ,Write levelling algorithm error" "-,Error" newline bitfld.word 0x00 2. " RD_DLY_ERROR_MASK ,Read delay algorithm error" "-,Error" bitfld.word 0x00 1. " CMD_DLY_ERROR_MASK ,Address/Command delay algorithm error" "-,Error" newline bitfld.word 0x00 0. " CPC_ERROR_MASK ,Clock period calculator algorithm error" "-,Error" tree.end endian.def width 0x0B tree.end tree "DMA2PLB6 (Direct Memory Access)" width 9. tree "PLB6" tree "Channel 0" group.long (dcr:0x80000A00+0x0)++0x03 line.long 0x00 "CR0,Channel Control Register 0" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x0+0x04)++0x03 line.long 0x00 "CTC0,Count Register 0" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x0+0x08)++0x03 line.long 0x00 "DSTR0,Data Stride Register 0" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x0+0x0C)++0x03 line.long 0x00 "SAH0,Source Address High Register 0" group.long (dcr:0x80000A00+0x0+0x10)++0x03 line.long 0x00 "SAL0,Source Address Low Register 0" group.long (dcr:0x80000A00+0x0+0x14)++0x03 line.long 0x00 "DAH0,Destination Address High Register 0" group.long (dcr:0x80000A00+0x0+0x18)++0x03 line.long 0x00 "DAL0,Destination Address Low Register 0" group.long (dcr:0x80000A00+0x0+0x1C)++0x03 line.long 0x00 "SGH0,Scatter/Gather Descriptor Address High Register 0" group.long (dcr:0x80000A00+0x0+0x20)++0x03 line.long 0x00 "SGL0,Scatter/Gather Descriptor Address Low Register 0" group.long (dcr:0x80000A00+0x0+0x24)++0x03 line.long 0x00 "SGC0,Scatter/Gather Command Register 0" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x0+0x28)++0x03 line.long 0x00 "CHRES0,Channel Resume Register 0" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x0+0x2C)++0x03 line.long 0x00 "CHLOCK0,Channel Lock Register 0" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x0+0x30)++0x03 line.long 0x00 "SGCA0,Scatter/Gather Command Attribute Register 0" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end tree "Channel 1" group.long (dcr:0x80000A00+0x100)++0x03 line.long 0x00 "CR1,Channel Control Register 1" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x100+0x04)++0x03 line.long 0x00 "CTC1,Count Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x100+0x08)++0x03 line.long 0x00 "DSTR1,Data Stride Register 1" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x100+0x0C)++0x03 line.long 0x00 "SAH1,Source Address High Register 1" group.long (dcr:0x80000A00+0x100+0x10)++0x03 line.long 0x00 "SAL1,Source Address Low Register 1" group.long (dcr:0x80000A00+0x100+0x14)++0x03 line.long 0x00 "DAH1,Destination Address High Register 1" group.long (dcr:0x80000A00+0x100+0x18)++0x03 line.long 0x00 "DAL1,Destination Address Low Register 1" group.long (dcr:0x80000A00+0x100+0x1C)++0x03 line.long 0x00 "SGH1,Scatter/Gather Descriptor Address High Register 1" group.long (dcr:0x80000A00+0x100+0x20)++0x03 line.long 0x00 "SGL1,Scatter/Gather Descriptor Address Low Register 1" group.long (dcr:0x80000A00+0x100+0x24)++0x03 line.long 0x00 "SGC1,Scatter/Gather Command Register 1" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x100+0x28)++0x03 line.long 0x00 "CHRES1,Channel Resume Register 1" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x100+0x2C)++0x03 line.long 0x00 "CHLOCK1,Channel Lock Register 1" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x100+0x30)++0x03 line.long 0x00 "SGCA1,Scatter/Gather Command Attribute Register 1" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end tree "Channel 2" group.long (dcr:0x80000A00+0x200)++0x03 line.long 0x00 "CR2,Channel Control Register 2" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x200+0x04)++0x03 line.long 0x00 "CTC2,Count Register 2" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x200+0x08)++0x03 line.long 0x00 "DSTR2,Data Stride Register 2" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x200+0x0C)++0x03 line.long 0x00 "SAH2,Source Address High Register 2" group.long (dcr:0x80000A00+0x200+0x10)++0x03 line.long 0x00 "SAL2,Source Address Low Register 2" group.long (dcr:0x80000A00+0x200+0x14)++0x03 line.long 0x00 "DAH2,Destination Address High Register 2" group.long (dcr:0x80000A00+0x200+0x18)++0x03 line.long 0x00 "DAL2,Destination Address Low Register 2" group.long (dcr:0x80000A00+0x200+0x1C)++0x03 line.long 0x00 "SGH2,Scatter/Gather Descriptor Address High Register 2" group.long (dcr:0x80000A00+0x200+0x20)++0x03 line.long 0x00 "SGL2,Scatter/Gather Descriptor Address Low Register 2" group.long (dcr:0x80000A00+0x200+0x24)++0x03 line.long 0x00 "SGC2,Scatter/Gather Command Register 2" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x200+0x28)++0x03 line.long 0x00 "CHRES2,Channel Resume Register 2" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x200+0x2C)++0x03 line.long 0x00 "CHLOCK2,Channel Lock Register 2" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x200+0x30)++0x03 line.long 0x00 "SGCA2,Scatter/Gather Command Attribute Register 2" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end tree "Channel 3" group.long (dcr:0x80000A00+0x300)++0x03 line.long 0x00 "CR3,Channel Control Register 3" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x300+0x04)++0x03 line.long 0x00 "CTC3,Count Register 3" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x300+0x08)++0x03 line.long 0x00 "DSTR3,Data Stride Register 3" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x300+0x0C)++0x03 line.long 0x00 "SAH3,Source Address High Register 3" group.long (dcr:0x80000A00+0x300+0x10)++0x03 line.long 0x00 "SAL3,Source Address Low Register 3" group.long (dcr:0x80000A00+0x300+0x14)++0x03 line.long 0x00 "DAH3,Destination Address High Register 3" group.long (dcr:0x80000A00+0x300+0x18)++0x03 line.long 0x00 "DAL3,Destination Address Low Register 3" group.long (dcr:0x80000A00+0x300+0x1C)++0x03 line.long 0x00 "SGH3,Scatter/Gather Descriptor Address High Register 3" group.long (dcr:0x80000A00+0x300+0x20)++0x03 line.long 0x00 "SGL3,Scatter/Gather Descriptor Address Low Register 3" group.long (dcr:0x80000A00+0x300+0x24)++0x03 line.long 0x00 "SGC3,Scatter/Gather Command Register 3" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x300+0x28)++0x03 line.long 0x00 "CHRES3,Channel Resume Register 3" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x300+0x2C)++0x03 line.long 0x00 "CHLOCK3,Channel Lock Register 3" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x300+0x30)++0x03 line.long 0x00 "SGCA3,Scatter/Gather Command Attribute Register 3" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end newline group.long (dcr:0x80000A00+0x400)++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " CS[0] ,Channel 0 terminal count status" "-,Occurred" eventfld.long 0x00 30. " CS[1] ,Channel 1 terminal count status" "-,Occurred" newline eventfld.long 0x00 29. " CS[2] ,Channel 2 terminal count status" "-,Occurred" eventfld.long 0x00 28. " CS[3] ,Channel 3 terminal count status" "-,Occurred" newline eventfld.long 0x00 27. " RI0 ,Channel 0 error status" "-,Error" bitfld.long 0x00 24.--26. " RS0 ,Channel 0 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 23. " RI1 ,Channel 1 error status" "-,Error" bitfld.long 0x00 20.--22. " RS1 ,Channel 1 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 19. " RI2 ,Channel 2 error status" "-,Error" bitfld.long 0x00 16.--18. " RS2 ,Channel 2 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 15. " RI3 ,Channel 3 error status" "-,Error" bitfld.long 0x00 12.--14. " RS3 ,Channel 3 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 11. " CB[0] ,Channel 0 busy" "Idle,Busy" eventfld.long 0x00 10. " CB[1] ,Channel 1 busy" "Idle,Busy" newline eventfld.long 0x00 9. " CB[2] ,Channel 2 busy" "Idle,Busy" eventfld.long 0x00 8. " CB[3] ,Channel 3 busy" "Idle,Busy" newline eventfld.long 0x00 7. " SG[0] ,Channel 0 scatter/gather operation in progress" "-,In progress" eventfld.long 0x00 6. " SG[1] ,Channel 1 scatter/gather operation in progress" "-,In progress" newline eventfld.long 0x00 5. " SG[2] ,Channel 2 scatter/gather operation in progress" "-,In progress" eventfld.long 0x00 4. " SG[3] ,Channel 3 scatter/gather operation in progress" "-,In progress" rgroup.long (dcr:0x80000A00+0x404)++0x03 line.long 0x00 "PMEAH,PLB Master Error Address High Register" rgroup.long (dcr:0x80000A00+0x408)++0x03 line.long 0x00 "PMEAL,PLB Master Error Address Low Register" group.long (dcr:0x80000A00+0x40C)++0x03 line.long 0x00 "PSE,PLB Slave Error Register" eventfld.long 0x00 31. " RE ,PLB request error for slave request" "-,Error" bitfld.long 0x00 27.--30. " RS ,Request error specific information" "Parity error on address write,Parity error on BE write,Write request incorrect BE,Write request on non-single-beat transfer,Write to reserved space,Write by unauthorized PLB master,,,Parity error on address read,Parity error on BE read,Read request incorrect BE,Read request on non-single-beat transfer,Read from reserved space,Read by unauthorized PLB master,?..." newline eventfld.long 0x00 26. " WE ,PLB write parity error on write data bus" "-,Error" eventfld.long 0x00 25. " PE ,PLB write parity error on write data bus" "-,Error" newline bitfld.long 0x00 19.--24. " MID ,Request master ID of PLB slave transfer with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--18. " RTG ,Request tag of PLB slave transfer with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long (dcr:0x80000A00+0x410)++0x03 line.long 0x00 "PSEAH,PLB Slave Error Address High Register" rgroup.long (dcr:0x80000A00+0x414)++0x03 line.long 0x00 "PSEAL,PLB Slave Error Address Low Register" group.long (dcr:0x80000A00+0x418)++0x03 line.long 0x00 "CRS,Channel Resume Status Register" eventfld.long 0x00 31. " CRS0 ,Channel 0 resume status" "LK = 1,LK = 0" eventfld.long 0x00 30. " CRS1 ,Channel 1 resume status" "LK = 1,LK = 0" eventfld.long 0x00 29. " CRS2 ,Channel 2 resume status" "LK = 1,LK = 0" eventfld.long 0x00 28. " CRS3 ,Channel 3 resume status" "LK = 1,LK = 0" rgroup.long (dcr:0x80000A00+0x41C)++0x03 line.long 0x00 "REVID,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " RN ,Revision number" hexmask.long.byte 0x00 0.--7. 1. " BRN ,Branch revision number" group.long (dcr:0x80000A00+0x420)++0x03 line.long 0x00 "ARB,PLB Arbiter Mode Register" bitfld.long 0x00 31. " SM ,Arbiter single/multi-thread" "Single-thread,Multi-thread" bitfld.long 0x00 30. " FRR ,Arbiter fixed/round-robin" "Fixed,Round-robin" group.long (dcr:0x80000A00+0x424)++0x03 line.long 0x00 "OPTIONS,Options Enable Register" hexmask.long.byte 0x00 24.--31. 1. " ATTRIB ,Attribute" bitfld.long 0x00 23. " RPR ,PLB transfers read-pass-read enable" "-,Enabled" bitfld.long 0x00 22. " RPW ,PLB transfers read-pass-write enable" "-,Enabled" bitfld.long 0x00 21. " WPR ,PLB transfers write-pass-read enable" "-,Enabled" newline bitfld.long 0x00 20. " SL_PE ,Slave parity enable" "-,Enabled" bitfld.long 0x00 19. " M_ADPE ,Master address parity enable" "-,Enabled" bitfld.long 0x00 18. " M_BEPE ,Master byte enable (BE) parity enable" "-,Enabled" bitfld.long 0x00 17. " M_WDPE ,Master write bus parity enable" "-,Enabled" newline bitfld.long 0x00 16. " SL_INT ,DMA PLB slave error interrupt enable" "-,Enabled" bitfld.long 0x00 15. " SL_PEE ,Slave permissions error interrupt enable" "-,Enabled" group.long (dcr:0x80000A00+0x428)++0x03 line.long 0x00 "PERM,Permissions Register" bitfld.long 0x00 31. " MP[0] ,Master 0 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 30. " [1] ,Master 1 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 29. " [2] ,Master 2 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 28. " [3] ,Master 3 permitted to access DMA configuration registers" "-,Permitted" newline bitfld.long 0x00 27. " [4] ,Master 4 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 26. " [5] ,Master 5 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 25. " [6] ,Master 6 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 24. " [7] ,Master 7 permitted to access DMA configuration registers" "-,Permitted" newline bitfld.long 0x00 23. " [8] ,Master 8 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 22. " [9] ,Master 9 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 21. " [10] ,Master 10 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 20. " [11] ,Master 11 permitted to access DMA configuration registers" "-,Permitted" newline bitfld.long 0x00 19. " [12] ,Master 12 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 18. " [13] ,Master 13 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 17. " [14] ,Master 14 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 16. " [15] ,Master 15 permitted to access DMA configuration registers" "-,Permitted" rgroup.long (dcr:0x80000A00+0x42C)++0x03 line.long 0x00 "PNC,Master Retry Prime Number Count Register" hexmask.long.byte 0x00 0.--7. 1. " PNC ,Prime number count" tree.end tree "DCR" tree "Channel 0" group.long (dcr:0x80000A00+0x0)++0x03 line.long 0x00 "CR0,Channel Control Register 0" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x0+0x01)++0x03 line.long 0x00 "CTC0,Count Register 0" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x0+0x02)++0x03 line.long 0x00 "DSTR0,Data Stride Register 0" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x0+0x03)++0x03 line.long 0x00 "SAH0,Source Address High Register 0" group.long (dcr:0x80000A00+0x0+0x04)++0x03 line.long 0x00 "SAL0,Source Address Low Register 0" group.long (dcr:0x80000A00+0x0+0x05)++0x03 line.long 0x00 "DAH0,Destination Address High Register 0" group.long (dcr:0x80000A00+0x0+0x06)++0x03 line.long 0x00 "DAL0,Destination Address Low Register 0" group.long (dcr:0x80000A00+0x0+0x07)++0x03 line.long 0x00 "SGH0,Scatter/Gather Descriptor Address High Register 0" group.long (dcr:0x80000A00+0x0+0x08)++0x03 line.long 0x00 "SGL0,Scatter/Gather Descriptor Address Low Register 0" group.long (dcr:0x80000A00+0x0+0x09)++0x03 line.long 0x00 "SGC0,Scatter/Gather Command Register 0" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x0+0x0A)++0x03 line.long 0x00 "CHRES0,Channel Resume Register 0" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x0+0x0B)++0x03 line.long 0x00 "CHLOCK0,Channel Lock Register 0" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x0+0x0C)++0x03 line.long 0x00 "SGCA0,Scatter/Gather Command Attribute Register 0" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end tree "Channel 1" group.long (dcr:0x80000A00+0x10)++0x03 line.long 0x00 "CR1,Channel Control Register 1" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x10+0x01)++0x03 line.long 0x00 "CTC1,Count Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x10+0x02)++0x03 line.long 0x00 "DSTR1,Data Stride Register 1" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x10+0x03)++0x03 line.long 0x00 "SAH1,Source Address High Register 1" group.long (dcr:0x80000A00+0x10+0x04)++0x03 line.long 0x00 "SAL1,Source Address Low Register 1" group.long (dcr:0x80000A00+0x10+0x05)++0x03 line.long 0x00 "DAH1,Destination Address High Register 1" group.long (dcr:0x80000A00+0x10+0x06)++0x03 line.long 0x00 "DAL1,Destination Address Low Register 1" group.long (dcr:0x80000A00+0x10+0x07)++0x03 line.long 0x00 "SGH1,Scatter/Gather Descriptor Address High Register 1" group.long (dcr:0x80000A00+0x10+0x08)++0x03 line.long 0x00 "SGL1,Scatter/Gather Descriptor Address Low Register 1" group.long (dcr:0x80000A00+0x10+0x09)++0x03 line.long 0x00 "SGC1,Scatter/Gather Command Register 1" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x10+0x0A)++0x03 line.long 0x00 "CHRES1,Channel Resume Register 1" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x10+0x0B)++0x03 line.long 0x00 "CHLOCK1,Channel Lock Register 1" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x10+0x0C)++0x03 line.long 0x00 "SGCA1,Scatter/Gather Command Attribute Register 1" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end tree "Channel 2" group.long (dcr:0x80000A00+0x20)++0x03 line.long 0x00 "CR2,Channel Control Register 2" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x20+0x01)++0x03 line.long 0x00 "CTC2,Count Register 2" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x20+0x02)++0x03 line.long 0x00 "DSTR2,Data Stride Register 2" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x20+0x03)++0x03 line.long 0x00 "SAH2,Source Address High Register 2" group.long (dcr:0x80000A00+0x20+0x04)++0x03 line.long 0x00 "SAL2,Source Address Low Register 2" group.long (dcr:0x80000A00+0x20+0x05)++0x03 line.long 0x00 "DAH2,Destination Address High Register 2" group.long (dcr:0x80000A00+0x20+0x06)++0x03 line.long 0x00 "DAL2,Destination Address Low Register 2" group.long (dcr:0x80000A00+0x20+0x07)++0x03 line.long 0x00 "SGH2,Scatter/Gather Descriptor Address High Register 2" group.long (dcr:0x80000A00+0x20+0x08)++0x03 line.long 0x00 "SGL2,Scatter/Gather Descriptor Address Low Register 2" group.long (dcr:0x80000A00+0x20+0x09)++0x03 line.long 0x00 "SGC2,Scatter/Gather Command Register 2" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x20+0x0A)++0x03 line.long 0x00 "CHRES2,Channel Resume Register 2" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x20+0x0B)++0x03 line.long 0x00 "CHLOCK2,Channel Lock Register 2" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x20+0x0C)++0x03 line.long 0x00 "SGCA2,Scatter/Gather Command Attribute Register 2" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end tree "Channel 3" group.long (dcr:0x80000A00+0x30)++0x03 line.long 0x00 "CR3,Channel Control Register 3" bitfld.long 0x00 31. " CE ,Channel enable" "-,Enabled" bitfld.long 0x00 30. " TCIE ,Terminal count interrupt enable" "-,Enabled" bitfld.long 0x00 29. " EIE ,Error interrupt enable" "-,Enabled" bitfld.long 0x00 27.--28. " CIM ,Channel interrupt mode" "Level - wait for clear,,Pulse - wait for clear,Pulse - do not wait for clear" newline bitfld.long 0x00 24.--26. " PW ,Transfer width" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x00 21. " DSS ,Source data striding enable" "-,Enabled" bitfld.long 0x00 20. " DSD ,Destination data striding enable" "-,Enabled" bitfld.long 0x00 19. " TCE ,Terminal count enable" "-,Enabled" newline bitfld.long 0x00 17.--18. " CP ,Channel priority" "Low,Medium low,Medium high,High" bitfld.long 0x00 14.--16. " PF ,Read/write transfer size" "128 bits,256 bits,512 bits,1024 bits,?..." bitfld.long 0x00 13. " SSC ,Source address snoopable" "Nonsnoopable,Snoopable" bitfld.long 0x00 12. " DSC ,Destination address snoopable" "Nonsnoopable,Snoopable" group.long (dcr:0x80000A00+0x30+0x01)++0x03 line.long 0x00 "CTC3,Count Register 3" hexmask.long.tbyte 0x00 0.--19. 1. " TC ,Transfer count" group.long (dcr:0x80000A00+0x30+0x02)++0x03 line.long 0x00 "DSTR3,Data Stride Register 3" hexmask.long.word 0x00 16.--31. 1. " TBS ,Transfer block size" hexmask.long.word 0x00 0.--15. 1. " SBS ,Skip block size" group.long (dcr:0x80000A00+0x30+0x03)++0x03 line.long 0x00 "SAH3,Source Address High Register 3" group.long (dcr:0x80000A00+0x30+0x04)++0x03 line.long 0x00 "SAL3,Source Address Low Register 3" group.long (dcr:0x80000A00+0x30+0x05)++0x03 line.long 0x00 "DAH3,Destination Address High Register 3" group.long (dcr:0x80000A00+0x30+0x06)++0x03 line.long 0x00 "DAL3,Destination Address Low Register 3" group.long (dcr:0x80000A00+0x30+0x07)++0x03 line.long 0x00 "SGH3,Scatter/Gather Descriptor Address High Register 3" group.long (dcr:0x80000A00+0x30+0x08)++0x03 line.long 0x00 "SGL3,Scatter/Gather Descriptor Address Low Register 3" group.long (dcr:0x80000A00+0x30+0x09)++0x03 line.long 0x00 "SGC3,Scatter/Gather Command Register 3" bitfld.long 0x00 31. " SSG ,Start scatter/gather" "-,Started" group.long (dcr:0x80000A00+0x30+0x0A)++0x03 line.long 0x00 "CHRES3,Channel Resume Register 3" bitfld.long 0x00 31. " CHR ,Channel resume" "-,Resumed" group.long (dcr:0x80000A00+0x30+0x0B)++0x03 line.long 0x00 "CHLOCK3,Channel Lock Register 3" eventfld.long 0x00 31. " CHL ,Channel lock" "-,Locked" group.long (dcr:0x80000A00+0x30+0x0C)++0x03 line.long 0x00 "SGCA3,Scatter/Gather Command Attribute Register 3" bitfld.long 0x00 31. " CA ,Command attribute: SGDT memory location" "Nonsnoopable memory,Snoopable memory" tree.end newline group.long (dcr:0x80000A00+0x40)++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " CS[0] ,Channel 0 terminal count status" "-,Occurred" eventfld.long 0x00 30. " CS[1] ,Channel 1 terminal count status" "-,Occurred" newline eventfld.long 0x00 29. " CS[2] ,Channel 2 terminal count status" "-,Occurred" eventfld.long 0x00 28. " CS[3] ,Channel 3 terminal count status" "-,Occurred" newline eventfld.long 0x00 27. " RI0 ,Channel 0 error status" "-,Error" bitfld.long 0x00 24.--26. " RS0 ,Channel 0 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 23. " RI1 ,Channel 1 error status" "-,Error" bitfld.long 0x00 20.--22. " RS1 ,Channel 1 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 19. " RI2 ,Channel 2 error status" "-,Error" bitfld.long 0x00 16.--18. " RS2 ,Channel 2 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 15. " RI3 ,Channel 3 error status" "-,Error" bitfld.long 0x00 12.--14. " RS3 ,Channel 3 specific error status" "Write request error,,Read request error during regular data transfer,Read data error for regular read transfer,Read request error during fetch,Read data error for fetch,Source/destination address alignment error,Scatter/Gather address alignment error" newline eventfld.long 0x00 11. " CB[0] ,Channel 0 busy" "Idle,Busy" eventfld.long 0x00 10. " CB[1] ,Channel 1 busy" "Idle,Busy" newline eventfld.long 0x00 9. " CB[2] ,Channel 2 busy" "Idle,Busy" eventfld.long 0x00 8. " CB[3] ,Channel 3 busy" "Idle,Busy" newline eventfld.long 0x00 7. " SG[0] ,Channel 0 scatter/gather operation in progress" "-,In progress" eventfld.long 0x00 6. " SG[1] ,Channel 1 scatter/gather operation in progress" "-,In progress" newline eventfld.long 0x00 5. " SG[2] ,Channel 2 scatter/gather operation in progress" "-,In progress" eventfld.long 0x00 4. " SG[3] ,Channel 3 scatter/gather operation in progress" "-,In progress" rgroup.long (dcr:0x80000A00+0x41)++0x03 line.long 0x00 "PMEAH,PLB Master Error Address High Register" rgroup.long (dcr:0x80000A00+0x42)++0x03 line.long 0x00 "PMEAL,PLB Master Error Address Low Register" group.long (dcr:0x80000A00+0x43)++0x03 line.long 0x00 "PSE,PLB Slave Error Register" eventfld.long 0x00 31. " RE ,PLB request error for slave request" "-,Error" bitfld.long 0x00 27.--30. " RS ,Request error specific information" "Parity error on address write,Parity error on BE write,Write request incorrect BE,Write request on non-single-beat transfer,Write to reserved space,Write by unauthorized PLB master,,,Parity error on address read,Parity error on BE read,Read request incorrect BE,Read request on non-single-beat transfer,Read from reserved space,Read by unauthorized PLB master,?..." newline eventfld.long 0x00 26. " WE ,PLB write parity error on write data bus" "-,Error" eventfld.long 0x00 25. " PE ,PLB write parity error on write data bus" "-,Error" newline bitfld.long 0x00 19.--24. " MID ,Request master ID of PLB slave transfer with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--18. " RTG ,Request tag of PLB slave transfer with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long (dcr:0x80000A00+0x44)++0x03 line.long 0x00 "PSEAH,PLB Slave Error Address High Register" rgroup.long (dcr:0x80000A00+0x45)++0x03 line.long 0x00 "PSEAL,PLB Slave Error Address Low Register" group.long (dcr:0x80000A00+0x46)++0x03 line.long 0x00 "CRS,Channel Resume Status Register" eventfld.long 0x00 31. " CRS0 ,Channel 0 resume status" "LK = 1,LK = 0" eventfld.long 0x00 30. " CRS1 ,Channel 1 resume status" "LK = 1,LK = 0" eventfld.long 0x00 29. " CRS2 ,Channel 2 resume status" "LK = 1,LK = 0" eventfld.long 0x00 28. " CRS3 ,Channel 3 resume status" "LK = 1,LK = 0" rgroup.long (dcr:0x80000A00+0x47)++0x03 line.long 0x00 "REVID,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " RN ,Revision number" hexmask.long.byte 0x00 0.--7. 1. " BRN ,Branch revision number" group.long (dcr:0x80000A00+0x48)++0x03 line.long 0x00 "ARB,PLB Arbiter Mode Register" bitfld.long 0x00 31. " SM ,Arbiter single/multi-thread" "Single-thread,Multi-thread" bitfld.long 0x00 30. " FRR ,Arbiter fixed/round-robin" "Fixed,Round-robin" group.long (dcr:0x80000A00+0x49)++0x03 line.long 0x00 "OPTIONS,Options Enable Register" hexmask.long.byte 0x00 24.--31. 1. " ATTRIB ,Attribute" bitfld.long 0x00 23. " RPR ,PLB transfers read-pass-read enable" "-,Enabled" bitfld.long 0x00 22. " RPW ,PLB transfers read-pass-write enable" "-,Enabled" bitfld.long 0x00 21. " WPR ,PLB transfers write-pass-read enable" "-,Enabled" newline bitfld.long 0x00 20. " SL_PE ,Slave parity enable" "-,Enabled" bitfld.long 0x00 19. " M_ADPE ,Master address parity enable" "-,Enabled" bitfld.long 0x00 18. " M_BEPE ,Master byte enable (BE) parity enable" "-,Enabled" bitfld.long 0x00 17. " M_WDPE ,Master write bus parity enable" "-,Enabled" newline bitfld.long 0x00 16. " SL_INT ,DMA PLB slave error interrupt enable" "-,Enabled" bitfld.long 0x00 15. " SL_PEE ,Slave permissions error interrupt enable" "-,Enabled" group.long (dcr:0x80000A00+0x4A)++0x03 line.long 0x00 "PERM,Permissions Register" bitfld.long 0x00 31. " MP[0] ,Master 0 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 30. " [1] ,Master 1 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 29. " [2] ,Master 2 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 28. " [3] ,Master 3 permitted to access DMA configuration registers" "-,Permitted" newline bitfld.long 0x00 27. " [4] ,Master 4 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 26. " [5] ,Master 5 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 25. " [6] ,Master 6 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 24. " [7] ,Master 7 permitted to access DMA configuration registers" "-,Permitted" newline bitfld.long 0x00 23. " [8] ,Master 8 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 22. " [9] ,Master 9 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 21. " [10] ,Master 10 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 20. " [11] ,Master 11 permitted to access DMA configuration registers" "-,Permitted" newline bitfld.long 0x00 19. " [12] ,Master 12 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 18. " [13] ,Master 13 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 17. " [14] ,Master 14 permitted to access DMA configuration registers" "-,Permitted" bitfld.long 0x00 16. " [15] ,Master 15 permitted to access DMA configuration registers" "-,Permitted" rgroup.long (dcr:0x80000A00+0x4B)++0x03 line.long 0x00 "PNC,Master Retry Prime Number Count Register" hexmask.long.byte 0x00 0.--7. 1. " PNC ,Prime number count" tree.end width 0x0B tree.end tree.open "PLB6PLB4 (PLB6 To PLB4 Bridge)" tree "BR6T04" width 8. group.long (dcr:0x80000B00)++0x03 line.long 0x00 "P64CR,PLB6 To PLB4 Bridge Configuration Register" bitfld.long 0x00 27. " IFE1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 26. " IFE0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 21.--25. " IFMID1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IFMID0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. " IPC ,PLB4 to PLB6 bridge producer-consumer sideband signals ignore" "-,Ignored" bitfld.long 0x00 9. " OWEN ,Ordered write enable" "-,Enabled" bitfld.long 0x00 8. " SPEN ,Split range enable" "-,Enabled" bitfld.long 0x00 0.--1. " PRI ,PLB4 request priority" "Lowest,1,2,Highest" if ((per.l(dcr:0x80000B00+0x01)&0xFF800000)==0x00) group.long (dcr:0x80000B00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" eventfld.long 0x00 31. " P6APE ,PLB6 address parity error" "-,Error" eventfld.long 0x00 30. " P6BPE ,PLB6 byte enable parity error" "-,Error" eventfld.long 0x00 29. " P4RPE ,PLB4 read data parity error" "-,Error" eventfld.long 0x00 28. " P6WPE ,PLB6 write data parity error" "-,Error" newline eventfld.long 0x00 27. " P4MRE ,PLB4 master read error" "-,Error" eventfld.long 0x00 26. " P4MWE ,PLB4 master write error" "-,Error" eventfld.long 0x00 25. " P6SWE ,PLB6 slave write error" "-,Error" eventfld.long 0x00 24. " P4WTO ,PLB4 write request timeout" "-,Error" newline eventfld.long 0x00 23. " P4RTO ,PLB4 read request timeout" "-,Error" eventfld.long 0x00 22. " P6RERR ,Read/write operation error" "Write,Read" newline rbitfld.long 0x00 0. " P4_MIRQ ,PLB master interrupt request" "-,Requested" else group.long (dcr:0x80000B00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" eventfld.long 0x00 31. " P6APE ,PLB6 address parity error" "-,Error" eventfld.long 0x00 30. " P6BPE ,PLB6 byte enable parity error" "-,Error" eventfld.long 0x00 29. " P4RPE ,PLB4 read data parity error" "-,Error" eventfld.long 0x00 28. " P6WPE ,PLB6 write data parity error" "-,Error" newline eventfld.long 0x00 27. " P4MRE ,PLB4 master read error" "-,Error" eventfld.long 0x00 26. " P4MWE ,PLB4 master write error" "-,Error" eventfld.long 0x00 25. " P6SWE ,PLB6 slave write error" "-,Error" eventfld.long 0x00 24. " P4WTO ,PLB4 write request timeout" "-,Error" newline eventfld.long 0x00 23. " P4RTO ,PLB4 read request timeout" "-,Error" eventfld.long 0x00 22. " P6RERR ,Read/write operation error" "Write,Read" bitfld.long 0x00 17.--21. " P6MID ,PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0. " P4_MIRQ ,PLB master interrupt request" "-,Requested" endif rgroup.long (dcr:0x80000B00+0x02)++0x03 line.long 0x00 "P64REV,CoreConnect Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VNUMB ,Version number" hexmask.long.byte 0x00 0.--7. 1. " RVNUMB ,Revision number" rgroup.long (dcr:0x80000B00+0x03)++0x03 line.long 0x00 "EARH,Error Address Register High" rgroup.long (dcr:0x80000B00+0x04)++0x03 line.long 0x00 "EARL,Error Address Register Low" group.long (dcr:0x80000B00+0x05)++0x03 line.long 0x00 "ADDRL0,PLB6 Slave Address Register Low" group.long (dcr:0x80000B00+0x06)++0x03 line.long 0x00 "ADDRH0,PLB6 Slave Address Register High" group.long (dcr:0x80000B00+0x07)++0x03 line.long 0x00 "ADDRL1,Split Range PLB6 Slave Address Register Low" group.long (dcr:0x80000B00+0x08)++0x03 line.long 0x00 "ADDRH1,Split Range PLB6 Slave Address Register High" group.long (dcr:0x80000B00+0x09)++0x03 line.long 0x00 "TESR,(Test Only) Error Status Register" bitfld.long 0x00 31. " P6APE ,PLB6 address parity error" "-,Error" bitfld.long 0x00 30. " P6BPE ,PLB6 byte enable parity error" "-,Error" bitfld.long 0x00 29. " P4RPE ,PLB4 read data parity error" "-,Error" bitfld.long 0x00 28. " P6WPE ,PLB6 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4MRE ,PLB4 master read error" "-,Error" bitfld.long 0x00 26. " P4MWE ,PLB4 master write error" "-,Error" bitfld.long 0x00 25. " P6SWE ,PLB6 slave write error" "-,Error" bitfld.long 0x00 24. " P4WTO ,PLB4 write request timeout" "-,Error" newline bitfld.long 0x00 23. " P4RTO ,PLB4 read request timeout" "-,Error" bitfld.long 0x00 22. " P6RERR ,Read/write operation error" "Write,Read" bitfld.long 0x00 17.--21. " P6MID ,PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0. " P4_MIRQ ,PLB master interrupt request" "-,Requested" width 0x0B tree.end tree "BR6T042" width 8. group.long (dcr:0x80000E00)++0x03 line.long 0x00 "P64CR,PLB6 To PLB4 Bridge Configuration Register" bitfld.long 0x00 27. " IFE1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 26. " IFE0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 21.--25. " IFMID1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IFMID0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. " IPC ,PLB4 to PLB6 bridge producer-consumer sideband signals ignore" "-,Ignored" bitfld.long 0x00 9. " OWEN ,Ordered write enable" "-,Enabled" bitfld.long 0x00 8. " SPEN ,Split range enable" "-,Enabled" bitfld.long 0x00 0.--1. " PRI ,PLB4 request priority" "Lowest,1,2,Highest" if ((per.l(dcr:0x80000E00+0x01)&0xFF800000)==0x00) group.long (dcr:0x80000E00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" eventfld.long 0x00 31. " P6APE ,PLB6 address parity error" "-,Error" eventfld.long 0x00 30. " P6BPE ,PLB6 byte enable parity error" "-,Error" eventfld.long 0x00 29. " P4RPE ,PLB4 read data parity error" "-,Error" eventfld.long 0x00 28. " P6WPE ,PLB6 write data parity error" "-,Error" newline eventfld.long 0x00 27. " P4MRE ,PLB4 master read error" "-,Error" eventfld.long 0x00 26. " P4MWE ,PLB4 master write error" "-,Error" eventfld.long 0x00 25. " P6SWE ,PLB6 slave write error" "-,Error" eventfld.long 0x00 24. " P4WTO ,PLB4 write request timeout" "-,Error" newline eventfld.long 0x00 23. " P4RTO ,PLB4 read request timeout" "-,Error" eventfld.long 0x00 22. " P6RERR ,Read/write operation error" "Write,Read" newline rbitfld.long 0x00 0. " P4_MIRQ ,PLB master interrupt request" "-,Requested" else group.long (dcr:0x80000E00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" eventfld.long 0x00 31. " P6APE ,PLB6 address parity error" "-,Error" eventfld.long 0x00 30. " P6BPE ,PLB6 byte enable parity error" "-,Error" eventfld.long 0x00 29. " P4RPE ,PLB4 read data parity error" "-,Error" eventfld.long 0x00 28. " P6WPE ,PLB6 write data parity error" "-,Error" newline eventfld.long 0x00 27. " P4MRE ,PLB4 master read error" "-,Error" eventfld.long 0x00 26. " P4MWE ,PLB4 master write error" "-,Error" eventfld.long 0x00 25. " P6SWE ,PLB6 slave write error" "-,Error" eventfld.long 0x00 24. " P4WTO ,PLB4 write request timeout" "-,Error" newline eventfld.long 0x00 23. " P4RTO ,PLB4 read request timeout" "-,Error" eventfld.long 0x00 22. " P6RERR ,Read/write operation error" "Write,Read" bitfld.long 0x00 17.--21. " P6MID ,PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0. " P4_MIRQ ,PLB master interrupt request" "-,Requested" endif rgroup.long (dcr:0x80000E00+0x02)++0x03 line.long 0x00 "P64REV,CoreConnect Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VNUMB ,Version number" hexmask.long.byte 0x00 0.--7. 1. " RVNUMB ,Revision number" rgroup.long (dcr:0x80000E00+0x03)++0x03 line.long 0x00 "EARH,Error Address Register High" rgroup.long (dcr:0x80000E00+0x04)++0x03 line.long 0x00 "EARL,Error Address Register Low" group.long (dcr:0x80000E00+0x05)++0x03 line.long 0x00 "ADDRL0,PLB6 Slave Address Register Low" group.long (dcr:0x80000E00+0x06)++0x03 line.long 0x00 "ADDRH0,PLB6 Slave Address Register High" group.long (dcr:0x80000E00+0x07)++0x03 line.long 0x00 "ADDRL1,Split Range PLB6 Slave Address Register Low" group.long (dcr:0x80000E00+0x08)++0x03 line.long 0x00 "ADDRH1,Split Range PLB6 Slave Address Register High" group.long (dcr:0x80000E00+0x09)++0x03 line.long 0x00 "TESR,(Test Only) Error Status Register" bitfld.long 0x00 31. " P6APE ,PLB6 address parity error" "-,Error" bitfld.long 0x00 30. " P6BPE ,PLB6 byte enable parity error" "-,Error" bitfld.long 0x00 29. " P4RPE ,PLB4 read data parity error" "-,Error" bitfld.long 0x00 28. " P6WPE ,PLB6 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4MRE ,PLB4 master read error" "-,Error" bitfld.long 0x00 26. " P4MWE ,PLB4 master write error" "-,Error" bitfld.long 0x00 25. " P6SWE ,PLB6 slave write error" "-,Error" bitfld.long 0x00 24. " P4WTO ,PLB4 write request timeout" "-,Error" newline bitfld.long 0x00 23. " P4RTO ,PLB4 read request timeout" "-,Error" bitfld.long 0x00 22. " P6RERR ,Read/write operation error" "Write,Read" bitfld.long 0x00 17.--21. " P6MID ,PLB6 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0. " P4_MIRQ ,PLB master interrupt request" "-,Requested" width 0x0B tree.end tree.end tree.open "PLB4PLB6 (PLB4 To PLB6 Bridge)" tree "BR4T06" width 15. group.long (dcr:0x80000C00)++0x03 line.long 0x00 "P46CR,PLB4 To PLB6 Bridge Configuration Register" rbitfld.long 0x00 31. " RTY_MASK5[0] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 30. " RTY_MASK5[1] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 29. " RTY_MASK5[2] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" newline rbitfld.long 0x00 28. " RTY_MASK6[0] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 27. " RTY_MASK6[1] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 26. " RTY_MASK6[2] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" newline bitfld.long 0x00 25. " IFE1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 24. " IFE0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 20.--23. " IFMID1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " IFMID0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 15. " RTY_MASK7[0] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 14. " RTY_MASK7[1] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 13. " RTY_MASK7[2] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" newline bitfld.long 0x00 11. " IPC ,PLB6 to PLB4 bridge producer-consumer sideband signals ignore" "-,Ignored" bitfld.long 0x00 10. " OWEN ,Ordered write enable" "-,Enabled" bitfld.long 0x00 9. " SNPEN1 ,Snoopable address 1 registers enable" "-,Enabled" bitfld.long 0x00 8. " SNPEN0 ,Snoopable address 0 registers enable" "-,Enabled" newline hexmask.long.byte 0x00 0.--7. 1. " PNCR ,Prime number count register" newline if ((per.l(dcr:0x80000C00+0x01)&0xFE000000)==0x00) group.long (dcr:0x80000C00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" bitfld.long 0x00 31. " P6CRE ,PLB6 combined response error" "-,Error" bitfld.long 0x00 30. " P6MRE ,PLB6 master read error" "-,Error" bitfld.long 0x00 29. " P6RPE ,PLB6 read data parity error" "-,Error" bitfld.long 0x00 28. " P4WPE ,PLB4 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4APE ,PLB4 address parity error" "-,Error" bitfld.long 0x00 26. " P4BPE ,PLB4 byte-enable parity error" "-,Error" bitfld.long 0x00 25. " P4RERR ,Read/write operation error" "Write,Read" newline else group.long (dcr:0x80000C00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" bitfld.long 0x00 31. " P6CRE ,PLB6 combined response error" "-,Error" bitfld.long 0x00 30. " P6MRE ,PLB6 master read error" "-,Error" bitfld.long 0x00 29. " P6RPE ,PLB6 read data parity error" "-,Error" bitfld.long 0x00 28. " P4WPE ,PLB4 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4APE ,PLB4 address parity error" "-,Error" bitfld.long 0x00 26. " P4BPE ,PLB4 byte-enable parity error" "-,Error" bitfld.long 0x00 25. " P4RERR ,Read/write operation error" "Write,Read" newline bitfld.long 0x00 21.--24. " P4MID ,PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long (dcr:0x80000C00+0x02)++0x03 line.long 0x00 "P46REV,CoreConnect Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VNUMB ,Version number" hexmask.long.byte 0x00 0.--7. 1. " RVNUMB ,Revision number" if ((per.l(dcr:0x80000C00+0x01)&0xFE000000)==0x00) hgroup.long (dcr:0x80000C00+0x03)++0x03 hide.long 0x00 "EARH,Error Address Register High" hgroup.long (dcr:0x80000C00+0x04)++0x03 hide.long 0x00 "EARL,Error Address Register Low" else rgroup.long (dcr:0x80000C00+0x03)++0x03 line.long 0x00 "EARH,Error Address Register High" rgroup.long (dcr:0x80000C00+0x04)++0x03 line.long 0x00 "EARL,Error Address Register Low" endif if ((per.l(dcr:0x80000C00)&0x100)==0x100) group.long (dcr:0x80000C00+0x05)++0x03 line.long 0x00 "SNOOP_UADDRH0,Snoopable Upper Address High 0 Register" group.long (dcr:0x80000C00+0x06)++0x03 line.long 0x00 "SNOOP_LADDRH0,Snoopable Lower Address High 0 Register" group.long (dcr:0x80000C00+0x07)++0x03 line.long 0x00 "SNOOP_UADDRL0,Snoopable Upper Address Low 0 Register" group.long (dcr:0x80000C00+0x08)++0x03 line.long 0x00 "SNOOP_LADDRL0,Snoopable Lower Address Low 0 Register" else hgroup.long (dcr:0x80000C00+0x05)++0x03 hide.long 0x00 "SNOOP_UADDRH0,Snoopable Upper Address High 0 Register" hgroup.long (dcr:0x80000C00+0x06)++0x03 hide.long 0x00 "SNOOP_LADDRH0,Snoopable Lower Address High 0 Register" hgroup.long (dcr:0x80000C00+0x07)++0x03 hide.long 0x00 "SNOOP_UADDRL0,Snoopable Upper Address Low 0 Register" hgroup.long (dcr:0x80000C00+0x08)++0x03 hide.long 0x00 "SNOOP_LADDRL0,Snoopable Lower Address Low 0 Register" endif if ((per.l(dcr:0x80000C00)&0x200)==0x200) group.long (dcr:0x80000C00+0x09)++0x03 line.long 0x00 "SNOOP_UADDRH1,Snoopable Upper Address High 1 Register" group.long (dcr:0x80000C00+0x0A)++0x03 line.long 0x00 "SNOOP_LADDRH1,Snoopable Lower Address High 1 Register" group.long (dcr:0x80000C00+0x0B)++0x03 line.long 0x00 "SNOOP_UADDRL1,Snoopable Upper Address Low 1 Register" group.long (dcr:0x80000C00+0x0C)++0x03 line.long 0x00 "SNOOP_LADDRL1,Snoopable Lower Address Low 1 Register" else hgroup.long (dcr:0x80000C00+0x09)++0x03 hide.long 0x00 "SNOOP_UADDRH1,Snoopable Upper Address High 1 Register" hgroup.long (dcr:0x80000C00+0x0A)++0x03 hide.long 0x00 "SNOOP_LADDRH1,Snoopable Lower Address High 1 Register" hgroup.long (dcr:0x80000C00+0x0B)++0x03 hide.long 0x00 "SNOOP_UADDRL1,Snoopable Upper Address Low 1 Register" hgroup.long (dcr:0x80000C00+0x0C)++0x03 hide.long 0x00 "SNOOP_LADDRL1,Snoopable Lower Address Low 1 Register" endif group.long (dcr:0x80000C00+0x0D)++0x03 line.long 0x00 "TESR,(Test Only) Error Status Register" bitfld.long 0x00 31. " P6CRE ,PLB6 combined response error" "-,Error" bitfld.long 0x00 30. " P6MRE ,PLB6 master read error" "-,Error" bitfld.long 0x00 29. " P6RPE ,PLB6 read data parity error" "-,Error" bitfld.long 0x00 28. " P4WPE ,PLB4 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4APE ,PLB4 address parity error" "-,Error" bitfld.long 0x00 26. " P4BPE ,PLB4 byte-enable parity error" "-,Error" rbitfld.long 0x00 25. " P4RERR ,Read/write operation error" "Write,Read" newline rbitfld.long 0x00 21.--24. " P4MID ,PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--20. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "BR4T062" width 15. group.long (dcr:0x80000F00)++0x03 line.long 0x00 "P46CR,PLB4 To PLB6 Bridge Configuration Register" rbitfld.long 0x00 31. " RTY_MASK5[0] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 30. " RTY_MASK5[1] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 29. " RTY_MASK5[2] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" newline rbitfld.long 0x00 28. " RTY_MASK6[0] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 27. " RTY_MASK6[1] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 26. " RTY_MASK6[2] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" newline bitfld.long 0x00 25. " IFE1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 24. " IFE0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding enable" "-,Enabled" bitfld.long 0x00 20.--23. " IFMID1 ,I_SYS_FLUSHINTREQ[1] interrupt forwarding PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " IFMID0 ,I_SYS_FLUSHINTREQ[0] interrupt forwarding PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 15. " RTY_MASK7[0] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 14. " RTY_MASK7[1] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" rbitfld.long 0x00 13. " RTY_MASK7[2] ,LFSR associated bit passed to countdown timer" "Blocked,Passed" newline bitfld.long 0x00 11. " IPC ,PLB6 to PLB4 bridge producer-consumer sideband signals ignore" "-,Ignored" bitfld.long 0x00 10. " OWEN ,Ordered write enable" "-,Enabled" bitfld.long 0x00 9. " SNPEN1 ,Snoopable address 1 registers enable" "-,Enabled" bitfld.long 0x00 8. " SNPEN0 ,Snoopable address 0 registers enable" "-,Enabled" newline hexmask.long.byte 0x00 0.--7. 1. " PNCR ,Prime number count register" newline if ((per.l(dcr:0x80000F00+0x01)&0xFE000000)==0x00) group.long (dcr:0x80000F00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" bitfld.long 0x00 31. " P6CRE ,PLB6 combined response error" "-,Error" bitfld.long 0x00 30. " P6MRE ,PLB6 master read error" "-,Error" bitfld.long 0x00 29. " P6RPE ,PLB6 read data parity error" "-,Error" bitfld.long 0x00 28. " P4WPE ,PLB4 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4APE ,PLB4 address parity error" "-,Error" bitfld.long 0x00 26. " P4BPE ,PLB4 byte-enable parity error" "-,Error" bitfld.long 0x00 25. " P4RERR ,Read/write operation error" "Write,Read" newline else group.long (dcr:0x80000F00+0x01)++0x03 line.long 0x00 "ESR,Error Status Register" bitfld.long 0x00 31. " P6CRE ,PLB6 combined response error" "-,Error" bitfld.long 0x00 30. " P6MRE ,PLB6 master read error" "-,Error" bitfld.long 0x00 29. " P6RPE ,PLB6 read data parity error" "-,Error" bitfld.long 0x00 28. " P4WPE ,PLB4 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4APE ,PLB4 address parity error" "-,Error" bitfld.long 0x00 26. " P4BPE ,PLB4 byte-enable parity error" "-,Error" bitfld.long 0x00 25. " P4RERR ,Read/write operation error" "Write,Read" newline bitfld.long 0x00 21.--24. " P4MID ,PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long (dcr:0x80000F00+0x02)++0x03 line.long 0x00 "P46REV,CoreConnect Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VNUMB ,Version number" hexmask.long.byte 0x00 0.--7. 1. " RVNUMB ,Revision number" if ((per.l(dcr:0x80000F00+0x01)&0xFE000000)==0x00) hgroup.long (dcr:0x80000F00+0x03)++0x03 hide.long 0x00 "EARH,Error Address Register High" hgroup.long (dcr:0x80000F00+0x04)++0x03 hide.long 0x00 "EARL,Error Address Register Low" else rgroup.long (dcr:0x80000F00+0x03)++0x03 line.long 0x00 "EARH,Error Address Register High" rgroup.long (dcr:0x80000F00+0x04)++0x03 line.long 0x00 "EARL,Error Address Register Low" endif if ((per.l(dcr:0x80000F00)&0x100)==0x100) group.long (dcr:0x80000F00+0x05)++0x03 line.long 0x00 "SNOOP_UADDRH0,Snoopable Upper Address High 0 Register" group.long (dcr:0x80000F00+0x06)++0x03 line.long 0x00 "SNOOP_LADDRH0,Snoopable Lower Address High 0 Register" group.long (dcr:0x80000F00+0x07)++0x03 line.long 0x00 "SNOOP_UADDRL0,Snoopable Upper Address Low 0 Register" group.long (dcr:0x80000F00+0x08)++0x03 line.long 0x00 "SNOOP_LADDRL0,Snoopable Lower Address Low 0 Register" else hgroup.long (dcr:0x80000F00+0x05)++0x03 hide.long 0x00 "SNOOP_UADDRH0,Snoopable Upper Address High 0 Register" hgroup.long (dcr:0x80000F00+0x06)++0x03 hide.long 0x00 "SNOOP_LADDRH0,Snoopable Lower Address High 0 Register" hgroup.long (dcr:0x80000F00+0x07)++0x03 hide.long 0x00 "SNOOP_UADDRL0,Snoopable Upper Address Low 0 Register" hgroup.long (dcr:0x80000F00+0x08)++0x03 hide.long 0x00 "SNOOP_LADDRL0,Snoopable Lower Address Low 0 Register" endif if ((per.l(dcr:0x80000F00)&0x200)==0x200) group.long (dcr:0x80000F00+0x09)++0x03 line.long 0x00 "SNOOP_UADDRH1,Snoopable Upper Address High 1 Register" group.long (dcr:0x80000F00+0x0A)++0x03 line.long 0x00 "SNOOP_LADDRH1,Snoopable Lower Address High 1 Register" group.long (dcr:0x80000F00+0x0B)++0x03 line.long 0x00 "SNOOP_UADDRL1,Snoopable Upper Address Low 1 Register" group.long (dcr:0x80000F00+0x0C)++0x03 line.long 0x00 "SNOOP_LADDRL1,Snoopable Lower Address Low 1 Register" else hgroup.long (dcr:0x80000F00+0x09)++0x03 hide.long 0x00 "SNOOP_UADDRH1,Snoopable Upper Address High 1 Register" hgroup.long (dcr:0x80000F00+0x0A)++0x03 hide.long 0x00 "SNOOP_LADDRH1,Snoopable Lower Address High 1 Register" hgroup.long (dcr:0x80000F00+0x0B)++0x03 hide.long 0x00 "SNOOP_UADDRL1,Snoopable Upper Address Low 1 Register" hgroup.long (dcr:0x80000F00+0x0C)++0x03 hide.long 0x00 "SNOOP_LADDRL1,Snoopable Lower Address Low 1 Register" endif group.long (dcr:0x80000F00+0x0D)++0x03 line.long 0x00 "TESR,(Test Only) Error Status Register" bitfld.long 0x00 31. " P6CRE ,PLB6 combined response error" "-,Error" bitfld.long 0x00 30. " P6MRE ,PLB6 master read error" "-,Error" bitfld.long 0x00 29. " P6RPE ,PLB6 read data parity error" "-,Error" bitfld.long 0x00 28. " P4WPE ,PLB4 write data parity error" "-,Error" newline bitfld.long 0x00 27. " P4APE ,PLB4 address parity error" "-,Error" bitfld.long 0x00 26. " P4BPE ,PLB4 byte-enable parity error" "-,Error" rbitfld.long 0x00 25. " P4RERR ,Read/write operation error" "Write,Read" newline rbitfld.long 0x00 21.--24. " P4MID ,PLB4 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--20. " P6MTAG ,PLB6 master tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.end ; tree.open "PCIEXG2PIPEPCS04 (Rambus PCIe Gen2 PIPE PCS Layer)" ; tree "PCS" ; %include 476ibm/pipe_pcs.ph dcr:0x00 ; tree.end ; tree "PCS2" ; %include 476ibm/pipe_pcs.ph dcr:0x00 ; tree.end ; tree.end ; tree.open "WRAP1_T12_HS06GPF04L (Rambus High Speed Serializer/Deserializer)" ; tree "PMA" ; tree "Per-Lane Registers" ; %include 476ibm/hss_perlane.ph dcr:0x00 ; tree.end ; tree "Support Block Registers" ; %include 476ibm/hss_support.ph dcr:0x00 ; tree.end ; tree.end ; tree "PMA2" ; tree "Per-Lane Registers" ; %include 476ibm/hss_perlane.ph dcr:0x00 ; tree.end ; tree "Support Block Registers" ; %include 476ibm/hss_support.ph dcr:0x00 ; tree.end ; tree.end ; tree.end ; tree "PCIEXG2UTL (PCIe Generation 2 Upper Transaction Layer)" ; %include 476ibm/pciexg2utl.ph dcr:0x00 ; tree.end ; tree.open "PCIEXG2CFG (PCIe Generation 2 Configuration Space)" ; tree "PCI Legacy Header Configuration Space Registers" ; %include 476ibm/pciexg2cfg_lhcsr.ph dcr:0x00 ; tree.end ; tree "PCI Configuration Space Capability Structures" ; tree "PCI Power Management Capability Structure" ; %include 476ibm/pciexg2cfg_pm.ph dcr:0x00 ; tree.end ; tree "PCI Message Signalled Interrupt (MSI) Capability Structure" ; %include 476ibm/pciexg2cfg_msi.ph dcr:0x00 ; tree.end ; tree "PCI Message Signalled Interrupt Extension (MSIX) Capability Structure" ; %include 476ibm/pciexg2cfg_msix.ph dcr:0x00 ; tree.end ; tree "PCI Express Capability Structure" ; %include 476ibm/pciexg2cfg_ec.ph dcr:0x00 ; tree.end ; tree "PCI Vital Product Data Capability Structure" ; %include 476ibm/pciexg2cfg_vpd.ph dcr:0x00 ; tree.end ; tree.end ; tree "PCI Express Extended Capabilities Structures" ; tree "PCI Express Advanced Error Reporting Extended Capability Structure" ; %include 476ibm/pciexg2cfg_aer.ph dcr:0x00 ; tree.end ; tree "PCI Express Virtual Channel Extended Capability Structure" ; %include 476ibm/pciexg2cfg_vc.ph dcr:0x00 ; tree.end ; tree "PCI Express Device Serial Number Extended Capability Structure" ; %include 476ibm/pciexg2cfg_dsn.ph dcr:0x00 ; tree.end ; tree "PCI Express Power Budgeting Extended Capability Structure" ; %include 476ibm/pciexg2cfg_pb.ph dcr:0x00 ; tree.end ; tree "PCI Express SR-IOV Extended Capability Structure" ; %include 476ibm/pciexg2cfg_sr.ph dcr:0x00 ; tree.end ; tree "PCI Express ARI Extended Capability Structure" ; %include 476ibm/pciexg2cfg_ari.ph dcr:0x00 ; tree.end ; tree.end ; tree "Virtual Function Reduced Configuration Space Registers" ; tree "PCI Header Type 0" ; %include 476ibm/pciexg2cfg_vfheader.ph dcr:0x00 ; tree.end ; tree "PCI Express Capability" ; %include 476ibm/pciexg2cfg_vfec.ph dcr:0x00 ; tree.end ; tree "MSI Capability" ; %include 476ibm/pciexg2cfg_vfmsi.ph dcr:0x00 ; tree.end ; tree "MSI-X Capability" ; %include 476ibm/pciexg2cfg_vfmsix.ph dcr:0x00 ; tree.end ; tree "AER Extended Capability" ; %include 476ibm/pciexg2cfg_vfaer.ph dcr:0x00 ; tree.end ; tree "ARI Extended Capability" ; %include 476ibm/pciexg2cfg_vfari.ph dcr:0x00 ; tree.end ; tree.end ; tree.end tree.open "PCIEXGPL4DDR (GBIF To PLB4 DDR)" tree "PCIe 0 4x0" width 10. group.long dcr:0x00000060++0x03 line.long 0x00 "CBAHR,Configuration Base Address High Register" group.long (dcr:0x00000060+0x01)++0x03 line.long 0x00 "CBALR,Configuration Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Configuration base low" group.long (dcr:0x00000060+0x02)++0x03 line.long 0x00 "CMR,Configuration Mask Register" hexmask.long 0x00 7.--31. 0x80 " BAM ,Configuration region base address mask" bitfld.long 0x00 0. " VAL ,Configuration space region valid" "-,Valid" group.long (dcr:0x00000060+0x03)++0x03 line.long 0x00 "MBAHR,Message Base Address High Register" group.long (dcr:0x00000060+0x04)++0x03 line.long 0x00 "MBALR,Message Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Message region base address low" group.long (dcr:0x00000060+0x05)++0x03 line.long 0x00 "MMR,Message Mask Register" bitfld.long 0x00 15. " MSD ,Message data handling" "Discarded,Forwarded" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Message region base address mask" bitfld.long 0x00 0. " VAL ,Message region valid" "-,Valid" group.long (dcr:0x00000060+0x06)++0x03 line.long 0x00 "OMR1BAHR,Outbound Memory Region 1 Base Address High Register" group.long (dcr:0x00000060+0x07)++0x03 line.long 0x00 "OMR1BALR,Outbound Memory Region 1 Base Address Low Register" bitfld.long 0x00 27.--31. " BAL ,Base address low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (dcr:0x00000060+0x08)++0x03 line.long 0x00 "OMR1MHR,Outbound Memory Region 1 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x00000060+0x09)++0x03 line.long 0x00 "OMR1MLR,Outbound Memory Region 1 Mask Low Register" bitfld.long 0x00 27.--31. " BAML ,Mask bits low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. " SRV[0] ,Subregion 0 enable" "-,Enabled" bitfld.long 0x00 14. " [1] ,Subregion 1 enable" "-,Enabled" bitfld.long 0x00 13. " [2] ,Subregion 2 enable" "-,Enabled" bitfld.long 0x00 12. " [3] ,Subregion 3 enable" "-,Enabled" newline bitfld.long 0x00 11. " [4] ,Subregion 4 enable" "-,Enabled" bitfld.long 0x00 10. " [5] ,Subregion 5 enable" "-,Enabled" bitfld.long 0x00 9. " [6] ,Subregion 6 enable" "-,Enabled" bitfld.long 0x00 8. " [7] ,Subregion 7 enable" "-,Enabled" newline bitfld.long 0x00 1.--2. " TM ,TC mode" "Eight,Two,Single,?..." bitfld.long 0x00 0. " VAL ,Memory region 1 valid" "-,Valid" group.long (dcr:0x00000060+0x0A)++0x03 line.long 0x00 "OMR2BAHR,Outbound Memory Region 2 Base Address High Register" group.long (dcr:0x00000060+0x0B)++0x03 line.long 0x00 "OMR2BALR,Outbound Memory Region 2 Base Address Low Register" hexmask.long.word 0x00 20.--31. 0x10 " BAL ,Base address low" group.long (dcr:0x00000060+0x0C)++0x03 line.long 0x00 "OMR2MHR,Outbound Memory Region 2 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x00000060+0x0D)++0x03 line.long 0x00 "OMR2MLR,Outbound Memory Region 2 Mask Low Register" hexmask.long.word 0x00 20.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 0. " VAL ,Memory region 2 valid" "-,Valid" group.long (dcr:0x00000060+0x0E)++0x03 line.long 0x00 "OMR3BAHR,Outbound Memory Region 3 Base Address High Register" group.long (dcr:0x00000060+0x0F)++0x03 line.long 0x00 "OMR3BALR,Outbound Memory Region 3 Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Base address low" group.long (dcr:0x00000060+0x10)++0x03 line.long 0x00 "OMR3MHR,Outbound Memory Region 3 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x00000060+0x11)++0x03 line.long 0x00 "OMR3MLR,Outbound Memory Region 3 Mask Low Register" hexmask.long 0x00 7.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 1. " IOS ,IO space transaction type" "Fuse/memory,IO" bitfld.long 0x00 0. " VAL ,Memory region 3 valid" "-,Valid" group.long (dcr:0x00000060+0x12)++0x03 line.long 0x00 "RRBAHR,Register Region Base Address High Register" group.long (dcr:0x00000060+0x13)++0x03 line.long 0x00 "RRBALR,Register Region Base Address Low Register" hexmask.long 0x00 7.--31. 1. " BAL ,Base address low" group.long (dcr:0x00000060+0x14)++0x03 line.long 0x00 "RRMR,Register Region Mask Register" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Base address mask bits [49:56]" bitfld.long 0x00 0. " VAL ,Register region valid" "-,Valid" group.long (dcr:0x00000060+0x15)++0x03 line.long 0x00 "TSCR,TDC Slave Configuration Register" bitfld.long 0x00 28.--31. " ETM0 ,Enhanced TDC vector 0 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " ETE0 ,Enhanced TDC mask vector 0 enable" "-,Enabled" bitfld.long 0x00 20.--23. " ETM1 ,Enhanced TDC vector 1 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " ETE1 ,Enhanced TDC mask vector 1 enable" "-,Enabled" newline bitfld.long 0x00 12.--15. " ETM2 ,Enhanced TDC vector 2 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " ETE2 ,Enhanced TDC mask vector 2 enable" "-,Enabled" bitfld.long 0x00 4.--7. " ETM3 ,Enhanced TDC vector 3 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " ETE3 ,Enhanced TDC mask vector 3 enable" "-,Enabled" newline bitfld.long 0x00 0. " BTDE ,Base TDC masking enable" "-,Enabled" group.long (dcr:0x00000060+0x16)++0x03 line.long 0x00 "CR1,Configuration Register 1" bitfld.long 0x00 31. " IWPE ,Master parity check enable" "-,Enabled" bitfld.long 0x00 30. " ORPE ,Slave parity check enable" "-,Enabled" bitfld.long 0x00 28. " MGA ,PLB master guarded attribute" "0,1" bitfld.long 0x00 26.--27. " MPRI ,PLB master priority" "0,1,2,3" newline bitfld.long 0x00 25. " DMER ,Disable slave master write data error assertion" "No,Yes" bitfld.long 0x00 24. " DTMB ,Disable master base TDC masking" "No,Yes" bitfld.long 0x00 23. " DTME ,Disable master enhanced TDC masking" "No,Yes" bitfld.long 0x00 22. " DDSD ,Disable slave DDR transfers" "No,Yes" newline bitfld.long 0x00 21. " DDMD ,Disable master DDR transfers" "No,Yes" bitfld.long 0x00 20. " DSDC ,Disable slave PLB request decoding" "No,Yes" bitfld.long 0x00 19. " DMRQ ,Disable master transfers" "No,Yes" bitfld.long 0x00 16.--18. " MRRP ,Master read requests address-to-data pipeline" "1,2,4,8,16,?..." newline bitfld.long 0x00 12.--13. " MBRS ,Master burst size" "128 bytes,256 bytes,512 bytes,?..." bitfld.long 0x00 11. " DSDS ,Disable slave secondary PLB request decoding" "No,Yes" bitfld.long 0x00 8.--10. " SRRP ,Slave read request address-to-data pipeline" "1,2,3,8,16,?..." bitfld.long 0x00 7. " SLKE ,Slave lock/error control" "Lock,Error" group.long (dcr:0x00000060+0x17)++0x03 line.long 0x00 "ESAMR,Error Status And Mask Register" eventfld.long 0x00 31. " SEV ,Slave error valid" "-,Valid" eventfld.long 0x00 30. " MIRQ ,MIRQ received" "-,Received" eventfld.long 0x00 29. " MERR ,Master write data error" "-,Error" eventfld.long 0x00 28. " TOT ,Timeout received" "-,Received" newline eventfld.long 0x00 27. " SLPE ,Slave parity error" "-,Error" eventfld.long 0x00 26. " MSPE ,Master parity error" "-,Error" eventfld.long 0x00 25. " IADE ,Inbound address decoding error" "-,Error" eventfld.long 0x00 24. " MRDE ,Master read data error" "-,Error" newline bitfld.long 0x00 15. " SEM ,Slave error mask" "0,1" bitfld.long 0x00 14. " MIRM ,MIRQ received error mask" "0,1" bitfld.long 0x00 13. " MERM ,Master write data error mask" "0,1" bitfld.long 0x00 12. " TOTM ,Timeout received error mask" "0,1" newline bitfld.long 0x00 11. " SPEM ,Slave parity error mask" "0,1" bitfld.long 0x00 10. " MPEM ,Master parity error mask" "0,1" bitfld.long 0x00 9. " IAEM ,Inbound address error mask" "0,1" bitfld.long 0x00 8. " MRDM ,Master read data error mask" "0,1" rgroup.long (dcr:0x00000060+0x18)++0x03 line.long 0x00 "SEAHR,Slave Error Address High Register" rgroup.long (dcr:0x00000060+0x19)++0x03 line.long 0x00 "SEALR,Slave Error Address Low Register" rgroup.long (dcr:0x00000060+0x1A)++0x03 line.long 0x00 "SEAR,Slave Error Attribute Register" bitfld.long 0x00 31. " SERNW ,PLB read attribute" "0,1" bitfld.long 0x00 27.--30. " SESIZE ,PLB size attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23.--26. " SEMID ,PLB master ID attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x00000060+0x1B)++0x03 line.long 0x00 "GPCR,General Purpose Control Register" hexmask.long.tbyte 0x00 8.--31. 1. " GPC ,General purpose control bits" hexmask.long.byte 0x00 0.--7. 1. " DBSL ,Debug select" group.long (dcr:0x00000060+0x1C)++0x03 line.long 0x00 "CR2,Configuration Register 2" bitfld.long 0x00 31. " IRPW ,Allow inbound read requests bypass previous write request" "-,Allowed" bitfld.long 0x00 30. " ICPW ,Allow inbound read response bypass previous write request" "-,Allowed" bitfld.long 0x00 29. " ORPW ,Allow outbound read request bypass previous write request" "-,Allowed" rgroup.long (dcr:0x00000060+0x1D)++0x03 line.long 0x00 "DR,Debug Register" rgroup.long (dcr:0x00000060+0x1E)++0x03 line.long 0x00 "RIDR,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VERN ,Core version number" hexmask.long.byte 0x00 0.--7. 1. " REVN ,Core revision number" width 0x0B tree.end tree "PCIe 1 4x1" width 10. group.long dcr:0x00000080++0x03 line.long 0x00 "CBAHR,Configuration Base Address High Register" group.long (dcr:0x00000080+0x01)++0x03 line.long 0x00 "CBALR,Configuration Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Configuration base low" group.long (dcr:0x00000080+0x02)++0x03 line.long 0x00 "CMR,Configuration Mask Register" hexmask.long 0x00 7.--31. 0x80 " BAM ,Configuration region base address mask" bitfld.long 0x00 0. " VAL ,Configuration space region valid" "-,Valid" group.long (dcr:0x00000080+0x03)++0x03 line.long 0x00 "MBAHR,Message Base Address High Register" group.long (dcr:0x00000080+0x04)++0x03 line.long 0x00 "MBALR,Message Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Message region base address low" group.long (dcr:0x00000080+0x05)++0x03 line.long 0x00 "MMR,Message Mask Register" bitfld.long 0x00 15. " MSD ,Message data handling" "Discarded,Forwarded" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Message region base address mask" bitfld.long 0x00 0. " VAL ,Message region valid" "-,Valid" group.long (dcr:0x00000080+0x06)++0x03 line.long 0x00 "OMR1BAHR,Outbound Memory Region 1 Base Address High Register" group.long (dcr:0x00000080+0x07)++0x03 line.long 0x00 "OMR1BALR,Outbound Memory Region 1 Base Address Low Register" bitfld.long 0x00 27.--31. " BAL ,Base address low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (dcr:0x00000080+0x08)++0x03 line.long 0x00 "OMR1MHR,Outbound Memory Region 1 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x00000080+0x09)++0x03 line.long 0x00 "OMR1MLR,Outbound Memory Region 1 Mask Low Register" bitfld.long 0x00 27.--31. " BAML ,Mask bits low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. " SRV[0] ,Subregion 0 enable" "-,Enabled" bitfld.long 0x00 14. " [1] ,Subregion 1 enable" "-,Enabled" bitfld.long 0x00 13. " [2] ,Subregion 2 enable" "-,Enabled" bitfld.long 0x00 12. " [3] ,Subregion 3 enable" "-,Enabled" newline bitfld.long 0x00 11. " [4] ,Subregion 4 enable" "-,Enabled" bitfld.long 0x00 10. " [5] ,Subregion 5 enable" "-,Enabled" bitfld.long 0x00 9. " [6] ,Subregion 6 enable" "-,Enabled" bitfld.long 0x00 8. " [7] ,Subregion 7 enable" "-,Enabled" newline bitfld.long 0x00 1.--2. " TM ,TC mode" "Eight,Two,Single,?..." bitfld.long 0x00 0. " VAL ,Memory region 1 valid" "-,Valid" group.long (dcr:0x00000080+0x0A)++0x03 line.long 0x00 "OMR2BAHR,Outbound Memory Region 2 Base Address High Register" group.long (dcr:0x00000080+0x0B)++0x03 line.long 0x00 "OMR2BALR,Outbound Memory Region 2 Base Address Low Register" hexmask.long.word 0x00 20.--31. 0x10 " BAL ,Base address low" group.long (dcr:0x00000080+0x0C)++0x03 line.long 0x00 "OMR2MHR,Outbound Memory Region 2 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x00000080+0x0D)++0x03 line.long 0x00 "OMR2MLR,Outbound Memory Region 2 Mask Low Register" hexmask.long.word 0x00 20.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 0. " VAL ,Memory region 2 valid" "-,Valid" group.long (dcr:0x00000080+0x0E)++0x03 line.long 0x00 "OMR3BAHR,Outbound Memory Region 3 Base Address High Register" group.long (dcr:0x00000080+0x0F)++0x03 line.long 0x00 "OMR3BALR,Outbound Memory Region 3 Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Base address low" group.long (dcr:0x00000080+0x10)++0x03 line.long 0x00 "OMR3MHR,Outbound Memory Region 3 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x00000080+0x11)++0x03 line.long 0x00 "OMR3MLR,Outbound Memory Region 3 Mask Low Register" hexmask.long 0x00 7.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 1. " IOS ,IO space transaction type" "Fuse/memory,IO" bitfld.long 0x00 0. " VAL ,Memory region 3 valid" "-,Valid" group.long (dcr:0x00000080+0x12)++0x03 line.long 0x00 "RRBAHR,Register Region Base Address High Register" group.long (dcr:0x00000080+0x13)++0x03 line.long 0x00 "RRBALR,Register Region Base Address Low Register" hexmask.long 0x00 7.--31. 1. " BAL ,Base address low" group.long (dcr:0x00000080+0x14)++0x03 line.long 0x00 "RRMR,Register Region Mask Register" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Base address mask bits [49:56]" bitfld.long 0x00 0. " VAL ,Register region valid" "-,Valid" group.long (dcr:0x00000080+0x15)++0x03 line.long 0x00 "TSCR,TDC Slave Configuration Register" bitfld.long 0x00 28.--31. " ETM0 ,Enhanced TDC vector 0 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " ETE0 ,Enhanced TDC mask vector 0 enable" "-,Enabled" bitfld.long 0x00 20.--23. " ETM1 ,Enhanced TDC vector 1 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " ETE1 ,Enhanced TDC mask vector 1 enable" "-,Enabled" newline bitfld.long 0x00 12.--15. " ETM2 ,Enhanced TDC vector 2 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " ETE2 ,Enhanced TDC mask vector 2 enable" "-,Enabled" bitfld.long 0x00 4.--7. " ETM3 ,Enhanced TDC vector 3 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " ETE3 ,Enhanced TDC mask vector 3 enable" "-,Enabled" newline bitfld.long 0x00 0. " BTDE ,Base TDC masking enable" "-,Enabled" group.long (dcr:0x00000080+0x16)++0x03 line.long 0x00 "CR1,Configuration Register 1" bitfld.long 0x00 31. " IWPE ,Master parity check enable" "-,Enabled" bitfld.long 0x00 30. " ORPE ,Slave parity check enable" "-,Enabled" bitfld.long 0x00 28. " MGA ,PLB master guarded attribute" "0,1" bitfld.long 0x00 26.--27. " MPRI ,PLB master priority" "0,1,2,3" newline bitfld.long 0x00 25. " DMER ,Disable slave master write data error assertion" "No,Yes" bitfld.long 0x00 24. " DTMB ,Disable master base TDC masking" "No,Yes" bitfld.long 0x00 23. " DTME ,Disable master enhanced TDC masking" "No,Yes" bitfld.long 0x00 22. " DDSD ,Disable slave DDR transfers" "No,Yes" newline bitfld.long 0x00 21. " DDMD ,Disable master DDR transfers" "No,Yes" bitfld.long 0x00 20. " DSDC ,Disable slave PLB request decoding" "No,Yes" bitfld.long 0x00 19. " DMRQ ,Disable master transfers" "No,Yes" bitfld.long 0x00 16.--18. " MRRP ,Master read requests address-to-data pipeline" "1,2,4,8,16,?..." newline bitfld.long 0x00 12.--13. " MBRS ,Master burst size" "128 bytes,256 bytes,512 bytes,?..." bitfld.long 0x00 11. " DSDS ,Disable slave secondary PLB request decoding" "No,Yes" bitfld.long 0x00 8.--10. " SRRP ,Slave read request address-to-data pipeline" "1,2,3,8,16,?..." bitfld.long 0x00 7. " SLKE ,Slave lock/error control" "Lock,Error" group.long (dcr:0x00000080+0x17)++0x03 line.long 0x00 "ESAMR,Error Status And Mask Register" eventfld.long 0x00 31. " SEV ,Slave error valid" "-,Valid" eventfld.long 0x00 30. " MIRQ ,MIRQ received" "-,Received" eventfld.long 0x00 29. " MERR ,Master write data error" "-,Error" eventfld.long 0x00 28. " TOT ,Timeout received" "-,Received" newline eventfld.long 0x00 27. " SLPE ,Slave parity error" "-,Error" eventfld.long 0x00 26. " MSPE ,Master parity error" "-,Error" eventfld.long 0x00 25. " IADE ,Inbound address decoding error" "-,Error" eventfld.long 0x00 24. " MRDE ,Master read data error" "-,Error" newline bitfld.long 0x00 15. " SEM ,Slave error mask" "0,1" bitfld.long 0x00 14. " MIRM ,MIRQ received error mask" "0,1" bitfld.long 0x00 13. " MERM ,Master write data error mask" "0,1" bitfld.long 0x00 12. " TOTM ,Timeout received error mask" "0,1" newline bitfld.long 0x00 11. " SPEM ,Slave parity error mask" "0,1" bitfld.long 0x00 10. " MPEM ,Master parity error mask" "0,1" bitfld.long 0x00 9. " IAEM ,Inbound address error mask" "0,1" bitfld.long 0x00 8. " MRDM ,Master read data error mask" "0,1" rgroup.long (dcr:0x00000080+0x18)++0x03 line.long 0x00 "SEAHR,Slave Error Address High Register" rgroup.long (dcr:0x00000080+0x19)++0x03 line.long 0x00 "SEALR,Slave Error Address Low Register" rgroup.long (dcr:0x00000080+0x1A)++0x03 line.long 0x00 "SEAR,Slave Error Attribute Register" bitfld.long 0x00 31. " SERNW ,PLB read attribute" "0,1" bitfld.long 0x00 27.--30. " SESIZE ,PLB size attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23.--26. " SEMID ,PLB master ID attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x00000080+0x1B)++0x03 line.long 0x00 "GPCR,General Purpose Control Register" hexmask.long.tbyte 0x00 8.--31. 1. " GPC ,General purpose control bits" hexmask.long.byte 0x00 0.--7. 1. " DBSL ,Debug select" group.long (dcr:0x00000080+0x1C)++0x03 line.long 0x00 "CR2,Configuration Register 2" bitfld.long 0x00 31. " IRPW ,Allow inbound read requests bypass previous write request" "-,Allowed" bitfld.long 0x00 30. " ICPW ,Allow inbound read response bypass previous write request" "-,Allowed" bitfld.long 0x00 29. " ORPW ,Allow outbound read request bypass previous write request" "-,Allowed" rgroup.long (dcr:0x00000080+0x1D)++0x03 line.long 0x00 "DR,Debug Register" rgroup.long (dcr:0x00000080+0x1E)++0x03 line.long 0x00 "RIDR,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VERN ,Core version number" hexmask.long.byte 0x00 0.--7. 1. " REVN ,Core revision number" width 0x0B tree.end tree "PCIe 0 2x0" width 10. group.long dcr:0x000000A0++0x03 line.long 0x00 "CBAHR,Configuration Base Address High Register" group.long (dcr:0x000000A0+0x01)++0x03 line.long 0x00 "CBALR,Configuration Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Configuration base low" group.long (dcr:0x000000A0+0x02)++0x03 line.long 0x00 "CMR,Configuration Mask Register" hexmask.long 0x00 7.--31. 0x80 " BAM ,Configuration region base address mask" bitfld.long 0x00 0. " VAL ,Configuration space region valid" "-,Valid" group.long (dcr:0x000000A0+0x03)++0x03 line.long 0x00 "MBAHR,Message Base Address High Register" group.long (dcr:0x000000A0+0x04)++0x03 line.long 0x00 "MBALR,Message Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Message region base address low" group.long (dcr:0x000000A0+0x05)++0x03 line.long 0x00 "MMR,Message Mask Register" bitfld.long 0x00 15. " MSD ,Message data handling" "Discarded,Forwarded" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Message region base address mask" bitfld.long 0x00 0. " VAL ,Message region valid" "-,Valid" group.long (dcr:0x000000A0+0x06)++0x03 line.long 0x00 "OMR1BAHR,Outbound Memory Region 1 Base Address High Register" group.long (dcr:0x000000A0+0x07)++0x03 line.long 0x00 "OMR1BALR,Outbound Memory Region 1 Base Address Low Register" bitfld.long 0x00 27.--31. " BAL ,Base address low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (dcr:0x000000A0+0x08)++0x03 line.long 0x00 "OMR1MHR,Outbound Memory Region 1 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x000000A0+0x09)++0x03 line.long 0x00 "OMR1MLR,Outbound Memory Region 1 Mask Low Register" bitfld.long 0x00 27.--31. " BAML ,Mask bits low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. " SRV[0] ,Subregion 0 enable" "-,Enabled" bitfld.long 0x00 14. " [1] ,Subregion 1 enable" "-,Enabled" bitfld.long 0x00 13. " [2] ,Subregion 2 enable" "-,Enabled" bitfld.long 0x00 12. " [3] ,Subregion 3 enable" "-,Enabled" newline bitfld.long 0x00 11. " [4] ,Subregion 4 enable" "-,Enabled" bitfld.long 0x00 10. " [5] ,Subregion 5 enable" "-,Enabled" bitfld.long 0x00 9. " [6] ,Subregion 6 enable" "-,Enabled" bitfld.long 0x00 8. " [7] ,Subregion 7 enable" "-,Enabled" newline bitfld.long 0x00 1.--2. " TM ,TC mode" "Eight,Two,Single,?..." bitfld.long 0x00 0. " VAL ,Memory region 1 valid" "-,Valid" group.long (dcr:0x000000A0+0x0A)++0x03 line.long 0x00 "OMR2BAHR,Outbound Memory Region 2 Base Address High Register" group.long (dcr:0x000000A0+0x0B)++0x03 line.long 0x00 "OMR2BALR,Outbound Memory Region 2 Base Address Low Register" hexmask.long.word 0x00 20.--31. 0x10 " BAL ,Base address low" group.long (dcr:0x000000A0+0x0C)++0x03 line.long 0x00 "OMR2MHR,Outbound Memory Region 2 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x000000A0+0x0D)++0x03 line.long 0x00 "OMR2MLR,Outbound Memory Region 2 Mask Low Register" hexmask.long.word 0x00 20.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 0. " VAL ,Memory region 2 valid" "-,Valid" group.long (dcr:0x000000A0+0x0E)++0x03 line.long 0x00 "OMR3BAHR,Outbound Memory Region 3 Base Address High Register" group.long (dcr:0x000000A0+0x0F)++0x03 line.long 0x00 "OMR3BALR,Outbound Memory Region 3 Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Base address low" group.long (dcr:0x000000A0+0x10)++0x03 line.long 0x00 "OMR3MHR,Outbound Memory Region 3 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x000000A0+0x11)++0x03 line.long 0x00 "OMR3MLR,Outbound Memory Region 3 Mask Low Register" hexmask.long 0x00 7.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 1. " IOS ,IO space transaction type" "Fuse/memory,IO" bitfld.long 0x00 0. " VAL ,Memory region 3 valid" "-,Valid" group.long (dcr:0x000000A0+0x12)++0x03 line.long 0x00 "RRBAHR,Register Region Base Address High Register" group.long (dcr:0x000000A0+0x13)++0x03 line.long 0x00 "RRBALR,Register Region Base Address Low Register" hexmask.long 0x00 7.--31. 1. " BAL ,Base address low" group.long (dcr:0x000000A0+0x14)++0x03 line.long 0x00 "RRMR,Register Region Mask Register" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Base address mask bits [49:56]" bitfld.long 0x00 0. " VAL ,Register region valid" "-,Valid" group.long (dcr:0x000000A0+0x15)++0x03 line.long 0x00 "TSCR,TDC Slave Configuration Register" bitfld.long 0x00 28.--31. " ETM0 ,Enhanced TDC vector 0 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " ETE0 ,Enhanced TDC mask vector 0 enable" "-,Enabled" bitfld.long 0x00 20.--23. " ETM1 ,Enhanced TDC vector 1 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " ETE1 ,Enhanced TDC mask vector 1 enable" "-,Enabled" newline bitfld.long 0x00 12.--15. " ETM2 ,Enhanced TDC vector 2 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " ETE2 ,Enhanced TDC mask vector 2 enable" "-,Enabled" bitfld.long 0x00 4.--7. " ETM3 ,Enhanced TDC vector 3 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " ETE3 ,Enhanced TDC mask vector 3 enable" "-,Enabled" newline bitfld.long 0x00 0. " BTDE ,Base TDC masking enable" "-,Enabled" group.long (dcr:0x000000A0+0x16)++0x03 line.long 0x00 "CR1,Configuration Register 1" bitfld.long 0x00 31. " IWPE ,Master parity check enable" "-,Enabled" bitfld.long 0x00 30. " ORPE ,Slave parity check enable" "-,Enabled" bitfld.long 0x00 28. " MGA ,PLB master guarded attribute" "0,1" bitfld.long 0x00 26.--27. " MPRI ,PLB master priority" "0,1,2,3" newline bitfld.long 0x00 25. " DMER ,Disable slave master write data error assertion" "No,Yes" bitfld.long 0x00 24. " DTMB ,Disable master base TDC masking" "No,Yes" bitfld.long 0x00 23. " DTME ,Disable master enhanced TDC masking" "No,Yes" bitfld.long 0x00 22. " DDSD ,Disable slave DDR transfers" "No,Yes" newline bitfld.long 0x00 21. " DDMD ,Disable master DDR transfers" "No,Yes" bitfld.long 0x00 20. " DSDC ,Disable slave PLB request decoding" "No,Yes" bitfld.long 0x00 19. " DMRQ ,Disable master transfers" "No,Yes" bitfld.long 0x00 16.--18. " MRRP ,Master read requests address-to-data pipeline" "1,2,4,8,16,?..." newline bitfld.long 0x00 12.--13. " MBRS ,Master burst size" "128 bytes,256 bytes,512 bytes,?..." bitfld.long 0x00 11. " DSDS ,Disable slave secondary PLB request decoding" "No,Yes" bitfld.long 0x00 8.--10. " SRRP ,Slave read request address-to-data pipeline" "1,2,3,8,16,?..." bitfld.long 0x00 7. " SLKE ,Slave lock/error control" "Lock,Error" group.long (dcr:0x000000A0+0x17)++0x03 line.long 0x00 "ESAMR,Error Status And Mask Register" eventfld.long 0x00 31. " SEV ,Slave error valid" "-,Valid" eventfld.long 0x00 30. " MIRQ ,MIRQ received" "-,Received" eventfld.long 0x00 29. " MERR ,Master write data error" "-,Error" eventfld.long 0x00 28. " TOT ,Timeout received" "-,Received" newline eventfld.long 0x00 27. " SLPE ,Slave parity error" "-,Error" eventfld.long 0x00 26. " MSPE ,Master parity error" "-,Error" eventfld.long 0x00 25. " IADE ,Inbound address decoding error" "-,Error" eventfld.long 0x00 24. " MRDE ,Master read data error" "-,Error" newline bitfld.long 0x00 15. " SEM ,Slave error mask" "0,1" bitfld.long 0x00 14. " MIRM ,MIRQ received error mask" "0,1" bitfld.long 0x00 13. " MERM ,Master write data error mask" "0,1" bitfld.long 0x00 12. " TOTM ,Timeout received error mask" "0,1" newline bitfld.long 0x00 11. " SPEM ,Slave parity error mask" "0,1" bitfld.long 0x00 10. " MPEM ,Master parity error mask" "0,1" bitfld.long 0x00 9. " IAEM ,Inbound address error mask" "0,1" bitfld.long 0x00 8. " MRDM ,Master read data error mask" "0,1" rgroup.long (dcr:0x000000A0+0x18)++0x03 line.long 0x00 "SEAHR,Slave Error Address High Register" rgroup.long (dcr:0x000000A0+0x19)++0x03 line.long 0x00 "SEALR,Slave Error Address Low Register" rgroup.long (dcr:0x000000A0+0x1A)++0x03 line.long 0x00 "SEAR,Slave Error Attribute Register" bitfld.long 0x00 31. " SERNW ,PLB read attribute" "0,1" bitfld.long 0x00 27.--30. " SESIZE ,PLB size attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23.--26. " SEMID ,PLB master ID attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x000000A0+0x1B)++0x03 line.long 0x00 "GPCR,General Purpose Control Register" hexmask.long.tbyte 0x00 8.--31. 1. " GPC ,General purpose control bits" hexmask.long.byte 0x00 0.--7. 1. " DBSL ,Debug select" group.long (dcr:0x000000A0+0x1C)++0x03 line.long 0x00 "CR2,Configuration Register 2" bitfld.long 0x00 31. " IRPW ,Allow inbound read requests bypass previous write request" "-,Allowed" bitfld.long 0x00 30. " ICPW ,Allow inbound read response bypass previous write request" "-,Allowed" bitfld.long 0x00 29. " ORPW ,Allow outbound read request bypass previous write request" "-,Allowed" rgroup.long (dcr:0x000000A0+0x1D)++0x03 line.long 0x00 "DR,Debug Register" rgroup.long (dcr:0x000000A0+0x1E)++0x03 line.long 0x00 "RIDR,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VERN ,Core version number" hexmask.long.byte 0x00 0.--7. 1. " REVN ,Core revision number" width 0x0B tree.end tree "PCIe 1 2x1" width 10. group.long dcr:0x000000C0++0x03 line.long 0x00 "CBAHR,Configuration Base Address High Register" group.long (dcr:0x000000C0+0x01)++0x03 line.long 0x00 "CBALR,Configuration Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Configuration base low" group.long (dcr:0x000000C0+0x02)++0x03 line.long 0x00 "CMR,Configuration Mask Register" hexmask.long 0x00 7.--31. 0x80 " BAM ,Configuration region base address mask" bitfld.long 0x00 0. " VAL ,Configuration space region valid" "-,Valid" group.long (dcr:0x000000C0+0x03)++0x03 line.long 0x00 "MBAHR,Message Base Address High Register" group.long (dcr:0x000000C0+0x04)++0x03 line.long 0x00 "MBALR,Message Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Message region base address low" group.long (dcr:0x000000C0+0x05)++0x03 line.long 0x00 "MMR,Message Mask Register" bitfld.long 0x00 15. " MSD ,Message data handling" "Discarded,Forwarded" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Message region base address mask" bitfld.long 0x00 0. " VAL ,Message region valid" "-,Valid" group.long (dcr:0x000000C0+0x06)++0x03 line.long 0x00 "OMR1BAHR,Outbound Memory Region 1 Base Address High Register" group.long (dcr:0x000000C0+0x07)++0x03 line.long 0x00 "OMR1BALR,Outbound Memory Region 1 Base Address Low Register" bitfld.long 0x00 27.--31. " BAL ,Base address low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (dcr:0x000000C0+0x08)++0x03 line.long 0x00 "OMR1MHR,Outbound Memory Region 1 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x000000C0+0x09)++0x03 line.long 0x00 "OMR1MLR,Outbound Memory Region 1 Mask Low Register" bitfld.long 0x00 27.--31. " BAML ,Mask bits low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. " SRV[0] ,Subregion 0 enable" "-,Enabled" bitfld.long 0x00 14. " [1] ,Subregion 1 enable" "-,Enabled" bitfld.long 0x00 13. " [2] ,Subregion 2 enable" "-,Enabled" bitfld.long 0x00 12. " [3] ,Subregion 3 enable" "-,Enabled" newline bitfld.long 0x00 11. " [4] ,Subregion 4 enable" "-,Enabled" bitfld.long 0x00 10. " [5] ,Subregion 5 enable" "-,Enabled" bitfld.long 0x00 9. " [6] ,Subregion 6 enable" "-,Enabled" bitfld.long 0x00 8. " [7] ,Subregion 7 enable" "-,Enabled" newline bitfld.long 0x00 1.--2. " TM ,TC mode" "Eight,Two,Single,?..." bitfld.long 0x00 0. " VAL ,Memory region 1 valid" "-,Valid" group.long (dcr:0x000000C0+0x0A)++0x03 line.long 0x00 "OMR2BAHR,Outbound Memory Region 2 Base Address High Register" group.long (dcr:0x000000C0+0x0B)++0x03 line.long 0x00 "OMR2BALR,Outbound Memory Region 2 Base Address Low Register" hexmask.long.word 0x00 20.--31. 0x10 " BAL ,Base address low" group.long (dcr:0x000000C0+0x0C)++0x03 line.long 0x00 "OMR2MHR,Outbound Memory Region 2 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x000000C0+0x0D)++0x03 line.long 0x00 "OMR2MLR,Outbound Memory Region 2 Mask Low Register" hexmask.long.word 0x00 20.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 0. " VAL ,Memory region 2 valid" "-,Valid" group.long (dcr:0x000000C0+0x0E)++0x03 line.long 0x00 "OMR3BAHR,Outbound Memory Region 3 Base Address High Register" group.long (dcr:0x000000C0+0x0F)++0x03 line.long 0x00 "OMR3BALR,Outbound Memory Region 3 Base Address Low Register" hexmask.long 0x00 7.--31. 0x80 " BAL ,Base address low" group.long (dcr:0x000000C0+0x10)++0x03 line.long 0x00 "OMR3MHR,Outbound Memory Region 3 Mask High Register" hexmask.long 0x00 0.--30. 1. " BAMH ,Mask bits high" group.long (dcr:0x000000C0+0x11)++0x03 line.long 0x00 "OMR3MLR,Outbound Memory Region 3 Mask Low Register" hexmask.long 0x00 7.--31. 1. " BAML ,Mask bits low" bitfld.long 0x00 1. " IOS ,IO space transaction type" "Fuse/memory,IO" bitfld.long 0x00 0. " VAL ,Memory region 3 valid" "-,Valid" group.long (dcr:0x000000C0+0x12)++0x03 line.long 0x00 "RRBAHR,Register Region Base Address High Register" group.long (dcr:0x000000C0+0x13)++0x03 line.long 0x00 "RRBALR,Register Region Base Address Low Register" hexmask.long 0x00 7.--31. 1. " BAL ,Base address low" group.long (dcr:0x000000C0+0x14)++0x03 line.long 0x00 "RRMR,Register Region Mask Register" hexmask.long.word 0x00 7.--14. 0x80 " BAM ,Base address mask bits [49:56]" bitfld.long 0x00 0. " VAL ,Register region valid" "-,Valid" group.long (dcr:0x000000C0+0x15)++0x03 line.long 0x00 "TSCR,TDC Slave Configuration Register" bitfld.long 0x00 28.--31. " ETM0 ,Enhanced TDC vector 0 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " ETE0 ,Enhanced TDC mask vector 0 enable" "-,Enabled" bitfld.long 0x00 20.--23. " ETM1 ,Enhanced TDC vector 1 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " ETE1 ,Enhanced TDC mask vector 1 enable" "-,Enabled" newline bitfld.long 0x00 12.--15. " ETM2 ,Enhanced TDC vector 2 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " ETE2 ,Enhanced TDC mask vector 2 enable" "-,Enabled" bitfld.long 0x00 4.--7. " ETM3 ,Enhanced TDC vector 3 master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " ETE3 ,Enhanced TDC mask vector 3 enable" "-,Enabled" newline bitfld.long 0x00 0. " BTDE ,Base TDC masking enable" "-,Enabled" group.long (dcr:0x000000C0+0x16)++0x03 line.long 0x00 "CR1,Configuration Register 1" bitfld.long 0x00 31. " IWPE ,Master parity check enable" "-,Enabled" bitfld.long 0x00 30. " ORPE ,Slave parity check enable" "-,Enabled" bitfld.long 0x00 28. " MGA ,PLB master guarded attribute" "0,1" bitfld.long 0x00 26.--27. " MPRI ,PLB master priority" "0,1,2,3" newline bitfld.long 0x00 25. " DMER ,Disable slave master write data error assertion" "No,Yes" bitfld.long 0x00 24. " DTMB ,Disable master base TDC masking" "No,Yes" bitfld.long 0x00 23. " DTME ,Disable master enhanced TDC masking" "No,Yes" bitfld.long 0x00 22. " DDSD ,Disable slave DDR transfers" "No,Yes" newline bitfld.long 0x00 21. " DDMD ,Disable master DDR transfers" "No,Yes" bitfld.long 0x00 20. " DSDC ,Disable slave PLB request decoding" "No,Yes" bitfld.long 0x00 19. " DMRQ ,Disable master transfers" "No,Yes" bitfld.long 0x00 16.--18. " MRRP ,Master read requests address-to-data pipeline" "1,2,4,8,16,?..." newline bitfld.long 0x00 12.--13. " MBRS ,Master burst size" "128 bytes,256 bytes,512 bytes,?..." bitfld.long 0x00 11. " DSDS ,Disable slave secondary PLB request decoding" "No,Yes" bitfld.long 0x00 8.--10. " SRRP ,Slave read request address-to-data pipeline" "1,2,3,8,16,?..." bitfld.long 0x00 7. " SLKE ,Slave lock/error control" "Lock,Error" group.long (dcr:0x000000C0+0x17)++0x03 line.long 0x00 "ESAMR,Error Status And Mask Register" eventfld.long 0x00 31. " SEV ,Slave error valid" "-,Valid" eventfld.long 0x00 30. " MIRQ ,MIRQ received" "-,Received" eventfld.long 0x00 29. " MERR ,Master write data error" "-,Error" eventfld.long 0x00 28. " TOT ,Timeout received" "-,Received" newline eventfld.long 0x00 27. " SLPE ,Slave parity error" "-,Error" eventfld.long 0x00 26. " MSPE ,Master parity error" "-,Error" eventfld.long 0x00 25. " IADE ,Inbound address decoding error" "-,Error" eventfld.long 0x00 24. " MRDE ,Master read data error" "-,Error" newline bitfld.long 0x00 15. " SEM ,Slave error mask" "0,1" bitfld.long 0x00 14. " MIRM ,MIRQ received error mask" "0,1" bitfld.long 0x00 13. " MERM ,Master write data error mask" "0,1" bitfld.long 0x00 12. " TOTM ,Timeout received error mask" "0,1" newline bitfld.long 0x00 11. " SPEM ,Slave parity error mask" "0,1" bitfld.long 0x00 10. " MPEM ,Master parity error mask" "0,1" bitfld.long 0x00 9. " IAEM ,Inbound address error mask" "0,1" bitfld.long 0x00 8. " MRDM ,Master read data error mask" "0,1" rgroup.long (dcr:0x000000C0+0x18)++0x03 line.long 0x00 "SEAHR,Slave Error Address High Register" rgroup.long (dcr:0x000000C0+0x19)++0x03 line.long 0x00 "SEALR,Slave Error Address Low Register" rgroup.long (dcr:0x000000C0+0x1A)++0x03 line.long 0x00 "SEAR,Slave Error Attribute Register" bitfld.long 0x00 31. " SERNW ,PLB read attribute" "0,1" bitfld.long 0x00 27.--30. " SESIZE ,PLB size attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23.--26. " SEMID ,PLB master ID attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x000000C0+0x1B)++0x03 line.long 0x00 "GPCR,General Purpose Control Register" hexmask.long.tbyte 0x00 8.--31. 1. " GPC ,General purpose control bits" hexmask.long.byte 0x00 0.--7. 1. " DBSL ,Debug select" group.long (dcr:0x000000C0+0x1C)++0x03 line.long 0x00 "CR2,Configuration Register 2" bitfld.long 0x00 31. " IRPW ,Allow inbound read requests bypass previous write request" "-,Allowed" bitfld.long 0x00 30. " ICPW ,Allow inbound read response bypass previous write request" "-,Allowed" bitfld.long 0x00 29. " ORPW ,Allow outbound read request bypass previous write request" "-,Allowed" rgroup.long (dcr:0x000000C0+0x1D)++0x03 line.long 0x00 "DR,Debug Register" rgroup.long (dcr:0x000000C0+0x1E)++0x03 line.long 0x00 "RIDR,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " VERN ,Core version number" hexmask.long.byte 0x00 0.--7. 1. " REVN ,Core revision number" width 0x0B tree.end tree.end ; tree.open "PCIe Wrappers" ; tree "PCIEXG2WRAPP2P_0" ; tree "PCIE4X_MAC0" ; %include 476ibm/pciexg2wrapp2p.ph dcr:0x00 ; tree.end ; tree "PCIE4X_MAC1" ; %include 476ibm/pciexg2wrapp2p.ph dcr:0x00 ; tree.end ; tree.end ; tree "PCIEX2G2WRAPP2P_0" ; tree "PCIE2X_MAC0" ; %include 476ibm/pciexg2wrapp2p.ph dcr:0x00 ; tree.end ; tree "PCIE2X_MAC1" ; %include 476ibm/pciexg2wrapp2p.ph dcr:0x00 ; tree.end ; tree.end ; tree.end tree "PLBOPB32 (PLB4-OPB Bridge)" width 15. rgroup.long (dcr:0x00000030+0x0B2)++0x03 line.long 0x00 "GEAR,Bridge Error Address Register" rgroup.long (dcr:0x00000030+0x0B3)++0x03 line.long 0x00 "GEARU,Upper Error Address Register" bitfld.long 0x00 0.--3. " UEA ,Upper error address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (dcr:0x00000030+0xB0)++0x03 line.long 0x00 "GESR0_CLR,Error Status Register 0 Clear" bitfld.long 0x00 30.--31. " PTE0 _CLR ,PLB timeout error status master 0 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 29. (0x01<<2) 29. 0x00 29. " R/W0 _SET/CLR ,Read write status master 0 set/clear" "Write,Read" setclrfld.long 0x00 28. (0x01<<2) 28. 0x00 28. " FLK0 _SET/CLR ,GESR field lock master 0 set/clear" "-,Locked" setclrfld.long 0x00 27. (0x01<<2) 27. 0x00 27. " ALK0 _SET/CLR ,GEAR address lock master 0 set/clear" "-,Locked" setclrfld.long 0x00 26. (0x01<<2) 26. 0x00 26. " WIRQ0 _SET/CLR ,Write error interrupt master 0 set/clear" "-,Interrupt" newline bitfld.long 0x00 22.--23. " PTE1 _CLR ,PLB timeout error status master 1 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 21. (0x01<<2) 21. 0x00 21. " R/W1 _SET/CLR ,Read write status master 1 set/clear" "Write,Read" setclrfld.long 0x00 20. (0x01<<2) 20. 0x00 20. " FLK1 _SET/CLR ,GESR field lock master 1 set/clear" "-,Locked" setclrfld.long 0x00 19. (0x01<<2) 19. 0x00 19. " ALK1 _SET/CLR ,GEAR address lock master 1 set/clear" "-,Locked" setclrfld.long 0x00 18. (0x01<<2) 18. 0x00 18. " WIRQ1 _SET/CLR ,Write error interrupt master 1 set/clear" "-,Interrupt" newline bitfld.long 0x00 14.--15. " PTE2 _CLR ,PLB timeout error status master 2 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 13. (0x01<<2) 13. 0x00 13. " R/W2 _SET/CLR ,Read write status master 2 set/clear" "Write,Read" setclrfld.long 0x00 12. (0x01<<2) 12. 0x00 12. " FLK2 _SET/CLR ,GESR field lock master 2 set/clear" "-,Locked" setclrfld.long 0x00 11. (0x01<<2) 11. 0x00 11. " ALK2 _SET/CLR ,GEAR address lock master 2 set/clear" "-,Locked" setclrfld.long 0x00 10. (0x01<<2) 10. 0x00 10. " WIRQ2 _SET/CLR ,Write error interrupt master 2 set/clear" "-,Interrupt" newline bitfld.long 0x00 6.--7. " PTE3 _CLR ,PLB timeout error status master 3 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 5. (0x01<<2) 5. 0x00 5. " R/W3 _SET/CLR ,Read write status master 3 set/clear" "Write,Read" setclrfld.long 0x00 4. (0x01<<2) 4. 0x00 4. " FLK3 _SET/CLR ,GESR field lock master 3 set/clear" "-,Locked" setclrfld.long 0x00 3. (0x01<<2) 3. 0x00 3. " ALK3 _SET/CLR ,GEAR address lock master 3 set/clear" "-,Locked" setclrfld.long 0x00 2. (0x01<<2) 2. 0x00 2. " WIRQ3 _SET/CLR ,Write error interrupt master 3 set/clear" "-,Interrupt" wgroup.long (dcr:0x00000030+0xB0+0x01)++0x03 line.long 0x00 "GESR0_SET,Error Status Register 0 Set" bitfld.long 0x00 30.--31. " PTE0 _SET ,PLB timeout error status master 0 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 22.--23. " PTE1 _SET ,PLB timeout error status master 1 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 14.--15. " PTE2 _SET ,PLB timeout error status master 2 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 6.--7. " PTE3 _SET ,PLB timeout error status master 3 set" "-,Timeout error,Slave error,?..." group.long (dcr:0x00000030+0xB4)++0x03 line.long 0x00 "GESR1_CLR,Error Status Register 1 Clear" bitfld.long 0x00 30.--31. " PTE4 _CLR ,PLB timeout error status master 4 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 29. (0x01<<2) 29. 0x00 29. " R/W4 _SET/CLR ,Read write status master 4 set/clear" "Write,Read" setclrfld.long 0x00 28. (0x01<<2) 28. 0x00 28. " FLK4 _SET/CLR ,GESR field lock master 4 set/clear" "-,Locked" setclrfld.long 0x00 27. (0x01<<2) 27. 0x00 27. " ALK4 _SET/CLR ,GEAR address lock master 4 set/clear" "-,Locked" setclrfld.long 0x00 26. (0x01<<2) 26. 0x00 26. " WIRQ4 _SET/CLR ,Write error interrupt master 4 set/clear" "-,Interrupt" newline bitfld.long 0x00 22.--23. " PTE5 _CLR ,PLB timeout error status master 5 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 21. (0x01<<2) 21. 0x00 21. " R/W5 _SET/CLR ,Read write status master 5 set/clear" "Write,Read" setclrfld.long 0x00 20. (0x01<<2) 20. 0x00 20. " FLK5 _SET/CLR ,GESR field lock master 5 set/clear" "-,Locked" setclrfld.long 0x00 19. (0x01<<2) 19. 0x00 19. " ALK5 _SET/CLR ,GEAR address lock master 5 set/clear" "-,Locked" setclrfld.long 0x00 18. (0x01<<2) 18. 0x00 18. " WIRQ5 _SET/CLR ,Write error interrupt master 5 set/clear" "-,Interrupt" newline bitfld.long 0x00 14.--15. " PTE6 _CLR ,PLB timeout error status master 6 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 13. (0x01<<2) 13. 0x00 13. " R/W6 _SET/CLR ,Read write status master 6 set/clear" "Write,Read" setclrfld.long 0x00 12. (0x01<<2) 12. 0x00 12. " FLK6 _SET/CLR ,GESR field lock master 6 set/clear" "-,Locked" setclrfld.long 0x00 11. (0x01<<2) 11. 0x00 11. " ALK6 _SET/CLR ,GEAR address lock master 6 set/clear" "-,Locked" setclrfld.long 0x00 10. (0x01<<2) 10. 0x00 10. " WIRQ6 _SET/CLR ,Write error interrupt master 6 set/clear" "-,Interrupt" newline bitfld.long 0x00 6.--7. " PTE7 _CLR ,PLB timeout error status master 7 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 5. (0x01<<2) 5. 0x00 5. " R/W7 _SET/CLR ,Read write status master 7 set/clear" "Write,Read" setclrfld.long 0x00 4. (0x01<<2) 4. 0x00 4. " FLK7 _SET/CLR ,GESR field lock master 7 set/clear" "-,Locked" setclrfld.long 0x00 3. (0x01<<2) 3. 0x00 3. " ALK7 _SET/CLR ,GEAR address lock master 7 set/clear" "-,Locked" setclrfld.long 0x00 2. (0x01<<2) 2. 0x00 2. " WIRQ7 _SET/CLR ,Write error interrupt master 7 set/clear" "-,Interrupt" wgroup.long (dcr:0x00000030+0xB4+0x01)++0x03 line.long 0x00 "GESR1_SET,Error Status Register 1 Set" bitfld.long 0x00 30.--31. " PTE4 _SET ,PLB timeout error status master 4 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 22.--23. " PTE5 _SET ,PLB timeout error status master 5 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 14.--15. " PTE6 _SET ,PLB timeout error status master 6 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 6.--7. " PTE7 _SET ,PLB timeout error status master 7 set" "-,Timeout error,Slave error,?..." group.long (dcr:0x00000030+0xB8)++0x03 line.long 0x00 "GESR2_CLR,Error Status Register 2 Clear" bitfld.long 0x00 30.--31. " PTE8 _CLR ,PLB timeout error status master 8 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 29. (0x01<<2) 29. 0x00 29. " R/W8 _SET/CLR ,Read write status master 8 set/clear" "Write,Read" setclrfld.long 0x00 28. (0x01<<2) 28. 0x00 28. " FLK8 _SET/CLR ,GESR field lock master 8 set/clear" "-,Locked" setclrfld.long 0x00 27. (0x01<<2) 27. 0x00 27. " ALK8 _SET/CLR ,GEAR address lock master 8 set/clear" "-,Locked" setclrfld.long 0x00 26. (0x01<<2) 26. 0x00 26. " WIRQ8 _SET/CLR ,Write error interrupt master 8 set/clear" "-,Interrupt" newline bitfld.long 0x00 22.--23. " PTE9 _CLR ,PLB timeout error status master 9 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 21. (0x01<<2) 21. 0x00 21. " R/W9 _SET/CLR ,Read write status master 9 set/clear" "Write,Read" setclrfld.long 0x00 20. (0x01<<2) 20. 0x00 20. " FLK9 _SET/CLR ,GESR field lock master 9 set/clear" "-,Locked" setclrfld.long 0x00 19. (0x01<<2) 19. 0x00 19. " ALK9 _SET/CLR ,GEAR address lock master 9 set/clear" "-,Locked" setclrfld.long 0x00 18. (0x01<<2) 18. 0x00 18. " WIRQ9 _SET/CLR ,Write error interrupt master 9 set/clear" "-,Interrupt" newline bitfld.long 0x00 14.--15. " PTE10_CLR ,PLB timeout error status master 10 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 13. (0x01<<2) 13. 0x00 13. " R/W10_SET/CLR ,Read write status master 10 set/clear" "Write,Read" setclrfld.long 0x00 12. (0x01<<2) 12. 0x00 12. " FLK10_SET/CLR ,GESR field lock master 10 set/clear" "-,Locked" setclrfld.long 0x00 11. (0x01<<2) 11. 0x00 11. " ALK10_SET/CLR ,GEAR address lock master 10 set/clear" "-,Locked" setclrfld.long 0x00 10. (0x01<<2) 10. 0x00 10. " WIRQ10_SET/CLR ,Write error interrupt master 10 set/clear" "-,Interrupt" newline bitfld.long 0x00 6.--7. " PTE11_CLR ,PLB timeout error status master 11 clear" "-,Timeout error,Slave error,?..." setclrfld.long 0x00 5. (0x01<<2) 5. 0x00 5. " R/W11_SET/CLR ,Read write status master 11 set/clear" "Write,Read" setclrfld.long 0x00 4. (0x01<<2) 4. 0x00 4. " FLK11_SET/CLR ,GESR field lock master 11 set/clear" "-,Locked" setclrfld.long 0x00 3. (0x01<<2) 3. 0x00 3. " ALK11_SET/CLR ,GEAR address lock master 11 set/clear" "-,Locked" setclrfld.long 0x00 2. (0x01<<2) 2. 0x00 2. " WIRQ11_SET/CLR ,Write error interrupt master 11 set/clear" "-,Interrupt" wgroup.long (dcr:0x00000030+0xB8+0x01)++0x03 line.long 0x00 "GESR2_SET,Error Status Register 2 Set" bitfld.long 0x00 30.--31. " PTE8 _SET ,PLB timeout error status master 8 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 22.--23. " PTE9 _SET ,PLB timeout error status master 9 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 14.--15. " PTE10_SET ,PLB timeout error status master 10 set" "-,Timeout error,Slave error,?..." newline bitfld.long 0x00 6.--7. " PTE11_SET ,PLB timeout error status master 11 set" "-,Timeout error,Slave error,?..." newline group.long (dcr:0x00000030+0x0B6)++0x03 line.long 0x00 "GCONF_SET/CLR,Configuration Register Set/Clear" setclrfld.long 0x00 31. (0x01<<2) 31. 0x00 31. " ER ,Enable re-arbitration" "-,Enabled" group.long (dcr:0x00000030+0x0B8)++0x03 line.long 0x00 "GLATENCY_CLR,Burst Latency Timer Clear" setclrfld.long 0x00 31. (0x01<<2) 31. 0x00 31. " LATENB_SET/CLR ,Latency enable set" "-,Enabled" bitfld.long 0x00 27.--30. " LATCNT_CLR ,Latency count clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long (dcr:0x00000030+0x0B9)++0x03 line.long 0x00 "GLATENCY_SET,Burst Latency Timer Set" bitfld.long 0x00 27.--30. " LATCNT_SET ,Latency count set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (dcr:0x00000030+0x0BA)++0x03 line.long 0x00 "GREV,Revision ID" hexmask.long.word 0x00 8.--19. 1. " RN ,Revision number" hexmask.long.byte 0x00 0.--7. 1. " BRN ,Branch revision number" width 0x0B tree.end tree "EBC (External Bus Controller)" width 7. group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x0) line.long 0x00 "B0CR,Peripheral Bank 0 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x0+0x10) line.long 0x00 "B0AP,Peripheral Bank 0 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x1) line.long 0x00 "B1CR,Peripheral Bank 1 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x1+0x10) line.long 0x00 "B1AP,Peripheral Bank 1 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x2) line.long 0x00 "B2CR,Peripheral Bank 2 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x2+0x10) line.long 0x00 "B2AP,Peripheral Bank 2 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x3) line.long 0x00 "B3CR,Peripheral Bank 3 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x3+0x10) line.long 0x00 "B3AP,Peripheral Bank 3 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x4) line.long 0x00 "B4CR,Peripheral Bank 4 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x4+0x10) line.long 0x00 "B4AP,Peripheral Bank 4 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x5) line.long 0x00 "B5CR,Peripheral Bank 5 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x5+0x10) line.long 0x00 "B5AP,Peripheral Bank 5 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x6) line.long 0x00 "B6CR,Peripheral Bank 6 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x6+0x10) line.long 0x00 "B6AP,Peripheral Bank 6 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x7) line.long 0x00 "B7CR,Peripheral Bank 7 Configuration Register" hexmask.long.word 0x00 20.--31. 0x10 " BAS ,Base address select" bitfld.long 0x00 17.--19. " BS ,Bank size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 15.--16. " BU ,Bank usage" "Disabled,Read only,Write only,Read/Write" bitfld.long 0x00 13.--14. " BW ,Bus width" "8 bit,16 bit,,32 bit" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x7+0x10) line.long 0x00 "B7AP,Peripheral Bank 7 Access Parameter Register" bitfld.long 0x00 31. " BME ,Burst mode enable" "-,Enabled" bitfld.long 0x00 26.--30. " FWT ,First wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles,8 PerClk cycles,9 PerClk cycles,10 PerClk cycles,11 PerClk cycles,12 PerClk cycles,13 PerClk cycles,14 PerClk cycles,15 PerClk cycles,16 PerClk cycles,17 PerClk cycles,18 PerClk cycles,19 PerClk cycles,20 PerClk cycles,21 PerClk cycles,22 PerClk cycles,23 PerClk cycles,24 PerClk cycles,25 PerClk cycles,26 PerClk cycles,27 PerClk cycles,28 PerClk cycles,29 PerClk cycles,30 PerClk cycles,31 PerClk cycles" bitfld.long 0x00 23.--25. " BWT ,Burst wait" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 22. " BCE ,Fixed length burst read" "-,Enabled" newline bitfld.long 0x00 20.--21. " BCT ,Fixed length burst count" "2 transfers,4 transfers,8 transfers,16 transfers" bitfld.long 0x00 18.--19. " CSN ,Chip select on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 16.--17. " OEN ,Output enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 14.--15. " WBN ,Write byte enable on timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" newline bitfld.long 0x00 12.--13. " WBF ,Write byte enable off timing" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles" bitfld.long 0x00 9.--11. " TH ,Hold cycles at the end of transfer" "0 PerClk cycles,1 PerClk cycle,2 PerClk cycles,3 PerClk cycles,4 PerClk cycles,5 PerClk cycles,6 PerClk cycles,7 PerClk cycles" bitfld.long 0x00 8. " RE ,Ready enable" "-,Enabled" bitfld.long 0x00 7. " SOR ,Device paced sampling of ready" "Clock before,Same clock" newline bitfld.long 0x00 6. " BEM ,Byte enable mode" "Write,Read/Write" bitfld.long 0x00 5. " PEN ,Parity enable" "-,Enabled" rgroup.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x20) line.long 0x00 "BEAR,Peripheral Bus Error Address Register" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x21) line.long 0x00 "BESR,Peripheral Bus Error Status Register" bitfld.long 0x00 31. " PYE ,Parity error on read" "-,Error" bitfld.long 0x00 30. " PRE ,Bank protection error" "-,Error" bitfld.long 0x00 29. " EBE ,External bus input error" "-,Error" bitfld.long 0x00 28. " ETE ,External bus timeout error" "-,Error" newline bitfld.long 0x00 27. " RWS ,Read/Write error status for transfer" "Write,Read" bitfld.long 0x00 26. " SAS ,Sequential address status" "-,Active" bitfld.long 0x00 25. " EINT ,Error interrupt" "-,Error" bitfld.long 0x00 24. " DMAEP ,DMA external peripheral error" "-,Error" group.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x23) line.long 0x00 "CFG,External Bus Control Register" bitfld.long 0x00 31. " LE ,Lock error" "-,Locked" bitfld.long 0x00 30. " PTD ,Device paced timeout disable" "No,Yes" bitfld.long 0x00 27.--29. " RTC ,Ready timeout count" "16 PerClk cycles,32 PerClk cycles,64 PerClk cycles,128 PerClk cycles,256 PerClk cycles,512 PerClk cycles,1024 PerClk cycles,2048 PerClk cycles" bitfld.long 0x00 26. " ATC ,Address bus high impedance control" "Hi-Z,Previous value" newline bitfld.long 0x00 25. " DTC ,Data bus high impedance control" "Hi-Z,Previous value" bitfld.long 0x00 24. " CTC ,Control signal high impedance control" "Hi-Z,Inactive" bitfld.long 0x00 23. " OEO ,External bus override high impedance control enable" "-,Enabled" bitfld.long 0x00 22. " EMC ,External master high impedance control" "All EBC2OPB,All EBC2OPB except PerCS0:7" newline bitfld.long 0x00 17. " PME ,Power management enable" "-,Enabled" bitfld.long 0x00 12.--16. " PMT ,Power management timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--11. " PR ,Pending request timer" "16 OPB cycles,32 OPB cycles,64 OPB cycles,128 OPB cycles" rgroup.long (dcr:0x00000000+0x13)++0x03 saveout (dcr:0x00000000+0x12) %l (dcr:0x00000000+0x24) line.long 0x00 "CID,Revision ID Register" hexmask.long.word 0x00 8.--19. 1. " REV ,Revision number" hexmask.long.byte 0x00 0.--7. 1. " BREV ,Branch revision number" width 0x0B tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" width 5. if ((per.b(dcr:0x200:0x10000000+0x03)&0x01)==0x01) group.byte (dcr:0x200:0x10000000+0x00)++0x00 line.byte 0x00 "DLL,Divisor Latch Low Register" group.byte (dcr:0x200:0x10000000+0x01)++0x00 line.byte 0x00 "DLM,Divisor Latch High Register" else hgroup.byte (dcr:0x200:0x10000000+0x00)++0x00 hide.byte 0x00 "RBR,Receiver Buffer Register" in wgroup.byte (dcr:0x200:0x10000000+0x00)++0x00 line.byte 0x00 "THR,Transmitter Holding Register" group.byte (dcr:0x200:0x10000000+0x01)++0x00 line.byte 0x00 "IER,Interrupt Enable Register" bitfld.byte 0x00 7. " ERBFI ,Receive data available interrupt enable" "-,Enabled" bitfld.byte 0x00 6. " ETBEI ,Transmit holding register empty interrupt enable" "-,Enabled" newline bitfld.byte 0x00 5. " ELSI ,Receiver line status interrupt enable" "-,Enabled" bitfld.byte 0x00 4. " EDSSI ,Modem status interrupt enable" "-,Enabled" endif rgroup.byte (dcr:0x200:0x10000000+0x02)++0x00 line.byte 0x00 "IIR,Interrupt Identification Register" bitfld.byte 0x00 7. " PI ,Pending interrupt" "Pending,Not pending" bitfld.byte 0x00 4.--6. " IID ,Interrupt ID (priority level - interrupt type)" "4 - Modem status,3 - Transmitter holding register empty,2 - Received data available,1 - Receiver line status,,,2 - Character timeout indication,?..." newline bitfld.byte 0x00 1. " FIE[0] ,FIFO is enabled" "-,Enabled" bitfld.byte 0x00 0. " FIE[1] ,FIFO is enabled" "-,Enabled" wgroup.byte (dcr:0x200:0x10000000+0x02)++0x00 line.byte 0x00 "FCR,FIFO Control Register" bitfld.byte 0x00 7. " FE ,FIFO enable" "-,Enabled" bitfld.byte 0x00 6. " RFR ,Receiver FIFO reset" "-,Reset" newline bitfld.byte 0x00 5. " TFR ,Transmitter FIFO reset" "-,Reset" bitfld.byte 0x00 4. " DMS ,DMA mode select" "Single transfer,Multiple transfer" newline bitfld.byte 0x00 0.--1. " RFTL ,Receiver FIFO trigger level (16 byte/64 byte)" "01/01,04/16,08/32,14/56" group.byte (dcr:0x200:0x10000000+0x03)++0x00 line.byte 0x00 "LCR,Line Control Register" bitfld.byte 0x00 6.--7. " CWL ,Character word length" "5,6,7,8" bitfld.byte 0x00 5. " STB ,Stop bits number" "1,1.5 or 2" newline bitfld.byte 0x00 4. " PEN ,Parity enable" "-,Enabled" bitfld.byte 0x00 3. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 2. " SP ,Stick parity enable" "-,Enabled" bitfld.byte 0x00 1. " SB ,Set break enable" "-,Enabled" newline bitfld.byte 0x00 0. " DLAB ,Divisor latch access bit" "RBR/THR/IER,Divisor latches" group.byte (dcr:0x200:0x10000000+0x04)++0x00 line.byte 0x00 "MCR,Modem Control Register" bitfld.byte 0x00 7. " DTR ,Data terminal ready output value" "Low,High" bitfld.byte 0x00 6. " RTS ,Request to send output value" "Low,High" newline bitfld.byte 0x00 5. " OUT1 ,User output 1 value" "Low,High" bitfld.byte 0x00 4. " OUT2 ,User output 2 value" "Low,High" newline bitfld.byte 0x00 3. " LOOP ,Loopback mode activate" "-,Activated" bitfld.byte 0x00 2. " AFC ,Auto flow control enable" "-,Enabled" hgroup.byte (dcr:0x200:0x10000000+0x05)++0x00 hide.byte 0x00 "LSR,Line Status Register" in hgroup.byte (dcr:0x200:0x10000000+0x06)++0x00 hide.byte 0x00 "MSR,Modem Status Register" in group.byte (dcr:0x200:0x10000000+0x07)++0x00 line.byte 0x00 "SCR,Scratchpad Register" width 0x0B tree.end tree "GPIO (General Purpose IO)" width 6. group.long (dcr:0x200:0x20000000+0x00)++0x03 line.long 0x00 "OR,Output Register" bitfld.long 0x00 31. " OR[0] ,Pin 0 output" "Low,High" bitfld.long 0x00 30. " [1] ,Pin 1 output" "Low,High" bitfld.long 0x00 29. " [2] ,Pin 2 output" "Low,High" bitfld.long 0x00 28. " [3] ,Pin 3 output" "Low,High" newline bitfld.long 0x00 27. " [4] ,Pin 4 output" "Low,High" bitfld.long 0x00 26. " [5] ,Pin 5 output" "Low,High" bitfld.long 0x00 25. " [6] ,Pin 6 output" "Low,High" bitfld.long 0x00 24. " [7] ,Pin 7 output" "Low,High" newline bitfld.long 0x00 23. " [8] ,Pin 8 output" "Low,High" bitfld.long 0x00 22. " [9] ,Pin 9 output" "Low,High" bitfld.long 0x00 21. " [10] ,Pin 10 output" "Low,High" bitfld.long 0x00 20. " [11] ,Pin 11 output" "Low,High" newline bitfld.long 0x00 19. " [12] ,Pin 12 output" "Low,High" bitfld.long 0x00 18. " [13] ,Pin 13 output" "Low,High" bitfld.long 0x00 17. " [14] ,Pin 14 output" "Low,High" bitfld.long 0x00 16. " [15] ,Pin 15 output" "Low,High" newline bitfld.long 0x00 15. " [16] ,Pin 16 output" "Low,High" bitfld.long 0x00 14. " [17] ,Pin 17 output" "Low,High" bitfld.long 0x00 13. " [18] ,Pin 18 output" "Low,High" bitfld.long 0x00 12. " [19] ,Pin 19 output" "Low,High" newline bitfld.long 0x00 11. " [20] ,Pin 20 output" "Low,High" bitfld.long 0x00 10. " [21] ,Pin 21 output" "Low,High" bitfld.long 0x00 9. " [22] ,Pin 22 output" "Low,High" bitfld.long 0x00 8. " [23] ,Pin 23 output" "Low,High" newline bitfld.long 0x00 7. " [24] ,Pin 24 output" "Low,High" bitfld.long 0x00 6. " [25] ,Pin 25 output" "Low,High" bitfld.long 0x00 5. " [26] ,Pin 26 output" "Low,High" bitfld.long 0x00 4. " [27] ,Pin 27 output" "Low,High" newline bitfld.long 0x00 3. " [28] ,Pin 28 output" "Low,High" bitfld.long 0x00 2. " [29] ,Pin 29 output" "Low,High" bitfld.long 0x00 1. " [30] ,Pin 30 output" "Low,High" bitfld.long 0x00 0. " [31] ,Pin 31 output" "Low,High" group.long (dcr:0x200:0x20000000+0x04)++0x03 line.long 0x00 "TCR,Three-State Control Register" bitfld.long 0x00 31. " TCR[0] ,Pin 0 state" "Hi-Z,As OR[0]" bitfld.long 0x00 30. " [1] ,Pin 1 state" "Hi-Z,As OR[1]" bitfld.long 0x00 29. " [2] ,Pin 2 state" "Hi-Z,As OR[2]" bitfld.long 0x00 28. " [3] ,Pin 3 state" "Hi-Z,As OR[3]" newline bitfld.long 0x00 27. " [4] ,Pin 4 state" "Hi-Z,As OR[4]" bitfld.long 0x00 26. " [5] ,Pin 5 state" "Hi-Z,As OR[5]" bitfld.long 0x00 25. " [6] ,Pin 6 state" "Hi-Z,As OR[6]" bitfld.long 0x00 24. " [7] ,Pin 7 state" "Hi-Z,As OR[7]" newline bitfld.long 0x00 23. " [8] ,Pin 8 state" "Hi-Z,As OR[8]" bitfld.long 0x00 22. " [9] ,Pin 9 state" "Hi-Z,As OR[9]" bitfld.long 0x00 21. " [10] ,Pin 10 state" "Hi-Z,As OR[10]" bitfld.long 0x00 20. " [11] ,Pin 11 state" "Hi-Z,As OR[11]" newline bitfld.long 0x00 19. " [12] ,Pin 12 state" "Hi-Z,As OR[12]" bitfld.long 0x00 18. " [13] ,Pin 13 state" "Hi-Z,As OR[13]" bitfld.long 0x00 17. " [14] ,Pin 14 state" "Hi-Z,As OR[14]" bitfld.long 0x00 16. " [15] ,Pin 15 state" "Hi-Z,As OR[15]" newline bitfld.long 0x00 15. " [16] ,Pin 16 state" "Hi-Z,As OR[16]" bitfld.long 0x00 14. " [17] ,Pin 17 state" "Hi-Z,As OR[17]" bitfld.long 0x00 13. " [18] ,Pin 18 state" "Hi-Z,As OR[18]" bitfld.long 0x00 12. " [19] ,Pin 19 state" "Hi-Z,As OR[19]" newline bitfld.long 0x00 11. " [20] ,Pin 20 state" "Hi-Z,As OR[20]" bitfld.long 0x00 10. " [21] ,Pin 21 state" "Hi-Z,As OR[21]" bitfld.long 0x00 9. " [22] ,Pin 22 state" "Hi-Z,As OR[22]" bitfld.long 0x00 8. " [23] ,Pin 23 state" "Hi-Z,As OR[23]" newline bitfld.long 0x00 7. " [24] ,Pin 24 state" "Hi-Z,As OR[24]" bitfld.long 0x00 6. " [25] ,Pin 25 state" "Hi-Z,As OR[25]" bitfld.long 0x00 5. " [26] ,Pin 26 state" "Hi-Z,As OR[26]" bitfld.long 0x00 4. " [27] ,Pin 27 state" "Hi-Z,As OR[27]" newline bitfld.long 0x00 3. " [28] ,Pin 28 state" "Hi-Z,As OR[28]" bitfld.long 0x00 2. " [29] ,Pin 29 state" "Hi-Z,As OR[29]" bitfld.long 0x00 1. " [30] ,Pin 30 state" "Hi-Z,As OR[30]" bitfld.long 0x00 0. " [31] ,Pin 31 state" "Hi-Z,As OR[31]" newline group.long (dcr:0x200:0x20000000+0x08)++0x03 line.long 0x00 "OSL,Output Select Low Register" bitfld.long 0x00 30.--31. " OS[0] ,Pin 0 output source" "OR[0],ALT_OUTPUT_1[0],ALT_OUTPUT_2[0],ALT_OUTPUT_3[0]" bitfld.long 0x00 28.--29. " [1] ,Pin 1 output source" "OR[1],ALT_OUTPUT_1[1],ALT_OUTPUT_2[1],ALT_OUTPUT_3[1]" bitfld.long 0x00 26.--27. " [2] ,Pin 2 output source" "OR[2],ALT_OUTPUT_1[2],ALT_OUTPUT_2[2],ALT_OUTPUT_3[2]" bitfld.long 0x00 24.--25. " [3] ,Pin 3 output source" "OR[3],ALT_OUTPUT_1[3],ALT_OUTPUT_2[3],ALT_OUTPUT_3[3]" newline bitfld.long 0x00 22.--23. " [4] ,Pin 4 output source" "OR[4],ALT_OUTPUT_1[4],ALT_OUTPUT_2[4],ALT_OUTPUT_3[4]" bitfld.long 0x00 20.--21. " [5] ,Pin 5 output source" "OR[5],ALT_OUTPUT_1[5],ALT_OUTPUT_2[5],ALT_OUTPUT_3[5]" bitfld.long 0x00 18.--19. " [6] ,Pin 6 output source" "OR[6],ALT_OUTPUT_1[6],ALT_OUTPUT_2[6],ALT_OUTPUT_3[6]" bitfld.long 0x00 16.--17. " [7] ,Pin 7 output source" "OR[7],ALT_OUTPUT_1[7],ALT_OUTPUT_2[7],ALT_OUTPUT_3[7]" newline bitfld.long 0x00 14.--15. " [8] ,Pin 8 output source" "OR[8],ALT_OUTPUT_1[8],ALT_OUTPUT_2[8],ALT_OUTPUT_3[8]" bitfld.long 0x00 12.--13. " [9] ,Pin 9 output source" "OR[9],ALT_OUTPUT_1[9],ALT_OUTPUT_2[9],ALT_OUTPUT_3[9]" bitfld.long 0x00 10.--11. " [10] ,Pin 10 output source" "OR[10],ALT_OUTPUT_1[10],ALT_OUTPUT_2[10],ALT_OUTPUT_3[10]" bitfld.long 0x00 8.--9. " [11] ,Pin 11 output source" "OR[11],ALT_OUTPUT_1[11],ALT_OUTPUT_2[11],ALT_OUTPUT_3[11]" newline bitfld.long 0x00 6.--7. " [12] ,Pin 12 output source" "OR[12],ALT_OUTPUT_1[12],ALT_OUTPUT_2[12],ALT_OUTPUT_3[12]" bitfld.long 0x00 4.--5. " [13] ,Pin 13 output source" "OR[13],ALT_OUTPUT_1[13],ALT_OUTPUT_2[13],ALT_OUTPUT_3[13]" bitfld.long 0x00 2.--3. " [14] ,Pin 14 output source" "OR[14],ALT_OUTPUT_1[14],ALT_OUTPUT_2[14],ALT_OUTPUT_3[14]" bitfld.long 0x00 0.--1. " [15] ,Pin 15 output source" "OR[15],ALT_OUTPUT_1[15],ALT_OUTPUT_2[15],ALT_OUTPUT_3[15]" group.long (dcr:0x200:0x20000000+0x0C)++0x03 line.long 0x00 "OSH,Output Select High Register" bitfld.long 0x00 30.--31. " OS[16] ,Pin 16 output source" "OR[16],ALT_OUTPUT_1[16],ALT_OUTPUT_2[16],ALT_OUTPUT_3[16]" bitfld.long 0x00 28.--29. " [17] ,Pin 17 output source" "OR[17],ALT_OUTPUT_1[17],ALT_OUTPUT_2[17],ALT_OUTPUT_3[17]" bitfld.long 0x00 26.--27. " [18] ,Pin 18 output source" "OR[18],ALT_OUTPUT_1[18],ALT_OUTPUT_2[18],ALT_OUTPUT_3[18]" bitfld.long 0x00 24.--25. " [19] ,Pin 19 output source" "OR[19],ALT_OUTPUT_1[19],ALT_OUTPUT_2[19],ALT_OUTPUT_3[19]" newline bitfld.long 0x00 22.--23. " [20] ,Pin 20 output source" "OR[20],ALT_OUTPUT_1[20],ALT_OUTPUT_2[20],ALT_OUTPUT_3[20]" bitfld.long 0x00 20.--21. " [21] ,Pin 21 output source" "OR[21],ALT_OUTPUT_1[21],ALT_OUTPUT_2[21],ALT_OUTPUT_3[21]" bitfld.long 0x00 18.--19. " [22] ,Pin 22 output source" "OR[22],ALT_OUTPUT_1[22],ALT_OUTPUT_2[22],ALT_OUTPUT_3[22]" bitfld.long 0x00 16.--17. " [23] ,Pin 23 output source" "OR[23],ALT_OUTPUT_1[23],ALT_OUTPUT_2[23],ALT_OUTPUT_3[23]" newline bitfld.long 0x00 14.--15. " [24] ,Pin 24 output source" "OR[24],ALT_OUTPUT_1[24],ALT_OUTPUT_2[24],ALT_OUTPUT_3[24]" bitfld.long 0x00 12.--13. " [25] ,Pin 25 output source" "OR[25],ALT_OUTPUT_1[25],ALT_OUTPUT_2[25],ALT_OUTPUT_3[25]" bitfld.long 0x00 10.--11. " [26] ,Pin 26 output source" "OR[26],ALT_OUTPUT_1[26],ALT_OUTPUT_2[26],ALT_OUTPUT_3[26]" bitfld.long 0x00 8.--9. " [27] ,Pin 27 output source" "OR[27],ALT_OUTPUT_1[27],ALT_OUTPUT_2[27],ALT_OUTPUT_3[27]" newline bitfld.long 0x00 6.--7. " [28] ,Pin 28 output source" "OR[28],ALT_OUTPUT_1[28],ALT_OUTPUT_2[28],ALT_OUTPUT_3[28]" bitfld.long 0x00 4.--5. " [29] ,Pin 29 output source" "OR[29],ALT_OUTPUT_1[29],ALT_OUTPUT_2[29],ALT_OUTPUT_3[29]" bitfld.long 0x00 2.--3. " [30] ,Pin 30 output source" "OR[30],ALT_OUTPUT_1[30],ALT_OUTPUT_2[30],ALT_OUTPUT_3[30]" bitfld.long 0x00 0.--1. " [31] ,Pin 31 output source" "OR[31],ALT_OUTPUT_1[31],ALT_OUTPUT_2[31],ALT_OUTPUT_3[31]" group.long (dcr:0x200:0x20000000+0x10)++0x03 line.long 0x00 "TSL,Three-State Select Low Register" bitfld.long 0x00 30.--31. " TS[0] ,Pin 0 output source" "TCR[0],ALT_OUTPUT_1[0],ALT_OUTPUT_2[0],ALT_OUTPUT_3[0]" bitfld.long 0x00 28.--29. " [1] ,Pin 1 output source" "TCR[1],ALT_OUTPUT_1[1],ALT_OUTPUT_2[1],ALT_OUTPUT_3[1]" bitfld.long 0x00 26.--27. " [2] ,Pin 2 output source" "TCR[2],ALT_OUTPUT_1[2],ALT_OUTPUT_2[2],ALT_OUTPUT_3[2]" bitfld.long 0x00 24.--25. " [3] ,Pin 3 output source" "TCR[3],ALT_OUTPUT_1[3],ALT_OUTPUT_2[3],ALT_OUTPUT_3[3]" newline bitfld.long 0x00 22.--23. " [4] ,Pin 4 output source" "TCR[4],ALT_OUTPUT_1[4],ALT_OUTPUT_2[4],ALT_OUTPUT_3[4]" bitfld.long 0x00 20.--21. " [5] ,Pin 5 output source" "TCR[5],ALT_OUTPUT_1[5],ALT_OUTPUT_2[5],ALT_OUTPUT_3[5]" bitfld.long 0x00 18.--19. " [6] ,Pin 6 output source" "TCR[6],ALT_OUTPUT_1[6],ALT_OUTPUT_2[6],ALT_OUTPUT_3[6]" bitfld.long 0x00 16.--17. " [7] ,Pin 7 output source" "TCR[7],ALT_OUTPUT_1[7],ALT_OUTPUT_2[7],ALT_OUTPUT_3[7]" newline bitfld.long 0x00 14.--15. " [8] ,Pin 8 output source" "TCR[8],ALT_OUTPUT_1[8],ALT_OUTPUT_2[8],ALT_OUTPUT_3[8]" bitfld.long 0x00 12.--13. " [9] ,Pin 9 output source" "TCR[9],ALT_OUTPUT_1[9],ALT_OUTPUT_2[9],ALT_OUTPUT_3[9]" bitfld.long 0x00 10.--11. " [10] ,Pin 10 output source" "TCR[10],ALT_OUTPUT_1[10],ALT_OUTPUT_2[10],ALT_OUTPUT_3[10]" bitfld.long 0x00 8.--9. " [11] ,Pin 11 output source" "TCR[11],ALT_OUTPUT_1[11],ALT_OUTPUT_2[11],ALT_OUTPUT_3[11]" newline bitfld.long 0x00 6.--7. " [12] ,Pin 12 output source" "TCR[12],ALT_OUTPUT_1[12],ALT_OUTPUT_2[12],ALT_OUTPUT_3[12]" bitfld.long 0x00 4.--5. " [13] ,Pin 13 output source" "TCR[13],ALT_OUTPUT_1[13],ALT_OUTPUT_2[13],ALT_OUTPUT_3[13]" bitfld.long 0x00 2.--3. " [14] ,Pin 14 output source" "TCR[14],ALT_OUTPUT_1[14],ALT_OUTPUT_2[14],ALT_OUTPUT_3[14]" bitfld.long 0x00 0.--1. " [15] ,Pin 15 output source" "TCR[15],ALT_OUTPUT_1[15],ALT_OUTPUT_2[15],ALT_OUTPUT_3[15]" group.long (dcr:0x200:0x20000000+0x14)++0x03 line.long 0x00 "TSH,Three-State Select High Register" bitfld.long 0x00 30.--31. " TS[16] ,Pin 16 output source" "TCR[16],ALT_OUTPUT_1[16],ALT_OUTPUT_2[16],ALT_OUTPUT_3[16]" bitfld.long 0x00 28.--29. " [17] ,Pin 17 output source" "TCR[17],ALT_OUTPUT_1[17],ALT_OUTPUT_2[17],ALT_OUTPUT_3[17]" bitfld.long 0x00 26.--27. " [18] ,Pin 18 output source" "TCR[18],ALT_OUTPUT_1[18],ALT_OUTPUT_2[18],ALT_OUTPUT_3[18]" bitfld.long 0x00 24.--25. " [19] ,Pin 19 output source" "TCR[19],ALT_OUTPUT_1[19],ALT_OUTPUT_2[19],ALT_OUTPUT_3[19]" newline bitfld.long 0x00 22.--23. " [20] ,Pin 20 output source" "TCR[20],ALT_OUTPUT_1[20],ALT_OUTPUT_2[20],ALT_OUTPUT_3[20]" bitfld.long 0x00 20.--21. " [21] ,Pin 21 output source" "TCR[21],ALT_OUTPUT_1[21],ALT_OUTPUT_2[21],ALT_OUTPUT_3[21]" bitfld.long 0x00 18.--19. " [22] ,Pin 22 output source" "TCR[22],ALT_OUTPUT_1[22],ALT_OUTPUT_2[22],ALT_OUTPUT_3[22]" bitfld.long 0x00 16.--17. " [23] ,Pin 23 output source" "TCR[23],ALT_OUTPUT_1[23],ALT_OUTPUT_2[23],ALT_OUTPUT_3[23]" newline bitfld.long 0x00 14.--15. " [24] ,Pin 24 output source" "TCR[24],ALT_OUTPUT_1[24],ALT_OUTPUT_2[24],ALT_OUTPUT_3[24]" bitfld.long 0x00 12.--13. " [25] ,Pin 25 output source" "TCR[25],ALT_OUTPUT_1[25],ALT_OUTPUT_2[25],ALT_OUTPUT_3[25]" bitfld.long 0x00 10.--11. " [26] ,Pin 26 output source" "TCR[26],ALT_OUTPUT_1[26],ALT_OUTPUT_2[26],ALT_OUTPUT_3[26]" bitfld.long 0x00 8.--9. " [27] ,Pin 27 output source" "TCR[27],ALT_OUTPUT_1[27],ALT_OUTPUT_2[27],ALT_OUTPUT_3[27]" newline bitfld.long 0x00 6.--7. " [28] ,Pin 28 output source" "TCR[28],ALT_OUTPUT_1[28],ALT_OUTPUT_2[28],ALT_OUTPUT_3[28]" bitfld.long 0x00 4.--5. " [29] ,Pin 29 output source" "TCR[29],ALT_OUTPUT_1[29],ALT_OUTPUT_2[29],ALT_OUTPUT_3[29]" bitfld.long 0x00 2.--3. " [30] ,Pin 30 output source" "TCR[30],ALT_OUTPUT_1[30],ALT_OUTPUT_2[30],ALT_OUTPUT_3[30]" bitfld.long 0x00 0.--1. " [31] ,Pin 31 output source" "TCR[31],ALT_OUTPUT_1[31],ALT_OUTPUT_2[31],ALT_OUTPUT_3[31]" newline group.long (dcr:0x200:0x20000000+0x18)++0x03 line.long 0x00 "ODR,Open-Drain Register" bitfld.long 0x00 31. " ODR[0] ,Pin 0 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 30. " [1] ,Pin 1 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 29. " [2] ,Pin 2 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 28. " [3] ,Pin 3 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 27. " [4] ,Pin 4 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 26. " [5] ,Pin 5 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 25. " [6] ,Pin 6 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 24. " [7] ,Pin 7 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 23. " [8] ,Pin 8 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 22. " [9] ,Pin 9 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 21. " [10] ,Pin 10 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 20. " [11] ,Pin 11 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 19. " [12] ,Pin 12 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 18. " [13] ,Pin 13 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 17. " [14] ,Pin 14 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 16. " [15] ,Pin 15 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 15. " [16] ,Pin 16 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 14. " [17] ,Pin 17 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 13. " [18] ,Pin 18 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 12. " [19] ,Pin 19 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 11. " [20] ,Pin 20 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 10. " [21] ,Pin 21 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 9. " [22] ,Pin 22 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 8. " [23] ,Pin 23 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 7. " [24] ,Pin 24 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 6. " [25] ,Pin 25 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 5. " [26] ,Pin 26 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 4. " [27] ,Pin 27 open-drain emulation enable" "-,Enabled" newline bitfld.long 0x00 3. " [28] ,Pin 28 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 2. " [29] ,Pin 29 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 1. " [30] ,Pin 30 open-drain emulation enable" "-,Enabled" bitfld.long 0x00 0. " [31] ,Pin 31 open-drain emulation enable" "-,Enabled" rgroup.long (dcr:0x200:0x20000000+0x1C)++0x03 line.long 0x00 "IR,Input Register" bitfld.long 0x00 31. " IR[0] ,Pin 0 input" "Low,High" bitfld.long 0x00 30. " [1] ,Pin 1 input" "Low,High" bitfld.long 0x00 29. " [2] ,Pin 2 input" "Low,High" bitfld.long 0x00 28. " [3] ,Pin 3 input" "Low,High" newline bitfld.long 0x00 27. " [4] ,Pin 4 input" "Low,High" bitfld.long 0x00 26. " [5] ,Pin 5 input" "Low,High" bitfld.long 0x00 25. " [6] ,Pin 6 input" "Low,High" bitfld.long 0x00 24. " [7] ,Pin 7 input" "Low,High" newline bitfld.long 0x00 23. " [8] ,Pin 8 input" "Low,High" bitfld.long 0x00 22. " [9] ,Pin 9 input" "Low,High" bitfld.long 0x00 21. " [10] ,Pin 10 input" "Low,High" bitfld.long 0x00 20. " [11] ,Pin 11 input" "Low,High" newline bitfld.long 0x00 19. " [12] ,Pin 12 input" "Low,High" bitfld.long 0x00 18. " [13] ,Pin 13 input" "Low,High" bitfld.long 0x00 17. " [14] ,Pin 14 input" "Low,High" bitfld.long 0x00 16. " [15] ,Pin 15 input" "Low,High" newline bitfld.long 0x00 15. " [16] ,Pin 16 input" "Low,High" bitfld.long 0x00 14. " [17] ,Pin 17 input" "Low,High" bitfld.long 0x00 13. " [18] ,Pin 18 input" "Low,High" bitfld.long 0x00 12. " [19] ,Pin 19 input" "Low,High" newline bitfld.long 0x00 11. " [20] ,Pin 20 input" "Low,High" bitfld.long 0x00 10. " [21] ,Pin 21 input" "Low,High" bitfld.long 0x00 9. " [22] ,Pin 22 input" "Low,High" bitfld.long 0x00 8. " [23] ,Pin 23 input" "Low,High" newline bitfld.long 0x00 7. " [24] ,Pin 24 input" "Low,High" bitfld.long 0x00 6. " [25] ,Pin 25 input" "Low,High" bitfld.long 0x00 5. " [26] ,Pin 26 input" "Low,High" bitfld.long 0x00 4. " [27] ,Pin 27 input" "Low,High" newline bitfld.long 0x00 3. " [28] ,Pin 28 input" "Low,High" bitfld.long 0x00 2. " [29] ,Pin 29 input" "Low,High" bitfld.long 0x00 1. " [30] ,Pin 30 input" "Low,High" bitfld.long 0x00 0. " [31] ,Pin 31 input" "Low,High" group.long (dcr:0x200:0x20000000+0x20)++0x03 line.long 0x00 "RR1,Receive Register 1" bitfld.long 0x00 31. " RR1[0] ,Pin 0 alternative output 1" "Low,High" bitfld.long 0x00 30. " [1] ,Pin 1 alternative output 1" "Low,High" bitfld.long 0x00 29. " [2] ,Pin 2 alternative output 1" "Low,High" bitfld.long 0x00 28. " [3] ,Pin 3 alternative output 1" "Low,High" newline bitfld.long 0x00 27. " [4] ,Pin 4 alternative output 1" "Low,High" bitfld.long 0x00 26. " [5] ,Pin 5 alternative output 1" "Low,High" bitfld.long 0x00 25. " [6] ,Pin 6 alternative output 1" "Low,High" bitfld.long 0x00 24. " [7] ,Pin 7 alternative output 1" "Low,High" newline bitfld.long 0x00 23. " [8] ,Pin 8 alternative output 1" "Low,High" bitfld.long 0x00 22. " [9] ,Pin 9 alternative output 1" "Low,High" bitfld.long 0x00 21. " [10] ,Pin 10 alternative output 1" "Low,High" bitfld.long 0x00 20. " [11] ,Pin 11 alternative output 1" "Low,High" newline bitfld.long 0x00 19. " [12] ,Pin 12 alternative output 1" "Low,High" bitfld.long 0x00 18. " [13] ,Pin 13 alternative output 1" "Low,High" bitfld.long 0x00 17. " [14] ,Pin 14 alternative output 1" "Low,High" bitfld.long 0x00 16. " [15] ,Pin 15 alternative output 1" "Low,High" newline bitfld.long 0x00 15. " [16] ,Pin 16 alternative output 1" "Low,High" bitfld.long 0x00 14. " [17] ,Pin 17 alternative output 1" "Low,High" bitfld.long 0x00 13. " [18] ,Pin 18 alternative output 1" "Low,High" bitfld.long 0x00 12. " [19] ,Pin 19 alternative output 1" "Low,High" newline bitfld.long 0x00 11. " [20] ,Pin 20 alternative output 1" "Low,High" bitfld.long 0x00 10. " [21] ,Pin 21 alternative output 1" "Low,High" bitfld.long 0x00 9. " [22] ,Pin 22 alternative output 1" "Low,High" bitfld.long 0x00 8. " [23] ,Pin 23 alternative output 1" "Low,High" newline bitfld.long 0x00 7. " [24] ,Pin 24 alternative output 1" "Low,High" bitfld.long 0x00 6. " [25] ,Pin 25 alternative output 1" "Low,High" bitfld.long 0x00 5. " [26] ,Pin 26 alternative output 1" "Low,High" bitfld.long 0x00 4. " [27] ,Pin 27 alternative output 1" "Low,High" newline bitfld.long 0x00 3. " [28] ,Pin 28 alternative output 1" "Low,High" bitfld.long 0x00 2. " [29] ,Pin 29 alternative output 1" "Low,High" bitfld.long 0x00 1. " [30] ,Pin 30 alternative output 1" "Low,High" bitfld.long 0x00 0. " [31] ,Pin 31 alternative output 1" "Low,High" group.long (dcr:0x200:0x20000000+0x24)++0x03 line.long 0x00 "RR2,Receive Register 2" bitfld.long 0x00 31. " RR2[0] ,Pin 0 alternative output 2" "Low,High" bitfld.long 0x00 30. " [1] ,Pin 1 alternative output 2" "Low,High" bitfld.long 0x00 29. " [2] ,Pin 2 alternative output 2" "Low,High" bitfld.long 0x00 28. " [3] ,Pin 3 alternative output 2" "Low,High" newline bitfld.long 0x00 27. " [4] ,Pin 4 alternative output 2" "Low,High" bitfld.long 0x00 26. " [5] ,Pin 5 alternative output 2" "Low,High" bitfld.long 0x00 25. " [6] ,Pin 6 alternative output 2" "Low,High" bitfld.long 0x00 24. " [7] ,Pin 7 alternative output 2" "Low,High" newline bitfld.long 0x00 23. " [8] ,Pin 8 alternative output 2" "Low,High" bitfld.long 0x00 22. " [9] ,Pin 9 alternative output 2" "Low,High" bitfld.long 0x00 21. " [10] ,Pin 10 alternative output 2" "Low,High" bitfld.long 0x00 20. " [11] ,Pin 11 alternative output 2" "Low,High" newline bitfld.long 0x00 19. " [12] ,Pin 12 alternative output 2" "Low,High" bitfld.long 0x00 18. " [13] ,Pin 13 alternative output 2" "Low,High" bitfld.long 0x00 17. " [14] ,Pin 14 alternative output 2" "Low,High" bitfld.long 0x00 16. " [15] ,Pin 15 alternative output 2" "Low,High" newline bitfld.long 0x00 15. " [16] ,Pin 16 alternative output 2" "Low,High" bitfld.long 0x00 14. " [17] ,Pin 17 alternative output 2" "Low,High" bitfld.long 0x00 13. " [18] ,Pin 18 alternative output 2" "Low,High" bitfld.long 0x00 12. " [19] ,Pin 19 alternative output 2" "Low,High" newline bitfld.long 0x00 11. " [20] ,Pin 20 alternative output 2" "Low,High" bitfld.long 0x00 10. " [21] ,Pin 21 alternative output 2" "Low,High" bitfld.long 0x00 9. " [22] ,Pin 22 alternative output 2" "Low,High" bitfld.long 0x00 8. " [23] ,Pin 23 alternative output 2" "Low,High" newline bitfld.long 0x00 7. " [24] ,Pin 24 alternative output 2" "Low,High" bitfld.long 0x00 6. " [25] ,Pin 25 alternative output 2" "Low,High" bitfld.long 0x00 5. " [26] ,Pin 26 alternative output 2" "Low,High" bitfld.long 0x00 4. " [27] ,Pin 27 alternative output 2" "Low,High" newline bitfld.long 0x00 3. " [28] ,Pin 28 alternative output 2" "Low,High" bitfld.long 0x00 2. " [29] ,Pin 29 alternative output 2" "Low,High" bitfld.long 0x00 1. " [30] ,Pin 30 alternative output 2" "Low,High" bitfld.long 0x00 0. " [31] ,Pin 31 alternative output 2" "Low,High" group.long (dcr:0x200:0x20000000+0x28)++0x03 line.long 0x00 "RR3,Receive Register 3" bitfld.long 0x00 31. " RR3[0] ,Pin 0 alternative output 3" "Low,High" bitfld.long 0x00 30. " [1] ,Pin 1 alternative output 3" "Low,High" bitfld.long 0x00 29. " [2] ,Pin 2 alternative output 3" "Low,High" bitfld.long 0x00 28. " [3] ,Pin 3 alternative output 3" "Low,High" newline bitfld.long 0x00 27. " [4] ,Pin 4 alternative output 3" "Low,High" bitfld.long 0x00 26. " [5] ,Pin 5 alternative output 3" "Low,High" bitfld.long 0x00 25. " [6] ,Pin 6 alternative output 3" "Low,High" bitfld.long 0x00 24. " [7] ,Pin 7 alternative output 3" "Low,High" newline bitfld.long 0x00 23. " [8] ,Pin 8 alternative output 3" "Low,High" bitfld.long 0x00 22. " [9] ,Pin 9 alternative output 3" "Low,High" bitfld.long 0x00 21. " [10] ,Pin 10 alternative output 3" "Low,High" bitfld.long 0x00 20. " [11] ,Pin 11 alternative output 3" "Low,High" newline bitfld.long 0x00 19. " [12] ,Pin 12 alternative output 3" "Low,High" bitfld.long 0x00 18. " [13] ,Pin 13 alternative output 3" "Low,High" bitfld.long 0x00 17. " [14] ,Pin 14 alternative output 3" "Low,High" bitfld.long 0x00 16. " [15] ,Pin 15 alternative output 3" "Low,High" newline bitfld.long 0x00 15. " [16] ,Pin 16 alternative output 3" "Low,High" bitfld.long 0x00 14. " [17] ,Pin 17 alternative output 3" "Low,High" bitfld.long 0x00 13. " [18] ,Pin 18 alternative output 3" "Low,High" bitfld.long 0x00 12. " [19] ,Pin 19 alternative output 3" "Low,High" newline bitfld.long 0x00 11. " [20] ,Pin 20 alternative output 3" "Low,High" bitfld.long 0x00 10. " [21] ,Pin 21 alternative output 3" "Low,High" bitfld.long 0x00 9. " [22] ,Pin 22 alternative output 3" "Low,High" bitfld.long 0x00 8. " [23] ,Pin 23 alternative output 3" "Low,High" newline bitfld.long 0x00 7. " [24] ,Pin 24 alternative output 3" "Low,High" bitfld.long 0x00 6. " [25] ,Pin 25 alternative output 3" "Low,High" bitfld.long 0x00 5. " [26] ,Pin 26 alternative output 3" "Low,High" bitfld.long 0x00 4. " [27] ,Pin 27 alternative output 3" "Low,High" newline bitfld.long 0x00 3. " [28] ,Pin 28 alternative output 3" "Low,High" bitfld.long 0x00 2. " [29] ,Pin 29 alternative output 3" "Low,High" bitfld.long 0x00 1. " [30] ,Pin 30 alternative output 3" "Low,High" bitfld.long 0x00 0. " [31] ,Pin 31 alternative output 3" "Low,High" newline group.long (dcr:0x200:0x20000000+0x30)++0x03 line.long 0x00 "IS1L,Input Select Low Register 1" bitfld.long 0x00 30.--31. " IS1[0] ,ALT_INPUT_1[0] output" "As RR1[0],As IR[0],As latched IR[0],As ALT_RECEIVE_1[0]" bitfld.long 0x00 28.--29. " [1] ,ALT_INPUT_1[1] output" "As RR1[1],As IR[1],As latched IR[1],As ALT_RECEIVE_1[1]" bitfld.long 0x00 26.--27. " [2] ,ALT_INPUT_1[2] output" "As RR1[2],As IR[2],As latched IR[2],As ALT_RECEIVE_1[2]" bitfld.long 0x00 24.--25. " [3] ,ALT_INPUT_1[3] output" "As RR1[3],As IR[3],As latched IR[3],As ALT_RECEIVE_1[3]" newline bitfld.long 0x00 22.--23. " [4] ,ALT_INPUT_1[4] output" "As RR1[4],As IR[4],As latched IR[4],As ALT_RECEIVE_1[4]" bitfld.long 0x00 20.--21. " [5] ,ALT_INPUT_1[5] output" "As RR1[5],As IR[5],As latched IR[5],As ALT_RECEIVE_1[5]" bitfld.long 0x00 18.--19. " [6] ,ALT_INPUT_1[6] output" "As RR1[6],As IR[6],As latched IR[6],As ALT_RECEIVE_1[6]" bitfld.long 0x00 16.--17. " [7] ,ALT_INPUT_1[7] output" "As RR1[7],As IR[7],As latched IR[7],As ALT_RECEIVE_1[7]" newline bitfld.long 0x00 14.--15. " [8] ,ALT_INPUT_1[8] output" "As RR1[8],As IR[8],As latched IR[8],As ALT_RECEIVE_1[8]" bitfld.long 0x00 12.--13. " [9] ,ALT_INPUT_1[9] output" "As RR1[9],As IR[9],As latched IR[9],As ALT_RECEIVE_1[9]" bitfld.long 0x00 10.--11. " [10] ,ALT_INPUT_1[10] output" "As RR1[10],As IR[10],As latched IR[10],As ALT_RECEIVE_1[10]" bitfld.long 0x00 8.--9. " [11] ,ALT_INPUT_1[11] output" "As RR1[11],As IR[11],As latched IR[11],As ALT_RECEIVE_1[11]" newline bitfld.long 0x00 6.--7. " [12] ,ALT_INPUT_1[12] output" "As RR1[12],As IR[12],As latched IR[12],As ALT_RECEIVE_1[12]" bitfld.long 0x00 4.--5. " [13] ,ALT_INPUT_1[13] output" "As RR1[13],As IR[13],As latched IR[13],As ALT_RECEIVE_1[13]" bitfld.long 0x00 2.--3. " [14] ,ALT_INPUT_1[14] output" "As RR1[14],As IR[14],As latched IR[14],As ALT_RECEIVE_1[14]" bitfld.long 0x00 0.--1. " [15] ,ALT_INPUT_1[15] output" "As RR1[15],As IR[15],As latched IR[15],As ALT_RECEIVE_1[15]" group.long (dcr:0x200:0x20000000+0x30+0x04)++0x03 line.long 0x00 "IS1H,Input Select Low Register 1" bitfld.long 0x00 30.--31. " IS1[16] ,ALT_INPUT_1[16] output" "As RR1[16],As IR[16],As latched IR[16],As ALT_RECEIVE_1[16]" bitfld.long 0x00 28.--29. " [17] ,ALT_INPUT_1[17] output" "As RR1[17],As IR[17],As latched IR[17],As ALT_RECEIVE_1[17]" bitfld.long 0x00 26.--27. " [18] ,ALT_INPUT_1[18] output" "As RR1[18],As IR[18],As latched IR[18],As ALT_RECEIVE_1[18]" bitfld.long 0x00 24.--25. " [19] ,ALT_INPUT_1[19] output" "As RR1[19],As IR[19],As latched IR[19],As ALT_RECEIVE_1[19]" newline bitfld.long 0x00 22.--23. " [20] ,ALT_INPUT_1[20] output" "As RR1[20],As IR[20],As latched IR[20],As ALT_RECEIVE_1[20]" bitfld.long 0x00 20.--21. " [21] ,ALT_INPUT_1[21] output" "As RR1[21],As IR[21],As latched IR[21],As ALT_RECEIVE_1[21]" bitfld.long 0x00 18.--19. " [22] ,ALT_INPUT_1[22] output" "As RR1[22],As IR[22],As latched IR[22],As ALT_RECEIVE_1[22]" bitfld.long 0x00 16.--17. " [23] ,ALT_INPUT_1[23] output" "As RR1[23],As IR[23],As latched IR[23],As ALT_RECEIVE_1[23]" newline bitfld.long 0x00 14.--15. " [24] ,ALT_INPUT_1[24] output" "As RR1[24],As IR[24],As latched IR[24],As ALT_RECEIVE_1[24]" bitfld.long 0x00 12.--13. " [25] ,ALT_INPUT_1[25] output" "As RR1[25],As IR[25],As latched IR[25],As ALT_RECEIVE_1[25]" bitfld.long 0x00 10.--11. " [26] ,ALT_INPUT_1[26] output" "As RR1[26],As IR[26],As latched IR[26],As ALT_RECEIVE_1[26]" bitfld.long 0x00 8.--9. " [27] ,ALT_INPUT_1[27] output" "As RR1[27],As IR[27],As latched IR[27],As ALT_RECEIVE_1[27]" newline bitfld.long 0x00 6.--7. " [28] ,ALT_INPUT_1[28] output" "As RR1[28],As IR[28],As latched IR[28],As ALT_RECEIVE_1[28]" bitfld.long 0x00 4.--5. " [29] ,ALT_INPUT_1[29] output" "As RR1[29],As IR[29],As latched IR[29],As ALT_RECEIVE_1[29]" bitfld.long 0x00 2.--3. " [30] ,ALT_INPUT_1[30] output" "As RR1[30],As IR[30],As latched IR[30],As ALT_RECEIVE_1[30]" bitfld.long 0x00 0.--1. " [31] ,ALT_INPUT_1[31] output" "As RR1[31],As IR[31],As latched IR[31],As ALT_RECEIVE_1[31]" group.long (dcr:0x200:0x20000000+0x38)++0x03 line.long 0x00 "IS2L,Input Select Low Register 2" bitfld.long 0x00 30.--31. " IS2[0] ,ALT_INPUT_2[0] output" "As RR2[0],As IR[0],As latched IR[0],As ALT_RECEIVE_2[0]" bitfld.long 0x00 28.--29. " [1] ,ALT_INPUT_2[1] output" "As RR2[1],As IR[1],As latched IR[1],As ALT_RECEIVE_2[1]" bitfld.long 0x00 26.--27. " [2] ,ALT_INPUT_2[2] output" "As RR2[2],As IR[2],As latched IR[2],As ALT_RECEIVE_2[2]" bitfld.long 0x00 24.--25. " [3] ,ALT_INPUT_2[3] output" "As RR2[3],As IR[3],As latched IR[3],As ALT_RECEIVE_2[3]" newline bitfld.long 0x00 22.--23. " [4] ,ALT_INPUT_2[4] output" "As RR2[4],As IR[4],As latched IR[4],As ALT_RECEIVE_2[4]" bitfld.long 0x00 20.--21. " [5] ,ALT_INPUT_2[5] output" "As RR2[5],As IR[5],As latched IR[5],As ALT_RECEIVE_2[5]" bitfld.long 0x00 18.--19. " [6] ,ALT_INPUT_2[6] output" "As RR2[6],As IR[6],As latched IR[6],As ALT_RECEIVE_2[6]" bitfld.long 0x00 16.--17. " [7] ,ALT_INPUT_2[7] output" "As RR2[7],As IR[7],As latched IR[7],As ALT_RECEIVE_2[7]" newline bitfld.long 0x00 14.--15. " [8] ,ALT_INPUT_2[8] output" "As RR2[8],As IR[8],As latched IR[8],As ALT_RECEIVE_2[8]" bitfld.long 0x00 12.--13. " [9] ,ALT_INPUT_2[9] output" "As RR2[9],As IR[9],As latched IR[9],As ALT_RECEIVE_2[9]" bitfld.long 0x00 10.--11. " [10] ,ALT_INPUT_2[10] output" "As RR2[10],As IR[10],As latched IR[10],As ALT_RECEIVE_2[10]" bitfld.long 0x00 8.--9. " [11] ,ALT_INPUT_2[11] output" "As RR2[11],As IR[11],As latched IR[11],As ALT_RECEIVE_2[11]" newline bitfld.long 0x00 6.--7. " [12] ,ALT_INPUT_2[12] output" "As RR2[12],As IR[12],As latched IR[12],As ALT_RECEIVE_2[12]" bitfld.long 0x00 4.--5. " [13] ,ALT_INPUT_2[13] output" "As RR2[13],As IR[13],As latched IR[13],As ALT_RECEIVE_2[13]" bitfld.long 0x00 2.--3. " [14] ,ALT_INPUT_2[14] output" "As RR2[14],As IR[14],As latched IR[14],As ALT_RECEIVE_2[14]" bitfld.long 0x00 0.--1. " [15] ,ALT_INPUT_2[15] output" "As RR2[15],As IR[15],As latched IR[15],As ALT_RECEIVE_2[15]" group.long (dcr:0x200:0x20000000+0x38+0x04)++0x03 line.long 0x00 "IS2H,Input Select Low Register 2" bitfld.long 0x00 30.--31. " IS2[16] ,ALT_INPUT_2[16] output" "As RR2[16],As IR[16],As latched IR[16],As ALT_RECEIVE_2[16]" bitfld.long 0x00 28.--29. " [17] ,ALT_INPUT_2[17] output" "As RR2[17],As IR[17],As latched IR[17],As ALT_RECEIVE_2[17]" bitfld.long 0x00 26.--27. " [18] ,ALT_INPUT_2[18] output" "As RR2[18],As IR[18],As latched IR[18],As ALT_RECEIVE_2[18]" bitfld.long 0x00 24.--25. " [19] ,ALT_INPUT_2[19] output" "As RR2[19],As IR[19],As latched IR[19],As ALT_RECEIVE_2[19]" newline bitfld.long 0x00 22.--23. " [20] ,ALT_INPUT_2[20] output" "As RR2[20],As IR[20],As latched IR[20],As ALT_RECEIVE_2[20]" bitfld.long 0x00 20.--21. " [21] ,ALT_INPUT_2[21] output" "As RR2[21],As IR[21],As latched IR[21],As ALT_RECEIVE_2[21]" bitfld.long 0x00 18.--19. " [22] ,ALT_INPUT_2[22] output" "As RR2[22],As IR[22],As latched IR[22],As ALT_RECEIVE_2[22]" bitfld.long 0x00 16.--17. " [23] ,ALT_INPUT_2[23] output" "As RR2[23],As IR[23],As latched IR[23],As ALT_RECEIVE_2[23]" newline bitfld.long 0x00 14.--15. " [24] ,ALT_INPUT_2[24] output" "As RR2[24],As IR[24],As latched IR[24],As ALT_RECEIVE_2[24]" bitfld.long 0x00 12.--13. " [25] ,ALT_INPUT_2[25] output" "As RR2[25],As IR[25],As latched IR[25],As ALT_RECEIVE_2[25]" bitfld.long 0x00 10.--11. " [26] ,ALT_INPUT_2[26] output" "As RR2[26],As IR[26],As latched IR[26],As ALT_RECEIVE_2[26]" bitfld.long 0x00 8.--9. " [27] ,ALT_INPUT_2[27] output" "As RR2[27],As IR[27],As latched IR[27],As ALT_RECEIVE_2[27]" newline bitfld.long 0x00 6.--7. " [28] ,ALT_INPUT_2[28] output" "As RR2[28],As IR[28],As latched IR[28],As ALT_RECEIVE_2[28]" bitfld.long 0x00 4.--5. " [29] ,ALT_INPUT_2[29] output" "As RR2[29],As IR[29],As latched IR[29],As ALT_RECEIVE_2[29]" bitfld.long 0x00 2.--3. " [30] ,ALT_INPUT_2[30] output" "As RR2[30],As IR[30],As latched IR[30],As ALT_RECEIVE_2[30]" bitfld.long 0x00 0.--1. " [31] ,ALT_INPUT_2[31] output" "As RR2[31],As IR[31],As latched IR[31],As ALT_RECEIVE_2[31]" group.long (dcr:0x200:0x20000000+0x40)++0x03 line.long 0x00 "IS3L,Input Select Low Register 3" bitfld.long 0x00 30.--31. " IS3[0] ,ALT_INPUT_3[0] output" "As RR3[0],As IR[0],As latched IR[0],As ALT_RECEIVE_3[0]" bitfld.long 0x00 28.--29. " [1] ,ALT_INPUT_3[1] output" "As RR3[1],As IR[1],As latched IR[1],As ALT_RECEIVE_3[1]" bitfld.long 0x00 26.--27. " [2] ,ALT_INPUT_3[2] output" "As RR3[2],As IR[2],As latched IR[2],As ALT_RECEIVE_3[2]" bitfld.long 0x00 24.--25. " [3] ,ALT_INPUT_3[3] output" "As RR3[3],As IR[3],As latched IR[3],As ALT_RECEIVE_3[3]" newline bitfld.long 0x00 22.--23. " [4] ,ALT_INPUT_3[4] output" "As RR3[4],As IR[4],As latched IR[4],As ALT_RECEIVE_3[4]" bitfld.long 0x00 20.--21. " [5] ,ALT_INPUT_3[5] output" "As RR3[5],As IR[5],As latched IR[5],As ALT_RECEIVE_3[5]" bitfld.long 0x00 18.--19. " [6] ,ALT_INPUT_3[6] output" "As RR3[6],As IR[6],As latched IR[6],As ALT_RECEIVE_3[6]" bitfld.long 0x00 16.--17. " [7] ,ALT_INPUT_3[7] output" "As RR3[7],As IR[7],As latched IR[7],As ALT_RECEIVE_3[7]" newline bitfld.long 0x00 14.--15. " [8] ,ALT_INPUT_3[8] output" "As RR3[8],As IR[8],As latched IR[8],As ALT_RECEIVE_3[8]" bitfld.long 0x00 12.--13. " [9] ,ALT_INPUT_3[9] output" "As RR3[9],As IR[9],As latched IR[9],As ALT_RECEIVE_3[9]" bitfld.long 0x00 10.--11. " [10] ,ALT_INPUT_3[10] output" "As RR3[10],As IR[10],As latched IR[10],As ALT_RECEIVE_3[10]" bitfld.long 0x00 8.--9. " [11] ,ALT_INPUT_3[11] output" "As RR3[11],As IR[11],As latched IR[11],As ALT_RECEIVE_3[11]" newline bitfld.long 0x00 6.--7. " [12] ,ALT_INPUT_3[12] output" "As RR3[12],As IR[12],As latched IR[12],As ALT_RECEIVE_3[12]" bitfld.long 0x00 4.--5. " [13] ,ALT_INPUT_3[13] output" "As RR3[13],As IR[13],As latched IR[13],As ALT_RECEIVE_3[13]" bitfld.long 0x00 2.--3. " [14] ,ALT_INPUT_3[14] output" "As RR3[14],As IR[14],As latched IR[14],As ALT_RECEIVE_3[14]" bitfld.long 0x00 0.--1. " [15] ,ALT_INPUT_3[15] output" "As RR3[15],As IR[15],As latched IR[15],As ALT_RECEIVE_3[15]" group.long (dcr:0x200:0x20000000+0x40+0x04)++0x03 line.long 0x00 "IS3H,Input Select Low Register 3" bitfld.long 0x00 30.--31. " IS3[16] ,ALT_INPUT_3[16] output" "As RR3[16],As IR[16],As latched IR[16],As ALT_RECEIVE_3[16]" bitfld.long 0x00 28.--29. " [17] ,ALT_INPUT_3[17] output" "As RR3[17],As IR[17],As latched IR[17],As ALT_RECEIVE_3[17]" bitfld.long 0x00 26.--27. " [18] ,ALT_INPUT_3[18] output" "As RR3[18],As IR[18],As latched IR[18],As ALT_RECEIVE_3[18]" bitfld.long 0x00 24.--25. " [19] ,ALT_INPUT_3[19] output" "As RR3[19],As IR[19],As latched IR[19],As ALT_RECEIVE_3[19]" newline bitfld.long 0x00 22.--23. " [20] ,ALT_INPUT_3[20] output" "As RR3[20],As IR[20],As latched IR[20],As ALT_RECEIVE_3[20]" bitfld.long 0x00 20.--21. " [21] ,ALT_INPUT_3[21] output" "As RR3[21],As IR[21],As latched IR[21],As ALT_RECEIVE_3[21]" bitfld.long 0x00 18.--19. " [22] ,ALT_INPUT_3[22] output" "As RR3[22],As IR[22],As latched IR[22],As ALT_RECEIVE_3[22]" bitfld.long 0x00 16.--17. " [23] ,ALT_INPUT_3[23] output" "As RR3[23],As IR[23],As latched IR[23],As ALT_RECEIVE_3[23]" newline bitfld.long 0x00 14.--15. " [24] ,ALT_INPUT_3[24] output" "As RR3[24],As IR[24],As latched IR[24],As ALT_RECEIVE_3[24]" bitfld.long 0x00 12.--13. " [25] ,ALT_INPUT_3[25] output" "As RR3[25],As IR[25],As latched IR[25],As ALT_RECEIVE_3[25]" bitfld.long 0x00 10.--11. " [26] ,ALT_INPUT_3[26] output" "As RR3[26],As IR[26],As latched IR[26],As ALT_RECEIVE_3[26]" bitfld.long 0x00 8.--9. " [27] ,ALT_INPUT_3[27] output" "As RR3[27],As IR[27],As latched IR[27],As ALT_RECEIVE_3[27]" newline bitfld.long 0x00 6.--7. " [28] ,ALT_INPUT_3[28] output" "As RR3[28],As IR[28],As latched IR[28],As ALT_RECEIVE_3[28]" bitfld.long 0x00 4.--5. " [29] ,ALT_INPUT_3[29] output" "As RR3[29],As IR[29],As latched IR[29],As ALT_RECEIVE_3[29]" bitfld.long 0x00 2.--3. " [30] ,ALT_INPUT_3[30] output" "As RR3[30],As IR[30],As latched IR[30],As ALT_RECEIVE_3[30]" bitfld.long 0x00 0.--1. " [31] ,ALT_INPUT_3[31] output" "As RR3[31],As IR[31],As latched IR[31],As ALT_RECEIVE_3[31]" width 0x0B tree.end tree "I2C (Inter-Integrated Circuit)" width 12. endian.le hgroup.byte (dcr:0x200:0x00000000+0x00)++0x00 hide.byte 0x00 "MDBUF,Master Data Buffer" in hgroup.byte (dcr:0x200:0x00000000+0x02)++0x00 hide.byte 0x00 "SDBUF,Slave Data Buffer" in group.byte (dcr:0x200:0x00000000+0x04)++0x00 line.byte 0x00 "LMADR,Low Master Address Register" hexmask.byte 0x00 0.--7. 0x01 " ADB[7:0] ,Address data bits" if ((per.b(dcr:0x200:0x00000000+0x06)&0x40)==0x00) hgroup.byte (dcr:0x200:0x00000000+0x05)++0x00 hide.byte 0x00 "HMADR,High Master Address Register" else group.byte (dcr:0x200:0x00000000+0x05)++0x00 line.byte 0x00 "HMADR,High Master Address Register" hexmask.byte 0x00 0.--7. 0x01 " ADB[15:8] ,Address data bits" endif group.byte (dcr:0x200:0x00000000+0x06)++0x00 line.byte 0x00 "CNTL,Control Register" bitfld.byte 0x00 7. " HMT ,Halt master transfer" "-,Halted" bitfld.byte 0x00 6. " AMC ,10/7 bit addressing select" "7 bit,10 bit" bitfld.byte 0x00 4.--5. " XFC[5:4] ,Requested transfer byte count" "1,2,3,4" bitfld.byte 0x00 3. " BCL ,Hold bus ownership" "-,Held" newline bitfld.byte 0x00 2. " XFC[2] ,Chain transfer" "Only/Last,Chained" bitfld.byte 0x00 1. " RNW ,Read/Write" "Write,Read" bitfld.byte 0x00 0. " PXF ,Pending transfer" "-,Pending" group.byte (dcr:0x200:0x00000000+0x07)++0x00 line.byte 0x00 "MDCNTL,Mode Control Register" bitfld.byte 0x00 7. " FSB ,Flush slave data buffer" "-,Flushed" bitfld.byte 0x00 6. " FMB ,Flush master data buffer" "-,Flushed" bitfld.byte 0x00 5. " GCE ,General call enable" "-,Enabled" bitfld.byte 0x00 4. " SPMD ,Fast/Standard mode" "Standard (100 kHz),Fast (400 kHz)" newline bitfld.byte 0x00 3. " SMD ,Slave mode enable" "-,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable" "-,Enabled" bitfld.byte 0x00 1. " EUS ,I2C unknown bus state exit" "-,Exit" bitfld.byte 0x00 0. " PCL ,SCL hold" "-,Held" group.byte (dcr:0x200:0x00000000+0x08)++0x00 line.byte 0x00 "STAT,Status Register" rbitfld.byte 0x00 7. " SSET ,Slave status set" "-,Set" rbitfld.byte 0x00 6. " SLR ,Sleep request" "-,Sleep" rbitfld.byte 0x00 5. " MDH ,Master data buffer not empty" "Empty,Not empty" rbitfld.byte 0x00 4. " MDF ,Master data buffer full" "Not full,Full" newline eventfld.byte 0x00 3. " HLT ,Halted or stopped" "-,Halted/Stopped" rbitfld.byte 0x00 2. " ERR ,Error" "-,Error" eventfld.byte 0x00 1. " IRQ ,Interrupt request active" "-,Active" rbitfld.byte 0x00 0. " PXF ,Transfer pending" "-,Pending" if (((per.b(dcr:0x200:0x00000000+0x06)&0x04)==0x04)&&((per.b(dcr:0x200:0x00000000+0x08)&0x01)==0x00)) group.byte (dcr:0x200:0x00000000+0x09)++0x00 line.byte 0x00 "EXTSTAT,Extended Status Register" eventfld.byte 0x00 7. " ILLS ,Slave transfer illegal start/stop occurred" "-,Occurred" rbitfld.byte 0x00 4.--6. " BCS ,Bus control state" ",Slave selected,Slave transfer,Paused,I2C idle,I2C busy,I2C unknown,Wait" eventfld.byte 0x00 3. " ILL ,Master transfer illegal start/stop occurred" "-,Occurred" newline eventfld.byte 0x00 2. " LARB ,Loss of arbitration occurred" "-,Occurred" eventfld.byte 0x00 1. " IXF ,Incomplete transfer occurred" "-,Occurred" eventfld.byte 0x00 0. " ANAK ,Address not acknowledged" "ACK,NACK" else group.byte (dcr:0x200:0x00000000+0x09)++0x00 line.byte 0x00 "EXTSTAT,Extended Status Register" eventfld.byte 0x00 7. " ILLS ,Slave transfer illegal start/stop occurred" "-,Occurred" rbitfld.byte 0x00 4.--6. " BCS ,Bus control state" ",Slave selected,Slave transfer,Master transfer,I2C idle,I2C busy,I2C unknown,Wait" eventfld.byte 0x00 3. " ILL ,Master transfer illegal start/stop occurred" "-,Occurred" newline eventfld.byte 0x00 2. " LARB ,Loss of arbitration occurred" "-,Occurred" eventfld.byte 0x00 1. " IXF ,Incomplete transfer occurred" "-,Occurred" eventfld.byte 0x00 0. " ANAK ,Address not acknowledged" "ACK,NACK" endif group.byte (dcr:0x200:0x00000000+0x0A)++0x00 line.byte 0x00 "LSADR,Low Slave Address Register" hexmask.byte 0x00 0.--7. 0x01 " ADB[7:0] ,Address data bits" if ((per.b(dcr:0x200:0x00000000+0x06)&0x40)==0x00) hgroup.byte (dcr:0x200:0x00000000+0x0B)++0x00 hide.byte 0x00 "HSADR,High Slave Address Register" else group.byte (dcr:0x200:0x00000000+0x0B)++0x00 line.byte 0x00 "HSADR,High Slave Address Register" hexmask.byte 0x00 0.--7. 0x01 " ADB[15:8] ,Address data bits" endif group.byte (dcr:0x200:0x00000000+0x0C)++0x00 line.byte 0x00 "CLKDIV,Clock Divide Register" group.byte (dcr:0x200:0x00000000+0x0D)++0x00 line.byte 0x00 "INTRENAB,Interrupt Enable Register" bitfld.byte 0x00 7. " IRQSVC ,Slave read complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " IRQSVR ,Slave read needs service interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " IRQSW ,Slave write complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " IRQSVW ,Slave write needs service interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 3. " IRQH ,Halt executed interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " IRQI ,Incomplete transfer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " IRQA ,Address not acknowledged/illegal start or stop/loss of arbitration interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IRQM ,Requested master transfer complete interrupt enable" "Disabled,Enabled" group.byte (dcr:0x200:0x00000000+0x0E)++0x00 line.byte 0x00 "XFRCNT,Transfer Count Register" bitfld.byte 0x00 4.--6. " STC ,Slave transfer count" "0,1,2,3,4,?..." bitfld.byte 0x00 0.--2. " MTC ,Master transfer count" "0,1,2,3,4,?..." group.byte (dcr:0x200:0x00000000+0x0F)++0x00 line.byte 0x00 "XTCNTLSS,Extended Control And Slave Status Register" eventfld.byte 0x00 7. " COMR ,Slave read complete" "-,Completed" eventfld.byte 0x00 6. " SRVR ,Slave read needs service" "-,Yes" eventfld.byte 0x00 5. " COMW ,Slave write complete" "-,Completed" eventfld.byte 0x00 4. " SRVW ,Slave write needs service" "-,Yes" newline rbitfld.byte 0x00 3. " SHD ,Slave data buffer not empty" "Empty,Not empty" rbitfld.byte 0x00 2. " SFUL ,Slave data buffer full" "-,Full" bitfld.byte 0x00 1. " PIRQ ,Pulsed interrupt request enable" "-,Enabled" bitfld.byte 0x00 0. " SRST ,Soft reset" "-,Reset" group.byte (dcr:0x200:0x00000000+0x10)++0x00 line.byte 0x00 "DIRECTCNTL,Direct Control Register" bitfld.byte 0x00 3. " CSDA ,SDA output value" "Low,High" bitfld.byte 0x00 2. " CSCL ,SDL output value" "Low,High" rbitfld.byte 0x00 1. " SDA ,SDA input value" "Low,High" rbitfld.byte 0x00 0. " SCL ,SCL input value" "Low,High" rgroup.byte (dcr:0x200:0x00000000+0x11)++0x00 line.byte 0x00 "INTR,Interrupt Register" bitfld.byte 0x00 1. " IRQP ,Interrupt request pending" "-,Interrupt" bitfld.byte 0x00 0. " IRQD ,Interrupt request on-deck" "-,Interrupt" endian.def width 0x0B tree.end newline