; --------------------------------------------------------------------------------
; @Title: tbd. 
; @Props:
; @Author: -
; @Changelog: 
; @Manufacturer:
; @Doc: 
; @Core:
; @Chip:
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: per476cc.per 5900 2015-01-09 11:57:07Z askoncej $
width 11.
tree.open "Level 1"
group spr:0x3b3++0 
line.long      0. "CCR0,Core Configuration Register 0"
bitfld.long  0. 30.        " PRE ,Parity recoverability enable" "semi,full"
bitfld.long  0. 27.        "  CRPE ,Cache read parity enable" "-,ena"
bitfld.long  0. 21.        "  ICS ,icbi request size" "32,128"
bitfld.long  0. 20.--20.    "  DAPUIB ,Disable APU Instruction Broadcast" "ena,-"
hexmask.long.byte  0. 16.--19.    1. "  ICWRIDX ,Instruction cache write index (for JTAG)"
bitfld.long  0. 15.--15.    "  DTB ,Disable Trace Broadcast" "ena,-"
bitfld.long  0. 08.--08.    "  FLTSTA ,Force Load/Store Alignment" "no,yes"
bitfld.long  0. 02.--03.    "  DQWPM ,Data cache quadword prediction mode." "No,EA[19],value,NOT EA[19]"
bitfld.long  0. 01.        "  IQWPM ,Instruction cache quadword prediction mode." "value,EA[19]"
group spr:0x378++0 
line.long      0. "CCR1,Core Configuration Register 1"
bitfld.long  0. 27.        " ICDPEI-left ,Instruction cache data parity error insert." "odd,even"
bitfld.long  0. 26.        "  ICDPEI-right ,Instruction cache data parity error insert." "odd,even"
bitfld.long  0. 21.        "  DCDPEI-even ,Data cache data parity error insert." "odd,even"
bitfld.long  0. 20.        "  DCDPEI-odd ,Instruction cache parity error insert." "odd,even"
bitfld.long  0. 31.        "  GPRPEI ,GPR parity error insert" "-,I-pipe"
bitfld.long  0. 29.        "  FPRPEI ,Floating-Point Register (FPR) parity error insert." "-,1st"
bitfld.long  0. 15.        "  MMUTPEI ,Memory management unit tag parity error insert." "odd,even"
textline "                    "
bitfld.long  0. 25.        " ICLPEI-left ,Instruction cache LRU parity error insert." "odd,even"
bitfld.long  0. 24.        "  ICLPEI-right ,Instruction cache LRU parity error insert." "odd,even"
bitfld.long  0. 19.        "  DCLPEI-even ,Data cache LRU parity error insert." "odd,even"
bitfld.long  0. 18.        "  DCLPEI-odd ,Instruction LRU parity error insert." "odd,even"
bitfld.long  0. 30.        "  GPRPEI ,GPR parity error insert" "-,L-pipe"
bitfld.long  0. 28.        "  FPRPEI ,Floating-Point Register (FPR) parity error insert." "-,2nd"
bitfld.long  0. 14.        "  MMUDPEI ,Memory management unit data parity error insert." "odd,even"
textline "                    "
bitfld.long  0. 23.        " ICTPEI-left ,Instruction cache tag parity error insert." "odd,even"
bitfld.long  0. 22.        "  ICTPEI-right ,Instruction cache tag parity error insert." "odd,even"
bitfld.long  0. 17.        "  DCTPEI-even ,Data cache Tag parity error insert." "odd,even"
bitfld.long  0. 16.        "  DCTPEI-odd ,Instruction Tag parity error insert." "odd,even"
bitfld.long  0. 12.        "  TSS ,Timer clock source select" "cpu,alternate"
bitfld.long  0. 10.        "  DPC ,Disable parity checking in the L1 cache core (at reset,this bit is set to '1')" "ena,-"
bitfld.long  0. 08.--09.    "     TCS ,Timer clock select,watchdog timer select" "1,4,8,16"
group spr:0x379++0 
line.long      0. "CCR2,Core Configuration Register 2"
bitfld.long  0. 30.--31.    " DSTG ,diasable store gathering" "00,01,res,dis"
bitfld.long  0. 29.        "  DLFPD ,Data cache line fill prediction disable" "ena,-"
bitfld.long  0. 27.        "  DSTI ,Disable shadow TLB invalidate" "context,isync"
bitfld.long  0. 22.        "  PMUD ,Performance Monitor Unit Disable" "ena,-"
bitfld.long  0. 20.        "  DCSTGW ,Disable Cacheable Store Gathering Write-Through" "can,can-not"
hexmask.long.byte 0. 16.--19. 1. "  STGCTR ,Store Gathering Counter" 
bitfld.long  0. 15.        "  DISTG ,Disable Cache Inhibited Store Gathering" "ena,-"
bitfld.long  0. 11.        "  SPC5C1 ,ICU 'AT' Field Static Branch Predict on Code C5 and C1" "-,AT"
bitfld.long  0. 10.        "  MCDTO ,Machine Check on DCR Timeout Enable" "-,ena"
tree.end
tree.open "Level 2"
sif (CPUIS(ACP34*))
rgroup (dcr:0x300+0x4)++0 
SAVEOUT dcr:0x300 %l %be 0xc
line.long      0. "L2REVID,Revision ID Register"
hexmask.long.word 0. 8.--19. 1. " VerNo ,Version number"
hexmask.long.byte 0. 0.--7.  1. "  RevID ,Revision ID"
rgroup (dcr:0x300+0x4)++0 
SAVEOUT dcr:0x300 %l %be 0x10
line.long      0. "L2CNFG0,L2 Global Configuration Register 0"
hexmask.long.byte 0. 12.--16. 1. " MasterID ,Master self ID"
bitfld.long       0. 8.--10.     "  TSnoop ,TSnoop parameter" "8,Res,Res,Res,Res,5,6,7"
bitfld.long       0. 4.--5.      "  PlbClkRatio ,L2 to PLB6 Clock ratio" "1to1,2to1,Res,Res"
bitfld.long       0. 0.--1.      "  L2Size ,L2 Cache Size" "256kB,512kB,1MB,128kB"
endif
sif (CPU()=="PPC476FPE")
rgroup (dcr:0x80000200+0x4)++0 
SAVEOUT dcr:0x80000200 %l %be 0xc
line.long      0. "L2REVID,Revision ID Register"
hexmask.long.word 0. 8.--19. 1. " VerNo ,Version number"
hexmask.long.byte 0. 0.--7.  1. "  RevID ,Revision ID"
rgroup (dcr:0x80000200+0x4)++0 
SAVEOUT dcr:0x80000200 %l %be 0x10
line.long      0. "L2CNFG0,L2 Global Configuration Register 0"
hexmask.long.byte 0. 12.--16. 1. " MasterID ,Master self ID"
bitfld.long       0. 8.--10.     "  TSnoop ,TSnoop parameter" "8,Res,Res,Res,Res,5,6,7"
bitfld.long       0. 4.--5.      "  PlbClkRatio ,L2 to PLB6 Clock ratio" "1to1,2to1,Res,Res"
bitfld.long       0. 0.--1.      "  L2Size ,L2 Cache Size" "256kB,512kB,1MB,128kB"
endif
tree.end