; --------------------------------------------------------------------------------
; @Title: MPC4200 On-Chip Peripherals
; @Props:
; @Author: -
; @Changelog: 
; @Manufacturer:
; @Doc: 
; @Core:
; @Chip: MGT5100
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: per4200.per 5900 2015-01-09 11:57:07Z askoncej $
config 16. 8.
width 0x9
munging.le
base iobase()
tree "Core Specific Register"
;begin include file 4200/CSR4200.PH
;parameters:
RGROUP spr:0x11F--0x11F "Processor Version Register"
LINE.LONG 0. "PVR ,Processor Version Register"
HEXMASK.LONG 0. 16.--31. 1. 0. "VER ,Version"
HEXMASK.LONG 0. 00.--15. 1. 0. "  REV ,Revision"
RGROUP 0200++3 "JTAG ID Number"
LINE.LONG 0. "JTAGID,CDM Register 0x00 = JTAG ID Number (JTAGID): 01C5301D hex (read only)"
GROUP spr:0x3f0--0x3f0 "HID0-Register"
LINE.LONG 0. "HID0 , Hardware Implementation Register 0"
TEXTLINE "           "
BITFLD.long 0. 31. "  EMCP ,Enable machine check pin" "0,1"
BITFLD.long 0. 29. "   EBA ,Enable bus address parity checking" "0,1"
BITFLD.long 0. 28. "   EBD ,Enable bus data parity checking" "0,1"
BITFLD.long 0. 27. " SBCLK ,Select Bus Clock for test clock pin" "0,1"
BITFLD.long 0. 25. "  ECLK ,enable external test clock pin" "0,1"
BITFLD.long 0. 24. "   PAR ,Disable precharge of  !ARTRY  and shared signals" "0,1"
BITFLD.long 0. 23. "  DOZE ,Doze mode; PLL, time base, and snooping active" "0,1"
BITFLD.long 0. 22. "   NAP ,Nap mode; PLL and time base active" "0,1"
BITFLD.long 0. 21. " SLEEP ,Sleep mode; no external clock required" "0,1"
BITFLD.long 0. 20. "   DPM ,Enable dynamic power management" "0,1"
TEXTLINE "           "
BITFLD.long 0. 19. "ERISEG ,Read I SEG (For test only)" "0,1"
BITFLD.long 0. 16. "   NHR ,Not hard reset" "0,1"
BITFLD.long 0. 15. "   ICE ,Instruction cache enable" "0,1"
BITFLD.long 0. 14. "   DCE ,Data cache enable" "0,1"
BITFLD.long 0. 13. " ILOCK ,Instruction cache LOCK" "0,1"
BITFLD.long 0. 12. " DLOCK ,Data cache LOCK" "0,1"
BITFLD.long 0. 11. "  ICFI ,Instruction cache flash invalidate" "0,1"
BITFLD.long 0. 10. "  DCFI ,Data cache flash invalidate" "0,1"
TEXTLINE "           "
BITFLD.long 0. 7. "  IFEM ,Instruction fetch enable M" "0,1"
BITFLD.long 0. 4. " FBIOB ,Force branch inirect on bus" "0,1"
BITFLD.long 0. 3. "   ABE ,Address broadcast enable" "0,1"
BITFLD.long 0. 0. " NOOPTI ,No-op touch instructions" "0,1"
RGROUP spr:0x3f1--0x3f1 "HID1-Register"
LINE.long 0. "HID1, Hardware Implementation Register 1"
BITFLD.long 0. 31. "PC0 ,PLL configuration bit0 (read only)" "0,1"
BITFLD.long 0. 30. "  PC1 ,PLL configuration bit1 (read only)" "0,1"
BITFLD.long 0. 29. "  PC2 ,PLL configuration bit2 (read only)" "0,1"
BITFLD.long 0. 28. "  PC3 ,PLL configuration bit3 (read only)" "0,1"
BITFLD.long 0. 27. "  PC4 ,PLL configuration bit4 (read only)" "0,1"
BITFLD.long 0. 00. "    FPD ,Floating Point Disabled" "0,1"
GROUP spr:0x3f3--0x3f3 "HID2-Register"
LINE.long 0. "HID2, Hardware Implementation Register 2"
BITFLD.long 0. 27. "LET ,Little endian type. 0 = classic PowerPC LE 1 = true LE" "0,1"
BITFLD.long 0. 18. "  HiBatEN ,Enable IBAT 4-7 and DBAT 4-7. Abbreviated name for this bit is: HID2[13]HBE" "0,1"
BITFLD.long 0. 16. "  SFP ,Speed for low power" "0,1"
BITFLD.long 0. 13.--15. "  IWLCK ,Instruction cache way lock" "No Way    ,res,res,res,way 0,res,way 0/1,way 0/1/2"
BITFLD.long 0. 5.--7. "  DWLCK ,Data cache way lock" "No Way    ,res,res,res,way 0,res,way 0/1,way 0/1/2"
;end include file 4200/CSR4200.PH
tree.end
tree "IPbus Interface (IPBI)"
;begin include file 4200/mmap4200.ph
;parameters:
group 0x00000++0x57 "Memory Map Registers (MMAP)"
line.long    0x00 "IPBAR,IP-Bus or Module Base Address Register"
hexmask.long    0x00 00.--16. 8000 "MBAR ,Module Base Address Register"
line.long    0x04 "CS0STR  ,CS0 Start Address Register"
hexmask.long    0x04 00.--16. 8000 "  CS0STR ,"
bitfld.word    0x54 00.    "    CS0_en ,When set, address space is enabled" "0,V"
button "ViewArea" "d (d.l(d:(iobase()+0x04))*0x8000) /dialog"
line.long    0x08 "CS0STP  ,CS0 Stop Address Register"
hexmask.long    0x08 00.--16. 8000 "  CS0STP ,"
line.long    0x0c "CS1STR  ,CS1 Start Address Register"
hexmask.long    0x0c 00.--16. 8000 "  CS1STR ,"
bitfld.word    0x54 01.    "    CS1_en ,When set, address space is enabled" "0,V"
line.long    0x10 "CS1STP  ,CS1 Stop Address Register"
hexmask.long    0x10 00.--16. 8000 "  CS1STP ,"
line.long    0x14 "CS2STR  ,CS2 Start Address Register"
hexmask.long    0x14 00.--16. 8000 "  CS2STR ,"
bitfld.word    0x54 02.    "    CS2_en ,When set, address space is enabled" "0,V"
line.long    0x18 "CS2STP  ,CS2 Stop Address Register"
hexmask.long    0x18 00.--16. 8000 "  CS2STP ,"
line.long    0x1c "CS3STR  ,CS3 Start Address Register"
hexmask.long    0x1c 00.--16. 8000 "  CS3STR ,"
bitfld.word    0x54 03.    "    CS3_en ,When set, address space is enabled" "0,V"
line.long    0x20 "CS3STP  ,CS3 Stop Address Register"
hexmask.long    0x20 00.--16. 8000 "  CS3STP ,"
line.long    0x24 "CS4STR  ,CS4 Start Address Register"
hexmask.long    0x24 00.--16. 8000 "  CS4STR ,"
bitfld.word    0x54 04.    "    CS4_en ,When set, address space is enabled" "0,V"
line.long    0x28 "CS4STP  ,CS4 Stop Address Register"
hexmask.long    0x28 00.--16. 8000 "  CS4STP ,"
line.long    0x2c "CS5STR  ,CS5 Start Address Register"
hexmask.long    0x2c 00.--16. 8000 "  CS5STR ,"
bitfld.word    0x54 05.    "    CS5_en ,When set, address space is enabled" "0,V"
line.long    0x30 "CS5STP  ,CS5 Stop Address Register"
hexmask.long    0x30 00.--16. 8000 "  CS5STP ,"
line.long    0x34 "SDRAMSTR,SDRAM start address"
hexmask.long    0x34 00.--16. 8000 "SDRAMSTR ,"
bitfld.word    0x54 06.    "  SDRAM_en ,When set, address space is enabled" "0,V"
button "ViewArea" "d (d.l(d:(iobase()+0x34))*0x8000) /dialog"
line.long    0x38 "SDRAMSTP,SDRAM stop address"
hexmask.long    0x38 00.--16. 8000 "SDRAMSTP ,"
line.long    0x3c "PCI1STR ,PCI configuration space 1 start"
hexmask.long    0x3c 00.--16. 8000 " PCI1STR ,"
bitfld.word    0x54 07.    "   PCI1_en ,When set, address space is enabled" "0,V"
line.long    0x40 "PCI1STP ,PCI configuration space 1 stop"
hexmask.long    0x40 00.--16. 8000 " PCI1STP ,"
line.long    0x44 "PCI2STR ,PCI configuration space 2 start"
hexmask.long    0x44 00.--16. 8000 " PCI2STR ,"
bitfld.word    0x54 08.    "   PCI2_en ,When set, address space is enabled" "0,V"
line.long    0x48 "PCI2STP ,PCI configuration space 2 stop"
hexmask.long    0x48 00.--16. 8000 " PCI2STP ,"
line.long    0x4c "BOOTSTR ,Boot start address"
hexmask.long    0x4c 00.--16. 8000 " BOOTSTR ,"
bitfld.word    0x54 09.    "   Boot_en ,When set, Boot address space is enabled" "0,V"
button "ViewArea" "d (d.l(d:(iobase()+0x4c))*0x8000) /dialog"
line.long    0x50 "BOOTSTP ,Boot stop address"
hexmask.long    0x50 00.--16. 8000 " BOOTSTP ,"
line.word    0x54 "ADREN  ,Address Space Enable Register"
bitfld.word    0x54 09.    " Boot_en ,When set, Boot address space is enabled" "0,V"
bitfld.word    0x54 08.    "  PCI2_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 07.    "  PCI1_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 06.    "  SDRAM_en ,When set, address space is enabled" "0,V"
Textline "               "
bitfld.word    0x54 05.    " CS5_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 04.    "   CS4_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 03.    "   CS3_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 02.    "    CS2_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 01.    "   CS1_en ,When set, address space is enabled" "0,V"
bitfld.word    0x54 00.    "   CS0_en ,When set, address space is enabled" "0,V"
Textline "                   "
;end include file 4200/mmap4200.ph
tree.end
;"Memory Controller"
TREE "SDRAM Controller Internal Registers"
;begin include file 4200/memctr4200.ph
;parameters:
wgroup 0100++03 "Memory Controller Register Map"
line.long     0.        "MOD,Mode Register"
hexfld.word    0.         "mode_Code ,"
group 0104++0b
line.long    0.        "CTR,Control Register"
line.long    0.        "CFG1,Configuration Register 1"
line.long    0.        "CFG2,Configuration Register 2"
group 0140++03
line.long    0.        "ADRSEL,Address Select Register"
;end include file 4200/memctr4200.ph
TREE.END
TREE "Local Bus"
;"XLB Arbiter"
;"Master Bus Interface (MBI)"
;begin include file 4200/arb4200.ph
;parameters:
group 0080++3
line.long 0. "DPRAM,"
;end include file 4200/arb4200.ph
TREE.END
TREE "System Integration Unit (SIU)"
tree "Interrupt Controller"
;begin include file 4200/ictl4200.ph
;parameters:
group 0500++3
line.long 0. "DPRAM,"
;end include file 4200/ictl4200.ph
tree.end
tree "Real Time Clock"
;begin include file 4200/rtc4200.ph
;parameters:
group 0800++3
line.long 0. "DPRAM,"
;end include file 4200/rtc4200.ph
tree.end
tree "Smartcomm Timers Block"
;begin include file 4200/sctmr4200.ph
;parameters:
group 0400++3
line.long 0. "DPRAM,"
;end include file 4200/sctmr4200.ph
tree.end
TREE.END
TREE "PCI Controller"
;begin include file 4200/xcpci4200.ph
;parameters:
group 0d00++3
line.long 0. "DPRAM,"
;end include file 4200/xcpci4200.ph
;begin include file 4200/scpci4200.ph
;parameters:
group 3800++3
line.long 0. "DPRAM,"
;end include file 4200/scpci4200.ph
;%include kal/pci8240.ph
;base iobase()
TREE.END
TREE "ATA Controller"
;begin include file 4200/ata4200.ph
;parameters:
group 3a00++3
line.long 0. "DPRAM,"
;end include file 4200/ata4200.ph
TREE.END
;Local Plus
; Chip Select Controller (CSC) Programmer's Model
TREE "Universal Serial Bus (USB)"
;begin include file 4200/usb4200.ph
;parameters:
group 1000++3
line.long 0. "DPRAM,"
;end include file 4200/usb4200.ph
TREE.END
TREE "SmartComm Timer Register"
;begin include file 4200/sctmr4200.ph
;parameters:
group 0400++3
line.long 0. "DPRAM,"
;end include file 4200/sctmr4200.ph
TREE.END
TREE "Ethernet"
;begin include file 4200/eth4200.ph
;parameters:
group 3000++3
line.long 0. "DPRAM,"
;end include file 4200/eth4200.ph
TREE.END
TREE "IR Interface Port"
;begin include file 4200/ir4200.ph
;parameters:
group 0e00++3
line.long 0. "DPRAM,"
;end include file 4200/ir4200.ph
TREE.END
TREE.OPEN "Programmable Serial Controllers (PSC)"
;begin include file 4200/pscx4200.ph
;parameters: 0x2000 1
group 0x2000++3
line.long 0. "PSC1,"
;end include file 4200/pscx4200.ph
;begin include file 4200/pscx4200.ph
;parameters: 0x2400 2
group 0x2400++3
line.long 0. "PSC2,"
;end include file 4200/pscx4200.ph
;begin include file 4200/pscx4200.ph
;parameters: 0x2800 3
group 0x2800++3
line.long 0. "PSC3,"
;end include file 4200/pscx4200.ph
TREE.END
TREE "GPIO and Timers"
; GPIO Pin Multiplexing
;begin include file 4200/gpio_std4200.ph
;parameters:
group 0b00++3
line.long 0. "DPRAM,"
;end include file 4200/gpio_std4200.ph
; WakeUP GPIO Control Registers
;begin include file 4200/gpio_wkup4200.ph
;parameters:
group 0c00++3
line.long 0. "DPRAM,"
;end include file 4200/gpio_wkup4200.ph
; General Purpose Timers
;begin include file 4200/gptmr4200.ph
;parameters:
group 0600++3
line.long 0. "DPRAM,"
;end include file 4200/gptmr4200.ph
; Slice Timers
;begin include file 4200/sltimer4200.ph
;parameters:
group 0700++3
line.long 0. "DPRAM,"
;end include file 4200/sltimer4200.ph
TREE.END
TREE "I2C"
;begin include file 4200/i2c4200.ph
;parameters:
group 3d00++3
line.byte 0. "DPRAM,"
;end include file 4200/i2c4200.ph
TREE.END
; isdn
TREE "PLI Module"
;begin include file 4200/pli4200.ph
;parameters:
group 3c00++3
line.long 0. "DPRAM,"
;end include file 4200/pli4200.ph
TREE.END
TREE "SPI Module"
;begin include file 4200/spi4200.ph
;parameters:
group 0f00++3
line.word 2. "DPRAM,"
;end include file 4200/spi4200.ph
TREE.END
;"HDLC"
;SPI
TREE "MSCAN (Motorola Scalable CAN)"
;begin include file 4200/mscan4200.ph
;parameters:
group 0900++3
line.word 2. "DPRAM,"
;end include file 4200/mscan4200.ph
TREE.END
TREE.OPEN "System Support"
; Odin Reset Configuration Register
; Odin Clock Distribution Module (CDM)
;begin include file 4200/cdm4200.ph
;parameters:
group 0200++3
line.long 0. "DPRAM,"
;end include file 4200/cdm4200.ph
; Power Conservation Modes
; Clock Control Sequencer
; Real Time Clock
;begin include file 4200/rtc4200.ph
;parameters:
group 0800++3
line.long 0. "DPRAM,"
;end include file 4200/rtc4200.ph
TREE.END
TEXTLINE ""