; -------------------------------------------------------------------------------- ; @Title: PPC405xx Cache Registers ; @Author: JER ; @Changelog: 2013-09-05 JER ; @Chiplist: NPE405H, NPE405L, PPC405A, PPC405B, PPC405C, PPC405CR, PPC405D, ; PPC405E, PPC405EP, PPC405EX, PPC405EXR, PPC405F, PPC405GP, PPC405GPR, ; PPC405LP, PPC405PM, VIRTEXPPC, VIRTEXPPC1ST, VIRTEXPPC2ND ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: per405cc.per 7589 2017-02-18 09:58:03Z askoncej $ tree.open "Cache operations" width 0x08 config 16. 8. sif (cpu()=="PPC405EP") group spr:0x3b3++0 line.long 0. "CCR0,Core Configuration Register 0" bitfld.long 0. 25.--25. " LWL ,Load Word as a Line" "As requested,8 words" bitfld.long 0. 24.--24. " LWOA ,Load Without Allocate" "Line,Non-cachable" bitfld.long 0. 23.--23. " SWOA ,Store Without Allocate" "Line,Non-cachable" textline " " bitfld.long 0. 22.--22. " DPP1 ,DCU PLB Priority Bit 1" "0,1" bitfld.long 0. 20.--21. " IPP ,ICU PLB Priority Bits 0:1" "Lowest,next lowest,next highest,Highest" bitfld.long 0. 17.--17. " U0XE ,Enable U0 Exception" "-,ena" textline " " bitfld.long 0. 11.--11. " PFC ,ICU Prefetching for Cachable Regions" "-,ena" bitfld.long 0. 10.--10. " PFNC ,ICU Prefetching for Non-Cacheable Regions" "-,ena" bitfld.long 0. 9.--9. " NCRS ,Non-cacheable ICU request size" "four,eight" textline " " bitfld.long 0. 8.--8. " FWOA ,Fetch Without Allocate" "Line,Non-cachable" bitfld.long 0. 4.--4. " CIS ,Cache Information Select" "data,tag" bitfld.long 0. 0.--0. " CWS ,Cache Way Select" "A,B" group spr:0x3d3++0. line.long 0x0 "ICDBR,Instruction Cache Debug Data Register" elif ((cpu()=="NPE405L")||(cpu()=="NPE405H")||(cpu()=="PPC405GP")||(cpu()=="PPC405GPR")) group spr:0x3B3++0x00 line.long 0x00 "CCR0,Core Configuration Register 0" bitfld.long 0x00 25. " LWL ,Load Word as Line" "-,Enabled" bitfld.long 0x00 24. " LWOA ,Load Without Allocate" "-,Enabled" bitfld.long 0x00 23. " SWOA ,Store Without Allocate" "-,Enabled" bitfld.long 0x00 22. " DPP1 ,DCU PLB Priority Bit 1" "Priority 0,Priority 1" textline " " bitfld.long 0x00 20.--21. " IPP ,ICU PLB Priority Bits 0:1" "Lowest,Next to lowest,Next to highest,Highest" bitfld.long 0x00 17. " U0XE ,Enable U0 Exception" "-,Enabled" sif ((cpu()=="PPC405GP")||(cpu()=="PPC405GPR")) bitfld.long 0x00 16. " LDBE ,Load Debug Enable" "-,Enabled" endif textline " " bitfld.long 0x00 11. " PFC ,ICU Prefetching for Cachable Regions" "-,Enabled" bitfld.long 0x00 10. " PFNC ,ICU Prefetching for Non-Cachable Regions" "-,Enabled" bitfld.long 0x00 9. " NCRS ,Non-cachable ICU request size" "Four-word,Eight-word" textline " " bitfld.long 0x00 8. " FWOA ,Fetch Without Allocate" "-,Enabled" bitfld.long 0x00 4. " CIS ,Cache Information Select" "Data,Tag" bitfld.long 0x00 0. " CWS ,Cache Way Select" "A,B" elif (cpu()=="PPC405CR") group spr:0x3b3++0 line.long 0. "CCR0,Core Configuration Register 0" bitfld.long 0. 25.--25. " LWL ,Load Word as a Line" "- ,1" bitfld.long 0. 24.--24. " LWOA ,Load Without Allocate" "- ,1" bitfld.long 0. 23.--23. " SWOA ,Store Without Allocate" "- ,1" bitfld.long 0. 22.--22. " DPP1 ,DCU PLB Priority Bit 1" "- ,1" bitfld.long 0. 20.--21. " IPP ,ICU PLB Priority Bits 0:1" "Lowest,next lowest,next highest,Highest" textline " " bitfld.long 0. 17.--17. " U0XE ,Enable U0 Exception" "ena,-" bitfld.long 0. 16.--16. " LDBE ,Load Debug Enable" "invisible,visible" bitfld.long 0. 11.--11. " PFC ,ICU Prefetching for Cachable Regions" "-,ena" bitfld.long 0. 10.--10. " PFNC ,ICU Prefetching for Non-Cacheable Regions" "-,ena" bitfld.long 0. 9.--9. " NCRS ,Non-cacheable ICU request size" "four,eight" textline " " bitfld.long 0. 8.--8. " FWOA ,Fetch Without Allocate" "-,1" bitfld.long 0. 4.--4. " CIS ,Cache Information Select" "data,tag" bitfld.long 0. 0.--0. " CWS ,Cache Way Select" "A,B" else group spr:0x3b3++0. line.long 0. "CCR0,Core Configuration Register 0" bitfld.long 0. 25.--25. " LWL ,Load Word as a Line" "- ,1" bitfld.long 0. 24.--24. " LWOA ,Load Without Allocate" "- ,1" bitfld.long 0. 23.--23. " SWOA ,Store Without Allocate" "- ,1" bitfld.long 0. 17.--17. " DU0 ,Disable U0 Storage Attribute" "ena,-" bitfld.long 0. 16.--16. " LDBE ,Load Debug Enable" "invisible,visible" textline " " bitfld.long 0. 11.--11. " PFE ,ICU Prefetching for Cahceable Regions" "-,ena" bitfld.long 0. 10.--10. " PFNC ,ICU Prefetching for Non-Cacheable Regions" "-,ena" bitfld.long 0. 10.--10. " NCRS ,Non-cacheable ICU request size" "four,eight" bitfld.long 0. 09.--09. " FWOA ,Fetch Without Allocate" "-,1" textline " " bitfld.long 0. 08.--08. " CIS ,Cache Information Select" "data,tag" bitfld.long 0. 25.--25. " CWS ,Cache Way Select" "A,B" endif if ((d.l(spr:11f)&0x1c00)==0x1400) ;all derivatives with ppc405fx core, as well as group spr:0x378++0. line.long 0. "CCR1,Core Configuration Register 1" bitfld.long 0. 31. "ICTE ,Instruction Cache Tag Parity Insertion" "-,1" bitfld.long 0. 30. " ICDE ,Instruction Cache Data Parity Insertion" "-,1" bitfld.long 0. 29. " DCTE ,Data Cache Tag Parity Insertion" "-,1" bitfld.long 0. 28. " DCDE ,Data Cache Data Parity Insertion" "ena,-" bitfld.long 0. 27. " TLBE ,TLB Parity Insertion" "invisible,visible" endif tree.open "Real-Mode Storage Attribute Control" group spr:0x3ba--0x3ba " 00000000 08000000 10000000 18000000 20000000 28000000 30000000 38000000" line.long 0x0 "DCWR,Data Cache Copy-back/Write-thru Register" textline " 00000000 " bitfld.long 0x0 31. " " " copy, write" bitfld.long 0x0 30. " " " copy, write" bitfld.long 0x0 29. " " " copy, write" bitfld.long 0x0 28. " " " copy, write" bitfld.long 0x0 27. " " " copy, write" bitfld.long 0x0 26. " " " copy, write" bitfld.long 0x0 25. " " " copy, write" bitfld.long 0x0 24. " " " copy, write" textline " 40000000 " bitfld.long 0x0 23. " " " copy, write" bitfld.long 0x0 22. " " " copy, write" bitfld.long 0x0 21. " " " copy, write" bitfld.long 0x0 20. " " " copy, write" bitfld.long 0x0 19. " " " copy, write" bitfld.long 0x0 18. " " " copy, write" bitfld.long 0x0 17. " " " copy, write" bitfld.long 0x0 16. " " " copy, write" textline " 80000000 " bitfld.long 0x0 15. " " " copy, write" bitfld.long 0x0 14. " " " copy, write" bitfld.long 0x0 13. " " " copy, write" bitfld.long 0x0 12. " " " copy, write" bitfld.long 0x0 11. " " " copy, write" bitfld.long 0x0 10. " " " copy, write" bitfld.long 0x0 09. " " " copy, write" bitfld.long 0x0 08. " " " copy, write" textline " c0000000 " bitfld.long 0x0 07. " " " copy, write" bitfld.long 0x0 06. " " " copy, write" bitfld.long 0x0 05. " " " copy, write" bitfld.long 0x0 04. " " " copy, write" bitfld.long 0x0 03. " " " copy, write" bitfld.long 0x0 02. " " " copy, write" bitfld.long 0x0 01. " " " copy, write" bitfld.long 0x0 00. " " " copy, write" group spr:0x3fa--0x3fb line.long 0x0 "DCCR,Data Cache Cacheability Register" textline " 00000000 " bitfld.long 0x0 31. " " " -, enable" bitfld.long 0x0 30. " " " -, enable" bitfld.long 0x0 29. " " " -, enable" bitfld.long 0x0 28. " " " -, enable" bitfld.long 0x0 27. " " " -, enable" bitfld.long 0x0 26. " " " -, enable" bitfld.long 0x0 25. " " " -, enable" bitfld.long 0x0 24. " " " -, enable" textline " 40000000 " bitfld.long 0x0 23. " " " -, enable" bitfld.long 0x0 22. " " " -, enable" bitfld.long 0x0 21. " " " -, enable" bitfld.long 0x0 20. " " " -, enable" bitfld.long 0x0 19. " " " -, enable" bitfld.long 0x0 18. " " " -, enable" bitfld.long 0x0 17. " " " -, enable" bitfld.long 0x0 16. " " " -, enable" textline " 80000000 " bitfld.long 0x0 15. " " " -, enable" bitfld.long 0x0 14. " " " -, enable" bitfld.long 0x0 13. " " " -, enable" bitfld.long 0x0 12. " " " -, enable" bitfld.long 0x0 11. " " " -, enable" bitfld.long 0x0 10. " " " -, enable" bitfld.long 0x0 09. " " " -, enable" bitfld.long 0x0 08. " " " -, enable" textline " c0000000 " bitfld.long 0x0 07. " " " -, enable" bitfld.long 0x0 06. " " " -, enable" bitfld.long 0x0 05. " " " -, enable" bitfld.long 0x0 04. " " " -, enable" bitfld.long 0x0 03. " " " -, enable" bitfld.long 0x0 02. " " " -, enable" bitfld.long 0x0 01. " " " -, enable" bitfld.long 0x0 00. " " " -, enable" line.long 0x4 "ICCR,Instruction Cache Cacheability Register" textline " 00000000 " bitfld.long 0x4 31. " " " -, enable" bitfld.long 0x4 30. " " " -, enable" bitfld.long 0x4 29. " " " -, enable" bitfld.long 0x4 28. " " " -, enable" bitfld.long 0x4 27. " " " -, enable" bitfld.long 0x4 26. " " " -, enable" bitfld.long 0x4 25. " " " -, enable" bitfld.long 0x4 24. " " " -, enable" textline " 40000000 " bitfld.long 0x4 23. " " " -, enable" bitfld.long 0x4 22. " " " -, enable" bitfld.long 0x4 21. " " " -, enable" bitfld.long 0x4 20. " " " -, enable" bitfld.long 0x4 19. " " " -, enable" bitfld.long 0x4 18. " " " -, enable" bitfld.long 0x4 17. " " " -, enable" bitfld.long 0x4 16. " " " -, enable" textline " 80000000 " bitfld.long 0x4 15. " " " -, enable" bitfld.long 0x4 14. " " " -, enable" bitfld.long 0x4 13. " " " -, enable" bitfld.long 0x4 12. " " " -, enable" bitfld.long 0x4 11. " " " -, enable" bitfld.long 0x4 10. " " " -, enable" bitfld.long 0x4 09. " " " -, enable" bitfld.long 0x4 08. " " " -, enable" textline " c0000000 " bitfld.long 0x4 07. " " " -, enable" bitfld.long 0x4 06. " " " -, enable" bitfld.long 0x4 05. " " " -, enable" bitfld.long 0x4 04. " " " -, enable" bitfld.long 0x4 03. " " " -, enable" bitfld.long 0x4 02. " " " -, enable" bitfld.long 0x4 01. " " " -, enable" bitfld.long 0x4 00. " " " -, enable" group spr:0x3B9--0x3B9 line.long 0x0 "SGR,Storage Guarded Register" textline " 00000000 " bitfld.long 0x0 31. " " " -, guarded" bitfld.long 0x0 30. " " " -, guarded" bitfld.long 0x0 29. " " " -, guarded" bitfld.long 0x0 28. " " " -, guarded" bitfld.long 0x0 27. " " " -, guarded" bitfld.long 0x0 26. " " " -, guarded" bitfld.long 0x0 25. " " " -, guarded" bitfld.long 0x0 24. " " " -, guarded" textline " 40000000 " bitfld.long 0x0 23. " " " -, guarded" bitfld.long 0x0 22. " " " -, guarded" bitfld.long 0x0 21. " " " -, guarded" bitfld.long 0x0 20. " " " -, guarded" bitfld.long 0x0 19. " " " -, guarded" bitfld.long 0x0 18. " " " -, guarded" bitfld.long 0x0 17. " " " -, guarded" bitfld.long 0x0 16. " " " -, guarded" textline " 80000000 " bitfld.long 0x0 15. " " " -, guarded" bitfld.long 0x0 14. " " " -, guarded" bitfld.long 0x0 13. " " " -, guarded" bitfld.long 0x0 12. " " " -, guarded" bitfld.long 0x0 11. " " " -, guarded" bitfld.long 0x0 10. " " " -, guarded" bitfld.long 0x0 09. " " " -, guarded" bitfld.long 0x0 08. " " " -, guarded" textline " c0000000 " bitfld.long 0x0 07. " " " -, guarded" bitfld.long 0x0 06. " " " -, guarded" bitfld.long 0x0 05. " " " -, guarded" bitfld.long 0x0 04. " " " -, guarded" bitfld.long 0x0 03. " " " -, guarded" bitfld.long 0x0 02. " " " -, guarded" bitfld.long 0x0 01. " " " -, guarded" bitfld.long 0x0 00. " " " -, guarded" tree.end tree.open "Interrupts and Exceptions" group spr:0x3d6++0 line.long 0x00 "EVPR,Exception Vector Prefix Register" hexmask.long 0x00 16.--31. 0x10000 " EVP ,Exception Vector Prefix" textline " + 0x0100 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x100)" textfld " Critical Input" textline " + 0x0200 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x200)" textfld " Machine Check" textline " + 0x0300 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x300)" textfld " Data Storage" textline " + 0x0400 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x400)" textfld " Instruction Storage" textline " + 0x0600 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x600)" textfld " Alignment" textline " + 0x1100 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x1100)" textfld " Data TLB Error" textline " + 0x1200 " button "List Source" "d.l d:(((d.l(spr:0x3d6))&0xffff0000)|0x1200)" textfld " Instruction TLB Error" group spr:0x3D5++0 line.long 0x00 "DEAR,Data Exception Address Register" group spr:0x3d4++0 line.long 0x00 "ESR,Exception Syndrome Register" bitfld.long 0x00 31. " MCI ,Machine Check Instruction Fetch Exception" "-,xx" bitfld.long 0x00 27. " PIL ,Program Interrupt Illegal Instruction Exception" "-,xx" bitfld.long 0x00 26. " PPR ,Program Interrupt Privileged Instruction Exception" "-,xx" bitfld.long 0x00 25. " PTR ,Program Interrupt Trap Exception" "-,xx" bitfld.long 0x00 24. " PEU ,Floating Point Operation" "-,xx" bitfld.long 0x00 23. " DST ,Store Operation" "-,xx" bitfld.long 0x00 22. " DIZ ,Data/instruction storage interrupt - zone fault" "-,xx" bitfld.long 0x00 19. " PFP ,Program interrupt - FPU" "-,xx" textline " " bitfld.long 0x00 18. " PAP ,Program interrupt - APU" "-,xx" bitfld.long 0x00 15. " U0F ,Data storage interrupt" "-,xx" group spr:0x23C--0x23C line.long 0x00 "MCSR,Machine Check Status Register" bitfld.long 0x00 31. " MCS ,Machine Check Summary" "-,xx" bitfld.long 0x00 30. " IPLBE ,Instruction PLB Error" "-,xx" bitfld.long 0x00 29. " DPLBE ,Data PLB Error" "-,xx" bitfld.long 0x00 27. " TLBP ,Translation Lookaside Buffer Parity Error" "-,xx" bitfld.long 0x00 26. " ICPE ,Instruction Cache Parity Error" "-,xx" bitfld.long 0x00 25. " DCLPE ,Data Cache Load Parity Error" "-,xx" bitfld.long 0x00 24. " DCFPE ,Data Cache Flush Parity Error" "-,xx" bitfld.long 0x00 23. " IMCE ,Imprecise Machine Check Exception" "-,xx" bitfld.long 0x00 21.--22. " TLBS ,TLB Parity Source" "Inst. fetch,Data fetch,tlbsx,tlbre" group spr:0x01A++0 line.long 0x00 "SRR0,Save/Restore Register 0" hexmask.long 0x00 0.--31. 1. " SRR0 ,Return address for non-critical interrupts - rfi" group spr:0x01b++0 line.long 0x00 "SRR1,Save/Restore Register 1" hexmask.long 0x00 0.--31. 1. " SRR1 ,Return address for non-critical interrupts - rfi" group spr:0x3de++0 line.long 0x00 "SRR2,Save/Restore Register 2" hexmask.long 0x00 0.--31. 1. " SRR2 ,Return address for non-critical interrupts - rfci" group spr:0x3df++0 line.long 0x00 "SRR3,Save/Restore Register 3" hexmask.long 0x00 0.--31. 1. " SRR3 ,Return address for non-critical interrupts - rfci" tree.end width 0x0B tree.end