; -------------------------------------------------------------------------------- ; @Title: PPC403GC/GCX on chip peripherals and SPRs ; @Changelog: 2006-06-26 HST initial version ; @Author: HST ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: per403gc.per 5527 2014-09-01 09:45:18Z jerzy $ config 16. 8. tree "Processor Version" group spr:0x11f--0x11f line.long 0x0 "PVR,Prozessor Version Register" hexmask.long 0x0 20.--31. 0x1 "FAM ,Prozessor Family" bitfld.long 0x0 16.--19. " MEM ,Family Member" "403,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res" bitfld.long 0x0 12.--15. " CL ,Core Level" "g,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res" bitfld.long 0x0 8.--11. " CFG ,Configuration" "a,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res" textline " " hexmask.long 0x0 0x4--0x7 0x1 " MAJ ,Major Change Level" hexmask.long 0x0 0x0--0x3 0x1 " MIN ,Minor Change Level" tree.end tree "Memory and Peripheral Interface" group dcr:0x80--0x80 "Bank 0" line.long 0x0 "BR0,Bank Register 0" hexmask.long 0x0 24.--31. 0x100000 "BAS ,Base Address (Bit 1-3 = 111, since SRAM)" bitfld.long 0x0 21.--23. " BS ,Bank Size" "1MB,2MB,4MB,8MB,16MB,32MB,64MB,res" bitfld.long 0x0 19.--20. " BU ,Bank Usage" "disable,read only,write only,read/write" bitfld.long 0x0 15.--16. " BW ,Bus Width" "8-bit,16-bit,32-bit,res" textline " " bitfld.long 0x0 18. " SLF ,Sequential Line Fill" "off,one" bitfld.long 0x0 17. " BME ,Burst Mode Enable" "off,on" bitfld.long 0x0 14. " RE ,Ready Enable" "dis,ena" bitfld.long 0x0 8.--13. " TWT ,Transfer Wait Timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 7. " CST ,Chip Select On Timing" "address,delayed" bitfld.long 0x0 6. " OET ,Output Enable On Timing" "select,delayed" textline " " bitfld.long 0x0 5. " WBN ,Write Byte Enable On Timing" "select,delayed" bitfld.long 0x0 4. " WBF ,Write Byte Enable Off Timing" "select,before" bitfld.long 0x0 0x1--0x3 " TH ,Transfer Hold" "0,1,2,3,4,5,6,7" group dcr:0x81--0x81 "Bank 1" copy group dcr:0x82--0x82 "Bank 2" copy group dcr:0x83--0x83 "Bank 3" copy group dcr:0x84--0x84 "Bank 4" line.long 0x0 "BR0,Bank Register 0" hexmask.long 0x0 24.--31. 0x100000 "BAS ,Base Address (SRAM->Bit 1-3=111, DRAM->Bit 1-3=000)" bitfld.long 0x0 21.--23. " BS ,Bank Size" "1MB,2MB,4MB,8MB,16MB,32MB,64MB,res" bitfld.long 0x0 19.--20. " BU ,Bank Usage" "disable,read only,write only,read/write" bitfld.long 0x0 15.--16. " BW ,Bus Width" "8-bit,16-bit,32-bit,res" bitfld.long 0x0 0x0 " SD ,SRAM/DRAM Selection" "dram,sram" textline " DRAM " bitfld.long 0x0 14. " IEM ,Internal/External Multiplex" "intern,extern" bitfld.long 0x0 13. " RCT ,RAS/CAS Timing" "one clk,two clk" bitfld.long 0x0 12. " ARM ,Alternate Refresh Mode" "nrm,imd" bitfld.long 0x0 11. " PM ,Page Mode" "no,yes" bitfld.long 0x0 9.--10. " FAC ,First Access Timing" "2,3,4,5" bitfld.long 0x0 7.--8. " BAC ,Burst Access Timing" "1,2,3,4" textline " " bitfld.long 0x0 18. " SLF ,Sequential Line Fills" "TWF,seq" bitfld.long 0x0 17. " ERM ,Early RAS Mode" "nrm,erl" bitfld.long 0x0 6. " PCC ,Precharge Cycles" "1.5,2.5" bitfld.long 0x0 5. " RAR ,RAS Active During Refresh" "1.5,2.5" bitfld.long 0x0 1.--4. " RR ,Refresh Interval" "none,res,64,96,128,192,256,384,512,768,1024,1536,2048,3072,4096,6144" textline " SRAM " bitfld.long 0x0 14. " RE ,Ready Enable" "disable,enable" bitfld.long 0x0 8.--13. " TWT ,Transfer Wait Timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 7. " CST ,Chip Select On Timing" "address,delayed" bitfld.long 0x0 6. " OET ,Output Enable On Timing" "select,delayed" textline " " bitfld.long 0x0 18. " SLF ,Sequential Line Fill" "off,one" bitfld.long 0x0 17. " BME ,Burst Mode Enable" "off,on" bitfld.long 0x0 5. " WBN ,Write Byte Enable On Timing" "select,delayed" bitfld.long 0x0 4. " WBF ,Write Byte Enable Off Timing" "select,before" bitfld.long 0x0 0x1--0x3 " TH ,Transfer Hold" "0,1,2,3,4,5,6,7" group dcr:0x85--0x85 "Bank 5" copy group dcr:0x86--0x86 "Bank 6" copy group dcr:0x87--0x87 "Bank 7" copy tree.end tree "DMA" group dcr:0x0e0--0x0e0 "DMA Status" line.long 0x0 "DMASR,DMA Status Register" bitfld.long 0x0 31. "CS0 ,Channel 0 Terminal Count Status" "no,yes" bitfld.long 0x0 27. " TS0 ,Channel 0 End of Transfer Status" "no,yes" bitfld.long 0x0 23. " RI0 ,Channel 0 Error Status" "ok,error" bitfld.long 0x0 18. " IR0 ,Internal DMA Request Channel 0" "no,yes" bitfld.long 0x0 14. " ER0 ,External DMA Request Channel 0" "no,yes" bitfld.long 0x0 10. " CB0 ,Channel 0 Busy" "no,yes" bitfld.long 0x0 19. " CT0 ,Chained Transfer on Channel 0" "no,yes" textline " " bitfld.long 0x0 30. " CS1 ,Channel 1 Terminal Count Status" "no,yes" bitfld.long 0x0 26. " TS1 ,Channel 1 End of Transfer Status" "no,yes" bitfld.long 0x0 22. " RI1 ,Channel 1 Error Status" "ok,error" bitfld.long 0x0 17. " IR1 ,Internal DMA Request Channel 1" "no,yes" bitfld.long 0x0 13. " ER1 ,External DMA Request Channel 1" "no,yes" bitfld.long 0x0 9. " CB1 ,Channel 1 Busy" "no,yes" bitfld.long 0x0 6. " CT1 ,Chained Transfer on Channel 1" "no,yes" textline " " bitfld.long 0x0 29. " CS2 ,Channel 2 Terminal Count Status" "no,yes" bitfld.long 0x0 25. " TS2 ,Channel 2 End of Transfer Status" "no,yes" bitfld.long 0x0 21. " RI2 ,Channel 2 Error Status" "ok,error" bitfld.long 0x0 16. " IR2 ,Internal DMA Request Channel 2" "no,yes" bitfld.long 0x0 12. " ER2 ,External DMA Request Channel 2" "no,yes" bitfld.long 0x0 8. " CB2 ,Channel 2 Busy" "no,yes" bitfld.long 0x0 5. " CT2 ,Chained Transfer on Channel 2" "no,yes" textline " " bitfld.long 0x0 28. " CS3 ,Channel 3 Terminal Count Status" "no,yes" bitfld.long 0x0 24. " TS3 ,Channel 3 End of Transfer Status" "no,yes" bitfld.long 0x0 20. " RI3 ,Channel 3 Error Status" "ok,error" bitfld.long 0x0 15. " IR3 ,Internal DMA Request Channel 3" "no,yes" bitfld.long 0x0 11. " ER3 ,External DMA Request Channel 3" "no,yes" bitfld.long 0x0 7. " CB3 ,Channel 3 Busy" "no,yes" bitfld.long 0x0 4. " CT3 ,Chained Transfer on Channel 3" "no,yes" group dcr:0x0c0--0x0c4 "DMA 0" line.long 0x0 "DMACR,DMA Channel Control Register" bitfld.long 0x0 31. "CE ,Channel Enable" "no,yes" bitfld.long 0x0 30. " CIE ,Channel Interrupt Enable" "no,yes" bitfld.long 0x0 29. " TD ,Transfer Direction" "mem to per,per to mem" bitfld.long 0x0 28. " PL ,Peripheral Location" "external,inside" bitfld.long 0x0 26.--27. " PW ,Peripheral Width" "8-bit,16-bit,32-bit,res" bitfld.long 0x0 25. " DAI ,Destination Address Increment" "hold,inc" textline " " bitfld.long 0x0 24. " SAI ,Source Address Increment" "hold,inc" bitfld.long 0x0 23. " CP ,Channel Priority" "low,high" bitfld.long 0x0 21.--22. " TM ,Transfer Mode" "bufferd,fly-by,sw mem->mem,hw mem->mem" bitfld.long 0x0 9. " ETD ,End of Transfer / Terminal Count" "eot,tc" bitfld.long 0x0 8. " TCE ,Terminal Count Enable" "no,yes" bitfld.long 0x0 7. " CH ,Chaining Enable" "no,yes" textline " " bitfld.long 0x0 6. " BME ,Burst Mode Enable" "no,yes" bitfld.long 0x0 5. " ECE ,EOT Chain Mode Enable" "stop,chain" bitfld.long 0x0 4. " TCD ,TC Chain Mode Disable" "chain,dis" bitfld.long 0x0 19.--20. " PSC ,Peripheral Setup Cycles" "0,1,2,3" bitfld.long 0x0 13.--18. " PWC ,Peripheral Wait Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 10.--12. " PHC ,Peripheral Hold Cycles" "0,1,2,3,4,5,6,7" line.long 0x4 "DMACT,DMA Count Register" line.long 0x8 "DMADA,DMA Destination Address Register" line.long 12. "DMASA,DMA Source Address Register" line.long 16. "DMACC,DMA Chained Count" group dcr:0x0c8--0x0cc "DMA 1" copy group dcr:0x0d0--0x0d4 "DMA 2" copy group dcr:0x0d8--0x0dc "DMA 3" copy tree.end tree "Exception and Interrupts" group dcr:0x42--0x42 "External Interrupt" line.long 0x0 "EXIER,External Interrupt Enable Register" bitfld.long 0x0 31. "CIE ,Critical Interrupt Enable" "disable,enable" bitfld.long 0x0 27. " SRIE ,Serial Port Receiver Interrupt Enable" "disable,enable" bitfld.long 0x0 26. " STIE ,Serial Port Transmitter Interrupt Enable" "disable,enable" bitfld.long 0x0 25. " JRIE ,JTAG Serial Port Receiver Interrupt Enable" "disable,enable" bitfld.long 0x0 24. " JTIE ,JTAG Serial Port Transmitter Interrupt Enable" "disable,enable" textline " " bitfld.long 0x0 23. " D0IE ,DMA Channel 0 Interrupt Enable" "disable,enable" bitfld.long 0x0 22. " D1IE ,DMA Channel 1 Interrupt Enable" "disable,enable" bitfld.long 0x0 21. " D2IE ,DMA Channel 2 Interrupt Enable" "disable,enable" bitfld.long 0x0 20. " D3IE ,DMA Channel 3 Interrupt Enable" "disable,enable" textline " " bitfld.long 0x0 4. " E0IE ,External Interrupt 0 Enable" "disable,enable" bitfld.long 0x0 3. " E1IE ,External Interrupt 1 Enable" "disable,enable" bitfld.long 0x0 2. " E2IE ,External Interrupt 2 Enable" "disable,enable" bitfld.long 0x0 1. " E3IE ,External Interrupt 3 Enable" "disable,enable" bitfld.long 0x0 0. " E4IE ,External Interrupt 4 Enable" "disable,enable" group dcr:0x40--0x40 line.long 0x0 "EXISR,External Interrupt Status Register" eventfld.long 0x0 31. "CIS ,Critical Interrupt Status" "wait,pending" eventfld.long 0x0 27. " SRIS ,Serial Port Receiver Interrupt Status" "wait,pending" eventfld.long 0x0 26. " STIS ,Serial Port Transmitter Interrupt Status" "wait,pending" eventfld.long 0x0 25. " JRIS ,JTAG Serial Port Receiver Interrupt Status" "wait,pending" eventfld.long 0x0 24. " JTIS ,JTAG Serial Port Transmitter Interrupt Status" "wait,pending" textline " " eventfld.long 0x0 23. " D0IS ,DMA Channel 0 Interrupt Status" "wait,pending" eventfld.long 0x0 22. " D1IS ,DMA Channel 1 Interrupt Status" "wait,pending" eventfld.long 0x0 21. " D2IS ,DMA Channel 2 Interrupt Status" "wait,pending" eventfld.long 0x0 20. " D3IS ,DMA Channel 3 Interrupt Status" "wait,pending" textline " " eventfld.long 0x0 4. " E0IS ,External Interrupt 0 Status" "wait,pending" eventfld.long 0x0 3. " E1IS ,External Interrupt 1 Status" "wait,pending" eventfld.long 0x0 2. " E2IS ,External Interrupt 2 Status" "wait,pending" eventfld.long 0x0 1. " E3IS ,External Interrupt 3 Status" "wait,pending" eventfld.long 0x0 0. " E4IS ,External Interrupt 4 Status" "wait,pending" group dcr:0x0a0--0x0a0 "Input / Output Configuration" line.long 0x0 "IOCR,Input/Output Configuration Register" bitfld.long 0x0 31. "E0T ,External Interrupt 0 Triggering" "level,edge" bitfld.long 0x0 29. " E1T ,External Interrupt 1 Triggering" "level,edge" bitfld.long 0x0 27. " E2T ,External Interrupt 2 Triggering" "level,edge" bitfld.long 0x0 25. " E3T ,External Interrupt 3 Triggering" "level,edge" bitfld.long 0x0 23. " E4T ,External Interrupt 4 Triggering" "level,edge" textline " " bitfld.long 0x0 30. " E0L ,External Interrupt 0 Active Level" "negative,positive" bitfld.long 0x0 28. " E1L ,External Interrupt 1 Active Level" "negative,positive" bitfld.long 0x0 26. " E2L ,External Interrupt 2 Active Level" "negative,positive" bitfld.long 0x0 24. " E3L ,External Interrupt 3 Active Level" "negative,positive" bitfld.long 0x0 22. " E4L ,External Interrupt 4 Active Level" "negative,positive" textline " " bitfld.long 0x0 0x3--0x4 " RDM ,Real-Time Debug Mode" "disabled,bus,trace,reserved" bitfld.long 0x0 2. " TCS ,Timer Clock Source" "sysclk,timerclk" bitfld.long 0x0 1. " SCS ,Serial Port Clock Source" "sysclk,serclk" bitfld.long 0x0 0. " SPC ,Serial Port Configuration" "dsr/dtr,cts/rts" textline " " bitfld.long 0x0 14. " 2CX ,Clock Doubled Core Enable (only 403GCX)" "disabled,enabled" group spr:0x3d4--0x3d5 "Exception" line.long 0x0 "ESR,Exception Syndrome Register" bitfld.long 0x0 31. "IMCP ,Instruction Machine Check - Protection" "not occur,occured" bitfld.long 0x0 30. " IMCN ,Instruction Machine Check - Non configured" "not occur,occured" bitfld.long 0x0 29. " IMCB ,Instruction Machine Check - Bus Error" "not occur,occured" bitfld.long 0x0 28. " IMCT ,Instruction Machine Check - Timeout" "not occur,occered" textline " " bitfld.long 0x0 27. " PEI ,Program Exception - Illegal" "not occur,occured" bitfld.long 0x0 26. " PEP ,Program Exception - Privileged" "not occur,occured" bitfld.long 0x0 25. " PET ,Program Exception - Trap" "not occur,occured" line.long 0x4 "DEAR,Data Exception Address Register" group dcr:0x90--0x91 "External Bus" line.long 0x4 "BESR,Bus Error Syndrome Register" bitfld.long 0x4 31. "DSES ,Data-Side Error Status" "no,yes" bitfld.long 0x4 30. " DMES ,DMA Error Status" "no,yes" bitfld.long 0x4 29. " RWS ,Read/Write Status" "write,read" bitfld.long 0x4 27.--28. " ET ,Error Type" "protection violation,non-configured bank,bus error pin,bus time-out" line.long 0x0 "BEAR,Bus Error Address Register" tree.end tree "Timer" group spr:0x3d8--0x3d8 line.long 0x0 "TSR,Timer Status Register" ;clear bits by overwriting with 1 bitfld.long 0x0 30. "WIS ,Watchdog Interrupt Status" "wait,pending" bitfld.long 0x0 28.--29. " WRS ,Watchdog Reset Status" "no,core,chip,system" bitfld.long 0x0 27. " PIS ,PIT Interrupt Status" "wait,pending" bitfld.long 0x0 26. " FIS ,FIT Interrupt Status" "wait,pending" group spr:0x3da--0x3dd line.long 0x0 "TCR,Timer Control Register" bitfld.long 0x0 30.--31. "WP ,Watchdog Period" "2^17,2^21,2^25,2^29" bitfld.long 0x0 28.--29. " WRC ,Watchdog Reset Control" "off,core,chip,system" bitfld.long 0x0 27. " WIE ,Watchdog Interrupt Enable" "disable,enable" textline " " bitfld.long 0x0 26. " PIE ,PIT Interrupt Enable" "disable,enable" bitfld.long 0x0 24.--25. " FP ,FIT Period" "2^9,2^13,2^17,2^21" bitfld.long 0x0 23. " FIE ,FIT Interrupt Enable" "disable,enable" bitfld.long 0x0 22. " ARE ,Auto Reload Enable" "disable,enable" line.long 0x4 "PIT,Programmable Intervall Timer" line.long 0x8 "TBHI,Timer Base High" line.long 12. "TBLO,Timer Base Low" tree.end tree "Serial Port" group d:0x40000000--0x40000000 line.byte 0x0 "SPLS,Line Status Register" bitfld 0x0 0x7 "RBR ,Receive Buffer Ready" "empty,full" bitfld 0x0 0x6 " FE ,Framing Error" "no error,error" bitfld 0x0 0x5 " OE ,Overrun Error" "no error,error" bitfld 0x0 0x4 " PE ,Parity Error" "no error,error" bitfld 0x0 0x3 " LB ,Line Break" "no break,break" textline " " bitfld 0x0 0x2 " TBR ,Transmit Buffer Ready" "full,empty" bitfld 0x0 0x1 " TSR ,Transmitter Shift Register Ready" "full,empty" group d:0x40000002--0x40000002 line.byte 0x0 "SPHS,Handshake Status Register" bitfld 0x0 0x7 "DIS ,DSR Input Inactive Error" "active,inactive" bitfld 0x0 0x6 " CS ,CTS Input Inactive Error" "active,inactive" group d:0x40000006--0x40000008 line.byte 0x0 "SPCTL,Control Register" bitfld 0x0 0x6--0x7 "LM ,Loopback Modes" "normal,internal,automatic,res" bitfld 0x0 0x5 " DTR ,Data Terminal Ready" "inactive,active" bitfld 0x0 0x4 " RTS ,Request to Send" "inactive,active" bitfld 0x0 0x3 " DB ,Data Bits" "7,8" textline " " bitfld 0x0 0x2 " PE ,Parity Enable" "disabled,enabled" bitfld 0x0 0x1 " PTY ,Parity" "even,odd" bitfld 0x0 0x0 " SB ,Stop Bits" "1,2" line.byte 0x1 "SPRC,Receiver Command Register" bitfld 0x1 0x7 "ER ,Enable Receiver" "disabled,enabled" bitfld 0x1 0x5--0x6 " DME ,DMA Mode and Interrupt Enable" "disabled,rbr int,dma 2,dma 3" bitfld 0x1 0x4 " EIE ,Error Interrupt Enable" "disabled,enabled" bitfld 0x1 0x3 " PME ,Pause Mode Enable" "software,hardware" line.byte 0x2 "SPTC,Transmitter Command Register" bitfld 0x2 0x7 "ET ,Enable Transmitter" "disabled,enabled" bitfld 0x2 0x5--0x6 " DME ,DMA Mode and Interrupt Enable" "disabled,tbr int,dma 2,dma 3" bitfld 0x2 0x4 " TIE ,Transmitter Empty Interrupt Enable" "disabled,enabled" bitfld 0x2 0x3 " EIE ,Transmitter Error Interrupt Enable" "disabled,enabled" textline " " bitfld 0x2 0x2 " SPE ,Stop/Pause on CTS Inactive" "pause mode,stop mode" bitfld 0x2 0x1 " TB ,Transmit Break" "disabled,enabled" hide.byte 0x3 "SPRB,Receive Buffer" in hide.byte 0x3 "SPTB,Transmit Buffer" group d:0x40000004--0x40000005 line.byte 0x0 "BRDH,Baud Rate Divisor High" line.byte 0x1 "BRDL,Baud Rate Divisor Low" tree.end tree "Cache" group spr:0x3ba--0x3ba " 00000000 08000000 10000000 18000000 20000000 28000000 30000000 38000000" line.long 0x0 "DCWR,Data Cache Copy-back/Write-thru Register" textline " 00000000 " bitfld.long 0x0 31. " " " copy, write" bitfld.long 0x0 30. " " " copy, write" bitfld.long 0x0 29. " " " copy, write" bitfld.long 0x0 28. " " " copy, write" bitfld.long 0x0 27. " " " copy, write" bitfld.long 0x0 26. " " " copy, write" bitfld.long 0x0 25. " " " copy, write" bitfld.long 0x0 24. " " " copy, write" textline " 40000000 " bitfld.long 0x0 23. " " " copy, write" bitfld.long 0x0 22. " " " copy, write" bitfld.long 0x0 21. " " " copy, write" bitfld.long 0x0 20. " " " copy, write" bitfld.long 0x0 19. " " " copy, write" bitfld.long 0x0 18. " " " copy, write" bitfld.long 0x0 17. " " " copy, write" bitfld.long 0x0 16. " " " copy, write" textline " 80000000 " bitfld.long 0x0 15. " " " copy, write" bitfld.long 0x0 14. " " " copy, write" bitfld.long 0x0 13. " " " copy, write" bitfld.long 0x0 12. " " " copy, write" bitfld.long 0x0 11. " " " copy, write" bitfld.long 0x0 10. " " " copy, write" bitfld.long 0x0 9. " " " copy, write" bitfld.long 0x0 8. " " " copy, write" textline " c0000000 " bitfld.long 0x0 7. " " " copy, write" bitfld.long 0x0 6. " " " copy, write" bitfld.long 0x0 5. " " " copy, write" bitfld.long 0x0 4. " " " copy, write" bitfld.long 0x0 3. " " " copy, write" bitfld.long 0x0 2. " " " copy, write" bitfld.long 0x0 1. " " " copy, write" bitfld.long 0x0 0. " " " copy, write" group spr:0x3fa--0x3fb line.long 0x0 "DCCR,Data Cache Cacheability Register" textline " 00000000 " bitfld.long 0x0 31. " " " no, enable" bitfld.long 0x0 30. " " " no, enable" bitfld.long 0x0 29. " " " no, enable" bitfld.long 0x0 28. " " " no, enable" bitfld.long 0x0 27. " " " no, enable" bitfld.long 0x0 26. " " " no, enable" bitfld.long 0x0 25. " " " no, enable" bitfld.long 0x0 24. " " " no, enable" textline " 40000000 " bitfld.long 0x0 23. " " " no, enable" bitfld.long 0x0 22. " " " no, enable" bitfld.long 0x0 21. " " " no, enable" bitfld.long 0x0 20. " " " no, enable" bitfld.long 0x0 19. " " " no, enable" bitfld.long 0x0 18. " " " no, enable" bitfld.long 0x0 17. " " " no, enable" bitfld.long 0x0 16. " " " no, enable" textline " 80000000 " bitfld.long 0x0 15. " " " no, enable" bitfld.long 0x0 14. " " " no, enable" bitfld.long 0x0 13. " " " no, enable" bitfld.long 0x0 12. " " " no, enable" bitfld.long 0x0 11. " " " no, enable" bitfld.long 0x0 10. " " " no, enable" bitfld.long 0x0 9. " " " no, enable" bitfld.long 0x0 8. " " " no, enable" textline " c0000000 " bitfld.long 0x0 7. " " " no, enable" bitfld.long 0x0 6. " " " no, enable" bitfld.long 0x0 5. " " " no, enable" bitfld.long 0x0 4. " " " no, enable" bitfld.long 0x0 3. " " " no, enable" bitfld.long 0x0 2. " " " no, enable" bitfld.long 0x0 1. " " " no, enable" bitfld.long 0x0 0. " " " no, enable" line.long 0x4 "ICCR,Instruction Cache Cacheability Register" textline " 00000000 " bitfld.long 0x4 31. " " " no, enable" bitfld.long 0x4 30. " " " no, enable" bitfld.long 0x4 29. " " " no, enable" bitfld.long 0x4 28. " " " no, enable" bitfld.long 0x4 27. " " " no, enable" bitfld.long 0x4 26. " " " no, enable" bitfld.long 0x4 25. " " " no, enable" bitfld.long 0x4 24. " " " no, enable" textline " 40000000 " bitfld.long 0x4 23. " " " no, enable" bitfld.long 0x4 22. " " " no, enable" bitfld.long 0x4 21. " " " no, enable" bitfld.long 0x4 20. " " " no, enable" bitfld.long 0x4 19. " " " no, enable" bitfld.long 0x4 18. " " " no, enable" bitfld.long 0x4 17. " " " no, enable" bitfld.long 0x4 16. " " " no, enable" textline " 80000000 " bitfld.long 0x4 15. " " " no, enable" bitfld.long 0x4 14. " " " no, enable" bitfld.long 0x4 13. " " " no, enable" bitfld.long 0x4 12. " " " no, enable" bitfld.long 0x4 11. " " " no, enable" bitfld.long 0x4 10. " " " no, enable" bitfld.long 0x4 9. " " " no, enable" bitfld.long 0x4 8. " " " no, enable" textline " c0000000 " bitfld.long 0x4 7. " " " no, enable" bitfld.long 0x4 6. " " " no, enable" bitfld.long 0x4 5. " " " no, enable" bitfld.long 0x4 4. " " " no, enable" bitfld.long 0x4 3. " " " no, enable" bitfld.long 0x4 2. " " " no, enable" bitfld.long 0x4 1. " " " no, enable" bitfld.long 0x4 0. " " " no, enable" group spr:0x3B9--0x3B9 line.long 0x0 "SGR,Storage Guarded Register" textline " 00000000 " bitfld.long 0x0 31. " " " no, guarded" bitfld.long 0x0 30. " " " no, guarded" bitfld.long 0x0 29. " " " no, guarded" bitfld.long 0x0 28. " " " no, guarded" bitfld.long 0x0 27. " " " no, guarded" bitfld.long 0x0 26. " " " no, guarded" bitfld.long 0x0 25. " " " no, guarded" bitfld.long 0x0 24. " " " no, guarded" textline " 40000000 " bitfld.long 0x0 23. " " " no, guarded" bitfld.long 0x0 22. " " " no, guarded" bitfld.long 0x0 21. " " " no, guarded" bitfld.long 0x0 20. " " " no, guarded" bitfld.long 0x0 19. " " " no, guarded" bitfld.long 0x0 18. " " " no, guarded" bitfld.long 0x0 17. " " " no, guarded" bitfld.long 0x0 16. " " " no, guarded" textline " 80000000 " bitfld.long 0x0 15. " " " no, guarded" bitfld.long 0x0 14. " " " no, guarded" bitfld.long 0x0 13. " " " no, guarded" bitfld.long 0x0 12. " " " no, guarded" bitfld.long 0x0 11. " " " no, guarded" bitfld.long 0x0 10. " " " no, guarded" bitfld.long 0x0 9. " " " no, guarded" bitfld.long 0x0 8. " " " no, guarded" textline " c0000000 " bitfld.long 0x0 7. " " " no, guarded" bitfld.long 0x0 6. " " " no, guarded" bitfld.long 0x0 5. " " " no, guarded" bitfld.long 0x0 4. " " " no, guarded" bitfld.long 0x0 3. " " " no, guarded" bitfld.long 0x0 2. " " " no, guarded" bitfld.long 0x0 1. " " " no, guarded" bitfld.long 0x0 0. " " " no, guarded" tree.end tree "Protection" group spr:0x3fc--0x3fc "Real-mode Access Protection Registers" line.long 0x0 "PBL1,Protection Bound Lower 1" group spr:0x3fe--0x3fe line.long 0x0 "PBL2,Protection Bound Lower 2" group spr:0x3fd--0x3fd line.long 0x0 "PBU1,Protection Bound Upper 1" group spr:0x3ff--0x3ff line.long 0x0 "PBU2,Protection Bound Upper 2" GROUP SPR:0x3B1--0x3B1 "Virtual-mode Access Protection Registers" LINE.LONG 0x0 "PID,Process ID" GROUP SPR:0x3B0--0x3B0 LINE.LONG 0x0 "ZPR,Zone Protection Register" BITFLD.LONG 0x0 30.--31. "Z00 ,Zone 0" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 28.--29. " Z01 ,Zone 1" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 26.--27. " Z02 ,Zone 2" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 24.--25. " Z03 ,Zone 3" "no access,EX | WR,EX | WR, EX & WR" TEXTLINE " " BITFLD.LONG 0x0 22.--23. "Z04 ,Zone 4" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 20.--21. " Z05 ,Zone 5" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 18.--19. " Z06 ,Zone 6" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 16.--17. " Z07 ,Zone 7" "no access,EX | WR,EX | WR, EX & WR" TEXTLINE " " BITFLD.LONG 0x0 14.--15. "Z08 ,Zone 8" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 12.--13. " Z09 ,Zone 9" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 10.--11. " Z10 ,Zone 10" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 08.--09. " Z11 ,Zone 11" "no access,EX | WR,EX | WR, EX & WR" TEXTLINE " " BITFLD.LONG 0x0 06.--07. "Z12 ,Zone 12" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 04.--05. " Z13 ,Zone 13" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 02.--03. " Z14 ,Zone 14" "no access,EX | WR,EX | WR, EX & WR" BITFLD.LONG 0x0 00.--01. " Z15 ,Zone 15" "no access,EX | WR,EX | WR, EX & WR" group spr:0x3fc--0x3fc "Real-mode Access Protection Registers" line.long 0x0 "PBL1,Protection Bound Lower 1" group spr:0x3fe--0x3fe line.long 0x0 "PBL2,Protection Bound Lower 2" group spr:0x3fd--0x3fd line.long 0x0 "PBU1,Protection Bound Upper 1" group spr:0x3ff--0x3ff line.long 0x0 "PBU2,Protection Bound Upper 2" tree.end tree "Debugging" group spr:0x3f2--0x3f2 line.long 0x0 "DBCR,Debug Control Register" bitfld.long 0x0 31. "EDM ,Ext Debug" "dis,en" bitfld.long 0x0 30. " IDM ,Int Debug" "dis,en" bitfld.long 0x0 28.--29. " RST ,Reset" "no,core,chip,system" textline " " bitfld.long 0x0 27. " IC ,Instr Compl DE" "dis,en" bitfld.long 0x0 26. " BT ,Branch Taken DE" "dis,en" bitfld.long 0x0 25. " EDE ,Exeption DE" "dis,en" bitfld.long 0x0 24. " TDE ,Trap DE" "dis,en" bitfld.long 0x0 18. " FT ,Freeze Timers on DE" "run,freeze" textline " " bitfld.long 0x0 17. " IA1 ,Instr Comp 1" "dis,en" bitfld.long 0x0 16. " IA2 ,Instr Comp 2" "dis,en" textline " " bitfld.long 0x0 15. " D1R ,Data Comp 1 Read" "dis,en" bitfld.long 0x0 14. " D1W ,Data Comp 1 Write" "dis,en" bitfld.long 0x0 12.--13. " D1S ,Data Comp 1 Size" "byte,half-word,word,quad-word" textline " " bitfld.long 0x0 11. " D2R ,Data Comp 2 Read" "dis,en" bitfld.long 0x0 10. " D2W ,Data Comp 2 Write" "dis,en" bitfld.long 0x0 8.--9. " D2S ,Data Comp 2 Size" "byte,half-word,word,quad-word" textline " " bitfld.long 0x0 0x7 " TFI ,Trace Fifo Inhibit ?????" "dis,en" textline " " bitfld.long 0x0 0x6 " SBT ,Second Branch Taken Debug Event" "dis,en" bitfld.long 0x0 0x5 " SED ,Second Exception Debug Event" "dis,en" bitfld.long 0x0 0x4 " STD ,Second Trap Debug Event" "dis,en" bitfld.long 0x0 0x3 " SIA ,Second Instruction Address Compare Enable" "dis,en" bitfld.long 0x0 0x2 " SDA ,Second Data Address Compare Enable" "dis,en" bitfld.long 0x0 0x1 " JOI ,Outb Int" "dis,en" bitfld.long 0x0 0x0 " JLL ,Inb Int" "dis,en" group spr:0x3f0--0x3f0 line.long 0x0 "DBSR,Debug Status Register" bitfld.long 0x0 31. "IC ,Instr Compl DE" "wait,occur" bitfld.long 0x0 30. " BT ,Branch Taken DE" "wait,occur" bitfld.long 0x0 29. " EDE ,Exeption DE" "wait,occur" bitfld.long 0x0 28. " TDE ,Trap DE" "wait,occur" bitfld.long 0x0 27. " UDE ,Uncond DE" "wait,occur" textline " " bitfld.long 0x0 26. " IA1 ,Instr Comp 1" "wait,occur" bitfld.long 0x0 25. " IA2 ,Instr Comp 2" "wait,occur" bitfld.long 0x0 24. " D1R ,Data Comp 1 Read" "wait,occur" bitfld.long 0x0 23. " D1W ,Data Comp 1 Write" "wait,occur" bitfld.long 0x0 22. " D2R ,Data Comp 2 Read" "wait,occur" bitfld.long 0x0 21. " D2W ,Data Comp 2 Write" "wait,occur" textline " " bitfld.long 0x0 20. " IDE ,Imprecise DE" "wait,occur" bitfld.long 0x0 0x8--0x9 " MRR ,Most Recent RESET" "no,core,chip,system" bitfld.long 0x0 0x2 " JIF ,Inb full" "empty,full" bitfld.long 0x0 0x1 " JIO ,Inb overrun" "no,over" bitfld.long 0x0 0x0 " JOE ,Outb Empty" "full,empty" group spr:0x3f6--0x3f7 line.long 0x0 "DAC1,Data Address Compare 1" line.long 0x4 "DAC2,Data Address Compare 2" group spr:0x3f4--0x3f5 line.long 0x0 "IAC1,Instruction Address Compare 1" line.long 0x4 "IAC2,Instruction Address Compare 2" tree.end