; -------------------------------------------------------------------------------- ; @Title: PPC401GF on chip peripherals and SPRs ; @Changelog: 2006-06-26 HST initial version ; @Author: HST ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: per401gf.per 6819 2016-04-12 09:30:10Z sphilipp $ config 16. 8. tree "Processor Version" group spr:0x11f--0x11f "Processor Version" line.long 0x0 "PVR,Prozessor Version Register" hexmask.long 0x0 20.--31. 0x1 "FAM ,Prozessor Family" bitfld.long 0x0 16.--19. " MEM ,Family Member" "403,401GF,res,res,res,res,res,res,res,res,res,res,res,res,res,res" textline " " hexmask.long 0x0 8.--15. 0x0 " CR ,Core Revision" hexmask.long 0x0 0.--7. 0x0 " CHIP ,Chip Revision" tree.end tree "Bus Interface" group dcr:0x0a0--0x0a0 "Bus Input/Output Configuration" line.long 0x0 "IOCR,Input/Output Configuration Register" bitfld.long 0x0 31. "CIL ,Critical Interrupt Level" "Active LOW,Active HIGH" bitfld.long 0x0 30. " IL ,Interrupt Level" "Active LOW,Active HIGH" textline " " bitfld.long 0x0 8. " MCA ,MemClk Alignment" "aligned,unaligned" bitfld.long 0x0 0.--1. " EBS ,External Bus Speed" "MemClk=intern,MemClk=1/2int.,MemClk=1/3int.,MemClk=1/4int." group dcr:0x80--0x80 "Bus Region 0" line.long 0x0 "BRCR,Bus Region Control Register " ; hexmask.long 0 24.--31. 100000 "BAS ,Base Address (Bit 1-3 = 111, since SRAM)" bitfld.long 0x0 4.--6. "TH ,Transfer Hold" "res,1-cycle,2-cycles,3-cycles,4-cycles,5-cycles,6-cycles,7-cycless" bitfld.long 0x0 3. " MB ,Maximum burst of four beats" "max. burst=4,cont. after trans." textline " " bitfld.long 0x0 0.--1. " BW ,Bus Width" "8-bit,16-bit,32-bit,res" bitfld.long 0x0 2. " SLF ,Sequential Line Fills" "Target Word First,Sequential" group dcr:0x81--0x81 "Bus Region 1" copy group dcr:0x82--0x82 "Bus Region 2" copy group dcr:0x83--0x83 "Bus Region 3" copy group dcr:0x84--0x84 "Bus Region 4" copy group dcr:0x85--0x85 "Bus Region 5" copy group dcr:0x86--0x86 "Bus Region 6" copy group dcr:0x87--0x87 "Bus Region 7" copy tree.end tree "Exception and Interrupts" group dcr:0x0a0--0x0a0 "Bus Input/Output Configuration" line.long 0x0 "IOCR,Input/Output Configuration Register" bitfld.long 0x0 31. "CIL ,Critical Interrupt Level" "Active LOW,Active HIGH" bitfld.long 0x0 30. " IL ,Interrupt Level" "Active LOW,Active HIGH" textline " " bitfld.long 0x0 8. " MCA ,MemClk Alignment" "aligned,unaligned" bitfld.long 0x0 0.--1. " EBS ,External Bus Speed" "MemClk=intern,MemClk=1/2int.,MemClk=1/3int.,MemClk=1/4int." group spr:0x3D4--0x3D6 "Exception" line.long 0x0 "ESR,Exception Syndrome Register" bitfld.long 0x0 31. "MCI ,Machine Check - Instruction" "not occur,occured" bitfld.long 0x0 27. " PIL ,Program Exception - Illegal" "not occur,occured" bitfld.long 0x0 26. " PPR ,Program Exception - Privileged" "not occur,occured" bitfld.long 0x0 25. " PTR ,Program Exception - Trap" "not occur,occered" textline " " bitfld.long 0x0 20.--21. " DLK ,Data Storage Exception - lock fault" "not occur,occured,?..." bitfld.long 0x0 19. " PAU ,Program Exception - auxiliary processor" "not occur,occured" line.long 0x4 "DEAR,Data Exception Address Register" line.long 0x8 "EVPR,Exeption Vector Prefix Register" group dcr:0x90--0x91 "External Bus" line.long 0x4 "BESR,Bus Error Syndrome Register" bitfld.long 0x4 28.--30. "IET ,Instruction Side Error Type" "no,res,res,res,res,res,yes,res" bitfld.long 0x4 27. " DRWS ,Data Read/Write Status" "w-error,r-error" bitfld.long 0x4 24.--26. " DET ,Data Side Error Type" "no,res,res,res,res,res,yes,res" line.long 0x0 "BEAR,Bus Error Address Register" tree.end tree "Timer" group spr:0x3d8--0x3d8 line.long 0x0 "TSR,Timer Status Register" ;clear bits by overwriting with 1 bitfld.long 0x0 30. "WIS ,Watchdog Interrupt Status" "wait,pending " bitfld.long 0x0 28.--29. " WRS ,Watchdog Reset Status" "no,core,chip,system" bitfld.long 0x0 27. " PIS ,PIT Interrupt Status" "wait,pending" bitfld.long 0x0 26. " FIS ,FIT Interrupt Status" "wait,pending" group spr:0x3da--0x3db line.long 0x0 "TCR,Timer Control Register" bitfld.long 0x0 30.--31. "WP ,Watchdog Period" "2^17,2^21 ,2^25,2^29" bitfld.long 0x0 28.--29. " WRC ,Watchdog Reset Control" "off,core,chip,system" bitfld.long 0x0 27. " WIE ,Watchdog Interrupt Enable" "disable,enable" textline " " bitfld.long 0x0 26. " PIE ,PIT Interrupt Enable" "disable ,enable" bitfld.long 0x0 24.--25. " FP ,FIT Period" "2^9 ,2^13,2^17,2^21" bitfld.long 0x0 23. " FIE ,FIT Interrupt Enable" "disable,enable" line.long 0x4 "PIT,Programmable Intervall Timer" group spr:0x11c--0x11d line.long 0x4 "TBU,Timer Base Upper" hexmask.long 0x0 0.--31. 0x0 "TBL,Timer Base Lower" tree.end tree "Cache" group spr:0x3ba--0x3ba " 00000000 08000000 10000000 18000000 20000000 28000000 30000000 38000000" line.long 0x0 "DCWR,Data Cache Copy-back/Write-thru Register" textline " 00000000 " bitfld.long 0x0 31. " " " copy, write" bitfld.long 0x0 30. " " " copy, write" bitfld.long 0x0 29. " " " copy, write" bitfld.long 0x0 28. " " " copy, write" bitfld.long 0x0 27. " " " copy, write" bitfld.long 0x0 26. " " " copy, write" bitfld.long 0x0 25. " " " copy, write" bitfld.long 0x0 24. " " " copy, write" textline " 40000000 " bitfld.long 0x0 23. " " " copy, write" bitfld.long 0x0 22. " " " copy, write" bitfld.long 0x0 21. " " " copy, write" bitfld.long 0x0 20. " " " copy, write" bitfld.long 0x0 19. " " " copy, write" bitfld.long 0x0 18. " " " copy, write" bitfld.long 0x0 17. " " " copy, write" bitfld.long 0x0 16. " " " copy, write" textline " 80000000 " bitfld.long 0x0 15. " " " copy, write" bitfld.long 0x0 14. " " " copy, write" bitfld.long 0x0 13. " " " copy, write" bitfld.long 0x0 12. " " " copy, write" bitfld.long 0x0 11. " " " copy, write" bitfld.long 0x0 10. " " " copy, write" bitfld.long 0x0 9. " " " copy, write" bitfld.long 0x0 8. " " " copy, write" textline " c0000000 " bitfld.long 0x0 7. " " " copy, write" bitfld.long 0x0 6. " " " copy, write" bitfld.long 0x0 5. " " " copy, write" bitfld.long 0x0 4. " " " copy, write" bitfld.long 0x0 3. " " " copy, write" bitfld.long 0x0 2. " " " copy, write" bitfld.long 0x0 1. " " " copy, write" bitfld.long 0x0 0. " " " copy, write" group spr:0x3fa--0x3fb line.long 0x0 "DCCR,Data Cache Cacheability Register" textline " 00000000 " bitfld.long 0x0 31. " " " no, enable" bitfld.long 0x0 30. " " " no, enable" bitfld.long 0x0 29. " " " no, enable" bitfld.long 0x0 28. " " " no, enable" bitfld.long 0x0 27. " " " no, enable" bitfld.long 0x0 26. " " " no, enable" bitfld.long 0x0 25. " " " no, enable" bitfld.long 0x0 24. " " " no, enable" textline " 40000000 " bitfld.long 0x0 23. " " " no, enable" bitfld.long 0x0 22. " " " no, enable" bitfld.long 0x0 21. " " " no, enable" bitfld.long 0x0 20. " " " no, enable" bitfld.long 0x0 19. " " " no, enable" bitfld.long 0x0 18. " " " no, enable" bitfld.long 0x0 17. " " " no, enable" bitfld.long 0x0 16. " " " no, enable" textline " 80000000 " bitfld.long 0x0 15. " " " no, enable" bitfld.long 0x0 14. " " " no, enable" bitfld.long 0x0 13. " " " no, enable" bitfld.long 0x0 12. " " " no, enable" bitfld.long 0x0 11. " " " no, enable" bitfld.long 0x0 10. " " " no, enable" bitfld.long 0x0 9. " " " no, enable" bitfld.long 0x0 8. " " " no, enable" textline " c0000000 " bitfld.long 0x0 7. " " " no, enable" bitfld.long 0x0 6. " " " no, enable" bitfld.long 0x0 5. " " " no, enable" bitfld.long 0x0 4. " " " no, enable" bitfld.long 0x0 3. " " " no, enable" bitfld.long 0x0 2. " " " no, enable" bitfld.long 0x0 1. " " " no, enable" bitfld.long 0x0 0. " " " no, enable" line.long 0x4 "ICCR,Instruction Cache Cacheability Register" textline " 00000000 " bitfld.long 0x4 31. " " " no, enable" bitfld.long 0x4 30. " " " no, enable" bitfld.long 0x4 29. " " " no, enable" bitfld.long 0x4 28. " " " no, enable" bitfld.long 0x4 27. " " " no, enable" bitfld.long 0x4 26. " " " no, enable" bitfld.long 0x4 25. " " " no, enable" bitfld.long 0x4 24. " " " no, enable" textline " 40000000 " bitfld.long 0x4 23. " " " no, enable" bitfld.long 0x4 22. " " " no, enable" bitfld.long 0x4 21. " " " no, enable" bitfld.long 0x4 20. " " " no, enable" bitfld.long 0x4 19. " " " no, enable" bitfld.long 0x4 18. " " " no, enable" bitfld.long 0x4 17. " " " no, enable" bitfld.long 0x4 16. " " " no, enable" textline " 80000000 " bitfld.long 0x4 15. " " " no, enable" bitfld.long 0x4 14. " " " no, enable" bitfld.long 0x4 13. " " " no, enable" bitfld.long 0x4 12. " " " no, enable" bitfld.long 0x4 11. " " " no, enable" bitfld.long 0x4 10. " " " no, enable" bitfld.long 0x4 9. " " " no, enable" bitfld.long 0x4 8. " " " no, enable" textline " c0000000 " bitfld.long 0x4 7. " " " no, enable" bitfld.long 0x4 6. " " " no, enable" bitfld.long 0x4 5. " " " no, enable" bitfld.long 0x4 4. " " " no, enable" bitfld.long 0x4 3. " " " no, enable" bitfld.long 0x4 2. " " " no, enable" bitfld.long 0x4 1. " " " no, enable" bitfld.long 0x4 0. " " " no, enable" group spr:0x3B9--0x3B9 line.long 0x0 "SGR,Storage Guarded Register" textline " 00000000 " bitfld.long 0x0 31. " " " no, guarded" bitfld.long 0x0 30. " " " no, guarded" bitfld.long 0x0 29. " " " no, guarded" bitfld.long 0x0 28. " " " no, guarded" bitfld.long 0x0 27. " " " no, guarded" bitfld.long 0x0 26. " " " no, guarded" bitfld.long 0x0 25. " " " no, guarded" bitfld.long 0x0 24. " " " no, guarded" textline " 40000000 " bitfld.long 0x0 23. " " " no, guarded" bitfld.long 0x0 22. " " " no, guarded" bitfld.long 0x0 21. " " " no, guarded" bitfld.long 0x0 20. " " " no, guarded" bitfld.long 0x0 19. " " " no, guarded" bitfld.long 0x0 18. " " " no, guarded" bitfld.long 0x0 17. " " " no, guarded" bitfld.long 0x0 16. " " " no, guarded" textline " 80000000 " bitfld.long 0x0 15. " " " no, guarded" bitfld.long 0x0 14. " " " no, guarded" bitfld.long 0x0 13. " " " no, guarded" bitfld.long 0x0 12. " " " no, guarded" bitfld.long 0x0 11. " " " no, guarded" bitfld.long 0x0 10. " " " no, guarded" bitfld.long 0x0 9. " " " no, guarded" bitfld.long 0x0 8. " " " no, guarded" textline " c0000000 " bitfld.long 0x0 7. " " " no, guarded" bitfld.long 0x0 6. " " " no, guarded" bitfld.long 0x0 5. " " " no, guarded" bitfld.long 0x0 4. " " " no, guarded" bitfld.long 0x0 3. " " " no, guarded" bitfld.long 0x0 2. " " " no, guarded" bitfld.long 0x0 1. " " " no, guarded" bitfld.long 0x0 0. " " " no, guarded" group spr:0x3bb--0x3bb line.long 0x0 "SLER,Storage Little-Endian Register" textline " 00000000 " bitfld.long 0x0 31. " " " big, little" bitfld.long 0x0 30. " " " big, little" bitfld.long 0x0 29. " " " big, little" bitfld.long 0x0 28. " " " big, little" bitfld.long 0x0 27. " " " big, little" bitfld.long 0x0 26. " " " big, little" bitfld.long 0x0 25. " " " big, little" bitfld.long 0x0 24. " " " big, little" textline " 40000000 " bitfld.long 0x0 23. " " " big, little" bitfld.long 0x0 22. " " " big, little" bitfld.long 0x0 21. " " " big, little" bitfld.long 0x0 20. " " " big, little" bitfld.long 0x0 19. " " " big, little" bitfld.long 0x0 18. " " " big, little" bitfld.long 0x0 17. " " " big, little" bitfld.long 0x0 16. " " " big, little" textline " 80000000 " bitfld.long 0x0 15. " " " big, little" bitfld.long 0x0 14. " " " big, little" bitfld.long 0x0 13. " " " big, little" bitfld.long 0x0 12. " " " big, little" bitfld.long 0x0 11. " " " big, little" bitfld.long 0x0 10. " " " big, little" bitfld.long 0x0 9. " " " big, little" bitfld.long 0x0 8. " " " big, little" textline " c0000000 " bitfld.long 0x0 7. " " " big, little" bitfld.long 0x0 6. " " " big, little" bitfld.long 0x0 5. " " " big, little" bitfld.long 0x0 4. " " " big, little" bitfld.long 0x0 3. " " " big, little" bitfld.long 0x0 2. " " " big, little" bitfld.long 0x0 1. " " " big, little" bitfld.long 0x0 0. " " " big, little" tree.end tree "Power Management" group dcr:0x0A1--0x0A1 line.long 0x0 "PMCR0 ,Power Managment Control Register" bitfld.long 0x0 31. "DS ,Deep sleep (1.5ms to wake up)" "Clk enabled,Clk & Osci disabled" textline " " bitfld.long 0x0 30. " NAP ,Nap mode (35 CLK-Cykle to wake up)" "Clk & Osci enabled,Clk & Osci disabled" textline " " bitfld.long 0x0 29. " CDE ,Chip doze enable (2 CLK-Cykle to wake up)" "Chip Clk running,Chip Clk off" textline " " bitfld.long 0x0 28. " TDE ,Timer doze enable (2 CLK-Cykle to wake up)" "Timer Clk running,Timer Clk off" textline " " bitfld.long 0x0 14.--15. " CSC ,Chip Internal Clock Speed Control" "2x,1x,1/2x,1/4x" tree.end tree "Debugging" group spr:0x3f2--0x3f2 line.long 0x0 "DBCR,Debug Control Register" bitfld.long 0x0 31. "EDM ,Ext Debug" "disable,enable" bitfld.long 0x0 30. " IDM ,Int Debug" "disable,enable" bitfld.long 0x0 28.--29. " RST ,Reset" "no,core,chip,system" textline " " bitfld.long 0x0 27. " IC ,Instr Compl DE" "disable,enable" bitfld.long 0x0 26. " BT ,Branch Taken DE" "disable,enable" bitfld.long 0x0 25. " EDE ,Exeption DE" "disable,enable" bitfld.long 0x0 24. " TDE ,Trap DE" "disable,enable" bitfld.long 0x0 18. " FT ,Freeze Timers on DE" "run,freeze" textline " " bitfld.long 0x0 17. " IA1 ,Instr Comp 1" "disable,enable" textline " " bitfld.long 0x0 15. " D1R ,Data Comp 1 Read" "disable,enable" bitfld.long 0x0 14. " D1W ,Data Comp 1 Write" "disable,enable" bitfld.long 0x0 12.--13. " D1S ,Data Comp 1 Size" "byte,half-word,word,quad-word" group spr:0x3f0--0x3f0 line.long 0x0 "DBSR,Debug Status Register" bitfld.long 0x0 31. "IC ,Instr Compl DE" "wait,occur" bitfld.long 0x0 30. " BT ,Branch Taken DE" "wait,occur" bitfld.long 0x0 29. " EDE ,Exeption DE" "wait,occur" bitfld.long 0x0 28. " TIE ,Trap DE" "wait,occur" bitfld.long 0x0 27. " UDE ,Uncond DE" "wait,occur" textline " " bitfld.long 0x0 26. " IA1 ,Instr Comp 1" "wait,occur" bitfld.long 0x0 24. " DR1 ,Data Comp 1 Read" "wait,occur" bitfld.long 0x0 23. " DW1 ,Data Comp 1 Write" "wait,occur" textline " " bitfld.long 0x0 20. " IDE ,Imprecise DE" "wait,occur" bitfld.long 0x0 8.--9. " MRR ,Most Recent RESET" "no,core,chip,system" group spr:0x3f6--0x3f6 line.long 0x0 "DAC1,Data Address Compare 1" group spr:0x3f4--0x3f4 line.long 0x0 "IAC1,Instruction Address Compare 1" tree.end