; --------------------------------------------------------------------------------
; @Title: Initializing the PQ2FADS board to work with the Linux example
; @Description: -
; @Author: DIE
; @Chip: MPC8280
; @Board: PQ2FADS
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pq2fads.cmm 7474 2014-07-28 10:52:43Z rweiss $


LOCAL &base &SACS2

; remap the IO base to 0xf0000000

 &base=IOBASE()                         ; get current io base addr
 MAP.NoDenyAccess &base++0xfffff	    ; grant access
 PER.Set.simple &base+0x101a8 %Long 0xf0000000 ; set IMMR
 SYStem.Option BASE 0xf0000000          ; tell it to debugger
 &base=IOBASE()					        ; get new base addr

; set CS1 to BCSR at 0xf4500000
 PER.Set.simple &base+0x1010C %Long 0xffff8010
 PER.Set.simple &base+0x10108 %Long 0xf4501801
; enable RS232-1 in BCSR1
 Data.Set ASD:0xF4500004 %Long 0xbd000000

; init SDRAM MT48LC4M32B2 on CS2 (32MB)

;BR-Reg.
; BR(BA)                = 0      -- BaseAddress=0
; BR(PS)                = 00     -- 64-bit
; BR(DECC)              = 00     -- no error check
; BR(WP)                = 0      -- no write protect
; BR(MS)                = 010    -- SDRAM-60x Bus
; BR(V)	                = 1      -- Valid
 Data.Set nc:&base+0x10110 %Long 0x00000041

;OR-reg
; ORx(AM)                       -- 32MByte block size
; ORx(BPD)              = 01    -- 4 banks per device
; ORx(ROWST)            = 0110  -- ROW starts at A07
; ORx(NUMR)             = 011   -- there are 12 ROW lines
; ORx(IBID)             = 0     -- internal bank interleaving allowed
 Data.Set nc:&base+0x10114 %Long 0x0fe002ec0


 &SACS2=(Data.Long(d:(&base+0x010110))&0xffff8000)        ;startaddress CS2

; PSDMR(PBI)	= 1	        -- Page Mode
; PSDMR(RFEN)   = 1 	-- Refresh enabled
; PSDMR(SDAM)	= 010	-- address muxing mode 2
; PSDMR(BSMA)	= 010	-- BankAddr  is muxed with BusPin A14..16 on BNKSEL
; PSDMR(SDA10)	= 010	-- A10 (AP)  is muxed with BusPin A08
; PSDMR(RFRC)   = 110	-- 8 clocks refresh recovery
; PSDMR(PRETOACT)=011   -- 3 clocks precharge to activate delay
; PSDMR(ACTTORW)= 011   -- 3 clocks activate to read/write delay
; PSDMR(BL)     = 0     -- 4 beat burst length
; PSDMR(LDOTOPRE)=10    -- 2 clock last data out to precharge
; PSDMR(WRC)    = 10    -- 2 clock write recovery time
; PSDMR(EAMUX)  = 0     -- no extra cycle on address phase
; PSDMR(BUFCMD) = 0     -- normal timing for control lines
; PSDMR(CL)		= 11    -- 3 clocks CAS latency
; normal operation mode


;PSDMR-reg, Precharge-All-Banks
 Data.Set nc:&base+0x10190 %Long 0x0EA4B36A3    ;0xa94d1203
 Data.Set &SACS2 %Byte 0

;PSDMR-reg, CBR-Refresh
 Data.Set nc:&base+0x10190 %Long 0x0CA4B36A3    ;0x894d1203
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0
 Data.Set &SACS2 %Byte 0

;PSDMR-reg, Mode-Reg-Write
 Data.Set nc:&base+0x10190 %Long 0x0DA4B36A3    ;0x994d1203
 Data.Set &SACS2 %Byte 0

;PSDMR-reg
 Data.Set nc:&base+0x10190 %Long 0x0C24B36A3    ;0x814d1203
 Data.Set &SACS2 %Byte 0

ENDDO