; --------------------------------------------------------------------------------
; @Title: 837xMDS initialization file
; @Description: -
; @Chip: MPC8377
; @Author: DIE
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: 8379mds_init.cmm 7476 2014-07-28 12:03:02Z rweiss $


;setMMRBaseAddr 0xFF400000
Data.Set spr:0x137 %Long 0xff400000

; change internal MMR base from 0xff400000 (reset value) to 0xe0000000
Data.Set 0xff400000 %Long 0xe0000000

;setMMRBaseAddr 0xe0000000
Data.Set spr:0x137 %Long 0xe0000000

; --------------------------------------------------------------------------------
;# Local Bus Local Access Windows
; --------------------------------------------------------------------------------
; WINDOW 0 - configuration space - Initially mapped by RCWHR[BMS], relocated to 0xe0000000
Data.Set 0xe0000020 %Long 0xe0000000 ; LBLAWBAR0  - begining at 0xe0000000

; WINDOW 1 - FLASH
Data.Set 0xe0000028 %Long 0xFE000000 ; LBLAWBAR1  - begining at 0xfe000000
Data.Set 0xe000002C %Long 0x80000018 ; LBLAWAR1   - enable, size = 32MB 

; WINDOW 2 - board BCSRs
Data.Set 0xe0000030 %Long 0xf8000000 ; LBLAWBAR2  - begining at 0xf8000000
Data.Set 0xe0000034 %Long 0x8000000e ; LBLAWAR2   - enable, size = 32KB 

; --------------------------------------------------------------------------------
;# DDR Local Access Windows
; --------------------------------------------------------------------------------
; WINDOW 0 - 1st DDR SODIMM
Data.Set 0xe00000a0 %Long 0x00000000 ; DDRLAWBAR0 - begining at 0x00000000
Data.Set 0xe00000a4 %Long 0x8000001c ; DDRLAWAR0  - enable, size = 512MB


; --------------------------------------------------------------------------------
;# DDR Controller Configuration
; --------------------------------------------------------------------------------

; DDRCDR
Data.Set 0xE0000128 %Long 0x80080001
WAIT 300.ms

; CS0_BNDS
Data.Set 0xe0002000 %Long 0x0000001f

; CS0_CONFIG
Data.Set 0xe0002080 %Long 0x80010202
WAIT 100.ms

; TIMING_CONFIG_0
Data.Set 0xe0002104 %Long 0x00620802

; TIMING_CONFIG_1
Data.Set 0xe0002108 %Long 0x3935D322

; TIMING_CONFIG_2
Data.Set 0xe000210c %Long 0x231088C8

; TIMING_CONFIG_3
Data.Set 0xe0002100 %Long 0x00000000

; DDR_SDRAM_CFG
Data.Set 0xe0002110 %Long 0x43000000

; DDR_SDRAM_CFG_2
Data.Set 0xe0002114 %Long 0x00001000

; DDR_SDRAM_MODE
Data.Set 0xe0002118 %Long 0x04501432

; DDR_SDRAM_MODE_2
Data.Set 0xe000211c %Long 0x00000000

; DDR_SDRAM_INTERVAL
Data.Set 0xe0002124 %Long 0x03E00100

; DDR_SDRAM_CLK_CNTL
Data.Set 0xe0002130 %Long 0x02000000

WAIT 300.ms

; enable the DDR memory controller
; DDR_SDRAM_CFG
Data.Set 0xe0002110 %Long 0xc3000000 

; --------------------------------------------------------------------------------
;# Local Bus Interface (LBIU) Configuration
; --------------------------------------------------------------------------------

; CS0 - 32MB FLASH 
Data.Set 0xe0005000 %Long 0xfe001001 ; BR0 base address at 0xFE000000, port size 16 bit, GPCM, valid
Data.Set 0xe0005004 %Long 0xfe000ff7 ; OR0 32MB flash size, 15 w.s., timing relaxed

; CS1 - board BCSRs
Data.Set 0xe0005008 %Long 0xf8000801 ; BR1 base address at 0xF8000000, port size 8 bit, GPCM, valid
Data.Set 0xe000500c %Long 0xffff89f7      ; OR1 32KB size, 15 w.s., timing relaxed

; LBCR - local bus enable
Data.Set 0xe00050d0 %Long 0x00000000

; LCRR - divide 8
Data.Set 0xE00050d4 %Long 0x80000008

; SICRL
Data.Set 0xE0000114 %Long 0x00000000

; SICRH
Data.Set 0xE0000118 %Long 0x00000000

; SCCR
Data.Set 0xE0000a08 %Long 0x5fffffff

Register.Set MSR 0x3000 ;machine check enable, exception vectors at 0x0000_0000

;unlock flash in BCSR9
Data.Set 0xf8000009 %Byte 0x01

;clear interrupt in BCSR14
Data.Set 0xf800000e %Byte 0xff

;ANDMem.l    0xe0000800 0x00300000
Data.Set 0xe0000800 %Long Data.Long(d:0xe0000800)&0x00300000