; --------------------------------------------------------------------------------
; @Title: Board setup script for Freescale MPC8536DS evaluation board
; @Description: -
; @Author: REI
; @Board: MPC8536DS
; @Chip: MPC8536E
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: init.cmm 7495 2014-07-29 14:24:45Z rweiss $


SYStem.RESet

;turn off display updates during init
SCREEN.OFF

SYStem.CPU MPC8536
SYStem.Up

;MMU TLB setup
MMU.Set TLB1 1. 0x80000900 0x00000000 0x00000015 0x00000000
MMU.Set TLB1 2. 0x80000900 0xE0000000 0xE0000015 0x00000000

;set base address for on-chip peripherials to 0xFFE00000
Data.Set ANC:0xFF700000 %Long 0x000FFE00
IF SIMULATOR()
  SYStem.Option.BASE 0xFFE00000

Data.Set ANC:0xFFE05000 %Long 0xE8001001	; BR0
Data.Set ANC:0xFFE05004 %Long 0xF8000FF7	; OR0
Data.Set ANC:0xFFE05008 %Long 0xE0001001	; BR1
Data.Set ANC:0xFFE0500C %Long 0xF8000FF7	; OR1
Data.Set ANC:0xE0005010 %Long 0xF8201001	; BR2
Data.Set ANC:0xE0005014 %Long 0xFFF06FF7	; OR2
Data.Set ANC:0xFFE05018 %Long 0xFFDF0801	; BR3
Data.Set ANC:0xFFE0501C %Long 0xFFFFEFF7	; OR3

Data.Set ANC:0xFFE00C28 %Long 0x00000000	; LAWBAR1 -> SDRAM
Data.Set ANC:0xFFE00C30 %Long 0x80F0001C	; LAWAR1
Data.Set ANC:0xFFE00C88 %Long 0x000E0000	; LAWBAR4 -> LBC
Data.Set ANC:0xFFE00C90 %Long 0x8040001B	; LAWAR4
Data.Set ANC:0xFFE00D68 %Long 0x000FFDF0	; LAWBAR11 -> LBC
Data.Set ANC:0xFFE00D70 %Long 0x8040000B	; LAWAR11

Data.Set ANC:0xFFE02000 %Long 0x0000001F	; CS0BNDS
Data.Set ANC:0xFFE02080 %Long 0x80010202	; CS0CONFIG
Data.Set ANC:0xFFE020C0 %Long 0x00000000	; CS0_CONFIG_2
Data.Set ANC:0xFFE02008 %Long 0x00000000	; CS1_BND
Data.Set ANC:0xFFE02084 %Long 0x00000000	; CS1_CONFIG
Data.Set ANC:0xFFE020C4 %Long 0x00000000	; CS1_CONFIG_2
Data.Set ANC:0xFFE02100 %Long 0x00000000	; EXT_REFREC
Data.Set ANC:0xFFE02104 %Long 0x00260802	; TIMING_CFG_0
Data.Set ANC:0xFFE02108 %Long 0x3935D322	; TIMING_CFG_1
Data.Set ANC:0xFFE0210C %Long 0x051054C8	; TIMING_CFG_2
Data.Set ANC:0xFFE02114 %Long 0x24401010	; DDR_SDRAM_CFG2
Data.Set ANC:0xFFE02118 %Long 0x00440432	; DDR_SDRAM_MODE
Data.Set ANC:0xFFE0211C %Long 0x00000000	; DDR_SDRAM_MODE2
Data.Set ANC:0xFFE02124 %Long 0x06DB03E8	; DDR_SDRAM_MD_CNTL
Data.Set ANC:0xFFE02128 %Long 0xDEADBEEF	; DDR_DATA_INIT
Data.Set ANC:0xFFE02130 %Long 0x03800000	; DDR_SDRAM_CLK_CNT
Data.Set ANC:0xFFE02148 %Long 0x00000000	; DDR_INIT_ADDR
Data.Set ANC:0xFFE0214C %Long 0x00000000	; DDR_INIT_EX_ADDR
Data.Set ANC:0xFFE02160 %Long 0x00000000	; TIMING_CFG_4
Data.Set ANC:0xFFE02164 %Long 0x00000000	; TIMING_CFG_5
Data.Set ANC:0xFFE02170 %Long 0x00000000	; DDR_ZQ_CNTL
Data.Set ANC:0xFFE02174 %Long 0x00000000	; DDR_WRLVL_CNTL
Data.Set ANC:0xFFE0217C %Long 0x00000000	; DDR_SR_CNTR
Data.Set ANC:0xFFE02180 %Long 0x00000000	; DDR_SDRAM_RCW_1
Data.Set ANC:0xFFE02184 %Long 0x00000000	; DDR_SDRAM_RCW_2
Data.Set ANC:0xFFE02110 %Long 0xC3008000	; DDR_SDRAM_CFG
WAIT 250.ms

SCREEN.ON


; setup interrupt vectors
; set to SDRAM
; IVPR = 0x00000000
Data.Set SPR:63.  %Long 0x00000000
; IVOR0 - IVOR15
Data.Set SPR:400. %Long 0x00000000
Data.Set SPR:401. %Long 0x00000100
Data.Set SPR:402. %Long 0x00000200
Data.Set SPR:403. %Long 0x00000300
Data.Set SPR:404. %Long 0x00000400
Data.Set SPR:405. %Long 0x00000500
Data.Set SPR:406. %Long 0x00000600
Data.Set SPR:407. %Long 0x00000700
Data.Set SPR:408. %Long 0x00000800
Data.Set SPR:409. %Long 0x00000900
Data.Set SPR:410. %Long 0x00000A00
Data.Set SPR:411. %Long 0x00000B00
Data.Set SPR:412. %Long 0x00000C00
Data.Set SPR:413. %Long 0x00000D00
Data.Set SPR:414. %Long 0x00000E00
Data.Set SPR:415. %Long 0x00000F00
; IVOR32 - IVOR35
Data.Set SPR:528. %Long 0x00001000
Data.Set SPR:529. %Long 0x00001100
Data.Set SPR:530. %Long 0x00001200
Data.Set SPR:531. %Long 0x00001300

Data.Assemble 0x0000 B 0x0000
Data.Assemble 0x0100 B 0x0100
Data.Assemble 0x0200 B 0x0200
Data.Assemble 0x0300 B 0x0300
Data.Assemble 0x0400 B 0x0400
Data.Assemble 0x0500 B 0x0500
Data.Assemble 0x0600 B 0x0600
Data.Assemble 0x0700 B 0x0700
Data.Assemble 0x0800 B 0x0800
Data.Assemble 0x0900 B 0x0900
Data.Assemble 0x0A00 B 0x0A00
Data.Assemble 0x0B00 B 0x0B00
Data.Assemble 0x0C00 B 0x0C00
Data.Assemble 0x0D00 B 0x0D00
Data.Assemble 0x0E00 B 0x0E00
Data.Assemble 0x0F00 B 0x0F00
Data.Assemble 0x1000 B 0x1000
Data.Assemble 0x1100 B 0x1100
Data.Assemble 0x1200 B 0x1200
Data.Assemble 0x1300 B 0x1300

ENDDO