; --------------------------------------------------------------------------------
; @Title: Initialization script for Freescale Intrepid MPC8533 evaluation board
; @Description: -
; @Author: REI
; @Board: MPC8533DS
; @Chip: MPC8533E
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: init.cmm 7495 2014-07-29 14:24:45Z rweiss $


;29.01.2008

SYStem.CPU MPC8533
SYStem.Up
SYStem.Option.FREEZE OFF

;TLB setup
MMU.Set TLB1 1. 0x80000900 0x00000000 0x00000015 0x00000000
MMU.Set TLB1 2. 0x80000900 0xE0000000 0xE0000015 0x00000000

;set CCSR base address to 0xE0000000
Data.Set ANC:IOBASE() %Long 0x000E0000

;enable Local access error check
Data.Set ANC:IOBASE()+0x00001E08 %Long 0x00000001 ;ECM_EEER

;Local Bus config
Data.Set ANC:IOBASE()+0x00005000 %Long 0xFF801001 ;BR0
Data.Set ANC:IOBASE()+0x00005004 %Long 0xFF806E65 ;OR0
Data.Set ANC:IOBASE()+0x0000500C %Long 0xFF806E65 ;OR1
Data.Set ANC:IOBASE()+0x00005008 %Long 0xFE801001 ;BR1
Data.Set ANC:IOBASE()+0x0000501C %Long 0xFFF06FF7 ;OR3
Data.Set ANC:IOBASE()+0x00005018 %Long 0xF8100801 ;BR3

;UART0 config
Data.Set ANC:IOBASE()+0x00004501 %Byte 0x00
Data.Set ANC:IOBASE()+0x00004503 %Byte 0x83
Data.Set ANC:IOBASE()+0x00004501 %Byte 0x00
Data.Set ANC:IOBASE()+0x00004503 %Byte 0x03
Data.Set ANC:IOBASE()+0x00004504 %Byte 0x03
Data.Set ANC:IOBASE()+0x00004502 %Byte 0x07

;UART1 config
Data.Set ANC:IOBASE()+0x00004601 %Byte 0x00
Data.Set ANC:IOBASE()+0x00004603 %Byte 0x83
Data.Set ANC:IOBASE()+0x00004600 %Byte 0xD9
Data.Set ANC:IOBASE()+0x00004601 %Byte 0x00
Data.Set ANC:IOBASE()+0x00004603 %Byte 0x03
Data.Set ANC:IOBASE()+0x00004604 %Byte 0x03
Data.Set ANC:IOBASE()+0x00004602 %Byte 0x07

;LBC
Data.Set ANC:IOBASE()+0x000050D4 %Long 0x80030008 ;LBC_LCRR

;DDR config
Data.Set ANC:IOBASE()+0x00002000 %Long 0x0000001F ;CS0_BNDS
Data.Set ANC:IOBASE()+0x00002080 %Long 0x80010202 ;CS0_CONFIG
Data.Set ANC:IOBASE()+0x00002104 %Long 0x00260802 ;TIMING_CFG_0
Data.Set ANC:IOBASE()+0x00002100 %Long 0x00000000 ;TIMING_CFG_3
Data.Set ANC:IOBASE()+0x00002108 %Long 0x3935D322 ;TIMING_CFG_1
Data.Set ANC:IOBASE()+0x0000210C %Long 0x14904CC8 ;TIMING_CFG_2
Data.Set ANC:IOBASE()+0x00002118 %Long 0x00480432 ;DDR_SDRAM_MODE
Data.Set ANC:IOBASE()+0x0000211C %Long 0x00000000 ;DDR_SDRAM_MODE_2
Data.Set ANC:IOBASE()+0x00002124 %Long 0x06180100 ;DDR_SDRAM_INTERVAL
Data.Set ANC:IOBASE()+0x00002128 %Long 0xDEADBEEF ;DDR_DATA_INIT
Data.Set ANC:IOBASE()+0x00002114 %Long 0x04400010 ;DDR_SDRAM_CFG_2
Data.Set ANC:IOBASE()+0x00002130 %Long 0x83800000 ;DDR_SDRAM_CLK_CNTL
WAIT 250.ms
Data.Set ANC:IOBASE()+0x00002110 %Long 0xE3008000 ;DDR_SDRAM_CFG
WAIT 250.ms

;LAW
Data.Set ANC:IOBASE()+0x00000C28 %Long 0x00000000 ;LAWBAR1
Data.Set ANC:IOBASE()+0x00000C30 %Long 0x80F0001C ;LAWAR1
Data.Set ANC:IOBASE()+0x00000C10 %Long 0x00000000 ;LAWAR0

ENDDO