; --------------------------------------------------------------------------------
; @Title: Initialization script for Freescale ADS5121e evaluation board
; @Description: -
; @Author: REI
; @Board: ADS5121
; @Chip: MPC5121
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: init.cmm 7496 2014-07-29 14:25:53Z rweiss $


;Debugger Setup
  SYStem.CPU MPC5121
  SYStem.Option.WATCHDOG.OFF
  SYStem.Up
  IF !SIMULATOR()
    SYStem.BdmClock 20.MHz

;initialize R1
  Register.Set R1 0x00000000

;set base address of on-chip peripherals
  IF SIMULATOR()
    SYStem.Option.BASE 0xE0000000
    
  Data.Set ANC:IOBASE()         %Long %BE 0xE0000000 ;IMMR

;set internal SRAM base address
  Data.Set ANC:IOBASE()+0x000C4 %Long %BE 0x30000000 ;SRAMBAR = 0x30000000

; enable the clocks of all modules
  Data.Set ANC:IOBASE()+0x00F04 %Long %BE 0xFFFFFFFF ;SCCR1
  Data.Set ANC:IOBASE()+0x00F08 %Long %BE 0xFFFFFFFF ;SCCR2

; access windows
  Data.Set ANC:IOBASE()+0x00024 %Long %BE 0xFC00FFFF ;LPCS0AW: FLASH window -> 0xfc000000
  Data.Set ANC:IOBASE()+0x0002C %Long %BE 0xE200E200 ;LPCS2AW: BCSR window  -> 0xe2000000++0x0000ffff

; CS0: FLASH
  Data.Set ANC:IOBASE()+0x10000 %Long %BE 0x05059310 ;LPC_CS0BCR
  Data.Set ANC:IOBASE()+0x10020 %Long %BE 0x01000000 ;LPC_CSCR - master enable

; CS2: BCSR
  Data.Set ANC:IOBASE()+0x10008 %Long %BE 0x05059010 ;LPC_CS2CR

; enable write access to FLASH (using BCSR register)
Data.Set 0xe2000008           %Byte     0xD1

; DDR memory configuration
  Data.Set ANC:IOBASE()+0x0A000 %Long %BE 0x00000036 ;IO_CONTROL_MEM: 
  Data.Set ANC:IOBASE()+0x000A0 %Long %BE 0x00000000 ;DDRLAWBAR -> 0x00000000
  Data.Set ANC:IOBASE()+0x000A4 %Long %BE 0x0000001A ;DDRLAWAR  -> 128 MByte
  Data.Set ANC:IOBASE()+0x09000 %Long %BE 0x30000000 ;DDRSCR

  Data.Set ANC:IOBASE()+0x09080 %Long %BE 0x000777AA ;PR_CONF1
  Data.Set ANC:IOBASE()+0x09084 %Long %BE 0x00000055 ;PR_CONF2
  Data.Set ANC:IOBASE()+0x09088 %Long %BE 0x00000000 ;HIPR_CONF

  Data.Set ANC:IOBASE()+0x0908C %Long %BE 0x11111117 ;LUT0MUR
  Data.Set ANC:IOBASE()+0x090A0 %Long %BE 0x7777777A ;LUT0MLR
  Data.Set ANC:IOBASE()+0x090B4 %Long %BE 0x33333377 ;LUT0AUR
  Data.Set ANC:IOBASE()+0x090C8 %Long %BE 0x7777EEEE ;LUT0ALR

  Data.Set ANC:IOBASE()+0x09090 %Long %BE 0x444EEEEE ;LUT1MUR
  Data.Set ANC:IOBASE()+0x090A4 %Long %BE 0xEEEEEEEE ;LUT1MLR
  Data.Set ANC:IOBASE()+0x090B8 %Long %BE 0x11111111 ;LUT1AUR
  Data.Set ANC:IOBASE()+0x090CC %Long %BE 0x11111111 ;LUT1ALR

  Data.Set ANC:IOBASE()+0x090A8 %Long %BE 0x44444444 ;LUT2MLR
  Data.Set ANC:IOBASE()+0x09094 %Long %BE 0x44444444 ;LUT2MUR
  Data.Set ANC:IOBASE()+0x090BC %Long %BE 0x11111111 ;LUT2AUR
  Data.Set ANC:IOBASE()+0x090D0 %Long %BE 0x11111111 ;LUT2ALR

  Data.Set ANC:IOBASE()+0x09098 %Long %BE 0x55555555 ;LUT3MUR
  Data.Set ANC:IOBASE()+0x090AC %Long %BE 0x55555558 ;LUT3MLR
  Data.Set ANC:IOBASE()+0x090C0 %Long %BE 0x11111111 ;LUT3AUR
  Data.Set ANC:IOBASE()+0x090D4 %Long %BE 0x11111111 ;LUT3ALR

  Data.Set ANC:IOBASE()+0x0909C %Long %BE 0x11111111 ;LUT4MUR
  Data.Set ANC:IOBASE()+0x090B0 %Long %BE 0x1111117C ;LUT4MLR
  Data.Set ANC:IOBASE()+0x090C4 %Long %BE 0x11111111 ;LUT4AUR
  Data.Set ANC:IOBASE()+0x090D8 %Long %BE 0x11111111 ;LUT4ALR

  Data.Set ANC:IOBASE()+0x09000 %Long %BE 0xF8604200 ;DDRSCR
  Data.Set ANC:IOBASE()+0x09004 %Long %BE 0x0000281E ;TC
  Data.Set ANC:IOBASE()+0x09008 %Long %BE 0x68EC1168 ;DDRTC1R
  Data.Set ANC:IOBASE()+0x0900C %Long %BE 0x37A10864 ;DDRTC2R

  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01100400 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01020000 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01030000 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01010000 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01000932 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01100400 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01080000 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01080000 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01000832 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01010780 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01010400 ;CR 
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)
  Data.Set ANC:IOBASE()+0x09010 %Long %BE 0x01380000 ;CR (NOP)

  Data.Set ANC:IOBASE()+0x09004 %Long %BE 0x01F4281E ;TC
  Data.Set ANC:IOBASE()+0x09000 %Long %BE 0xE8604200 ;DDRSCR

WAIT 500.ms

ENDDO