/************************************************************************** generic type definitions **************************************************************************/ #define TRUE 1 #define FALSE 0 #define NULL 0 typedef unsigned char byte; typedef unsigned short word; typedef unsigned long dword; typedef signed char sbyte; typedef signed short sword; typedef signed long sdword; /************************************************************************** MPC860 (PowerQUICC) Registers **************************************************************************/ struct ethernet_pram { /* * SCC parameter RAM */ unsigned short rbase; /* RX BD base address */ unsigned short tbase; /* TX BD base address */ unsigned char rfcr; /* Rx function code */ unsigned char tfcr; /* Tx function code */ unsigned short mrblr; /* Rx buffer length */ unsigned long rstate; /* Rx internal state */ unsigned long rptr; /* Rx internal data pointer */ unsigned short rbptr; /* rb BD Pointer */ unsigned short rcount; /* Rx internal byte count */ unsigned long rtemp; /* Rx temp */ unsigned long tstate; /* Tx internal state */ unsigned long tptr; /* Tx internal data pointer */ unsigned short tbptr; /* Tx BD pointer */ unsigned short tcount; /* Tx byte count */ unsigned long ttemp; /* Tx temp */ unsigned long rcrc; /* temp receive CRC */ unsigned long tcrc; /* temp transmit CRC */ /* * ETHERNET specific parameter RAM */ unsigned long c_pres; /* preset CRC */ unsigned long c_mask; /* constant mask for CRC */ unsigned long crcec; /* CRC error counter */ unsigned long alec; /* alighnment error counter */ unsigned long disfc; /* discard frame counter */ unsigned short pads; /* short frame PAD characters */ unsigned short ret_lim; /* retry limit threshold */ unsigned short ret_cnt; /* retry limit counter */ unsigned short mflr; /* maximum frame length reg */ unsigned short minflr; /* minimum frame length reg */ unsigned short maxd1; /* maximum DMA1 length reg */ unsigned short maxd2; /* maximum DMA2 length reg */ unsigned short maxd; /* rx max DMA */ unsigned short dma_cnt; /* rx dma counter */ unsigned short max_b; /* max bd byte count */ unsigned short gaddr1; /* group address filter 1 */ unsigned short gaddr2; /* group address filter 2 */ unsigned short gaddr3; /* group address filter 3 */ unsigned short gaddr4; /* group address filter 4 */ unsigned long tbuf0_data0; /* save area 0 - current frm */ unsigned long tbuf0_data1; /* save area 1 - current frm */ unsigned long tbuf0_rba0; unsigned long tbuf0_crc; unsigned short tbuf0_bcnt; unsigned short paddr_h; /* physical address (MSB) */ unsigned short paddr_m; /* physical address */ unsigned short paddr_l; /* physical address (LSB) */ unsigned short p_per; /* persistence */ unsigned short rfbd_ptr; /* rx first bd pointer */ unsigned short tfbd_ptr; /* tx first bd pointer */ unsigned short tlbd_ptr; /* tx last bd pointer */ unsigned long tbuf1_data0; /* save area 0 - next frame */ unsigned long tbuf1_data1; /* save area 1 - next frame */ unsigned long tbuf1_rba0; unsigned long tbuf1_crc; unsigned short tbuf1_bcnt; unsigned short tx_len; /* tx frame length counter */ unsigned short iaddr1; /* individual address filter 1*/ unsigned short iaddr2; /* individual address filter 2*/ unsigned short iaddr3; /* individual address filter 3*/ unsigned short iaddr4; /* individual address filter 4*/ unsigned short boff_cnt; /* back-off counter */ unsigned short taddr_h; /* temp address (MSB) */ unsigned short taddr_m; /* temp address */ unsigned short taddr_l; /* temp address (LSB) */ }; typedef struct fec { /* offset = 0x00 */ volatile unsigned long AddrLow; /* lower 32 bits of our address */ volatile unsigned long AddrHigh; /* upper 16 bits of our address */ volatile unsigned long HashTableHigh; /* upper 32 bits of hash table */ volatile unsigned long HashTableLow; /* lower 32 bits of hash table */ volatile unsigned long RDesStart; /* Beginning of Recv descriptor ring */ volatile unsigned long XDesStart; /* Beginning of Xmit descriptor ring */ volatile unsigned long RBuffSize; /* Receive Buffer Size */ volatile unsigned long resrv1[9]; /* offset = 0x40 */ volatile unsigned long ECntrl; /* Ethernet Control Register */ volatile unsigned long IEvent; /* Interrupt Event Register */ volatile unsigned long IMask; /* Interrupt Mask Register */ volatile unsigned long IVec; /* Interrupt Vector Register */ volatile unsigned long RDesActive; /* Receive ring updated flag */ volatile unsigned long XDesActive; /* Transmit ring updated flag */ volatile unsigned long resrv2[10]; /* offset = 0x80 */ volatile unsigned long MiiData; /* MII data register */ volatile unsigned long MiiSpeed; /* MII speed register */ volatile unsigned long resrv3[17]; /* offset = 0xcc */ volatile unsigned long RBound; /* End of RAM */ volatile unsigned long RFStart; /* Receive fifo start address */ volatile unsigned long resrv4[6]; /* offset = 0xec */ volatile unsigned long XFStart; /* Transmit fifo start address */ volatile unsigned long resrv5[17]; /* offset = 0x134 */ volatile unsigned long DmaFcnCode; /* DMA function code */ volatile unsigned long resrv6[3]; /* offset = 0x144 */ volatile unsigned long RCntrl; /* Receive control register */ volatile unsigned long RHash; /* Receive control register */ volatile unsigned long resrv7[14]; /* offset = 0x184 */ volatile unsigned long XCntrl; /* Transmit control register */ volatile unsigned long resrv8[14]; volatile unsigned long resrv9[16]; /* offset = 0x200 */ }; typedef struct { /* BASE + 0x0000: INTERNAL REGISTERS */ /* SIU */ volatile unsigned long siu_mcr; /* module configuration reg */ volatile unsigned long siu_sypcr; /* System protection cnt */ unsigned char RESERVED58[0x6]; volatile unsigned short siu_swsr; /* sw service */ volatile unsigned long siu_sipend; /* Interrupt pend reg */ volatile unsigned long siu_simask; /* Interrupt mask reg */ volatile unsigned long siu_siel; /* Interrupt edge level mask reg */ volatile unsigned long siu_sivec; /* Interrupt vector */ volatile unsigned long siu_tesr; /* Transfer error status */ volatile unsigned char RESERVED1[0xc];/* Reserved area */ volatile unsigned long dma_sdcr; /* SDMA configuration reg */ unsigned char RESERVED55[0x4c]; /* PCMCIA */ volatile unsigned long pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */ volatile unsigned long pcmcia_por0; /* PCMCIA Option Reg: Window 0 */ volatile unsigned long pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */ volatile unsigned long pcmcia_por1; /* PCMCIA Option Reg: Window 1 */ volatile unsigned long pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */ volatile unsigned long pcmcia_por2; /* PCMCIA Option Reg: Window 2 */ volatile unsigned long pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */ volatile unsigned long pcmcia_por3; /* PCMCIA Option Reg: Window 3 */ volatile unsigned long pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */ volatile unsigned long pcmcia_por4; /* PCMCIA Option Reg: Window 4 */ volatile unsigned long pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */ volatile unsigned long pcmcia_por5; /* PCMCIA Option Reg: Window 5 */ volatile unsigned long pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */ volatile unsigned long pcmcia_por6; /* PCMCIA Option Reg: Window 6 */ volatile unsigned long pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */ volatile unsigned long pcmcia_por7; /* PCMCIA Option Reg: Window 7 */ volatile unsigned char RESERVED2[0x20];/* Reserved area */ volatile unsigned long pcmcia_pgcra; /* PCMCIA Slot A Control Reg */ volatile unsigned long pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */ volatile unsigned long pcmcia_pscr; /* PCMCIA Status Reg */ volatile unsigned char RESERVED2a[0x4];/* Reserved area */ volatile unsigned long pcmcia_pipr; /* PCMCIA Pins Value Reg */ volatile unsigned char RESERVED2b[0x4];/* Reserved area */ volatile unsigned long pcmcia_per; /* PCMCIA Enable Reg */ volatile unsigned char RESERVED2c[0x4];/* Reserved area */ /* MEMC */ volatile unsigned long memc_br0; /* base register 0 */ volatile unsigned long memc_or0; /* option register 0 */ volatile unsigned long memc_br1; /* base register 1 */ volatile unsigned long memc_or1; /* option register 1 */ volatile unsigned long memc_br2; /* base register 2 */ volatile unsigned long memc_or2; /* option register 2 */ volatile unsigned long memc_br3; /* base register 3 */ volatile unsigned long memc_or3; /* option register 3 */ volatile unsigned long memc_br4; /* base register 3 */ volatile unsigned long memc_or4; /* option register 3 */ volatile unsigned long memc_br5; /* base register 3 */ volatile unsigned long memc_or5; /* option register 3 */ volatile unsigned long memc_br6; /* base register 3 */ volatile unsigned long memc_or6; /* option register 3 */ volatile unsigned long memc_br7; /* base register 3 */ volatile unsigned long memc_or7; /* option register 3 */ unsigned char RESERVED3[0x24]; /* Reserved area */ volatile unsigned long memc_mar; /* Memory address */ volatile unsigned long memc_mcr; /* Memory command */ volatile unsigned char RESERVED4[0x4]; /* Reserved area */ volatile unsigned long memc_mamr; /* Machine A mode */ volatile unsigned long memc_mbmr; /* Machine B mode */ volatile unsigned short memc_mstat; /* Memory status */ volatile unsigned short memc_mptpr; /* Memory preidic timer prescalar */ volatile unsigned long memc_mdr; /* Memory data */ volatile unsigned char RESERVED5[0x80];/* Reserved area */ /* SYSTEM INTEGRATION TIMERS */ volatile unsigned short simt_tbscr; /* Time base stat&ctr */ volatile unsigned char RESERVED100[0x2]; /* Reserved area */ volatile unsigned long simt_tbreff0; /* Time base reference 0 */ volatile unsigned long simt_tbreff1; /* Time base reference 1 */ volatile unsigned char RESERVED6[0x14];/* Reserved area */ volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */ volatile unsigned char RESERVED110[0x2]; /* Reserved area */ volatile unsigned long simt_rtc; /* Realtime clock */ volatile unsigned long simt_rtsec; /* Realtime alarm seconds */ volatile unsigned long simt_rtcal; /* Realtime alarm */ volatile unsigned char RESERVED56[0x10];/* Reserved area */ volatile unsigned long simt_piscr; /* PIT stat&ctrl */ volatile unsigned long simt_pitc; /* PIT counter */ volatile unsigned long simt_pitr; /* PIT */ volatile unsigned char RESERVED7[0x34];/* Reserved area */ /* CLOCKS, RESET */ volatile unsigned long clkr_sccr; /* System clk cntrl */ volatile unsigned long clkr_plprcr; /* PLL reset&ctrl */ volatile unsigned long clkr_rsr; /* reset status */ unsigned char RESERVED8a[0x74]; /* Reserved area */ /* System Integration Timers Keys */ volatile unsigned long simt_tbscrk; /* Timebase Status&Ctrl Key */ volatile unsigned long simt_tbreff0k; /* Timebase Reference 0 Key */ volatile unsigned long simt_tbreff1k; /* Timebase Reference 1 Key */ volatile unsigned long simt_tbk; /* Timebase and Decrementer Key */ unsigned char RESERVED66b[0x10];/* Reserved area */ volatile unsigned long simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */ volatile unsigned long simt_rtck; /* Real-Time Clock Key */ volatile unsigned long simt_rtseck; /* Real-Time Alarm Seconds Key */ volatile unsigned long simt_rtcalk; /* Real-Time Alarm Key */ unsigned char RESERVED66c[0x10];/* Reserved area */ volatile unsigned long simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */ volatile unsigned long simt_pitck; /* Periodic Interrupt Count Key */ unsigned char RESERVED66d[0x38];/* Reserved area */ /* Clock and Reset Keys */ volatile unsigned long clkr_sccrk; /* System Clock Control Key */ volatile unsigned long clkr_plprcrk; /* PLL, Low Power and Reset Control Key */ volatile unsigned long clkr_rsrk; /* Reset Status Key */ unsigned char RESERVED66e[0x4d4];/* Reserved area */ /* I2C */ volatile unsigned char i2c_i2mod; /* i2c mode */ unsigned char RESERVED59[3]; volatile unsigned char i2c_i2add; /* i2c address */ unsigned char RESERVED60[3]; volatile unsigned char i2c_i2brg; /* i2c brg */ unsigned char RESERVED61[3]; volatile unsigned char i2c_i2com; /* i2c command */ unsigned char RESERVED62[3]; volatile unsigned char i2c_i2cer; /* i2c event */ unsigned char RESERVED63[3]; volatile unsigned char i2c_i2cmr; /* i2c mask */ volatile unsigned char RESERVED10[0x8b];/* Reserved area */ /* DMA */ volatile unsigned char RESERVED11[0x4];/* Reserved area */ volatile unsigned long dma_sdar; /* SDMA address reg */ volatile unsigned char RESERVED12[0x2];/* Reserved area */ volatile unsigned char dma_sdsr; /* SDMA status reg */ volatile unsigned char RESERVED13[0x3];/* Reserved area */ volatile unsigned char dma_sdmr; /* SDMA mask reg */ volatile unsigned char RESERVED14[0x1];/* Reserved area */ volatile unsigned char dma_idsr1; /* IDMA1 status reg */ volatile unsigned char RESERVED15[0x3];/* Reserved area */ volatile unsigned char dma_idmr1; /* IDMA1 mask reg */ volatile unsigned char RESERVED16[0x3];/* Reserved area */ volatile unsigned char dma_idsr2; /* IDMA2 status reg */ volatile unsigned char RESERVED17[0x3];/* Reserved area */ volatile unsigned char dma_idmr2; /* IDMA2 mask reg */ volatile unsigned char RESERVED18[0x13];/* Reserved area */ /* CPM Interrupt Controller */ volatile unsigned short cpmi_civr; /* CP interrupt vector reg */ volatile unsigned char RESERVED19[0xe];/* Reserved area */ volatile unsigned long cpmi_cicr; /* CP interrupt configuration reg */ volatile unsigned long cpmi_cipr; /* CP interrupt pending reg */ volatile unsigned long cpmi_cimr; /* CP interrupt mask reg */ volatile unsigned long cpmi_cisr; /* CP interrupt in-service reg */ /* I/O port */ volatile unsigned short pio_padir; /* port A data direction reg */ volatile unsigned short pio_papar; /* port A pin assignment reg */ volatile unsigned short pio_paodr; /* port A open drain reg */ volatile unsigned short pio_padat; /* port A data register */ volatile unsigned char RESERVED20[0x8]; /* Reserved area */ volatile unsigned short pio_pcdir; /* port C data direction reg */ volatile unsigned short pio_pcpar; /* port C pin assignment reg */ volatile unsigned short pio_pcso; /* port C special options */ volatile unsigned short pio_pcdat; /* port C data register */ volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */ unsigned char RESERVED64[6]; volatile unsigned short pio_pddir; /* port D Data Direction reg */ volatile unsigned short pio_pdpar; /* port D pin assignment reg */ unsigned char RESERVED65[2]; volatile unsigned short pio_pddat; /* port D data reg */ volatile unsigned char RESERVED21[0x8]; /* Reserved area */ /* CPM Timer */ volatile unsigned short timer_tgcr; /* timer global configuration reg */ volatile unsigned char RESERVED22[0xe]; /* Reserved area */ volatile unsigned short timer_tmr1; /* timer 1 mode reg */ volatile unsigned short timer_tmr2; /* timer 2 mode reg */ volatile unsigned short timer_trr1; /* timer 1 referance reg */ volatile unsigned short timer_trr2; /* timer 2 referance reg */ volatile unsigned short timer_tcr1; /* timer 1 capture reg */ volatile unsigned short timer_tcr2; /* timer 2 capture reg */ volatile unsigned short timer_tcn1; /* timer 1 counter reg */ volatile unsigned short timer_tcn2; /* timer 2 counter reg */ volatile unsigned short timer_tmr3; /* timer 3 mode reg */ volatile unsigned short timer_tmr4; /* timer 4 mode reg */ volatile unsigned short timer_trr3; /* timer 3 referance reg */ volatile unsigned short timer_trr4; /* timer 4 referance reg */ volatile unsigned short timer_tcr3; /* timer 3 capture reg */ volatile unsigned short timer_tcr4; /* timer 4 capture reg */ volatile unsigned short timer_tcn3; /* timer 3 counter reg */ volatile unsigned short timer_tcn4; /* timer 4 counter reg */ volatile unsigned short timer_ter1; /* timer 1 event reg */ volatile unsigned short timer_ter2; /* timer 2 event reg */ volatile unsigned short timer_ter3; /* timer 3 event reg */ volatile unsigned short timer_ter4; /* timer 4 event reg */ volatile unsigned char RESERVED23[0x8]; /* Reserved area */ /* CP */ volatile unsigned short cp_cr; /* command register */ volatile unsigned char RESERVED24[0x2]; /* Reserved area */ volatile unsigned short cp_rccr; /* main configuration reg */ volatile unsigned char RESERVED25; /* Reserved area */ volatile unsigned char cp_resv1; /* Reserved reg */ volatile unsigned long cp_resv2; /* Reserved reg */ volatile unsigned short cp_rctr1; /* ram break register 1 */ volatile unsigned short cp_rctr2; /* ram break register 2 */ volatile unsigned short cp_rctr3; /* ram break register 3 */ volatile unsigned short cp_rctr4; /* ram break register 4 */ volatile unsigned char RESERVED26[0x2]; /* Reserved area */ volatile unsigned short cp_rter; /* RISC timers event reg */ volatile unsigned char RESERVED27[0x2]; /* Reserved area */ volatile unsigned short cp_rtmr; /* RISC timers mask reg */ volatile unsigned char RESERVED28[0x14]; /* Reserved area */ /* BRG */ volatile unsigned long brgc1; /* BRG1 configuration reg */ volatile unsigned long brgc2; /* BRG2 configuration reg */ volatile unsigned long brgc3; /* BRG3 configuration reg */ volatile unsigned long brgc4; /* BRG4 configuration reg */ /* SCC registers */ struct scc_regs { volatile unsigned long scc_gsmr_l; /* SCC Gen mode (LOW) */ volatile unsigned long scc_gsmr_h; /* SCC Gen mode (HIGH) */ volatile unsigned short scc_psmr; /* protocol specific mode register */ volatile unsigned char RESERVED29[0x2]; /* Reserved area */ volatile unsigned short scc_todr; /* SCC transmit on demand */ volatile unsigned short scc_dsr; /* SCC data sync reg */ volatile unsigned short scc_scce; /* SCC event reg */ volatile unsigned char RESERVED30[0x2];/* Reserved area */ volatile unsigned short scc_sccm; /* SCC mask reg */ volatile unsigned char RESERVED31[0x1];/* Reserved area */ volatile unsigned char scc_sccs; /* SCC status reg */ volatile unsigned char RESERVED32[0x8]; /* Reserved area */ } scc_regs[4]; /* SMC */ struct smc_regs { volatile unsigned char RESERVED34[0x2]; /* Reserved area */ volatile unsigned short smc_smcmr; /* SMC mode reg */ volatile unsigned char RESERVED35[0x2];/* Reserved area */ volatile unsigned char smc_smce; /* SMC event reg */ volatile unsigned char RESERVED36[0x3]; /* Reserved area */ volatile unsigned char smc_smcm; /* SMC mask reg */ volatile unsigned char RESERVED37[0x5]; /* Reserved area */ } smc_regs[2]; /* SPI */ volatile unsigned short spi_spmode; /* SPI mode reg */ volatile unsigned char RESERVED38[0x4]; /* Reserved area */ volatile unsigned char spi_spie; /* SPI event reg */ volatile unsigned char RESERVED39[0x3]; /* Reserved area */ volatile unsigned char spi_spim; /* SPI mask reg */ volatile unsigned char RESERVED40[0x2]; /* Reserved area */ volatile unsigned char spi_spcom; /* SPI command reg */ volatile unsigned char RESERVED41[0x4]; /* Reserved area */ /* PIP */ volatile unsigned short pip_pipc; /* pip configuration reg */ volatile unsigned char RESERVED42[0x2]; /* Reserved area */ volatile unsigned short pip_ptpr; /* pip timing parameters reg */ volatile unsigned long pip_pbdir; /* port b data direction reg */ volatile unsigned long pip_pbpar; /* port b pin assignment reg */ volatile unsigned char RESERVED43[0x2]; /* Reserved area */ volatile unsigned short pip_pbodr; /* port b open drain reg */ volatile unsigned char pip_pbdat_hh; volatile unsigned char pip_pbdat_h; volatile unsigned char pip_pbdat_m; volatile unsigned char pip_pbdat_l; volatile unsigned char RESERVED44[0x18]; /* Reserved area */ /* Serial Interface */ volatile unsigned long si_simode; /* SI mode register */ volatile unsigned char si_sigmr; /* SI global mode register */ volatile unsigned char RESERVED45; /* Reserved area */ volatile unsigned char si_sistr; /* SI status register */ volatile unsigned char si_sicmr; /* SI command register */ volatile unsigned char RESERVED46[0x4]; /* Reserved area */ volatile unsigned long si_sicr; /* SI clock routing */ volatile unsigned long si_sirp; /* SI ram pointers */ volatile unsigned char RESERVED47[0x10c]; /* Reserved area */ volatile unsigned char si_siram[0x200]; /* SI routing ram */ struct fec fec; volatile unsigned char RESERVED48[0x1000]; /* Reserved area */ /* BASE + 0x2000: user data memory */ volatile unsigned char udata_bd_ucode[0x200]; /*user data bd's or Ucode (small) */ volatile unsigned char udata_bd_ucode2[0x200]; /*user data bd's or Ucode (medium) */ volatile unsigned char udata_bd_ucode3[0x400]; /*user data bd's or Ucode (large)*/ volatile unsigned char udata_bd[0x700]; /*user data bd's*/ volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram*/ volatile unsigned char RESERVED49[0x0c00]; /* Reserved area */ /* BASE + 0x3c00: PARAMETER RAM */ union { struct scc_pram { union { unsigned char RESERVED50[0x80]; } pscc; /* scc parameter area (protocol dependent) */ union { struct { unsigned char RESERVED57[0x4c]; } spi_timer_idma; } pothers; } scc; struct ethernet_pram enet_scc; unsigned char pr[0x100]; } pram[4]; } QUICC; #define SCC1_PRAM 0 #define SOFTWARE_RESET 0x8000 #define CMD_FLAG 0x0001 /* MPC860T specifics */ #define MIIInt 0x00800000 #define TransmitFrameInt 0x08000000 #define ReceiveFrameInt 0x02000000 #define IVECLevel 29 /* rotate offset */ #define MiiSPEED 1 /* rotate offset */ #define MiiDisPreamble 0x00000008 /************************************************************************** MPC8260 (PowerQUICC II) Registers **************************************************************************/ typedef struct { word riptr; /* Rx internal temporary data pointer. */ word tiptr; /* Tx internal temporary data pointer. */ word RESERVED0; /* Reserved */ word mrblr; /* Rx buffer length */ dword rstate; /* Rx internal state */ dword rbase; /* RX BD base address */ word rbdstat; /* Rx BD status and control */ word rbdlen; /* Rx BD data length */ dword rdptr; /* rx BD data pointer */ dword tstate; /* Tx internal state */ dword tbase; /* TX BD base address */ word tbdstat; /* Tx BD status and control */ word tbdlen; /* Tx BD data length */ dword tdptr; /* Tx data pointer */ dword rbptr; /* rx BD pointer */ dword tbptr; /* Tx BD pointer */ dword rcrc; /* Temp receive CRC */ dword reserved_1[0x1]; dword tcrc; /* Temp transmit CRC */ } t_Fcc_Pram; typedef struct { t_Fcc_Pram FccPram; /* area of general FCC parameters. */ dword stat_bus; /* Internal use buffer. */ dword cam_ptr; /* CAM address. */ dword c_mask; /* CRC constant mask*/ dword c_pres; /* CRC preset */ dword crcec; /* CRC error counter */ dword alec; /* alignment error counter */ dword disfc; /* discarded frame counter */ word ret_lim; /* Retry limit threshold. */ word ret_cnt; /* Retry limit counter. */ word p_per; /* persistence */ word boff_cnt; /* back-off counter */ dword gaddr_h; /* group address filter, high */ dword gaddr_l; /* group address filter, low */ word tfcstat; /* out of sequece Tx BD staus. */ word tfclen; /* out of sequece Tx BD length. */ dword tfcptr; /* out of sequece Tx BD data pointer. */ word mflr; /* maximum frame length reg */ word paddr1_h; /* physical address (MSB) */ word paddr1_m; /* physical address */ word paddr1_l; /* physical address (LSB) */ word ibd_cnt; /* internal BD counter. */ word ibd_start; /* internal BD start pointer. */ word ibd_end; /* internal BD end pointer. */ word tx_len; /* tx frame length counter */ byte ibd_base[0x20]; /* internal micro code usage. */ dword iaddr_h; /* individual address filter, high */ dword iaddr_l; /* individual address filter, low */ word minflr; /* minimum frame length reg */ word taddr_h; /* temp address (MSB) */ word taddr_m; /* temp address */ word taddr_l; /* temp address (LSB) */ word pad_ptr; /* pad_ptr. */ byte RESERVED1[0x2]; /* Reserved area */ word cf_range; /* flow control frame range. */ word max_b; /* max buffer descriptor byte count. */ word maxd1; /* max DMA1 length register. */ word maxd2; /* max DMA2 length register. */ word maxd; /* Rx max DMA. */ word dma_cnt; /* Rx DMA counter. */ /* counter: */ dword octc; /* received octets counter. */ dword colc; /* estimated number of collisions */ dword broc; /* received good packets of broadcast address */ dword mulc; /* received good packets of multicast address */ dword uspc; /* received packets shorter then 64 octets. */ dword frgc; /* as uspc + bad packets */ dword ospc; /* received packets longer then 1518 octets. */ dword jbrc; /* as ospc + bad packets */ dword p64c; /* received packets of 64 octets.. */ dword p65c; /* received packets of 65-128 octets.. */ dword p128c; /* received packets of 128-255 octets.. */ dword p256c; /* received packets of 256-511 octets.. */ dword p512c; /* received packets of 512-1023 octets.. */ dword p1024c; /* received packets of 1024-1518 octets.. */ dword cam_buf; /* cam respond internal buffer. */ word rfthr; /* received frames threshold */ word rfcnt; /* received frames count */ } t_EnetFcc_Pram; typedef struct { /* cpm_ram */ byte mch_pram[0x4000]; volatile byte RESERVED0[0x4000]; /* Reserved area */ /* DPR_BASE+0x8000*/ union { struct serials { byte scc_pram[4][0x100]; byte fcc_pram[3][0x100]; byte mcc_pram[2][0x100]; volatile byte RESERVED1[0x700]; } serials; struct atm{ volatile unsigned char RESERVED2[0x400]; volatile unsigned char atm_pram[0x100]; volatile unsigned char RESERVED3[0xa00]; } atm; struct general{ volatile byte scc1[0x100]; volatile byte scc2[0x100]; volatile byte scc3[0x100]; volatile byte scc4[0x100]; volatile byte fcc1[0x100]; volatile byte fcc2[0x100]; volatile byte fcc3[0x100]; volatile byte mcc1[0x80]; volatile byte RESERVED_0[0x7c]; volatile word smc1; volatile word idma1; volatile byte mcc2[0x80]; volatile byte RESERVED_1[0x7c]; volatile word smc2; volatile word idma2; volatile byte RESERVED_2[0xfc]; volatile byte spi[0x2]; volatile word idma3; volatile byte RESERVED_3[0xe0]; volatile byte timers[0x10]; volatile byte Rev_num[0x2]; volatile byte D_ptr[0x2]; volatile byte RESERVED_4[0x4]; volatile byte rand[0x4]; volatile byte i2c[0x2]; volatile word idma4; volatile byte RESERVED_5[0x500]; }general; } pram; volatile byte RESERVED11[0x2000]; /* Reserved area */ volatile byte cpm_ram_dpram_2[0x1000]; /* Internal RAM */ volatile byte RESERVED12[0x4000]; /* Reserved area */ /* siu */ volatile dword siu_siumcr; /* SIU Module Configuration Register */ volatile dword siu_sypcr; /* System Protection Control Register */ volatile byte RESERVED13[0x6]; /* Reserved area */ volatile word siu_swsr; /* Software Service Register */ volatile byte RESERVED14[0x14]; /* Reserved area */ volatile dword bcr; /* Bus Configuration Register */ volatile byte ppc_acr; /* Arbiter Configuration Register */ volatile byte RESERVED15[0x3]; /* Reserved area */ volatile dword ppc_alrh; /* Arbitration level Register (First clients)*/ volatile dword ppc_alrl; /* Arbitration Level Register (Next clients) */ volatile byte lcl_acr; /* LCL Arbiter Configuration Register */ volatile byte RESERVED16[0x3]; /* Reserved area */ volatile dword lcl_alrh; /* LCL Arbitration level Register (First clients)*/ volatile dword lcl_alrl; /* LCL Arbitration Level Register (Next clients) */ volatile dword tescr1; /* PPC bus transfer error status control register 1 */ volatile dword tescr2; /* PPC bus transfer error status control register 2 */ volatile dword ltescr1; /* Local bus transfer error status control register 1 */ volatile dword ltescr2; /* Local bus transfer error status control register 2 */ volatile dword pdtea; /* PPC bus DMA Transfer Error Address */ volatile byte pdtem; /* PPC bus DMA Transfer Error MSNUM */ volatile byte RESERVED17[0x3]; volatile dword ldtea; /* PPC bus DMA Transfer Error Address */ volatile byte ldtem; /* PPC bus DMA Transfer Error MSNUM */ volatile byte RESERVED18[0xa3]; /* Reserved area */ /* memc */ struct mem_regs { volatile dword memc_br; /* Base Register */ volatile dword memc_or; /* Option Register */ } mem_regs[12]; volatile byte RESERVED19[0x8]; /* Reserved area */ volatile dword memc_mar; /* Memory Address Register */ volatile byte RESERVED20[0x4]; /* Reserved area */ volatile dword memc_mamr; /* Machine A Mode Register */ volatile dword memc_mbmr; /* Machine B Mode Register */ volatile dword memc_mcmr; /* Machine C Mode Register */ volatile dword memc_mdmr; /* Machine D Mode Register */ volatile byte RESERVED21[0x4]; /* Reserved area */ volatile word memc_mptpr; /* Memory Periodic Timer Prescaler */ volatile byte RESERVED22[0x2]; /* Reserved area */ volatile dword memc_mdr; /* Memory Data Register */ volatile byte RESERVED23[0x4]; /* Reserved area */ volatile dword memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */ volatile dword memc_lsdmr; /* Local Bus SDRAM machine Mode Registe */ volatile byte memc_purt; /* PowerPC Bus assigned UPM Refresh Timer */ volatile byte RESERVED24[0x3]; /* Reserved area */ volatile byte memc_psrt; /* PowerPC BusBus assigned SDRAM Refresh Timer */ volatile byte RESERVED25[0x3]; /* Reserved area */ volatile byte memc_lurt; /* Local Bus assigned UPM Refresh Timer */ volatile byte RESERVED26[0x3]; /* Reserved area */ volatile byte memc_lsrt; /* Local Bus assigned SDRAM Refresh Timer */ volatile byte RESERVED27[0x3]; /* Reserved area */ volatile dword memc_immr; /* Internal Memory Map Register */ volatile dword pcibr0; volatile dword pcibr1; volatile byte RESERVED28[0x10]; /* Reserved area */ volatile dword pcimsk0; volatile dword pcimsk1; volatile byte RESERVED29[0x54]; /* Reserved area */ /* si_timers */ volatile word si_timers_tmcntsc; /* Time Counter Status and Control Register */ volatile byte RESERVED30[0x2]; /* Reserved area */ volatile dword si_timers_tmcnt; /* Time Counter Register */ volatile dword si_timers_tmcntsec; /* Time Counter Seconds*/ volatile dword si_timers_tmcntal; /* Time Counter Alarm Register */ volatile byte RESERVED31[0x10]; /* Reserved area */ volatile word si_timers_piscr; /* Periodic Interrupt Status and Control Register */ volatile byte RESERVED32[0x2]; /* Reserved area */ volatile dword si_timers_pitc; /* Periodic Interrupt Count Register */ volatile dword si_timers_pitr; /* Periodic Interrupt Timer Register */ volatile byte RESERVED33[0x54]; /* Reserved area */ volatile dword tstmhr; volatile dword tstmlr; volatile word tster; volatile byte RESERVED34[0x156]; /* Reserved area */ /* pci */ volatile dword pci_pci; /* PCI Configuration space */ volatile byte RESERVED35[0x7fc]; /* Reserved area */ /* ic */ volatile word ic_sicr; /* Interrupt Configuration Register */ volatile byte RESERVED36[0x2]; /* Reserved area */ volatile dword ic_sivec; /* CP Interrupt Vector Register */ volatile dword ic_sipnr_h; /* Interrupt Pending Register (HIGH) */ volatile dword ic_sipnr_l; /* Interrupt Pending Register (LOW) */ volatile dword ic_siprr; /* SIU Interrupt Priority Register */ volatile dword ic_scprr_h; /* Interrupt Priority Register (HIGH) */ volatile dword ic_scprr_l; /* Interrupt Priority Register (LOW) */ volatile dword ic_simr_h; /* Interrupt Mask Register (HIGH) */ volatile dword ic_simr_l; /* Interrupt Mask Register (LOW) */ volatile dword ic_siexr; /* External Interrupt Control Register */ volatile byte RESERVED37[0x58]; /* Reserved area */ /* clocks */ volatile dword clocks_sccr; /* System Clock Control Register */ volatile byte RESERVED38[0x4]; /* Reserved area */ volatile dword clocks_scmr; /* System Clock Mode Register */ volatile byte RESERVED39[0x4]; /* Reserved area */ volatile dword clocks_rsr; /* Reset Status Register */ volatile dword clocks_rmr; /* Reset Moode Register */ volatile byte RESERVED40[0x68]; /* Reserved area */ /* io_port */ struct io_regs { volatile dword io_port_pdir; /* Port A-D Data Direction Register */ volatile dword io_port_ppar; /* Port A-D Pin Assignment Register */ volatile dword io_port_psor; /* Port A-D Special Operation Register */ volatile dword io_port_podr; /* Port A-D Open Drain Register */ volatile dword io_port_pdat; /* Port A-D Data Register */ volatile byte RESERVED41[0xc]; } io_regs[4]; /* cpm_timers */ volatile byte cpm_timers_tgcr1; /* Timer Global Configuration Register */ volatile byte RESERVED42[0x3]; /* Reserved area */ volatile byte cpm_timers_tgcr2; /* Timer Global Configuration Register */ volatile byte RESERVED43[0xb]; /* Reserved area */ volatile word cpm_timers_tmr1; /* Timer Mode Register */ volatile word cpm_timers_tmr2; /* Timer Mode Register */ volatile word cpm_timers_trr1; /* Timer Reference Register */ volatile word cpm_timers_trr2; /* Timer Reference Register */ volatile word cpm_timers_tcr1; /* Timer Capture Register */ volatile word cpm_timers_tcr2; /* Timer Capture Register */ volatile word cpm_timers_tcn1; /* Timer Counter */ volatile word cpm_timers_tcn2; /* Timer Counter */ volatile word cpm_timers_tmr3; /* Timer Mode Register */ volatile word cpm_timers_tmr4; /* Timer Mode Register */ volatile word cpm_timers_trr3; /* Timer Reference Register */ volatile word cpm_timers_trr4; /* Timer Reference Register */ volatile word cpm_timers_tcr3; /* Timer Capture Register */ volatile word cpm_timers_tcr4; /* Timer Capture Register */ volatile word cpm_timers_tcn3; /* Timer Counter */ volatile word cpm_timers_tcn4; /* Timer Counter */ volatile word cpm_timers_ter[4]; /* Timer Event Register */ volatile byte RESERVED44[0x260]; /* Reserved area */ /* sdma general */ volatile byte sdma_sdsr; /* SDMA Status Register */ volatile byte RESERVED45[0x3]; /* Reserved area */ volatile byte sdma_sdmr; /* SDMA Mask Register */ volatile byte RESERVED46[0x3]; /* Reserved area */ /* idma */ volatile byte idma_idsr1; /* IDMA Status Register */ volatile byte RESERVED47[0x3]; /* Reserved area */ volatile byte idma_idmr1; /* IDMA Mask Register */ volatile byte RESERVED48[0x3]; /* Reserved area */ volatile byte idma_idsr2; /* IDMA Status Register */ volatile byte RESERVED49[0x3]; /* Reserved area */ volatile byte idma_idmr2; /* IDMA Mask Register */ volatile byte RESERVED50[0x3]; /* Reserved area */ volatile byte idma_idsr3; /* IDMA Status Register */ volatile byte RESERVED51[0x3]; /* Reserved area */ volatile byte idma_idmr3; /* IDMA Mask Register */ volatile byte RESERVED52[0x3]; /* Reserved area */ volatile byte idma_idsr4; /* IDMA Status Register */ volatile byte RESERVED53[0x3]; /* Reserved area */ volatile byte idma_idmr4; /* IDMA Mask Register */ volatile byte RESERVED54[0x2c3]; /* Reserved area */ /* fcc */ struct fcc_regs { volatile dword fcc_gfmr; /* FCC General Mode Register */ volatile dword fcc_psmr; /* FCC Protocol Specific Mode Register */ volatile word fcc_todr; /* FCC Transmit On Demand Register */ volatile byte RESERVED55[0x2]; /* Reserved area */ volatile word fcc_dsr; /* FCC Data Sync. Register */ volatile byte RESERVED56[0x2]; /* Reserved area */ volatile word fcc_fcce; /* FCC Event Register */ volatile word res1; volatile word fcc_fccm; /* FCC Mask Register */ volatile word res2; volatile byte fcc_fccs; /* FCC Status Register */ volatile byte RESERVED57[0x3]; /* Reserved area */ volatile dword fcc_ftirr; /* FCC Transmit Internal Rate Register */ } fcc_regs[3]; volatile byte RESERVED58[0x290]; /* Reserved area */ /* brgs_5_ */ volatile dword brgs_5__brgc5; /* BRG Configuration Register */ volatile dword brgs_5__brgc6; /* BRG Configuration Register */ volatile dword brgs_5__brgc7; /* BRG Configuration Register */ volatile dword brgs_5__brgc8; /* BRG Configuration Register */ volatile byte RESERVED59[0x260]; /* Reserved area */ /* i2c */ volatile byte i2c_i2mod; /* IC Mode Register */ volatile byte RESERVED60[0x3]; /* Reserved area */ volatile byte i2c_i2add; /* IC Address Register */ volatile byte RESERVED61[0x3]; /* Reserved area */ volatile byte i2c_i2brg; /* IC BRG Register */ volatile byte RESERVED62[0x3]; /* Reserved area */ volatile byte i2c_i2com; /* IC Command Register */ volatile byte RESERVED63[0x3]; /* Reserved area */ volatile byte i2c_i2cer; /* IC Event Register */ volatile byte RESERVED64[0x3]; /* Reserved area */ volatile byte i2c_i2cmr; /* IC Mask Register */ volatile byte RESERVED65[0x14b]; /* Reserved area */ /* cpm */ volatile dword cpm_cpcr; /* Communication Processor Command Register */ volatile dword cpm_rccr; /* RISC Configuration Register */ volatile dword cpm_rmdr; /* RISC Microcode Development Support Control Register */ volatile word cpm_rctr1; /* RISC Controller Trap Register */ volatile word cpm_rctr2; /* RISC Controller Trap Register */ volatile word cpm_rctr3; /* RISC Controller Trap Register */ volatile word cpm_rctr4; /* RISC Controller Trap Register */ volatile byte RESERVED66[0x2]; /* Reserved area */ volatile word cpm_rter; /* RISC Timers Event Register */ volatile byte RESERVED67[0x2]; /* Reserved area */ volatile word cpm_rtmr; /* RISC Timers Mask Register */ volatile word cpm_rtscr; /* RISC Time-Stamp Timer Control Register */ volatile word cpm_rmds; /* RISC Development Support Status Register */ volatile dword cpm_rtsr; /* RISC Time-Stamp Register */ volatile byte RESERVED68[0xc]; /* Reserved area */ /* brgs_1_ */ volatile dword brgs_1__brgc1; /* BRG Configuration Register */ volatile dword brgs_1__brgc2; /* BRG Configuration Register */ volatile dword brgs_1__brgc3; /* BRG Configuration Register */ volatile dword brgs_1__brgc4; /* BRG Configuration Register */ /* scc */ struct scc_regs2 { volatile dword scc_gsmr_l; /* SCC General Mode Register */ volatile dword scc_gsmr_h; /* SCC General Mode Register */ volatile word scc_psmr; /* SCC Protocol Specific Mode Register */ volatile byte RESERVED69[0x2]; /* Reserved area */ volatile word scc_todr; /* SCC Transmit-On-Demand Register */ volatile word scc_dsr; /* SCC Data Synchronization Register */ volatile word scc_scce; /* SCC Event Register */ volatile byte RESERVED70[0x2]; /* Reserved area */ volatile word scc_sccm; /* SCC Mask Register */ volatile byte RESERVED71; /* Reserved area */ volatile byte scc_sccs; /* SCC Status Register */ volatile byte RESERVED72[0x8]; /* Reserved area */ } scc_regs[4]; /* smc */ struct smc_regs2 { volatile byte RESERVED73[0x2]; /* Reserved area */ volatile word smc_smcmr; /* SMC Mode Register */ volatile byte RESERVED74[0x2]; /* Reserved area */ volatile byte smc_smce; /* SMC Event Register */ volatile byte RESERVED75[0x3]; /* Reserved area */ volatile byte smc_smcm; /* SMC Mask Register */ volatile byte RESERVED76[0x5]; /* Reserved area */ } smc_regs[2]; /* spi */ volatile word spi_spmode; /* SPI Mode Register */ volatile byte RESERVED77[0x4]; /* Reserved area */ volatile byte spi_spie; /* SPI Event Register */ volatile byte RESERVED78[0x3]; /* Reserved area */ volatile byte spi_spim; /* SPI Mask Register */ volatile byte RESERVED79[0x2]; /* Reserved area */ volatile byte spi_spcom; /* SPI Command Register */ volatile byte RESERVED80[0x52]; /* Reserved area */ /* cpm_mux */ volatile byte cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */ volatile byte RESERVED81; /* Reserved area */ volatile byte cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */ volatile byte RESERVED82; /* Reserved area */ volatile dword cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */ volatile dword cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */ volatile byte cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */ volatile byte RESERVED83; /* Reserved area */ volatile word cpm_mux_cmxuar; /* CPM MUX UTOPIA Address Register */ volatile byte RESERVED84[0x10]; /* Reserved area */ /* si */ struct si_regs { volatile word si_simr[4]; /* SI TDM Mode Registers */ volatile byte si_sigmr; /* SI Global Mode Register */ volatile byte RESERVED85; /* Reserved area */ volatile byte si_sicmdr; /* SI Command Register */ volatile byte RESERVED86; /* Reserved area */ volatile byte si_sistr; /* SI Status Register */ volatile byte RESERVED87; /* Reserved area */ volatile word si_sirsr; /* SI RAM Shadow Address Register */ volatile word mcc_mcce; volatile byte RESERVED88[0x2]; /* Reserved area */ volatile word mcc_mccm; volatile byte RESERVED89[0x2]; /* Reserved area */ volatile byte mcc_mccf; volatile byte RESERVED90[0x7]; /* Reserved area */ } si_regs[2]; volatile byte RESERVED91[0x4a0]; /* Reserved area */ /* si_ram */ struct si_ram { word si_ram_si_tx_ram[0x100]; /* SI Transmit Routing RAM */ volatile byte RESERVED92[0x200]; /* Reserved area */ word si_ram_si_rx_ram[0x100]; /* SI Receive Routing RAM */ volatile byte RESERVED93[0x200]; /* Reserved area */ } si_ram[2]; volatile byte RESERVED94[0x1000]; /* Reserved area */ } POWERQUICCII; #define PORTA 0 /* Index into Parallel I/O Regs Array */ #define PORTB 1 /* Index into Parallel I/O Regs Array */ #define PORTC 2 /* Index into Parallel I/O Regs Array */ #define PORTD 3 /* Index into Parallel I/O Regs Array */ #define CMD_FLAG2 0x00010000 #define SOFTWARE_RESET2 0x80000000 #define CMD_PAGE_FCC1 0x10000000 #define CMD_PAGE_FCC2 0x16200300 /************************************************************************** Common Definitions **************************************************************************/ #define INIT_RXTX_PARAMS 0x0000 #define GR_STOP_TX 0x0500 #define RESTART_TX 0x0600 /***************************************************************** tbase and rbase registers *****************************************************************/ #define TBD_ADDR2(quicc,pram) ((struct quicc_bd *) pram->FccPram.tbase) #define RBD_ADDR2(quicc,pram) ((struct quicc_bd *) pram->FccPram.rbase) #define TBD_CUR_ADDR2(quicc,pram) ((struct quicc_bd *) pram->FccPram.tbptr) #define RBD_CUR_ADDR2(quicc,pram) ((struct quicc_bd *) pram->FccPram.rbptr) #define TBD_SET_CUR_ADDR2(bd,quicc,pram) pram->FccPram.tbptr = (dword)(bd) #define RBD_SET_CUR_ADDR2(bd,quicc,pram) pram->FccPram.rbptr = (dword)(bd) #define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \ (quicc->udata_bd_ucode + pram->tbase)) #define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \ (quicc->udata_bd_ucode + pram->rbase)) #define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ (quicc->udata_bd_ucode + pram->tbptr)) #define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ (quicc->udata_bd_ucode + pram->rbptr)) #define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \ ((unsigned short)((char *)(bd) - (char *)(quicc->udata_bd_ucode))) #define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \ ((unsigned short)((char *)(bd) - (char *)(quicc->udata_bd_ucode))) #define INCREASE_TBD(bd,first) { \ if((bd)->status & T_W) \ (bd) = (first); \ else \ (bd)++; \ } #define DECREASE_TBD(bd,first) { \ if ((bd) == (first)) \ while (!((bd)->status & T_W)) \ (bd)++; \ else \ (bd)--; \ } #define INCREASE_RBD(bd,first) { \ if((bd)->status & R_W) \ (bd) = (first); \ else \ (bd)++; \ } /* Buffer Descriptors */ typedef struct quicc_bd { volatile unsigned short status; volatile unsigned short length; volatile unsigned char *buf; } QUICC_BD; /* * transmit BD's */ #define T_R 0x8000 /* ready bit */ #define T_PAD 0x4000 /* short frame padding */ #define T_W 0x2000 /* wrap bit */ #define T_I 0x1000 /* interrupt on completion */ #define T_L 0x0800 /* last in frame */ #define T_TC 0x0400 /* transmit CRC (when last) */ #define T_DEF 0x0200 /* defer indication */ #define T_HB 0x0100 /* heartbeat */ #define T_LC 0x0080 /* error: late collision */ #define T_RL 0x0040 /* error: retransmission limit */ #define T_RC 0x003c /* retry count */ #define T_UN 0x0002 /* error: underrun */ #define T_CSL 0x0001 /* carier sense lost */ #define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL) /* * receive BD's */ #define R_E 0x8000 /* buffer empty */ #define R_W 0x2000 /* wrap bit */ #define R_I 0x1000 /* interrupt on reception */ #define R_L 0x0800 /* last BD in frame */ #define R_MISS 0x0100 /* miss (FEC only) */ #define R_LG 0x0020 /* frame too long */ #define R_NO 0x0010 /* non-octet aligned */ #define R_SH 0x0008 /* short frame */ #define R_CR 0x0004 /* receive CRC error */ #define R_OV 0x0002 /* receive overrun */ #define R_CL 0x0001 /* collision/truncated */ #define R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL) /* * ethernet interrupts */ #define ETHERNET_GRA 0x0080 /* graceful stop complete */ #define ETHERNET_TXE 0x0010 /* transmit error */ #define ETHERNET_RXF 0x0008 /* receive frame */ #define ETHERNET_BSY 0x0004 /* busy condition */ #define ETHERNET_TXB 0x0002 /* transmit buffer */ #define ETHERNET_RXB 0x0001 /* receive buffer */ /* * ethernet specific parameters */ #define MRBLR 1520 /* Max ethernet frame length (aligned to to 4) */ #define MRBLR32 0x600 /* Max ethernet frame length (aligned to to 32) */ #define MFLR 0x05ee /* 1518 max frame size */ #define net2hs(x) (x) #define hs2net(x) (x) /************************************************************************** BASIC ADDRESS TYPES **************************************************************************/ typedef struct { word w[2]; } ipaddr; typedef struct { word w[3]; } etheraddr; #define IPADDR_NEQ(a,b) ((a).w[0] != (b).w[0] || (a).w[1] != (b).w[1] ) #define ETHERADDR_IS_MULTICAST(a) (((a).w[0] & 0x8000)) /************************************************************************** UDP-PACKETS **************************************************************************/ #define MAXUDPDATA 1024 #define UDPHLEN 8 struct iudp { word srcprt; /* source port */ word dstprt; /* destination port */ word length; /* length */ word cksum; /* checksum */ byte data[MAXUDPDATA]; /* raw data */ }; /************************************************************************** ICMP-PACKETS **************************************************************************/ #define ICRPECH 0 /* Echo Reply */ #define ICRQECH 8 /* Echo request */ struct icmp { byte ic_typ; /* ICMP message type */ byte ic_code; /* Code */ word ic_cksum; /* Checksum of header */ word ic_id; /* for echo type, a message id */ word ic_seq; /* for echo type, a seq. num */ byte ic_data[1]; /* data area of ICMP */ }; /************************************************************************** ARP-PACKETS **************************************************************************/ #define AR_HRD 1 /* Ethernet hardware type code */ #define AR_PROT 0x0800 /* IP protocol address code */ #define AR_HLEN 6 /* Ethernet physical address length */ #define AR_PLEN 4 /* IP Protocol address length */ #define AR_TAB 6 /* size of IP to Ether addr. cache */ #define AR_TIME 60 /* time to wait for reply in 100 ms */ #define AR_RTRY 2 /* number of times to retry ARPs */ #define AR_REQ 1 /* arp request to resolve address */ #define AR_RPLY 2 /* reply to a resolve request */ #define AR_RREQ 3 /* reverse ARP request */ #define AR_RRLY 4 /* reply to a RARP */ typedef struct arppak { word ar_hrd; word ar_prot; byte ar_hlen; byte ar_plen; word ar_op; etheraddr ar_sha; ipaddr ar_spa; etheraddr ar_tha; ipaddr ar_tpa; } arppak; /************************************************************************** IP-PACKETS **************************************************************************/ /* IP Packet: min: 46 bytes max: 1500 Vers Len Type TLen ID Flags Frag Time Proto Chk Src Dst Opt Pad Data .5 .5 1 2 2 .5 1.5 1 1 2 4 4 0 0 26-1480 */ #define IPTMASK 0300 /* Mask for IP type in top byte */ #define IPATYP 0000 /* IP Class A address */ #define IPBTYP 0200 /* IP Class B address */ #define IPCTYP 0300 /* IP Class C address */ #define IPHLEN 20 /* IP datagram header length */ #define IMAXLEN 1400 /* Max IP datagram */ #define IPRO_ICMP 1 /* Protocol type for ICMP */ #define IPRO_TCP 6 /* Protocol type for ICMP */ #define IPRO_UDP 17 /* Protocol type for UDP packets */ #define IVERLEN 0x45 /* current version length field */ #define ISVCTYP '\0' /* Service type for normal service */ #define IFRAGOFF 0 /* Fragment offset (0 for no frag */ #define ITIM2LIV 10 /* Initial time-to-live */ #define MAXIPDATA 1480 struct ip { byte i_verlen; /* IP version */ byte i_svctyp; /* Service type */ word i_paclen; /* Packet length in bytes */ word i_id; /* datagram ID for fragmentation */ word i_fragoff; /* Fragment offset */ byte i_tim2liv; /* time to live in gateway hops */ byte i_proto; /* IP protocol */ word i_cksum; /* 1's compl. of sum of shorts (header) */ ipaddr i_src; /* IP address of source */ ipaddr i_dest; /* IP address of destination */ union { struct iudp i_udp; struct icmp i_icmp; byte data[MAXIPDATA]; } i_data; /* IP datagram data area */ }; /************************************************************************** ETHERNET-PACKETS **************************************************************************/ /* Ethernet Frame: min: 72 bytes max: 1526 bytes Preamble Destination Source Type Data CRC 8 bytes 6 bytes 6 bytes 2 bytes 46-1500 bytes 4 bytes */ #define EHLEN 14 /* Ethernet header length */ #define MINTRANSMIT 60 /* minimum Ethernet transmit size */ #define MAXETHERDATA 1500 #define EP_RAW 0x0000 /* Raw packet */ #define EP_LOOP 0x0060 /* Loopback packet */ #define EP_ECHO 0x0200 /* Echo */ #define EP_PUP 0x0201 /* Xerox PUP */ #define EP_IP 0x0800 /* DARPA Internet protocol */ #define EP_ARP 0x0806 /* ARP packet */ #define EP_RARP 0x8035 /* reverse ARP packet */ typedef struct eheader { etheraddr e_dest; /* Destination address */ etheraddr e_src; /* Source address */ word e_ptype; /* Ethernet packet type */ } eheader; typedef struct epacket { struct eheader ep_hdr; /* packet header */ union { struct ip ep_ip; struct arppak ep_arp; byte raw[MAXETHERDATA+8]; } ep_data; } epacket;