/******************************************************************************* * Freescale Semiconductor Inc. * (c) Copyright 2014 Freescale Semiconductor, Inc. * ALL RIGHTS RESERVED. ******************************************************************************** Services performed by FREESCALE in this matter are performed AS IS and without any warranty. CUSTOMER retains the final decision relative to the total design and functionality of the end product. FREESCALE neither guarantees nor will be held liable by CUSTOMER for the success of this project. FREESCALE DISCLAIMS ALL WARRANTIES, EXPRESSED, IMPLIED OR STATUTORY INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ON ANY HARDWARE, SOFTWARE ORE ADVISE SUPPLIED TO THE PROJECT BY FREESCALE, AND OR NAY PRODUCT RESULTING FROM FREESCALE SERVICES. IN NO EVENT SHALL FREESCALE BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT. CUSTOMER agrees to hold FREESCALE harmless against any and all claims demands or actions by anyone on account of any damage, or injury, whether commercial, contractual, or tortuous, rising directly or indirectly as a result of the advise or assistance supplied CUSTOMER in connection with product, services or goods supplied under this Agreement. ******************************************************************************** * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL *******************************************************************************/ /******************************************************************************* * Includes *******************************************************************************/ #include "stdint.h" typedef volatile uint8_t vuint8_t; typedef volatile uint16_t vuint16_t; typedef volatile uint32_t vuint32_t; /******************************************************************************* * Constants and macros *******************************************************************************/ #define DRUN_MODE 0x3 /******************************************************************************* * External objects *******************************************************************************/ extern void _start(void); /******************************************************************************* * declarations from MPC5748G_401.h *******************************************************************************/ /* =============================== Module: PFLASH ============================= */ struct MC_CGM_tag { uint8_t MC_CGM_reserved0[384]; union { /* Clockout 1 Select Register */ vuint32_t R; struct { vuint32_t :4; vuint32_t SELCTL:4; /* CLKOUT1 Source Select */ vuint32_t :24; } B; } CLKOUT1_SC; uint8_t MC_CGM_reserved[4]; union { /* CLKOUT1_DC Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; /* CLKOUT1_DC enable */ vuint32_t :4; vuint32_t DIV:11; /* Divider */ vuint32_t :16; } B; } CLKOUT1_DC; uint8_t MC_CGM_reserved1[52]; union { /* Auxiliary Clock 5 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC5_SC; union { /* Auxiliary Clock 5 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELSTAT:1; vuint32_t :24; } B; } AC5_SS; uint8_t MC_CGM_reserved2[56]; union { /* System Clock Divider 6 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :12; vuint32_t DIV:3; /* Divider */ vuint32_t :16; } B; } SC_DC6; uint8_t MC_CGM_reserved3[60]; union { /* Auxiliary Clock 7 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC7_SC; union { /* Auxiliary Clock 7 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC7_SS; uint8_t MC_CGM_reserved4[56]; union { /* Auxiliary Clock 8 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC8_SC; union { /* Auxiliary Clock 8 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC8_SS; uint8_t MC_CGM_reserved5[56]; union { /* Auxiliary Clock 9 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC9_SC; union { /* Auxiliary Clock 9 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC9_SS; uint8_t MC_CGM_reserved6[1080]; union { /* PCS Switch Duration Register */ vuint8_t R; struct { vuint8_t SDUR:8; } B; } PCS_SDUR; uint8_t MC_CGM_reserved7[3]; union { /* PCS Divider Change Register 1 */ vuint32_t R; struct { vuint32_t INIT:16; vuint32_t :8; vuint32_t RATE:8; } B; } PCS_DIVC1; union { /* PCS Divider End Register 1 */ vuint32_t R; struct { vuint32_t :12; vuint32_t DIVE:20; } B; } PCS_DIVE1; union { /* PCS Divider Start Register 1 */ vuint32_t R; struct { vuint32_t :12; vuint32_t DIVS:20; } B; } PCS_DIVS1; union { /* PCS Divider Change Register 2 */ vuint32_t R; struct { vuint32_t INIT:16; vuint32_t :8; vuint32_t RATE:8; } B; } PCS_DIVC2; union { /* PCS Divider End Register 2 */ vuint32_t R; struct { vuint32_t :12; vuint32_t DIVE:20; } B; } PCS_DIVE2; union { /* PCS Divider Start Register 2 */ vuint32_t R; struct { vuint32_t :12; vuint32_t DIVS:20; } B; } PCS_DIVS2; uint8_t MC_CGM_reserved8[176]; union { /* Divider Update Abort Register */ vuint32_t R; struct { vuint32_t :31; vuint32_t DIV_UPD_ABRTD:1; } B; } DIV_UPD_ABRTD; union { /* System Clock Divider Ratio Change Register */ vuint32_t R; struct { vuint32_t :30; vuint32_t HALT_ABORT_DIS:1; vuint32_t SYS_DIV_RATIO_CHNG:1; } B; } SC_DIV_RC; union { /* Divider Update Type Register */ vuint32_t R; struct { vuint32_t SYS_UPD_TYPE:1; /* System Clock Divider Update Type */ vuint32_t :24; vuint32_t AUX_UPD_TYPE:1; /* Auxiliary Clock Divider Update Type */ vuint32_t :6; } B; } DIV_UPD_TYPE; union { /* Divider Update Trigger Register */ vuint32_t R; struct { vuint32_t DIV_UPD_TRIGGER:32; } B; } DIV_UPD_TRIG; union { /* Divider Update Status Register */ vuint32_t R; struct { vuint32_t SYS_UPD_STAT:1; /* System Clock Divider Update Status */ vuint32_t :24; vuint32_t AUX_UPD_STAT:1; /* Auxiliary Clock Divider Status Type */ vuint32_t :6; } B; } DIV_UPD_STAT; uint8_t MC_CGM_reserved9[4]; union { /* System Clock Select Status Register */ vuint32_t R; struct { vuint32_t :4; vuint32_t SELSTAT:4; vuint32_t :4; vuint32_t SWTRG:3; vuint32_t SWIP:1; vuint32_t :16; } B; } SC_SS; union { /* System Clock Divider 0 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :12; vuint32_t DIV:3; vuint32_t :16; } B; } SC_DC0; union { /* System Clock Divider 1 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :12; vuint32_t DIV:3; vuint32_t :16; } B; } SC_DC1; union { /* System Clock Divider 2 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :11; vuint32_t DIV:4; vuint32_t :16; } B; } SC_DC2; union { /* System Clock Divider 3 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :13; vuint32_t DIV:2; vuint32_t :16; } B; } SC_DC3; union { /* System Clock Divider 4 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :13; vuint32_t DIV:2; vuint32_t :16; } B; } SC_DC4; union { /* System Clock Divider 5 Configuration Register */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :12; vuint32_t DIV:3; vuint32_t :16; } B; } SC_DC5; uint8_t MC_CGM_reserved10[64]; union { /* Auxiliary Clock 2 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELSTAT:1; vuint32_t :24; } B; } AC2_SC; union { /* Auxiliary Clock 2 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELSTAT:1; vuint32_t :24; } B; } AC2_SS; uint8_t MC_CGM_reserved12[24]; union { /* Auxiliary Clock 3 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC3_SC; union { /* Auxiliary Clock 3 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELSTAT:1; vuint32_t :24; } B; } AC3_SS; uint8_t MC_CGM_reserved13[24]; union { /* Auxiliary Clock 4 Select Control Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELCTL:1; vuint32_t :24; } B; } AC4_SC; union { /* Auxiliary Clock 4 Select Status Register */ vuint32_t R; struct { vuint32_t :7; vuint32_t SELSTAT:1; vuint32_t :24; } B; } AC4_SS; uint8_t MC_CGM_reserved14[56]; union { /* Auxiliary Clock 6 Select Control Register */ vuint32_t R; struct { vuint32_t :4; vuint32_t SELCTL:4; vuint32_t :24; } B; } AC6_SC; union { /* Auxiliary Clock 6 Select Status Register */ vuint32_t R; struct { vuint32_t :4; vuint32_t SELSTAT:4; vuint32_t :24; } B; } AC6_SS; union { /* Aux Clock 6 Divider Configuration 0 for CLKOUT_0 */ vuint32_t R; struct { vuint32_t DE:1; vuint32_t :10; vuint32_t DIV:5; vuint32_t :16; } B; } AC6_DC0; }; /* =============================== Module: PIT ================================ */ struct MC_ME_tag { union { /* Global Status Register */ vuint32_t R; struct { vuint32_t S_CURRENT_MODE:4; vuint32_t S_MTRANS:1; vuint32_t :1; vuint32_t :2; vuint32_t S_PDO:1; vuint32_t :2; vuint32_t S_MVR:1; vuint32_t :2; vuint32_t S_FLA:2; vuint32_t :7; vuint32_t S_SXOSC:1; /* 32 KHz external oscillator status */ vuint32_t S_SIRCON:1; /* 128 KHz internal RC oscillator status */ vuint32_t S_PLLON:1; /* PLL status */ vuint32_t S_FXOSC:1; /* 8-40 MHz crystal oscillator status */ vuint32_t S_FIRCON:1; vuint32_t S_SYSCLK:4; } B; } GS; union { /* Mode Control Register */ vuint32_t R; struct { vuint32_t TARGET_MODE:4; /* Target chip mode */ vuint32_t :12; vuint32_t KEY:16; } B; } MCTL; union { /* Mode Enable Register */ vuint32_t R; struct { vuint32_t :16; vuint32_t RESET_DEST:1; vuint32_t :1; vuint32_t STANDBY0:1; /* STANDBY0 mode enable */ vuint32_t :2; vuint32_t STOP0:1; vuint32_t :1; vuint32_t :1; vuint32_t RUN3:1; vuint32_t RUN2:1; vuint32_t RUN1:1; vuint32_t RUN0:1; vuint32_t DRUN:1; vuint32_t SAFE:1; vuint32_t :1; vuint32_t RESET_FUNC:1; } B; } ME; union { /* Interrupt Status Register */ vuint32_t R; struct { vuint32_t :26; vuint32_t I_ICONF_CC:1; vuint32_t :1; vuint32_t I_ICONF:1; vuint32_t I_IMODE:1; vuint32_t I_SAFE:1; vuint32_t I_MTC:1; } B; } IS; union { /* Interrupt Mask Register */ vuint32_t R; struct { vuint32_t :26; vuint32_t M_ICONF_CC:1; vuint32_t :1; vuint32_t M_ICONF:1; vuint32_t M_IMODE:1; vuint32_t M_SAFE:1; vuint32_t M_MTC:1; } B; } IM; union { /* Invalid Mode Transition Status Register */ vuint32_t R; struct { vuint32_t :26; vuint32_t S_MRIG:1; vuint32_t S_MTI:1; vuint32_t S_MRI:1; vuint32_t S_DMA:1; vuint32_t S_NMA:1; vuint32_t S_SEA:1; } B; } IMTS; union { /* Debug Mode Transition Status Register */ vuint32_t R; struct { vuint32_t PREVIOUS_MODE:4; vuint32_t :4; vuint32_t MPH_BUSY:1; vuint32_t :2; vuint32_t PMC_PROG:1; vuint32_t DBG_MODE:1; vuint32_t CCKL_PROG:1; vuint32_t PCS_PROG:1; vuint32_t SMR:1; vuint32_t CDP_PRPH_0_255:1; /* Clock Disable Process Pending status for Peripherals 0…255 */ vuint32_t VREG_CSRC_SC:1; vuint32_t CSRC_CSRC_SC:1; vuint32_t IRC_SC:1; vuint32_t SCSRC_SC:1; vuint32_t SYSCLK_SW:1; vuint32_t :1; vuint32_t FLASH_SC:1; vuint32_t :4; vuint32_t CDP_PRPH_96_127:1; vuint32_t CDP_PRPH_64_95:1; vuint32_t CDP_PRPH_32_63:1; vuint32_t CDP_PRPH_0_31:1; } B; } DMTS; uint8_t MC_ME_reserved0[4]; union { /* RESET Mode Configuration Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t PWRLVL:3; vuint32_t :4; vuint32_t PDO:1; vuint32_t :2; vuint32_t MVRON:1; vuint32_t :2; vuint32_t FLAON:2; vuint32_t :7; vuint32_t SXOSCON:1; /* 32Khz external oscillator control */ vuint32_t SIRCON:1; vuint32_t PLLON:1; vuint32_t FXOSCON:1; vuint32_t FIRCON:1; vuint32_t SYSCLK:4; } B; } RESET_MC; uint8_t MC_ME_reserved1[4]; union { /* SAFE Mode Configuration Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t PWRLVL:3; vuint32_t :4; vuint32_t PDO:1; vuint32_t :2; vuint32_t MVRON:1; vuint32_t :2; vuint32_t FLAON:2; vuint32_t :7; vuint32_t SXOSCON:1; /* 32Khz external oscillator control */ vuint32_t SIRCON:1; vuint32_t PLLON:1; vuint32_t FXOSCON:1; vuint32_t FIRCON:1; vuint32_t SYSCLK:4; } B; } SAFE_MC; union { /* DRUN Mode Configuration Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t PWRLVL:3; vuint32_t :4; vuint32_t PDO:1; vuint32_t :2; vuint32_t MVRON:1; vuint32_t :2; vuint32_t FLAON:2; vuint32_t :7; vuint32_t SXOSCON:1; /* 32Khz external oscillator control */ vuint32_t SIRCON:1; vuint32_t PLLON:1; vuint32_t FXOSCON:1; vuint32_t FIRCON:1; vuint32_t SYSCLK:4; } B; } DRUN_MC; union { /* RUN0 Mode Configuration Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t PWRLVL:3; vuint32_t :4; vuint32_t PDO:1; vuint32_t :2; vuint32_t MVRON:1; vuint32_t :2; vuint32_t FLAON:2; vuint32_t :7; vuint32_t SXOSCON:1; /* 32 KHz external oscillator control */ vuint32_t SIRCON:1; vuint32_t PLLON:1; vuint32_t FXOSCON:1; vuint32_t FIRCON:1; vuint32_t SYSCLK:4; } B; } RUN_MC[4]; uint8_t MC_ME_reserved2[8]; union { /* STOP0 Mode Configuration Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t PWRLVL:3; vuint32_t :4; vuint32_t PDO:1; vuint32_t :2; vuint32_t MVRON:1; vuint32_t :2; vuint32_t FLAON:2; vuint32_t :7; vuint32_t SXOSCON:1; /* 32 KHz external oscillator control */ vuint32_t SIRCON:1; vuint32_t PLLON:1; vuint32_t FXOSCON:1; vuint32_t FIRCON:1; vuint32_t SYSCLK:4; } B; } STOP_MC; uint8_t MC_ME_reserved3[8]; union { /* STANDBY0 Mode Configuration Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t PWRLVL:3; vuint32_t :4; vuint32_t PDO:1; vuint32_t :2; vuint32_t MVRON:1; vuint32_t :2; vuint32_t FLAON:2; vuint32_t :7; vuint32_t SXOSCON:1; /* 32 KHz external oscillator control */ vuint32_t SIRCON:1; vuint32_t PLLON:1; vuint32_t FXOSCON:1; vuint32_t FIRCON:1; vuint32_t SYSCLK:4; } B; } STANDBY_MC; uint8_t MC_ME_reserved4[8]; union { /* Peripheral Status Register 0 */ vuint32_t R; struct { vuint32_t S_IIC_1:1; vuint32_t S_IIC_0:1; vuint32_t :1; vuint32_t S_FlexRay:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. */ vuint32_t :2; vuint32_t S_ADC_1:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active. */ vuint32_t S_ADC_0:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t :1; vuint32_t S_ACMP_2:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t S_ACMP_1:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t S_ACMP_0:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t :4; vuint32_t S_ENET:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t :2; vuint32_t S_SAI_2:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t S_SAI_1:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active. */ vuint32_t S_SAI_0:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t :2; vuint32_t S_SDHC:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t S_MLB:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t S_USB_SPH:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t S_USBOTG:1; vuint32_t S_eMIOS_2:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. */ vuint32_t S_eMIOS_1:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. */ vuint32_t S_eMIOS_0:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. */ vuint32_t S_BCTU:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ } B; } PS0; union { /* Peripheral Status Register 1 */ vuint32_t R; struct { vuint32_t S_LIN:14; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t :6; vuint32_t S_DSPI:4; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ vuint32_t :6; vuint32_t S_IIC:2; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. 0: Peripheral is frozen 1: Peripheral is active */ } B; } PS1; union { /* Peripheral Status Register 2 */ vuint32_t R; struct { vuint32_t :1; vuint32_t :1; vuint32_t S_WKPU:1; vuint32_t S_LPU_CTL:1; vuint32_t S_PIT_RTI_0:1; vuint32_t S_DMAMUX:1; /* Peripheral status - These bits specify the current status of each peripheral which is controlled by the MC_ME. */ vuint32_t :5; vuint32_t S_CRC:1; vuint32_t S_MEMU_0:1; vuint32_t S_JDC:1; vuint32_t S_TDM:1; vuint32_t :1; vuint32_t :2; vuint32_t S_FLEXCAN:8; vuint32_t :2; vuint32_t S_LIN:4; } B; } PS2; union { /* Peripheral Status Register 3 */ vuint32_t R; struct { vuint32_t :22; vuint32_t S_MEMU_1:1; vuint32_t :1; vuint32_t :1; vuint32_t S_RTC_API:1; vuint32_t S_SPI:6; } B; } PS3; uint8_t MC_ME_reserved5[16]; union { /* Run Peripheral Configuration Register */ vuint32_t R; struct { vuint32_t :24; vuint32_t RUN3:1; vuint32_t RUN2:1; vuint32_t RUN1:1; vuint32_t RUN0:1; vuint32_t DRUN:1; vuint32_t SAFE:1; vuint32_t :1; vuint32_t RESET:1; } B; } RUN_PC[8]; union { /* Low-Power Peripheral Configuration Register */ vuint32_t R; struct { vuint32_t :18; vuint32_t STANDBY0:1; /* Peripheral control during STANDBY0 */ vuint32_t :2; vuint32_t STOP0:1; vuint32_t :1; vuint32_t :1; vuint32_t :8; } B; } LP_PC[8]; /* Note on PCTL registers: There are only some PCTL implemented */ /* In order to make the PCTL easily addressable, these are defined */ /* as an array (ie ME.PCTL[x].R). This means you have to be careful */ /* when addressing these registers in order not to access a PCTL that */ /* is not implemented. Following are available: 0-7, 10-12, 15, 20-25, */ /* 28, 30-33, 40-43, 50-67, 70-77, 80-84, 90-91, 93-94, 96-102, 104 */ union { /* BCTU Peripheral Control Register */ vuint8_t R; struct { vuint8_t :1; vuint8_t DBG_F:1; vuint8_t LP_CFG:3; vuint8_t RUN_CFG:3; } B; } PCTL[104]; uint8_t MC_ME_reserved6[152]; union { /* Core Status Register */ vuint32_t R; struct { vuint32_t :28; vuint32_t S_CORE3:1; /* Core3 Status */ vuint32_t S_CORE2:1; /* Core2 Status */ vuint32_t S_CORE1:1; vuint32_t :1; } B; } CS; union { vuint16_t R; struct { vuint16_t :1; vuint16_t STANDBY0:2; vuint16_t :2; vuint16_t STOP0:1; vuint16_t :1; vuint16_t :1; vuint16_t RUN3:1; vuint16_t RUN2:1; vuint16_t RUN1:1; vuint16_t RUN0:1; vuint16_t DRUN:1; vuint16_t SAFE:1; vuint16_t :1; vuint16_t RESET:1; } B; } CCTL[4]; uint8_t MC_ME_reserved7[20]; union { vuint32_t R; struct { vuint32_t ADDR:30; vuint32_t :1; vuint32_t RMC:1; /* Reset on Mode Change */ } B; } CADDR[4]; }; /* =============================== Module: PLLDIG ============================= */ struct PLLDIG_tag { uint8_t PLLDIG_reserved0[24]; union { /* PLL Calibration Register 3 */ vuint32_t R; struct { vuint32_t :2; vuint32_t MFDEN:16; /* Denominator fo fractional loop division factor. */ vuint32_t :14; } B; } PLLCAL3; uint8_t PLLDIG_reserved1[4]; union { /* PLLDIG PLL Control Register */ vuint32_t R; struct { vuint32_t :21; vuint32_t :1; vuint32_t :2; vuint32_t EXPDIE:1; /* External Power Down Cycle Complete indication interrupt enable. */ vuint32_t :1; vuint32_t :1; vuint32_t :1; vuint32_t LOLIE:1; /* Loss-of-lock interrupt enable. */ vuint32_t LOLRE:1; /* Loss-of-lock reset enable. */ vuint32_t :1; vuint32_t :1; } B; } PLLCR; union { /* PLLDIG PLL Status Register */ vuint32_t R; struct { vuint32_t :22; vuint32_t ENPHI1:1; /* PLL PHI1 Output Enable */ vuint32_t ENPHI:1; /* PLL PHI Output Enable */ vuint32_t EXTPDF:1; vuint32_t :1; vuint32_t :1; vuint32_t :1; vuint32_t LOLF:1; /* Loss-of-lock flag. */ vuint32_t LOCK:1; vuint32_t :1; vuint32_t :1; } B; } PLLSR; union { /* PLLDIG PLL Divider Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t RFDPHI1:6; /* PHI1 reduced frequency divider. */ vuint32_t :3; vuint32_t RFDPHI:6; /* PHI reduced frequency divider. */ vuint32_t :1; vuint32_t PREDIV:3; /* Input clock predivider. */ vuint32_t :1; vuint32_t :3; vuint32_t MFD:8; /* Loop multiplication factor divider. */ } B; } PLLDV; union { /* PLLDIG PLL Frequency Modulation Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t SSCGBYP:1; /* Modulation enable. */ vuint32_t MODSEL:1; /* Modulation selection. */ vuint32_t :3; vuint32_t MODPRD:10; /* Modulation period. */ vuint32_t :5; vuint32_t INCSTP:11; /* Increment step. */ } B; } PLLFM; union { /* PLLDIG PLL Fractional Divide Register */ vuint32_t R; struct { vuint32_t :1; vuint32_t SMDEN:1; /* Sigma Delta Modulation Enable */ vuint32_t SDM2:1; /* Second Order Sigma Delta Modulation Select */ vuint32_t SDM3:1; /* Third Order Sigma Delta Modulation Select */ vuint32_t :6; vuint32_t DTHRCTL:4; /* Dither Control. */ vuint32_t DTHDIS:2; /* Dither Disable. */ vuint32_t :1; vuint32_t MFN:15; } B; } PLLFD; }; /* =============================== Module: SIUL2 ============================== */ struct SIUL2_tag { uint8_t SIUL2_reserved0[4]; union { /* SIUL2 MCU ID Register #1 */ vuint32_t R; struct { vuint32_t PARTNUM:16; /* MCU Part Number */ vuint32_t :1; vuint32_t PKG:5; /* Package Settings */ vuint32_t :2; vuint32_t MAJOR_MASK:4; /* Major Mask Revision */ vuint32_t MINOR_MASK:4; /* Minor Mask Revision */ } B; } MIDR1; union { /* SIUL2 MCU ID Register #2 */ vuint32_t R; struct { vuint32_t :1; vuint32_t FLASH_SIZE_1:4; /* Coarse granularity for flash memory size */ vuint32_t FLASH_SIZE_2:4; /* Fine granularity for flash memory size */ vuint32_t :7; vuint32_t PARTNUM:8; /* ASCII character in MCU Part Number */ vuint32_t :8; } B; } MIDR2; uint8_t SIUL2_reserved1[4]; union { /* SIUL2 Interrupt Status Flag Register0 */ vuint32_t R; struct { vuint32_t EIF31:1; /* External Interrupt Status Flag x */ vuint32_t EIF30:1; /* External Interrupt Status Flag x */ vuint32_t EIF29:1; /* External Interrupt Status Flag x */ vuint32_t EIF28:1; /* External Interrupt Status Flag x */ vuint32_t EIF27:1; /* External Interrupt Status Flag x */ vuint32_t EIF26:1; /* External Interrupt Status Flag x */ vuint32_t EIF25:1; /* External Interrupt Status Flag x */ vuint32_t EIF24:1; /* External Interrupt Status Flag x */ vuint32_t EIF23:1; /* External Interrupt Status Flag x */ vuint32_t EIF22:1; /* External Interrupt Status Flag x */ vuint32_t EIF21:1; /* External Interrupt Status Flag x */ vuint32_t EIF20:1; /* External Interrupt Status Flag x */ vuint32_t EIF19:1; /* External Interrupt Status Flag x */ vuint32_t EIF18:1; /* External Interrupt Status Flag x */ vuint32_t EIF17:1; /* External Interrupt Status Flag x */ vuint32_t EIF16:1; /* External Interrupt Status Flag x */ vuint32_t EIF15:1; /* External Interrupt Status Flag x */ vuint32_t EIF14:1; /* External Interrupt Status Flag x */ vuint32_t EIF13:1; /* External Interrupt Status Flag x */ vuint32_t EIF12:1; /* External Interrupt Status Flag x */ vuint32_t EIF11:1; /* External Interrupt Status Flag x */ vuint32_t EIF10:1; /* External Interrupt Status Flag x */ vuint32_t EIF9:1; /* External Interrupt Status Flag x */ vuint32_t EIF8:1; /* External Interrupt Status Flag x */ vuint32_t EIF7:1; /* External Interrupt Status Flag x */ vuint32_t EIF6:1; /* External Interrupt Status Flag x */ vuint32_t EIF5:1; /* External Interrupt Status Flag x */ vuint32_t EIF4:1; /* External Interrupt Status Flag x */ vuint32_t EIF3:1; /* External Interrupt Status Flag x */ vuint32_t EIF2:1; /* External Interrupt Status Flag x */ vuint32_t EIF1:1; /* External Interrupt Status Flag x */ vuint32_t EIF0:1; /* External Interrupt Status Flag x */ } B; } ISR0; uint8_t SIUL2_reserved2[4]; union { /* SIUL2 Interrupt Request Enable Register0 */ vuint32_t R; struct { vuint32_t EIRE31:1; vuint32_t EIRE30:1; vuint32_t EIRE29:1; vuint32_t EIRE28:1; vuint32_t EIRE27:1; vuint32_t EIRE26:1; vuint32_t EIRE25:1; vuint32_t EIRE24:1; vuint32_t EIRE23:1; vuint32_t EIRE22:1; vuint32_t EIRE21:1; vuint32_t EIRE20:1; vuint32_t EIRE19:1; vuint32_t EIRE18:1; vuint32_t EIRE17:1; vuint32_t EIRE16:1; vuint32_t EIRE15:1; vuint32_t EIRE14:1; vuint32_t EIRE13:1; vuint32_t EIRE12:1; vuint32_t EIRE11:1; vuint32_t EIRE10:1; vuint32_t EIRE9:1; vuint32_t EIRE8:1; vuint32_t EIRE7:1; vuint32_t EIRE6:1; vuint32_t EIRE5:1; vuint32_t EIRE4:1; vuint32_t EIRE3:1; vuint32_t EIRE2:1; vuint32_t EIRE1:1; vuint32_t EIRE0:1; } B; } IRER0; uint8_t SIUL2_reserved3[4]; union { /* SIUL2 Interrupt Request Select Register0 */ vuint32_t R; struct { vuint32_t DIRSR31:1; vuint32_t DIRSR30:1; vuint32_t DIRSR29:1; vuint32_t DIRSR28:1; vuint32_t DIRSR27:1; vuint32_t DIRSR26:1; vuint32_t DIRSR25:1; vuint32_t DIRSR24:1; vuint32_t DIRSR23:1; vuint32_t DIRSR22:1; vuint32_t DIRSR21:1; vuint32_t DIRSR20:1; vuint32_t DIRSR19:1; vuint32_t DIRSR18:1; vuint32_t DIRSR17:1; vuint32_t DIRSR16:1; vuint32_t DIRSR15:1; vuint32_t DIRSR14:1; vuint32_t DIRSR13:1; vuint32_t DIRSR12:1; vuint32_t DIRSR11:1; vuint32_t DIRSR10:1; vuint32_t DIRSR9:1; vuint32_t DIRSR8:1; vuint32_t DIRSR7:1; vuint32_t DIRSR6:1; vuint32_t DIRSR5:1; vuint32_t DIRSR4:1; vuint32_t DIRSR3:1; vuint32_t DIRSR2:1; vuint32_t DIRSR1:1; vuint32_t DIRSR0:1; } B; } IRSR0; uint8_t SIUL2_reserved4[4]; union { /* SIUL2 Interrupt Rising-Edge Event Enable Register 0 */ vuint32_t R; struct { vuint32_t IREE31:1; vuint32_t IREE30:1; vuint32_t IREE29:1; vuint32_t IREE28:1; vuint32_t IREE27:1; vuint32_t IREE26:1; vuint32_t IREE25:1; vuint32_t IREE24:1; vuint32_t IREE23:1; vuint32_t IREE22:1; vuint32_t IREE21:1; vuint32_t IREE20:1; vuint32_t IREE19:1; vuint32_t IREE18:1; vuint32_t IREE17:1; vuint32_t IREE16:1; vuint32_t IREE15:1; vuint32_t IREE14:1; vuint32_t IREE13:1; vuint32_t IREE12:1; vuint32_t IREE11:1; vuint32_t IREE10:1; vuint32_t IREE9:1; vuint32_t IREE8:1; vuint32_t IREE7:1; vuint32_t IREE6:1; vuint32_t IREE5:1; vuint32_t IREE4:1; vuint32_t IREE3:1; vuint32_t IREE2:1; vuint32_t IREE1:1; vuint32_t IREE0:1; } B; } IREER0; uint8_t SIUL2_reserved5[4]; union { /* SIUL2 Interrupt Falling-Edge Event Enable Register 0 */ vuint32_t R; struct { vuint32_t IFEE31:1; vuint32_t IFEE30:1; vuint32_t IFEE29:1; vuint32_t IFEE28:1; vuint32_t IFEE27:1; vuint32_t IFEE26:1; vuint32_t IFEE25:1; vuint32_t IFEE24:1; vuint32_t IFEE23:1; vuint32_t IFEE22:1; vuint32_t IFEE21:1; vuint32_t IFEE20:1; vuint32_t IFEE19:1; vuint32_t IFEE18:1; vuint32_t IFEE17:1; vuint32_t IFEE16:1; vuint32_t IFEE15:1; vuint32_t IFEE14:1; vuint32_t IFEE13:1; vuint32_t IFEE12:1; vuint32_t IFEE11:1; vuint32_t IFEE10:1; vuint32_t IFEE9:1; vuint32_t IFEE8:1; vuint32_t IFEE7:1; vuint32_t IFEE6:1; vuint32_t IFEE5:1; vuint32_t IFEE4:1; vuint32_t IFEE3:1; vuint32_t IFEE2:1; vuint32_t IFEE1:1; vuint32_t IFEE0:1; } B; } IFEER0; uint8_t SIUL2_reserved6[4]; union { /* SIUL2 Interrupt Filter Enable Register 0 */ vuint32_t R; struct { vuint32_t IFE31:1; vuint32_t IFE30:1; vuint32_t IFE29:1; vuint32_t IFE28:1; vuint32_t IFE27:1; vuint32_t IFE26:1; vuint32_t IFE25:1; vuint32_t IFE24:1; vuint32_t IFE23:1; vuint32_t IFE22:1; vuint32_t IFE21:1; vuint32_t IFE20:1; vuint32_t IFE19:1; vuint32_t IFE18:1; vuint32_t IFE17:1; vuint32_t IFE16:1; vuint32_t IFE15:1; vuint32_t IFE14:1; vuint32_t IFE13:1; vuint32_t IFE12:1; vuint32_t IFE11:1; vuint32_t IFE10:1; vuint32_t IFE9:1; vuint32_t IFE8:1; vuint32_t IFE7:1; vuint32_t IFE6:1; vuint32_t IFE5:1; vuint32_t IFE4:1; vuint32_t IFE3:1; vuint32_t IFE2:1; vuint32_t IFE1:1; vuint32_t IFE0:1; } B; } IFER0; uint8_t SIUL2_reserved7[4]; union { /* SIUL2 Interrupt Filter Maximum Counter Register */ vuint32_t R; struct { vuint32_t :28; vuint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter setting */ } B; } IFMCR[32]; union { /* SIUL2 Interrupt Filter Clock Prescaler Register */ vuint32_t R; struct { vuint32_t :28; vuint32_t IFCP:4; /* Interrupt Filter Clock Prescaler setting */ } B; } IFCPR; uint8_t SIUL2_reserved8[380]; union { /* SIUL2 Multiplexed Signal Configuration Register */ vuint32_t R; struct { vuint32_t :2; vuint32_t SRC:2; /* Slew Rate Control */ vuint32_t :2; vuint32_t OBE:1; /* GPIO Output Buffer Enable */ vuint32_t ODE:1; /* Open Drain Enable */ vuint32_t SMC:1; /* Safe Mode Control */ vuint32_t APC:1; /* Analog Pad Control */ vuint32_t :1; vuint32_t TTL:1; /* TTL/Automotive mode selection */ vuint32_t IBE:1; /* Input Buffer Enable */ vuint32_t HYS:1; /* Input Hysteresis */ vuint32_t PUS:1; /* Pull Select */ vuint32_t PUE:1; /* Pull Enable */ vuint32_t :8; vuint32_t :4; vuint32_t SSS:4; /* Source Signal Select */ } B; } MSCR[264]; uint8_t SIUL2_reserved9[992]; union { /* SIUL2 Input Multiplexed Signal Configuration Register */ vuint32_t R; struct { vuint32_t :24; vuint32_t :4; vuint32_t SSS:4; /* Source Signal Select */ } B; } IMCR[512]; uint8_t SIUL2_reserved10[192]; union { /* SIUL2 GPIO Pad Data Output Register */ vuint8_t R; struct { vuint8_t :7; vuint8_t PDO_4n:1; /* Pad Data Out */ } B; } GPDO[264]; uint8_t SIUL2_reserved11[248]; union { /* SIUL2 GPIO Pad Data Input Register */ vuint8_t R; struct { vuint8_t :7; vuint8_t PDI_4n:1; /* Pad Data In */ } B; } GPDI[264]; uint8_t SIUL2_reserved12[248]; union { /* SIUL2 Parallel GPIO Pad Data Out Register */ vuint16_t R; struct { vuint16_t PPDO:16; /* Parallel Pad Data Out */ } B; } PGPDO[32]; union { /* SIUL2 Parallel GPIO Pad Data In Register */ vuint16_t R; struct { vuint16_t PPDI:16; /* Parallel Pad Data In */ } B; } PGPDI[32]; union { /* SIUL2 Masked Parallel GPIO Pad Data Out Register */ vuint32_t R; struct { vuint32_t MASK:16; /* Mask Field */ vuint32_t MPPDO:16; /* Masked Parallel Pad Data Out */ } B; } MPGPDO[32]; }; /* ============================================================================ */ #define MC_CGM (*(volatile struct MC_CGM_tag *) 0xFFFB0000UL) #define MC_ME (*(volatile struct MC_ME_tag *) 0xFFFB8000UL) #define PLLDIG (*(volatile struct PLLDIG_tag *) 0xFFFB0080UL) #define SIUL2 (*(volatile struct SIUL2_tag *) 0xFFFC0000UL) /******************************************************************************* Function Name : Sys_Init Engineer : b21190 Date : Oct-29-2014 Parameters : NONE Modifies : NONE Returns : NONE Notes : Clock settings Issues : NONE *******************************************************************************/ void Sys_Init(void) { //Clk Out MC_CGM.AC5_SC.B.SELCTL = 1; //Select FIRC 16MHz MC_CGM.AC6_DC0.B.DE = 1; //Enable output clock devided MC_CGM.AC6_DC0.B.DIV = 0x13; //Divide output clock by 20 //Configure RunPeripheralConfiguration registers in ME_RUN_PC0 MC_ME.RUN_PC[0].B.DRUN = 1; //Enable DRUN mode for all peripherals using ME_RUN_PC[0] //Enable external oscilator MC_ME.DRUN_MC.B.FXOSCON = 1; //AUX Clock Selector 5 setup MC_CGM.AC5_SC.B.SELCTL = 1; //connect (8..40MHz) XTALL to the PLL input MC_ME.DRUN_MC.B.PLLON = 1; //Enable PLL for DRUN mode // Set PLL0 to 160MHz (40MHz XTAL) // VCO Frequency Range 600 - 1280 MHz // RFDPHI1 = 10, RFDPHI = 2, PREDIV = 4, MFD = 0x40h (64) PLLDIG.PLLDV.R = 0x50000000 |0x00010000 |0x00004000 |0x0040 ; //predefined PLL0 divider register PLLDIG.PLLCAL3.R = 0x09C3C000; /* switch to PLL */ MC_ME.DRUN_MC.R = 0x00130172; /* FLASH in normal mode, PLLON, FXOSC ON, Use PLL_PHI_0 */ MC_CGM.AC6_SC.B.SELCTL = 0x2; /* PLL_CLKOUT1 */ #if 0 /* Enable Cores and set start address */ MC_ME.CADDR[2].R = (unsigned int)_start; MC_ME.CADDR[2].B.RMC = 1; MC_ME.CADDR[3].R = (unsigned int)_start; MC_ME.CADDR[3].B.RMC = 1; MC_ME.CCTL[2].R = 0x00FE; MC_ME.CCTL[3].R = 0x00FE; #endif //Mode transition to apply the PLL0 setup and set Normal mode with PLL running MC_ME.MCTL.R = 0x30005AF0; //DRUN Mode & Key MC_ME.MCTL.R = 0x3000A50F; //DRUN Mode & Key while(!MC_ME.GS.B.S_PLLON); //ME_GS Wait for PLL stabilization. while(MC_ME.GS.B.S_MTRANS); //Waiting for end of transaction while(MC_ME.GS.B.S_CURRENT_MODE != DRUN_MODE); // ME_GS Check DRUN mode has successfully been entered }//Sys_Init /******************************************************************************* Function Name : SIUL2_Init Engineer : b21190 Date : Nov-20-2014 Parameters : NONE Modifies : NONE Returns : NONE Notes : Configure SIUL2 unit - SYSCLK0 Issues : NONE *******************************************************************************/ void SIUL2_Init (void) { // Configure PA[0] as SYSCLK0 // SIUL must be configured after mode transition! SIUL2.MSCR[103].R = 0x02000000 | 0x03; //PG[7] - ODC_PUSH_PULL and SSS_PF8_SYSCLK0 }//SIUL2_Init