; -------------------------------------------------------------------------------- ; @Title: Beaglebone Black X-Loader Setup Script ; @Description: ; This script does X-Loader setup using PRACTICE commands ; @Keywords: AM3359*, Beagle*, Setup, TI, X-Loader ; @Author: ydaoud ; @Board: Beaglebone black ; @Chip: AM3359 ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: beaglebone_black_setup.cmm 15217 2019-11-04 16:17:15Z bschroefel $ //Disable_watchdog Data.Set ASD:0x44E35048 %LE %Long 0x0000AAAA ; WDT_WSPR Data.Set ASD:0x44E35048 %LE %Long 0x00005555 ; WDT_WSPR //Console Init ;configure module pin mux Data.Set NSD:0x44E10970 %LE %Long 0x00000030 ; CONF_UART0_RXD Data.Set NSD:0x44E10974 %LE %Long 0x00000000 ; CONF_UART0_TXD ;Setup Clocks For console Data.Set NSD:0x44E00400 %LE %Long 0x00000616 ; CM_WKUP_CLKSTCTRL Data.Set NSD:0x44E0011C %LE %Long 0x0000000A ; CM_PER_L4HS_CLKSTCTRL Data.Set NSD:0x44E004B4 %LE %Long 0x00030002 ; CM_WKUP_UART0_CLKCTRL Data.Set NSD:0x44E0006C %LE %Long 0x00030002 ; CM_PER_UART1_CLKCTRL Data.Set NSD:0x44E00070 %LE %Long 0x00030002 ; CM_PER_UART2_CLKCTRL Data.Set NSD:0x44E00074 %LE %Long 0x00030002 ; CM_PER_UART3_CLKCTRL Data.Set NSD:0x44E00078 %LE %Long 0x00030002 ; CM_PER_UART4_CLKCTRL Data.Set NSD:0x44E00038 %LE %Long 0x00030002 ; CM_PER_UART5_CLKCTRL ;RTc32K Enable Data.Set NSD:0x44E3E06C %LE %Long 0x83E70B13 ; KICK0 Data.Set NSD:0x44E3E070 %LE %Long 0x95A4F1E0 ; KICK1 Data.Set NSD:0x44E3E054 %LE %Long 0x00000048 ; OSC_REG ;Enable Clocks Domains Data.Set NSD:0x44E0000C %LE %Long 0x0000001A ; CM_PER_L3_CLKSTCTRL Data.Set NSD:0x44E00008 %LE %Long 0x00000102 ; CM_PER_L4FW_CLKSTCTRL Data.Set NSD:0x44E00004 %LE %Long 0x0000000A ; CM_PER_L3S_CLKSTCTRL Data.Set NSD:0x44E00000 %LE %Long 0x00004502 ; CM_PER_L4LS_CLKSTCTRL Data.Set NSD:0x44E000D0 %LE %Long 0x00000002 ; CM_PER_EMIF_FW_CLKCTRL Data.Set NSD:0x44E00804 %LE %Long 0x00000302 ; CM_RTC_CLKSTCTRL ;Enable Clocks Modules Data.Set NSD:0x44E000E0 %LE %Long 0x00000002 ; CM_PER_L3_CLKCTRL Data.Set NSD:0x44E00060 %LE %Long 0x00000002 ; CM_PER_L4LS_CLKCTRL Data.Set NSD:0x44E00064 %LE %Long 0x00000002 ; CM_PER_L4FW_CLKCTRL Data.Set NSD:0x44E0040C %LE %Long 0x00000002 ; CM_WKUP_L4WKUP_CLKCTRL Data.Set NSD:0x44E000DC %LE %Long 0x00000002 ; CM_PER_L3_INSTR_CLKCTRL Data.Set NSD:0x44E00120 %LE %Long 0x00000002 ; CM_PER_L4HS_CLKCTRL Data.Set NSD:0x44E00408 %LE %Long 0x00030002 ; CM_WKUP_GPIO0_CLKCTRL Data.Set NSD:0x44E00404 %LE %Long 0x00000002 ; CM_WKUP_CONTROL_CLKCTRL Data.Set NSD:0x44E00080 %LE %Long 0x00000002 ; CM_PER_TIMER2_CLKCTRL Data.Set NSD:0x44E00030 %LE %Long 0x00000002 ; CM_PER_GPMC_CLKCTRL Data.Set NSD:0x44E00040 %LE %Long 0x00030002 ; CM_PER_ELM_CLKCTRL Data.Set NSD:0x44E0003C %LE %Long 0x00030002 ; CM_PER_MMC0_CLKCTRL Data.Set NSD:0x44E000F4 %LE %Long 0x00000002 ; CM_PER_MMC1_CLKCTRL Data.Set NSD:0x44E004B8 %LE %Long 0x00030002 ; CM_WKUP_I2C0_CLKCTRL Data.Set NSD:0x44E000AC %LE %Long 0x00030002 ; CM_PER_GPIO1_CLKCTRL Data.Set NSD:0x44E000B0 %LE %Long 0x00030002 ; CM_PER_GPIO2_CLKCTRL Data.Set NSD:0x44E000B4 %LE %Long 0x00030002 ; CM_PER_GPIO3_CLKCTRL Data.Set NSD:0x44E00048 %LE %Long 0x00030002 ; CM_WKUP_I2C0_CLKCTRL Data.Set NSD:0x44E00014 %LE %Long 0x00070002 ; CM_PER_CPGMAC0_CLKCTRL Data.Set NSD:0x44E0004C %LE %Long 0x00030002 ; CM_PER_SPI0_CLKCTRL Data.Set NSD:0x44E00800 %LE %Long 0x00000002 ; CM_RTC_RTC_CLKCTRL Data.Set NSD:0x44E0001C %LE %Long 0x00030002 ; CM_PER_USB0_CLKCTRL Data.Set NSD:0x44E000D0 %LE %Long 0x00000002 ; CM_PER_EMIF_FW_CLKCTRL Data.Set NSD:0x44E00028 %LE %Long 0x00030002 ; CM_PER_EMIF_CLKCTRL ;Select the master osc 24 MHZ as Timer2 clock source Data.Set NSD:0x44E00508 %LE %Long 0x00000001 ; CLKSEL_TIMER2_CLK //Prcm_Init/Setup DPLL Data.Set NSD:0x44E00490 %LE %Long 0x00000004 ; CM_CLKMODE_DPLL_CORE Data.Set NSD:0x44E00468 %LE %Long 0x00003217 ; CM_CLKSEL_DPLL_CORE Data.Set NSD:0x44E00480 %LE %Long 0x00000001 ; CM_DIV_M4_DPLL_CORE Data.Set NSD:0x44E00484 %LE %Long 0x00000001 ; CM_DIV_M5_DPLL_CORE Data.Set NSD:0x44E004D8 %LE %Long 0x00000001 ; CM_DIV_M6_DPLL_CORE Data.Set NSD:0x44E00490 %LE %Long 0x00000007 ; CM_CLKMODE_DPLL_CORE Data.Set NSD:0x44E00488 %LE %Long 0x00000004 ; CM_CLKMODE_DPLL_MPU Data.Set NSD:0x44E0042C %LE %Long 0x00012C17 ; CM_CLKSEL_DPLL_MPU Data.Set NSD:0x44E004A8 %LE %Long 0x00000001 ; CM_DIV_M2_DPLL_MPU Data.Set NSD:0x44E00488 %LE %Long 0x00000007 ; CM_CLKMODE_DPLL_MPU Data.Set NSD:0x44E0048C %LE %Long 0x00000004 ; CM_CLKMODE_DPLL_PER Data.Set NSD:0x44E0049C %LE %Long 0x0403C017 ; CM_CLKSEL_DPLL_PERIPH Data.Set NSD:0x44E004AC %LE %Long 0x00000005 ; CM_DIV_M2_DPLL_PER Data.Set NSD:0x44E0048C %LE %Long 0x00000007 ; CM_CLKMODE_DPLL_PER Data.Set NSD:0x44E0047C %LE %Long 0x00000300 ; CM_CLKDCOLDO_DPLL_PER ;Configure Module Pin Mux Data.Set NSD:0x44E10988 %LE %Long 0x00000060 ; CONF_I2C0_SDA Data.Set NSD:0x44E1098C %LE %Long 0x00000060 ; CONF_I2C0_SCL //I2C Init Bus/Omap 24 I2C Init Data.Set NSD:0x44E0B010 %LE %Word 0x0002 ; I2C_SYSC wait 1.ms Data.Set NSD:0x44E0B0A4 %LE %Word 0x8000 ; I2C_CON ;Omap 24 I2C Init/Omap I2C Set Speed Data.Set NSD:0x44E0B0A4 %LE %Word 0x0000 ; I2C_CON Data.Set NSD:0x44E0B0B0 %LE %Word 0x0000 ; I2C_PSC Data.Set NSD:0x44E0B0A4 %LE %Word 0x8000 ; I2C_CON Data.Set NSD:0x44E0B028 %LE %Word 0xFFFF ; I2C_IRQSTATUS Data.Set NSD:0x44E0B0A8 %LE %Word 0x0001 ; I2C_OA Data.Set NSD:0x44E0B028 %LE %Word 0xFFFF ; I2C_IRQSTATUS Data.Set NSD:0x44E0B028 %LE %Word 0xFFFF ; I2C_IRQSTATUS Data.Set NSD:0x44E0B028 %LE %Word 0xFFFF ; I2C_IRQSTATUS wait 1.ms Data.Set NSD:0x44E0B028 %LE %Word 0xFFFF ; I2C_IRQSTATUS Data.Set NSD:0x44E0B028 %LE %Word 0xFFFF ; I2C_IRQSTATUS //Setup DPLL Data.Set NSD:0x44E00494 %LE %Long 0x00000004 ; CM_CLKMODE_DPLL_DDR Data.Set NSD:0x44E00440 %LE %Long 0x00019017 ; CM_CLKSEL_DPLL_DDR Data.Set NSD:0x44E004A0 %LE %Long 0x00000001 ; CM_DIV_M2_DPLL_DDR Data.Set NSD:0x44E00494 %LE %Long 0x00000007 ; CM_CLKMODE_DPLL_DDR //Set Mux Conf Regs/Enable Board Pin Mux/Configure Module Pin Mux Data.Set NSD:0x44E10910 %LE %Long 0x00000020 ; CONF_MII1_RXERR Data.Set NSD:0x44E10914 %LE %Long 0x00000000 ; CONF_MII1_TXEN Data.Set NSD:0x44E10918 %LE %Long 0x00000020 ; CONF_MII1_RXDV Data.Set NSD:0x44E1091C %LE %Long 0x00000000 ; CONF_MII1_TXD3 Data.Set NSD:0x44E10920 %LE %Long 0x00000000 ; CONF_MII1_TXD2 Data.Set NSD:0x44E10924 %LE %Long 0x00000000 ; CONF_MII1_TXD1 Data.Set NSD:0x44E10928 %LE %Long 0x00000000 ; CONF_MII1_TXD0 Data.Set NSD:0x44E1092C %LE %Long 0x00000020 ; CONF_MII1_TXCLK Data.Set NSD:0x44E10930 %LE %Long 0x00000020 ; CONF_MII1_RXCLK Data.Set NSD:0x44E10934 %LE %Long 0x00000020 ; CONF_MII1_RXD3 Data.Set NSD:0x44E10938 %LE %Long 0x00000020 ; CONF_MII1_RXD2 Data.Set NSD:0x44E1093C %LE %Long 0x00000020 ; CONF_MII1_RXD1 Data.Set NSD:0x44E10940 %LE %Long 0x00000020 ; CONF_MII1_RXD0 Data.Set NSD:0x44E10948 %LE %Long 0x00000030 ; CONF_MDIO_DATA Data.Set NSD:0x44E1094C %LE %Long 0x00000010 ; CONF_MDIO_CLK Data.Set NSD:0x44E108F0 %LE %Long 0x00000030 ; CONF_MMC0_DAT3 Data.Set NSD:0x44E108F4 %LE %Long 0x00000030 ; CONF_MMC0_DAT2 Data.Set NSD:0x44E108F8 %LE %Long 0x00000030 ; CONF_MMC0_DAT1 Data.Set NSD:0x44E108FC %LE %Long 0x00000030 ; CONF_MMC0_DAT0 Data.Set NSD:0x44E10900 %LE %Long 0x00000030 ; CONF_MMC0_CLK Data.Set NSD:0x44E10904 %LE %Long 0x00000030 ; CONF_MMC0_CMD Data.Set NSD:0x44E109A0 %LE %Long 0x00000024 ; CONF_MCASP0_ACLKR Data.Set NSD:0x44E10960 %LE %Long 0x00000037 ; CONF_SPI0_CS1 Data.Set NSD:0x44E1080C %LE %Long 0x00000031 ; CONF_GPMC_AD3 Data.Set NSD:0x44E10808 %LE %Long 0x00000031 ; CONF_GPMC_AD2 Data.Set NSD:0x44E10804 %LE %Long 0x00000031 ; CONF_GPMC_AD1 Data.Set NSD:0x44E10800 %LE %Long 0x00000031 ; CONF_GPMC_AD0 Data.Set NSD:0x44E10880 %LE %Long 0x00000032 ; CONF_GPMC_CSN1 Data.Set NSD:0x44E10884 %LE %Long 0x00000032 ; CONF_GPMC_CSN2 Data.Set NSD:0x44E1087C %LE %Long 0x00000037 ; CONF_GPMC_CSN0 Data.Set NSD:0x44E10890 %LE %Long 0x00000037 ; CONF_GPMC_ADVN_ALE //SDRAM init ;Config DDR/Config VTP Data.Set NSD:0x44E10E0C %LE %Long 0x00010167 ; VTP_CTRL Data.Set NSD:0x44E10E0C %LE %Long 0x00010166 ; VTP_CTRL Data.Set NSD:0x44E10E0C %LE %Long 0x00010147 ; VTP_CTRL ;Config DDR/Config_CMD_CTRL Data.Set NSD:0x44E1201C %LE %Long 0x00000080 ; CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 Data.Set NSD:0x44E1202C %LE %Long 0x00000000 ; CMD0_REG_PHY_INVERT_CLKOUT_0 Data.Set NSD:0x44E12050 %LE %Long 0x00000080 ; CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 Data.Set NSD:0x44E12060 %LE %Long 0x00000000 ; CMD1_REG_PHY_INVERT_CLKOUT_0 Data.Set NSD:0x44E12084 %LE %Long 0x00000080 ; CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 Data.Set NSD:0x44E12094 %LE %Long 0x00000000 ; CMD2_REG_PHY_INVERT_CLKOUT_0 ;Config DDR/Config_DDR_Data Data.Set NSD:0x44E120DC %LE %Long 0x00000044 ; DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 Data.Set NSD:0x44E120F0 %LE %Long 0x00000000 ; DATA0_REG_PHY_WRLVL_INIT_RATIO_0 Data.Set NSD:0x44E120FC %LE %Long 0x00000000 ; DATA0_REG_PHY_GATELVL_INIT_RATIO_0 Data.Set NSD:0x44E12108 %LE %Long 0x00000094 ; DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 Data.Set NSD:0x44E12120 %LE %Long 0x0000007D ; DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 Data.Set NSD:0x44E1216C %LE %Long 0x00000038 ; DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0 Data.Set NSD:0x44E12180 %LE %Long 0x00000044 ; DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0 Data.Set NSD:0x44E12194 %LE %Long 0x00000000 ; DATA1_REG_PHY_WRLVL_INIT_RATIO_0 Data.Set NSD:0x44E121A0 %LE %Long 0x00000000 ; DATA1_REG_PHY_GATELVL_INIT_RATIO_0 Data.Set NSD:0x44E121AC %LE %Long 0x00000094 ; DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 Data.Set NSD:0x44E121C4 %LE %Long 0x0000007D ; DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0 ;Config DDR/Config_IO_Ctrl Data.Set NSD:0x44E11404 %LE %Long 0x0000018B ; DDR_CMD0_IOCTRL Data.Set NSD:0x44E11408 %LE %Long 0x0000018B ; DDR_CMD1_IOCTRL Data.Set NSD:0x44E1140C %LE %Long 0x0000018B ; DDR_CMD2_IOCTRL Data.Set NSD:0x44E11440 %LE %Long 0x0000018B ; DDR_DATA0_IOCTRL Data.Set NSD:0x44E11444 %LE %Long 0x0000018B ; DDR_DATA1_IOCTRL ;Set CKE to be controlled by EMIF/DDR PHY Data.Set NSD:0x44E1131C %LE %Long 0x00000001 ; DDR_CKE_CTRL ;Config DDR/Config_DDR_PHY Data.Set NSD:0x4C000010 %LE %Long 0x80000C30 ; SDRAM_REF_CTRL Data.Set NSD:0x4C000010 %LE %Long 0x00003100 ; SDRAM_REF_CTRL Data.Set NSD:0x4C0000E4 %LE %Long 0x00100007 ; DDR_PHY_CTRL_1 Data.Set NSD:0x4C0000E8 %LE %Long 0x00100007 ; DDR_PHY_CTRL_1_SHDW ;Set SDRAM Timing Data.Set NSD:0x4C000018 %LE %Long 0x0AAAD4DB ; SDRAM_TIM_1 Data.Set NSD:0x4C00001C %LE %Long 0x0AAAD4DB ; SDRAM_TIM_1_SHD Data.Set NSD:0x4C000020 %LE %Long 0x266B7FDA ; SDRAM_TIM_2 Data.Set NSD:0x4C000024 %LE %Long 0x266B7FDA ; SDRAM_TIM_2_SHDW Data.Set NSD:0x4C000028 %LE %Long 0x501F867F ; SDRAM_TIM_3 Data.Set NSD:0x4C00002C %LE %Long 0x501F867F ; SDRAM_TIM_3_SHDW ;Config SDRAM Data.Set NSD:0x4C0000C8 %LE %Long 0x50074BE4 ; ZQ_CONFIG Data.Set NSD:0x44E10110 %LE %Long 0x61C05332 ; SECURE_EMIF_SDRAM_CONFIG Data.Set NSD:0x4C000008 %LE %Long 0x61C05332 ; SDRAM_CONFIG wait 1.ms Data.Set NSD:0x4C000010 %LE %Long 0x00003100 ; SDRAM_REF_CTRL wait 1.ms Data.Set NSD:0x4C000010 %LE %Long 0x00000C30 ; SDRAM_REF_CTRL Data.Set NSD:0x4C000014 %LE %Long 0x00000C30 ; SDRAM_REF_CTRL_SHDW Data.Set NSD:0x4C000010 %LE %Long 0x00000C30 ; SDRAM_REF_CTRL Data.Set NSD:0x4C000014 %LE %Long 0x00000C30 ; SDRAM_REF_CTRL_SHDW Data.Set NSD:0x4C000008 %LE %Long 0x61C05332 ; SDRAM_CONFIG