/* Based on CPU DB MC9S08SF4_20, version 3.00.021 (RegistersPrg V2.28) */ /* DataSheet : MC9S08SF4 Rev. 1, Draft D 12/2007 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTADSTR _PTAD; /* Port A Data Register; 0x00000000 */ volatile PTADDSTR _PTADD; /* Port A Data Direction Register; 0x00000001 */ volatile PTBDSTR _PTBD; /* Port B Data Register; 0x00000002 */ volatile PTBDDSTR _PTBDD; /* Port B Data Direction Register; 0x00000003 */ volatile PTCDSTR _PTCD; /* Port C Data Register; 0x00000004 */ volatile PTCDDSTR _PTCDD; /* Port C Data Direction Register; 0x00000005 */ volatile ADCSC1STR _ADCSC1; /* Status and Control Register 1; 0x00000008 */ volatile ADCSC2STR _ADCSC2; /* Status and Control Register 2; 0x00000009 */ volatile ADCCFGSTR _ADCCFG; /* Configuration Register; 0x0000000E */ volatile APCTL1STR _APCTL1; /* Pin Control 1 Register; 0x0000000F */ volatile PRACMP1CSSTR _PRACMP1CS; /* PRACMP1 Control and Status Register; 0x00000010 */ volatile PRACMP1C0STR _PRACMP1C0; /* PRACMP1 Control 0 Register; 0x00000011 */ volatile PRACMP1C1STR _PRACMP1C1; /* PRACMP1 Control 1 Register; 0x00000012 */ volatile PRACMP1C2STR _PRACMP1C2; /* PRACMP1 Control 2 Register; 0x00000013 */ volatile PRACMP2CSSTR _PRACMP2CS; /* PRACMP2 Control and Status Register; 0x00000014 */ volatile PRACMP2C0STR _PRACMP2C0; /* PRACMP2 Control 0 Register; 0x00000015 */ volatile PRACMP2C1STR _PRACMP2C1; /* PRACMP2 Control 1 Register; 0x00000016 */ volatile PRACMP2C2STR _PRACMP2C2; /* PRACMP2 Control 2 Register; 0x00000017 */ volatile ICSC1STR _ICSC1; /* ICS Control Register 1; 0x00000018 */ volatile ICSC2STR _ICSC2; /* ICS Control Register 2; 0x00000019 */ volatile ICSTRMSTR _ICSTRM; /* ICS Trim Register; 0x0000001A */ volatile ICSSCSTR _ICSSC; /* ICS Status and Control Register; 0x0000001B */ volatile TPM1SCSTR _TPM1SC; /* TPM1 Status and Control Register; 0x00000020 */ volatile TPM1C0SCSTR _TPM1C0SC; /* TPM1 Timer Channel 0 Status and Control Register; 0x00000025 */ volatile TPM1C1SCSTR _TPM1C1SC; /* TPM1 Timer Channel 1 Status and Control Register; 0x00000028 */ volatile TPM1C2SCSTR _TPM1C2SC; /* TPM1 Timer Channel 2 Status and Control Register; 0x0000002B */ volatile TPM1C3SCSTR _TPM1C3SC; /* TPM1 Timer Channel 3 Status and Control Register; 0x0000002E */ volatile TPM1C4SCSTR _TPM1C4SC; /* TPM1 Timer Channel 4 Status and Control Register; 0x00000031 */ volatile TPM1C5SCSTR _TPM1C5SC; /* TPM1 Timer Channel 5 Status and Control Register; 0x00000034 */ volatile TPM2SCSTR _TPM2SC; /* TPM2 Status and Control Register; 0x00000038 */ volatile TPM2C0SCSTR _TPM2C0SC; /* TPM2 Timer Channel 0 Status and Control Register; 0x0000003D */ volatile IICASTR _IICA; /* IIC Address Register; 0x00000040 */ volatile IICFSTR _IICF; /* IIC Frequency Divider Register; 0x00000041 */ volatile IICC1STR _IICC1; /* IIC Control Register 1; 0x00000042 */ volatile IICSSTR _IICS; /* IIC Status Register; 0x00000043 */ volatile IICDSTR _IICD; /* IIC Data I/O Register; 0x00000044 */ volatile IICC2STR _IICC2; /* IIC Control Register 2; 0x00000045 */ volatile FDSCSSTR _FDSCS; /* FDS Control and Status Register; 0x00000048 */ volatile FDSINESTR _FDSINE; /* FDS Input Enable Register; 0x00000049 */ volatile FDSPCESTR _FDSPCE; /* FDS Pin Configuration Enable Register; 0x0000004A */ volatile FDSPCDSTR _FDSPCD; /* FDS Pin Configuration Direction Register; 0x0000004B */ volatile FDSPCVSTR _FDSPCV; /* FDS Pin Configuration Value Register; 0x0000004C */ volatile FDSINLSTR _FDSINL; /* FPC Input Latched Register; 0x0000004D */ volatile MTIM1SCSTR _MTIM1SC; /* MTIM16 Status and Control Register; 0x00000050 */ volatile MTIM1CLKSTR _MTIM1CLK; /* MTIM16 Clock Configuration Register; 0x00000051 */ volatile MTIM2SCSTR _MTIM2SC; /* MTIM16 Status and Control Register; 0x00000058 */ volatile MTIM2CLKSTR _MTIM2CLK; /* MTIM16 Clock Configuration Register; 0x00000059 */ volatile IPCSCSTR _IPCSC; /* IPC Status and Control Register; 0x0000005E */ volatile IPMPSSTR _IPMPS; /* Interrupt Priority Mask Pseudo Stack Register; 0x0000005F */ volatile ILRS0STR _ILRS0; /* Interrupt Level Setting Register; 0x00000060 */ volatile ILRS1STR _ILRS1; /* Interrupt Level Setting Register; 0x00000061 */ volatile ILRS2STR _ILRS2; /* Interrupt Level Setting Register; 0x00000062 */ volatile ILRS3STR _ILRS3; /* Interrupt Level Setting Register; 0x00000063 */ volatile ILRS4STR _ILRS4; /* Interrupt Level Setting Register; 0x00000064 */ volatile ILRS5STR _ILRS5; /* Interrupt Level Setting Register; 0x00000065 */ volatile ILRS6STR _ILRS6; /* Interrupt Level Setting Register; 0x00000066 */ volatile ILRS7STR _ILRS7; /* Interrupt Level Setting Register; 0x00000067 */ volatile KBISCSTR _KBISC; /* KBI Status and Control Register; 0x00000068 */ volatile KBIPESTR _KBIPE; /* KBI Pin Enable Register; 0x00000069 */ volatile KBIESSTR _KBIES; /* KBI Edge Select Register; 0x0000006A */ volatile IRQSCSTR _IRQSC; /* Interrupt request status and control register; 0x0000006B */ volatile PWT1CSSTR _PWT1CS; /* Pulse Width Timer Control and Status Register; 0x00000070 */ volatile PWT1CRSTR _PWT1CR; /* Pulse Width Timer Control Register; 0x00000071 */ volatile PWT2CSSTR _PWT2CS; /* Pulse Width Timer Control and Status Register; 0x00000078 */ volatile PWT2CRSTR _PWT2CR; /* Pulse Width Timer Control Register; 0x00000079 */ volatile SRSSTR _SRS; /* System Reset Status Register; 0x00001800 */ volatile SBDFRSTR _SBDFR; /* System Background Debug Force Reset Register; 0x00001801 */ volatile SOPT1STR _SOPT1; /* System Options Register 1; 0x00001802 */ volatile SOPT2STR _SOPT2; /* System Options Register 2; 0x00001803 */ volatile SPMSC1STR _SPMSC1; /* System Power Management Status and Control 1 Register; 0x00001809 */ volatile SPMSC2STR _SPMSC2; /* System Power Management Status and Control 2 Register; 0x0000180A */ volatile DBGCSTR _DBGC; /* Debug Control Register; 0x00001816 */ volatile DBGTSTR _DBGT; /* Debug Trigger Register; 0x00001817 */ volatile DBGSSTR _DBGS; /* Debug Status Register; 0x00001818 */ volatile FCDIVSTR _FCDIV; /* FLASH Clock Divider Register; 0x00001820 */ volatile FOPTSTR _FOPT; /* FLASH Options Register; 0x00001821 */ volatile FCNFGSTR _FCNFG; /* FLASH Configuration Register; 0x00001823 */ volatile FPROTSTR _FPROT; /* FLASH Protection Register; 0x00001824 */ volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00001825 */ volatile FCMDSTR _FCMD; /* FLASH Command Register; 0x00001826 */ volatile PTAPESTR _PTAPE; /* Port A Pull Enable Register; 0x00001840 */ volatile PTASESTR _PTASE; /* Port A Slew Rate Enable Register; 0x00001841 */ volatile PTADSSTR _PTADS; /* Port A Drive Strength Selection Register; 0x00001842 */ volatile PTBPESTR _PTBPE; /* Port B Pull Enable Register; 0x00001844 */ volatile PTBSESTR _PTBSE; /* Port B Slew Rate Enable Register; 0x00001845 */ volatile PTBDSSTR _PTBDS; /* Port B Drive Strength Selection Register; 0x00001846 */ volatile PTCPESTR _PTCPE; /* Port C Pull Enable Register; 0x00001848 */ volatile PTCSESTR _PTCSE; /* Port C Slew Rate Enable Register; 0x00001849 */ volatile PTCDSSTR _PTCDS; /* Port C Drive Strength Selection Register; 0x0000184A */ /* NVFTRIM - macro for reading non volatile register Nonvolatile ICS Fine Trim; 0x0000FFAE */ /* Tip for register initialization in the user code: const byte NVFTRIM_INIT @0x0000FFAE = ; */ /* NVICSTRM - macro for reading non volatile register Nonvolatile ICS Trim Register; 0x0000FFAF */ /* Tip for register initialization in the user code: const byte NVICSTRM_INIT @0x0000FFAF = ; */ /* NVBACKKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x0000FFB0 */ /* Tip for register initialization in the user code: const byte NVBACKKEY0_INIT @0x0000FFB0 = ; */ /* NVBACKKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x0000FFB1 */ /* Tip for register initialization in the user code: const byte NVBACKKEY1_INIT @0x0000FFB1 = ; */ /* NVBACKKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x0000FFB2 */ /* Tip for register initialization in the user code: const byte NVBACKKEY2_INIT @0x0000FFB2 = ; */ /* NVBACKKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x0000FFB3 */ /* Tip for register initialization in the user code: const byte NVBACKKEY3_INIT @0x0000FFB3 = ; */ /* NVBACKKEY4 - macro for reading non volatile register Backdoor Comparison Key 4; 0x0000FFB4 */ /* Tip for register initialization in the user code: const byte NVBACKKEY4_INIT @0x0000FFB4 = ; */ /* NVBACKKEY5 - macro for reading non volatile register Backdoor Comparison Key 5; 0x0000FFB5 */ /* Tip for register initialization in the user code: const byte NVBACKKEY5_INIT @0x0000FFB5 = ; */ /* NVBACKKEY6 - macro for reading non volatile register Backdoor Comparison Key 6; 0x0000FFB6 */ /* Tip for register initialization in the user code: const byte NVBACKKEY6_INIT @0x0000FFB6 = ; */ /* NVBACKKEY7 - macro for reading non volatile register Backdoor Comparison Key 7; 0x0000FFB7 */ /* Tip for register initialization in the user code: const byte NVBACKKEY7_INIT @0x0000FFB7 = ; */ /* NVPROT - macro for reading non volatile register Nonvolatile FLASH Protection Register; 0x0000FFBD */ /* Tip for register initialization in the user code: const byte NVPROT_INIT @0x0000FFBD = ; */ /* NVOPT - macro for reading non volatile register Nonvolatile Flash Options Register; 0x0000FFBF */ /* Tip for register initialization in the user code: const byte NVOPT_INIT @0x0000FFBF = ; */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile ADCRSTR _ADCR; /* Data Result Register; 0x0000000A */ volatile ADCCVSTR _ADCCV; /* Compare Value Register; 0x0000000C */ volatile TPM1CNTSTR _TPM1CNT; /* TPM1 Timer Counter Register; 0x00000021 */ volatile TPM1MODSTR _TPM1MOD; /* TPM1 Timer Counter Modulo Register; 0x00000023 */ volatile TPM1C0VSTR _TPM1C0V; /* TPM1 Timer Channel 0 Value Register; 0x00000026 */ volatile TPM1C1VSTR _TPM1C1V; /* TPM1 Timer Channel 1 Value Register; 0x00000029 */ volatile TPM1C2VSTR _TPM1C2V; /* TPM1 Timer Channel 2 Value Register; 0x0000002C */ volatile TPM1C3VSTR _TPM1C3V; /* TPM1 Timer Channel 3 Value Register; 0x0000002F */ volatile TPM1C4VSTR _TPM1C4V; /* TPM1 Timer Channel 4 Value Register; 0x00000032 */ volatile TPM1C5VSTR _TPM1C5V; /* TPM1 Timer Channel 5 Value Register; 0x00000035 */ volatile TPM2CNTSTR _TPM2CNT; /* TPM2 Timer Counter Register; 0x00000039 */ volatile TPM2MODSTR _TPM2MOD; /* TPM2 Timer Counter Modulo Register; 0x0000003B */ volatile TPM2C0VSTR _TPM2C0V; /* TPM2 Timer Channel 0 Value Register; 0x0000003E */ volatile MTIM1CNTSTR _MTIM1CNT; /* MTIM16 Counter Register; 0x00000052 */ volatile MTIM1MODSTR _MTIM1MOD; /* MTIM16 Modulo Register; 0x00000054 */ volatile MTIM2CNTSTR _MTIM2CNT; /* MTIM16 Counter Register; 0x0000005A */ volatile MTIM2MODSTR _MTIM2MOD; /* MTIM16 Modulo Register; 0x0000005C */ volatile PWT1PPSTR _PWT1PP; /* Pulse Width Timer Positive Pulse Width Register; 0x00000072 */ volatile PWT1NPSTR _PWT1NP; /* Pulse Width Timer Negative Pulse Width Register; 0x00000074 */ volatile PWT1CNTSTR _PWT1CNT; /* Pulse Width Timer Counter Register; 0x00000076 */ volatile PWT2PPSTR _PWT2PP; /* Pulse Width Timer Positive Pulse Width Register; 0x0000007A */ volatile PWT2NPSTR _PWT2NP; /* Pulse Width Timer Negative Pulse Width Register; 0x0000007C */ volatile PWT2CNTSTR _PWT2CNT; /* Pulse Width Timer Counter Register; 0x0000007E */ volatile SDIDSTR _SDID; /* System Device Identification Register; 0x00001806 */ volatile DBGCASTR _DBGCA; /* Debug Comparator A Register; 0x00001810 */ volatile DBGCBSTR _DBGCB; /* Debug Comparator B Register; 0x00001812 */ volatile DBGFSTR _DBGF; /* Debug FIFO Register; 0x00001814 */ /*lint -restore */ /* EOF */