/* Based on CPU DB MC9S08RE16_44, version 2.89.123 (RegistersPrg V2.28) */ /* DataSheet : MC9S08RG60/D Rev. REVIEW 1.13 01/2005 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTADSTR _PTAD; /* Port A Data Register; 0x00000000 */ volatile PTAPESTR _PTAPE; /* Pullup Enable for Port; 0x00000001 */ volatile PTADDSTR _PTADD; /* Data Direction Register A; 0x00000003 */ volatile PTBDSTR _PTBD; /* Port B Data Register; 0x00000004 */ volatile PTBPESTR _PTBPE; /* Pullup Enable for Port B; 0x00000005 */ volatile PTBDDSTR _PTBDD; /* Data Direction Register B; 0x00000007 */ volatile PTCDSTR _PTCD; /* Port C Data Register; 0x00000008 */ volatile PTCPESTR _PTCPE; /* Pullup Enable for Port C; 0x00000009 */ volatile PTCDDSTR _PTCDD; /* Data Direction Register C; 0x0000000B */ volatile PTDDSTR _PTDD; /* Port D Data Register; 0x0000000C */ volatile PTDPESTR _PTDPE; /* Pullup Enable for Port D; 0x0000000D */ volatile PTDDDSTR _PTDDD; /* Data Direction Register D; 0x0000000F */ volatile PTEDSTR _PTED; /* Port E Data Register; 0x00000010 */ volatile PTEPESTR _PTEPE; /* Pullup Enable for Port E; 0x00000011 */ volatile PTEDDSTR _PTEDD; /* Data Direction Register E; 0x00000013 */ volatile KBI1SCSTR _KBI1SC; /* KBI1 Status and Control; 0x00000014 */ volatile KBI1PESTR _KBI1PE; /* KBI1 Pin Enable Register; 0x00000015 */ volatile KBI2SCSTR _KBI2SC; /* KBI2 Status and Control; 0x00000016 */ volatile KBI2PESTR _KBI2PE; /* KBI2 Pin Enable Register; 0x00000017 */ volatile SCI1C1STR _SCI1C1; /* SCI1 Control Register 1; 0x0000001A */ volatile SCI1C2STR _SCI1C2; /* SCI1 Control Register 2; 0x0000001B */ volatile SCI1S1STR _SCI1S1; /* SCI1 Status Register 1; 0x0000001C */ volatile SCI1S2STR _SCI1S2; /* SCI1 Status Register 2; 0x0000001D */ volatile SCI1C3STR _SCI1C3; /* SCI1 Control Register 3; 0x0000001E */ volatile SCI1DRLSTR _SCI1DRL; /* SCI1 Data Register; 0x0000001F */ volatile CMTOCSTR _CMTOC; /* CMT Output Control Register; 0x00000024 */ volatile CMTMSCSTR _CMTMSC; /* CMT Modulator Status and Control Register; 0x00000025 */ volatile IRQSCSTR _IRQSC; /* Interrupt Request Status and Control Register; 0x0000002A */ volatile ACMP1SCSTR _ACMP1SC; /* Analog Comparator Status and Control Register; 0x0000002B */ volatile TPM1SCSTR _TPM1SC; /* TPM1 Timer Status and Control Register; 0x00000030 */ volatile TPM1C0SCSTR _TPM1C0SC; /* TPM1 Timer Channel 0 Status and Control Register; 0x00000035 */ volatile TPM1C1SCSTR _TPM1C1SC; /* TPM1 Timer Channel 1 Status and Control Register; 0x00000038 */ volatile SRSSTR _SRS; /* System Reset Status Register; 0x00001800 */ volatile SBDFRSTR _SBDFR; /* System Background Debug Force Reset Register; 0x00001801 */ volatile SOPTSTR _SOPT; /* System Integration Module Options Register; 0x00001802 */ volatile SRTISCSTR _SRTISC; /* System RTI Status and Control Register; 0x00001808 */ volatile SPMSC1STR _SPMSC1; /* System Power Management Status and Control 1 Register; 0x00001809 */ volatile SPMSC2STR _SPMSC2; /* System Power Management Status and Control 2 Register; 0x0000180A */ volatile DBGCAHSTR _DBGCAH; /* Debug Comparator A High Register; 0x00001810 */ volatile DBGCALSTR _DBGCAL; /* Debug Comparator A Low Register; 0x00001811 */ volatile DBGCBHSTR _DBGCBH; /* Debug Comparator B High Register; 0x00001812 */ volatile DBGCBLSTR _DBGCBL; /* Debug Comparator B Low Register; 0x00001813 */ volatile DBGCSTR _DBGC; /* Debug Control Register; 0x00001816 */ volatile DBGTSTR _DBGT; /* Debug Trigger Register; 0x00001817 */ volatile DBGSSTR _DBGS; /* Debug Status Register; 0x00001818 */ volatile FCDIVSTR _FCDIV; /* FLASH Clock Divider Register; 0x00001820 */ volatile FOPTSTR _FOPT; /* FLASH Options Register; 0x00001821 */ volatile FCNFGSTR _FCNFG; /* FLASH Configuration Register; 0x00001823 */ volatile FPROTSTR _FPROT; /* FLASH Protection Register; 0x00001824 */ volatile FSTATSTR _FSTAT; /* FLASH Status Register; 0x00001825 */ volatile FCMDSTR _FCMD; /* FLASH Command Register; 0x00001826 */ /* NVBACKKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x0000FFB0 */ /* Tip for register initialization in the user code: const byte NVBACKKEY0_INIT @0x0000FFB0 = ; */ /* NVBACKKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x0000FFB1 */ /* Tip for register initialization in the user code: const byte NVBACKKEY1_INIT @0x0000FFB1 = ; */ /* NVBACKKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x0000FFB2 */ /* Tip for register initialization in the user code: const byte NVBACKKEY2_INIT @0x0000FFB2 = ; */ /* NVBACKKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x0000FFB3 */ /* Tip for register initialization in the user code: const byte NVBACKKEY3_INIT @0x0000FFB3 = ; */ /* NVBACKKEY4 - macro for reading non volatile register Backdoor Comparison Key 4; 0x0000FFB4 */ /* Tip for register initialization in the user code: const byte NVBACKKEY4_INIT @0x0000FFB4 = ; */ /* NVBACKKEY5 - macro for reading non volatile register Backdoor Comparison Key 5; 0x0000FFB5 */ /* Tip for register initialization in the user code: const byte NVBACKKEY5_INIT @0x0000FFB5 = ; */ /* NVBACKKEY6 - macro for reading non volatile register Backdoor Comparison Key 6; 0x0000FFB6 */ /* Tip for register initialization in the user code: const byte NVBACKKEY6_INIT @0x0000FFB6 = ; */ /* NVBACKKEY7 - macro for reading non volatile register Backdoor Comparison Key 7; 0x0000FFB7 */ /* Tip for register initialization in the user code: const byte NVBACKKEY7_INIT @0x0000FFB7 = ; */ /* NVPROT - macro for reading non volatile register Nonvolatile FLASH Protection Register; 0x0000FFBD */ /* Tip for register initialization in the user code: const byte NVPROT_INIT @0x0000FFBD = ; */ /* NVOPT - macro for reading non volatile register Nonvolatile FLASH Options Register; 0x0000FFBF */ /* Tip for register initialization in the user code: const byte NVOPT_INIT @0x0000FFBF = ; */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile SCI1BDSTR _SCI1BD; /* SCI1 Baud Rate Register; 0x00000018 */ volatile CMTCG1STR _CMTCG1; /* Carrier Generator Data Register 1; 0x00000020 */ volatile CMTCG2STR _CMTCG2; /* Carrier Generator Data Register 2; 0x00000022 */ volatile CMTCMD12STR _CMTCMD12; /* CMT Modulator Data Register 12; 0x00000026 */ volatile CMTCMD34STR _CMTCMD34; /* CMT Modulator Data Register 34; 0x00000028 */ volatile TPM1CNTSTR _TPM1CNT; /* TPM1 Counter Register; 0x00000031 */ volatile TPM1MODSTR _TPM1MOD; /* TPM1 Timer Counter Modulo Register; 0x00000033 */ volatile TPM1C0VSTR _TPM1C0V; /* TPM1 Timer Channel 0 Value Register; 0x00000036 */ volatile TPM1C1VSTR _TPM1C1V; /* TPM1 Timer Channel 1 Value Register; 0x00000039 */ volatile SDIDSTR _SDID; /* System Device Identification Register; 0x00001806 */ volatile DBGFSTR _DBGF; /* Debug FIFO Register; 0x00001814 */ /*lint -restore */ /* EOF */