/* Based on CPU DB MC68HC908RF2, version 2.87.075 (RegistersPrg V2.28) */
/* DataSheet : MC68HC908RF2/D Rev. 4 5/2004 */

#include <mc68hc908rf2.h>

/*lint -save -esym(765, *) */


/* * * * *  8-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile PTASTR _PTA;                                      /* Port A Data Register; 0x00000000 */
volatile PTBSTR _PTB;                                      /* Port B Data Register; 0x00000001 */
volatile DDRASTR _DDRA;                                    /* Data Direction Register A; 0x00000004 */
volatile DDRBSTR _DDRB;                                    /* Data Direction Register B; 0x00000005 */
volatile INTKBSCRSTR _INTKBSCR;                            /* Keyboard Status and Control Register; 0x0000001A */
volatile INTKBIERSTR _INTKBIER;                            /* Keyboard Interrrupt Enable Register KBIER; 0x0000001B */
volatile CONFIGSTR _CONFIG;                                /* Configuration Register; 0x0000001F */
volatile TSCSTR _TSC;                                      /* TIM Status and Control Register TSC; 0x00000020 */
volatile TSC0STR _TSC0;                                    /* TIM Channel 0 Status and Control Register; 0x00000025 */
volatile TSC1STR _TSC1;                                    /* TIM Channel 1 Status and Control Register; 0x00000028 */
volatile ICGCRSTR _ICGCR;                                  /* ICG Control Register; 0x00000036 */
volatile ICGMRSTR _ICGMR;                                  /* ICG Multiplier Register; 0x00000037 */
volatile ICGTRSTR _ICGTR;                                  /* ICG Trim Register; 0x00000038 */
volatile ICGDVRSTR _ICGDVR;                                /* ICG DCO Divider Control Register; 0x00000039 */
volatile ICGDSRSTR _ICGDSR;                                /* ICG DCO Stage Control Register; 0x0000003A */
volatile SBSRSTR _SBSR;                                    /* SIM Break Status Register; 0x0000FE00 */
volatile SRSRSTR _SRSR;                                    /* SIM Reset Status Register; 0x0000FE01 */
volatile SBFCRSTR _SBFCR;                                  /* SIM Break Flag Control Register; 0x0000FE02 */
volatile FLCRSTR _FLCR;                                    /* FLASH 2TS Control Register; 0x0000FE08 */
volatile BRKSCRSTR _BRKSCR;                                /* Break Status and Control Register; 0x0000FE0E */
volatile LVISRSTR _LVISR;                                  /* LVI Status Register; 0x0000FE0F */
/* FLBPR - macro for reading non volatile register         FLASH 2TS Block Protect Register; 0x0000FFF0 */
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FFF0 = <FLBPR_INITVAL>; */
volatile COPCTLSTR _COPCTL;                                /* COP Control Register; 0x0000FFFF */


/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile TCNTSTR _TCNT;                                    /* TIM Counter Register; 0x00000021 */
volatile TMODSTR _TMOD;                                    /* TIM Counter Modulo Register; 0x00000023 */
volatile TCH0STR _TCH0;                                    /* TIM Channel 0 Register; 0x00000026 */
volatile TCH1STR _TCH1;                                    /* TIM Channel 1 Register; 0x00000029 */
volatile BRKSTR _BRK;                                      /* Break Address Register; 0x0000FE0C */

/*lint -restore */

/* EOF */