/* Based on CPU DB MC68HC908QY4_P_DW, version 2.87.147 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908QY4/D Rev. 5 07/2005, MC68HLC908QY4/D Rev. 3 07/2005 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile PTAPUESTR _PTAPUE; /* Input Pull-Up Enable Register PTAPUE; 0x0000000B */ volatile PTBPUESTR _PTBPUE; /* Input Pull-Up Enable Register PTBPUE; 0x0000000C */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register; 0x0000001A */ volatile KBIERSTR _KBIER; /* Keyboard Interrrupt Enable Register KBIER; 0x0000001B */ volatile INTSCRSTR _INTSCR; /* IRQ Status and Control Register; 0x0000001D */ volatile CONFIG2STR _CONFIG2; /* Configuration Register 2; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register 1; 0x0000001F */ volatile TSCSTR _TSC; /* TIM Status and Control Register TSC; 0x00000020 */ volatile TSC0STR _TSC0; /* TIM Channel 0 Status and Control Register; 0x00000025 */ volatile TSC1STR _TSC1; /* TIM Channel 1 Status and Control Register; 0x00000028 */ volatile OSCSTATSTR _OSCSTAT; /* Oscillator Status Register; 0x00000036 */ volatile OSCTRIMSTR _OSCTRIM; /* Oscillator Trim Register; 0x00000038 */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x0000003C */ volatile ADRSTR _ADR; /* ADC Data Register; 0x0000003E */ volatile ADICLKSTR _ADICLK; /* ADC Input Clock Register; 0x0000003F */ volatile SBSRSTR _SBSR; /* Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile BRKARSTR _BRKAR; /* Break Auxiliary Register; 0x0000FE02 */ volatile BFCRSTR _BFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile INT1STR _INT1; /* Interrupt Status Register 1; 0x0000FE04 */ volatile INT2STR _INT2; /* Interrupt Status Register 2; 0x0000FE05 */ volatile INT3STR _INT3; /* Interrupt Status Register 3; 0x0000FE06 */ volatile FLCRSTR _FLCR; /* FLASH Control Register; 0x0000FE08 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0B */ volatile LVISRSTR _LVISR; /* LVI Status Register; 0x0000FE0C */ /* FLBPR - macro for reading non volatile register FLASH Block Protect Register; 0x0000FFBE */ /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FFBE = ; */ /* Optional - macro for reading non volatile register Internal Oscillator Trim; 0x0000FFC0 */ /* Tip for register initialization in the user code: const byte Optional_INIT @0x0000FFC0 = ; */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile TCNTSTR _TCNT; /* TIM Counter Register; 0x00000021 */ volatile TMODSTR _TMOD; /* TIM Counter Modulo Register; 0x00000023 */ volatile TCH0STR _TCH0; /* TIM Channel 0 Register; 0x00000026 */ volatile TCH1STR _TCH1; /* TIM Channel 1 Register; 0x00000029 */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE09 */ /*lint -restore */ /* EOF */