/* Based on CPU DB MC68HC908MR8_32, version 2.89.064 (RegistersPrg V2.28) */
/* DataSheet : MC68HC908MR8/D Rev. 4.1 August 16, 2005 */

#include <mc68hc908mr8.h>

/*lint -save -esym(765, *) */


/* * * * *  8-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile PTASTR _PTA;                                      /* Port A Data Register; 0x00000000 */
volatile PTBSTR _PTB;                                      /* Port B Data Register; 0x00000001 */
volatile PTCSTR _PTC;                                      /* Port C Data Register; 0x00000002 */
volatile DDRASTR _DDRA;                                    /* Data Direction Register A; 0x00000004 */
volatile DDRBSTR _DDRB;                                    /* Data Direction Register B; 0x00000005 */
volatile DDRCSTR _DDRC;                                    /* Data Direction Register C; 0x00000006 */
volatile TASCSTR _TASC;                                    /* TIMA Status/Control Register; 0x0000000E */
volatile TASC0STR _TASC0;                                  /* TIMA Channel 0 Status/Control Register; 0x00000013 */
volatile TASC1STR _TASC1;                                  /* TIMA Channel 1 Status/Control Register; 0x00000016 */
volatile CONFIGSTR _CONFIG;                                /* Configuration Register; 0x0000001F */
volatile PCTL1STR _PCTL1;                                  /* PWM Control Register 1; 0x00000020 */
volatile PCTL2STR _PCTL2;                                  /* PWM Control Register 2; 0x00000021 */
volatile FCRSTR _FCR;                                      /* Fault Control Register; 0x00000022 */
volatile FSRSTR _FSR;                                      /* Fault Status Register; 0x00000023 */
volatile FTACKSTR _FTACK;                                  /* Fault Acknowledge Register; 0x00000024 */
volatile PWMOUTSTR _PWMOUT;                                /* PWM Output Control Register; 0x00000025 */
volatile DEADTMSTR _DEADTM;                                /* Dead-Time Write-Once Register; 0x00000036 */
volatile DISMAPSTR _DISMAP;                                /* PWM Disable Mapping Write-Once Register; 0x00000037 */
volatile SCC1STR _SCC1;                                    /* SCI Control Register 1; 0x00000038 */
volatile SCC2STR _SCC2;                                    /* SCI Control Register 2; 0x00000039 */
volatile SCC3STR _SCC3;                                    /* SCI Control Register 3; 0x0000003A */
volatile SCS1STR _SCS1;                                    /* SCI Status Register 1; 0x0000003B */
volatile SCS2STR _SCS2;                                    /* SCI Status Register 2; 0x0000003C */
volatile SCDRSTR _SCDR;                                    /* SCI Data Register; 0x0000003D */
volatile SCBRSTR _SCBR;                                    /* SCI Baud Rate Register; 0x0000003E */
volatile ISCRSTR _ISCR;                                    /* IRQ Status and Control Register; 0x0000003F */
volatile ADSCRSTR _ADSCR;                                  /* ADC Status and Control Register; 0x00000040 */
volatile ADCLKSTR _ADCLK;                                  /* ADC Clock Register; 0x00000043 */
volatile TBSCSTR _TBSC;                                    /* TIMB Status/Control Register; 0x00000051 */
volatile TBSC0STR _TBSC0;                                  /* TIMB Channel 0 Status/Control Register; 0x00000056 */
volatile TBSC1STR _TBSC1;                                  /* IMB Channel Status and Control Register; 0x00000059 */
volatile PCTLSTR _PCTL;                                    /* PLL Control Register; 0x0000005C */
volatile PBWCSTR _PBWC;                                    /* PLL Bandwith Control Register; 0x0000005D */
volatile PPGSTR _PPG;                                      /* PLL Programming Register; 0x0000005E */
volatile SBSRSTR _SBSR;                                    /* SIM Break Status Register; 0x0000FE00 */
volatile SRSRSTR _SRSR;                                    /* SIM Reset Status Register; 0x0000FE01 */
volatile SBFCRSTR _SBFCR;                                  /* SIM Break Flag Control Register; 0x0000FE03 */
volatile FLCRSTR _FLCR;                                    /* FLASH Control Register; 0x0000FE08 */
volatile BRKSCRSTR _BRKSCR;                                /* Break Status and Control Register; 0x0000FE0E */
volatile LVISCRSTR _LVISCR;                                /* LVI Status and Control Register; 0x0000FE0F */
/* FLBPR - macro for reading non volatile register         FLASH Block Protect Register; 0x0000FF7E */
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FF7E = <FLBPR_INITVAL>; */
volatile COPCTLSTR _COPCTL;                                /* COP Control Register; 0x0000FFFF */


/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile TACNTSTR _TACNT;                                  /* TIMA Counter Register; 0x0000000F */
volatile TAMODSTR _TAMOD;                                  /* TIMA Counter Modulo Register; 0x00000011 */
volatile TACH0STR _TACH0;                                  /* TIMA Channel 0 Register; 0x00000014 */
volatile TACH1STR _TACH1;                                  /* TIMA Channel 1 Register; 0x00000017 */
volatile PCNTSTR _PCNT;                                    /* PWM Counter Register; 0x00000026 */
volatile PMODSTR _PMOD;                                    /* PWM Counter Modulo Register; 0x00000028 */
volatile PVAL1STR _PVAL1;                                  /* PWM1 Value Register; 0x0000002A */
volatile PVAL2STR _PVAL2;                                  /* PWM2 Value Register; 0x0000002C */
volatile PVAL3STR _PVAL3;                                  /* PWM3 Value Register; 0x0000002E */
volatile PVAL4STR _PVAL4;                                  /* PWM4 Value Register; 0x00000030 */
volatile PVAL5STR _PVAL5;                                  /* PWM5 Value Register; 0x00000032 */
volatile PVAL6STR _PVAL6;                                  /* PWM6 Value Register; 0x00000034 */
volatile ADRSTR _ADR;                                      /* ADC Data Register; 0x00000041 */
volatile TBCNTSTR _TBCNT;                                  /* TIMB Counter Register; 0x00000052 */
volatile TBMODSTR _TBMOD;                                  /* TIMB Counter Modulo Register; 0x00000054 */
volatile TBCH0STR _TBCH0;                                  /* TIMB Channel 0 Register; 0x00000057 */
volatile TBCH1STR _TBCH1;                                  /* TIMB Channel 1 Register; 0x0000005A */
volatile BRKSTR _BRK;                                      /* Break Address Register; 0x0000FE0C */

/*lint -restore */

/* EOF */