/* Based on CPU DB MC68HC908LD60, version 2.87.134 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908LD60/D REV 1 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x00000009 */ volatile TSCSTR _TSC; /* Timer Status & Control; 0x0000000A */ volatile TSC0STR _TSC0; /* TIM Channel Status and Control Register 0; 0x00000010 */ volatile TSC1STR _TSC1; /* TIM Channel Status and Control Register 1; 0x00000013 */ volatile DMCRSTR _DMCR; /* DDC Master Control Register; 0x00000016 */ volatile DADRSTR _DADR; /* DDC Address Register; 0x00000017 */ volatile DCRSTR _DCR; /* DDC Control Register; 0x00000018 */ volatile DSR_DDCSTR _DSR_DDC; /* DDC Status Register; 0x00000019 */ volatile DDTRSTR _DDTR; /* DDC Data Transmit Register; 0x0000001A */ volatile DDRRSTR _DDRR; /* DDC Data Receive Register; 0x0000001B */ volatile D2ADRSTR _D2ADR; /* DDC2 Address Register; 0x0000001C */ volatile INTSCRSTR _INTSCR; /* IRQ Status and Control Register; 0x0000001E */ volatile CONFIGSTR _CONFIG; /* Configuration Register; 0x0000001F */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x00000038 */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x00000039 */ volatile PPGSTR _PPG; /* PLL Programming Register; 0x0000003A */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x0000003B */ volatile ADRSTR _ADR; /* ADC Data Register; 0x0000003C */ volatile ADICLKSTR _ADICLK; /* ADC Input Clock Register; 0x0000003D */ volatile HVOCRSTR _HVOCR; /* H & V Sync Output Control Register; 0x0000003F */ volatile SPCSRSTR _SPCSR; /* Sync Processor Control and Status Register; 0x00000040 */ volatile VFHRSTR _VFHR; /* Vertical Frequency Register High; 0x00000041 */ volatile VFLRSTR _VFLR; /* Vertical Frequency Register Low; 0x00000042 */ volatile HFHRSTR _HFHR; /* Hsync Frequency Register High; 0x00000043 */ volatile HFLRSTR _HFLR; /* Hsync Frequency Register Low; 0x00000044 */ volatile SPIOCRSTR _SPIOCR; /* Sync Processor Input/Output Control Register; 0x00000045 */ volatile SPCR1STR _SPCR1; /* Sync Processor Control Register 1; 0x00000046 */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register; 0x0000004E */ volatile KBIERSTR _KBIER; /* Keyboard Interrupt Enable Register; 0x0000004F */ volatile KEBUF_13STR _KEBUF_13; /* 13k-Byte FLASH Even Byte Write Buffer; 0x00000066 */ volatile PDCRSTR _PDCR; /* Port D Configuration Register; 0x00000069 */ volatile MIMCRSTR _MIMCR; /* Multi-Master IIC Master Control Register; 0x0000006A */ volatile MMADRSTR _MMADR; /* Multi-Master IIC Address Register; 0x0000006B */ volatile MMCRSTR _MMCR; /* Multi-Master IIC Control Register; 0x0000006C */ volatile MMSRSTR _MMSR; /* Multi-Master IIC Status Register; 0x0000006D */ volatile MMDTRSTR _MMDTR; /* Multi-Master IIC Data Transmit Register; 0x0000006E */ volatile MMDRRSTR _MMDRR; /* Multi-Master IIC Data Receive Register; 0x0000006F */ volatile PWM0STR _PWM0; /* PWM Data Register 0; 0x00000070 */ volatile PWM1STR _PWM1; /* PWM Data Register 1; 0x00000071 */ volatile PWM2STR _PWM2; /* PWM Data Register 2; 0x00000072 */ volatile PWM3STR _PWM3; /* PWM Data Register 3; 0x00000073 */ volatile PWM4STR _PWM4; /* PWM Data Register 4; 0x00000074 */ volatile PWM5STR _PWM5; /* PWM Data Register 5; 0x00000075 */ volatile PWM6STR _PWM6; /* PWM Data Register 6; 0x00000076 */ volatile PWM7STR _PWM7; /* PWM Data Register 7; 0x00000077 */ volatile PWMCRSTR _PWMCR; /* PWM Control Register; 0x00000078 */ volatile SBSRSTR _SBSR; /* SIM Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile INT1STR _INT1; /* Interrupt Status Register 1; 0x0000FE04 */ volatile INT2STR _INT2; /* Interrupt Status Register 2; 0x0000FE05 */ volatile FLCRSTR _FLCR; /* 47,616 Bytes FLASH Control Register; 0x0000FE07 */ /* FLBPR - macro for reading non volatile register FLASH Block Protect Register; 0x0000FE08 */ /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FE08 = ; */ volatile FLCR1STR _FLCR1; /* 13k-Bytes FLASH Control Register; 0x0000FE0A */ volatile FLBPR1STR _FLBPR1; /* 13k-Bytes FLASH Block Protect Register; 0x0000FE0B */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile TCNTSTR _TCNT; /* TIM Counter Register; 0x0000000C */ volatile TMODSTR _TMOD; /* TIM Counter Modulo Register; 0x0000000E */ volatile TCH0STR _TCH0; /* TIM channel 0 register; 0x00000011 */ volatile TCH1STR _TCH1; /* TIM channel 1 register; 0x00000014 */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /*lint -restore */ /* EOF */