/* Based on CPU DB MC68HC908JR32, version 2.87.091 (RegistersPrg V2.28) */ /* DataSheet : PC68HC908JF32 — Rev. 1.2 review May 17, 2004 5:02 am */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x00000009 */ volatile T1SCSTR _T1SC; /* TIM1 Status and Control Register TSC; 0x0000000A */ volatile T1SC0STR _T1SC0; /* TIM1 Channel 0 Status and Control Register; 0x00000010 */ volatile T1SC1STR _T1SC1; /* TIM1 Channel 1 Status and Control Register; 0x00000013 */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register; 0x00000016 */ volatile KBIERSTR _KBIER; /* Keyboard Interrrupt Enable Register KBIER; 0x00000017 */ volatile TBCRSTR _TBCR; /* Timebase Control Register; 0x00000018 */ volatile PS2CSRSTR _PS2CSR; /* I/O Control Register ; 0x00000019 */ volatile POCR1STR _POCR1; /* Port Option Control Register 1; 0x0000001A */ volatile POCR2STR _POCR2; /* Port Option Control Register 2; 0x0000001B */ volatile IOCRSTR _IOCR; /* IRQ Option Register; 0x0000001C */ volatile CONFIG2STR _CONFIG2; /* Configuration Register 2; 0x0000001D */ volatile ISCRSTR _ISCR; /* IRQ Status and Control Register; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register 1; 0x0000001F */ volatile DC1CRSTR _DC1CR; /* Data Codec 1 Control Register; 0x00000020 */ volatile DC1SCR1STR _DC1SCR1; /* Data Codec 1 Status & Control Register 1; 0x00000021 */ volatile DC1SR2STR _DC1SR2; /* Data Codec 1 StatusRegister 2; 0x00000022 */ volatile DC1ICRSTR _DC1ICR; /* Data Codec 1 Interrupt Control Register; 0x00000023 */ volatile DC1CNTSTR _DC1CNT; /* Data Codec 1 Counter Register; 0x00000024 */ volatile DC1CCNTSTR _DC1CCNT; /* Data Codec 1 Compensated Counter Register; 0x00000025 */ volatile DC1VAL1STR _DC1VAL1; /* Data Codec 1 Comparator 1 Register; 0x00000026 */ volatile DC1VAL2STR _DC1VAL2; /* Data Codec 1 Comparator 2 Register; 0x00000027 */ volatile DC1VAL3STR _DC1VAL3; /* Data Codec 1 Comparator 3 Register; 0x00000028 */ volatile DC1VAL4STR _DC1VAL4; /* Data Codec 1 Comparator 4 Register; 0x00000029 */ volatile DC1TOLSTR _DC1TOL; /* Data Codec 1 Tolerance Register; 0x0000002A */ volatile DC1BAUDSTR _DC1BAUD; /* Data Codec 1 Baud Selection Register; 0x0000002B */ volatile DC1DCNTSTR _DC1DCNT; /* Data Codec 1 Data Count Register; 0x0000002C */ volatile DC1PAGESTR _DC1PAGE; /* Data Codec 1 Page Register; 0x0000002D */ volatile DC1DATSTR _DC1DAT; /* Data Codec 1 Data Register; 0x0000002E */ volatile DC2CRSTR _DC2CR; /* Data Codec 2 Control Register; 0x0000002F */ volatile DC2SCR1STR _DC2SCR1; /* Data Codec 2 Status & Control Register 1; 0x00000030 */ volatile DC2SR2STR _DC2SR2; /* Data Codec 2 StatusRegister 2; 0x00000031 */ volatile DC2ICRSTR _DC2ICR; /* Data Codec 2 Interrupt Control Register; 0x00000032 */ volatile DC2CNTSTR _DC2CNT; /* Data Codec 2 Counter Register; 0x00000033 */ volatile DC2CCNTSTR _DC2CCNT; /* Data Codec 2 Compensated Counter Register; 0x00000034 */ volatile DC2VAL1STR _DC2VAL1; /* Data Codec 2 Comparator 1 Register; 0x00000035 */ volatile DC2VAL2STR _DC2VAL2; /* Data Codec 2 Comparator 2 Register; 0x00000036 */ volatile DC2VAL3STR _DC2VAL3; /* Data Codec 2 Comparator 3 Register; 0x00000037 */ volatile DC2VAL4STR _DC2VAL4; /* Data Codec 2 Comparator 4 Register; 0x00000038 */ volatile DC2TOLSTR _DC2TOL; /* Data Codec 2 Tolerance Register; 0x00000039 */ volatile DC2BAUDSTR _DC2BAUD; /* Data Codec 2 Baud Selection Register; 0x0000003A */ volatile DC2DCNTSTR _DC2DCNT; /* Data Codec 2 Data Count Register; 0x0000003B */ volatile DC2PAGESTR _DC2PAGE; /* Data Codec 2 Page Register; 0x0000003C */ volatile DC2DATSTR _DC2DAT; /* Data Codec 2 Data Register; 0x0000003D */ volatile PULLCRSTR _PULLCR; /* Pullup Control Register; 0x0000003E */ volatile ADATCRSTR _ADATCR; /* Alternate Data Control Register; 0x0000003F */ volatile UE0D0STR _UE0D0; /* USB Endpoint 0 Data Register 0; 0x00000040 */ volatile UE0D1STR _UE0D1; /* USB Endpoint 0 Data Register 1; 0x00000041 */ volatile UE0D2STR _UE0D2; /* USB Endpoint 0 Data Register 2; 0x00000042 */ volatile UE0D3STR _UE0D3; /* USB Endpoint 0 Data Register 3; 0x00000043 */ volatile UE0D4STR _UE0D4; /* USB Endpoint 0 Data Register 4; 0x00000044 */ volatile UE0D5STR _UE0D5; /* USB Endpoint 0 Data Register 5; 0x00000045 */ volatile UE0D6STR _UE0D6; /* USB Endpoint 0 Data Register 6; 0x00000046 */ volatile UE0D7STR _UE0D7; /* USB Endpoint 0 Data Register 7; 0x00000047 */ volatile SPCRSTR _SPCR; /* SPI Control Register; 0x0000004C */ volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register; 0x0000004D */ volatile SPDRSTR _SPDR; /* SPI Data Register; 0x0000004E */ volatile USBCRSTR _USBCR; /* USB Control Register; 0x00000051 */ volatile USBSRSTR _USBSR; /* USB Status Register; 0x00000052 */ volatile USIMRSTR _USIMR; /* USB Status Interrupt Mask Register; 0x00000053 */ volatile UEP0CSRSTR _UEP0CSR; /* USB Endpoint 0 Control/Status Register; 0x00000054 */ volatile UEP1CSRSTR _UEP1CSR; /* USB Endpoint 1 Control/Status Register; 0x00000055 */ volatile UEP2CSRSTR _UEP2CSR; /* USB Endpoint 2 Control/Status Register; 0x00000056 */ volatile UEP3CSRSTR _UEP3CSR; /* USB Endpoint 3 Control/Status Register; 0x00000057 */ volatile UEP4CSRSTR _UEP4CSR; /* USB Endpoint 4 Control/Status Register; 0x00000058 */ volatile UEP1DSRSTR _UEP1DSR; /* USB Endpoint 1 Data Size Register; 0x00000059 */ volatile UEP2DSRSTR _UEP2DSR; /* USB Endpoint 2 Data Size Register; 0x0000005A */ volatile UEP3DSRSTR _UEP3DSR; /* USB Endpoint 3 Data Size Register; 0x0000005B */ volatile UEP4DSRSTR _UEP4DSR; /* USB Endpoint 4 Data Size Register; 0x0000005C */ volatile UEP12BPRSTR _UEP12BPR; /* USB Endpoint 1/2 Base Pointer Register; 0x0000005D */ volatile UEP34BPRSTR _UEP34BPR; /* USB Endpoint 3/4 Base Pointer Register; 0x0000005E */ volatile UINTFCRSTR _UINTFCR; /* USB Interface Control Register; 0x0000005F */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x00001090 */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x00001091 */ volatile PMRSSTR _PMRS; /* PLL VCO Range Select; 0x00001094 */ volatile PMDSSTR _PMDS; /* PLL Reference Divider Select Register; 0x00001095 */ volatile BSRSTR _BSR; /* Break Status Register; 0x0000FE00 */ volatile RSRSTR _RSR; /* Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile INT1STR _INT1; /* Interrupt Status Register 1; 0x0000FE04 */ volatile INT2STR _INT2; /* Interrupt Status Register 2; 0x0000FE05 */ volatile INT3STR _INT3; /* Interrupt Status Register 3; 0x0000FE06 */ volatile FLCRSTR _FLCR; /* FLASH Control Register; 0x0000FE08 */ volatile FLBPRSTR _FLBPR; /* FLASH Block Protect Register; 0x0000FE09 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile LVISRSTR _LVISR; /* LVI I/O Register; 0x0000FE0F */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile T1CNTSTR _T1CNT; /* TIM1 Counter Register; 0x0000000C */ volatile T1MODSTR _T1MOD; /* TIM1 Counter Modulo Register; 0x0000000E */ volatile T1CH0STR _T1CH0; /* TIM1 Channel 0 Register; 0x00000011 */ volatile T1CH1STR _T1CH1; /* TIM1 Channel 1 Register; 0x00000014 */ volatile PMSSTR _PMS; /* PLL Multiplier Select Register; 0x00001092 */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /*lint -restore */ /* EOF */