/* Based on CPU DB MC68HC908JL8_32, version 2.89.073 (RegistersPrg V2.28) */
/* DataSheet : MC68HC908JL8/D Rev. 2, 12/2002 */

#include <mc68hc908jl8.h>

/*lint -save -esym(765, *) */


/* * * * *  8-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile PTASTR _PTA;                                      /* Port A Data Register; 0x00000000 */
volatile PTBSTR _PTB;                                      /* Port B Data Register; 0x00000001 */
volatile PTDSTR _PTD;                                      /* Port D Data Register; 0x00000003 */
volatile DDRASTR _DDRA;                                    /* Data Direction Register A; 0x00000004 */
volatile DDRBSTR _DDRB;                                    /* Data Direction Register B; 0x00000005 */
volatile DDRDSTR _DDRD;                                    /* Data Direction Register D; 0x00000007 */
volatile PTESTR _PTE;                                      /* Port E Data Register; 0x00000008 */
volatile PDCRSTR _PDCR;                                    /* Port D Control Register; 0x0000000A */
volatile DDRESTR _DDRE;                                    /* Data Direction Register E; 0x0000000C */
volatile PTAPUESTR _PTAPUE;                                /* Input Pull-Up Enable Register; 0x0000000D */
volatile PTA7PUESTR _PTA7PUE;                              /* Input Pull-Up Enable Register; 0x0000000E */
volatile SCC1STR _SCC1;                                    /* SCI Control Register 1; 0x00000013 */
volatile SCC2STR _SCC2;                                    /* SCI Control Register 2; 0x00000014 */
volatile SCC3STR _SCC3;                                    /* SCI Control Register 3; 0x00000015 */
volatile SCS1STR _SCS1;                                    /* SCI Status Register 1; 0x00000016 */
volatile SCS2STR _SCS2;                                    /* SCI Status Register 2; 0x00000017 */
volatile SCDRSTR _SCDR;                                    /* SCI Data Register; 0x00000018 */
volatile SCBRSTR _SCBR;                                    /* SCI Baud Rate Register; 0x00000019 */
volatile KBSCRSTR _KBSCR;                                  /* Keyboard Status and Control Register; 0x0000001A */
volatile KBIERSTR _KBIER;                                  /* Keyboard Interrrupt Enable Register; 0x0000001B */
volatile INTSCRSTR _INTSCR;                                /* IRQ Status and Control Register; 0x0000001D */
volatile CONFIG2STR _CONFIG2;                              /* Configuration Register 2; 0x0000001E */
volatile CONFIG1STR _CONFIG1;                              /* Configuration Register 1; 0x0000001F */
volatile T1SCSTR _T1SC;                                    /* TIM1 Status and Control Register TSC; 0x00000020 */
volatile T1SC0STR _T1SC0;                                  /* TIM1 Channel 0 Status and Control Register; 0x00000025 */
volatile T1SC1STR _T1SC1;                                  /* TIM1 Channel 1 Status and Control Register; 0x00000028 */
volatile T2SCSTR _T2SC;                                    /* TIM2 Status and Control Register; 0x00000030 */
volatile T2SC0STR _T2SC0;                                  /* TIM2 Channel 0 Status and Control Register; 0x00000035 */
volatile T2SC1STR _T2SC1;                                  /* TIM2 Channel 1 Status and Control Register; 0x00000038 */
volatile ADSCRSTR _ADSCR;                                  /* ADC Status and Control Register; 0x0000003C */
volatile ADRSTR _ADR;                                      /* ADC Data Register; 0x0000003D */
volatile ADICLKSTR _ADICLK;                                /* ADC Input Clock Register; 0x0000003E */
volatile BSRSTR _BSR;                                      /* Break Status Register; 0x0000FE00 */
volatile RSRSTR _RSR;                                      /* Reset Status Register; 0x0000FE01 */
volatile BFCRSTR _BFCR;                                    /* Break Flag Control Register; 0x0000FE03 */
volatile INT1STR _INT1;                                    /* Interrupt Status Register 1; 0x0000FE04 */
volatile INT2STR _INT2;                                    /* Interrupt Status Register 2; 0x0000FE05 */
volatile INT3STR _INT3;                                    /* Interrupt Status Register 3; 0x0000FE06 */
volatile FLCRSTR _FLCR;                                    /* FLASH Control Register; 0x0000FE08 */
volatile BRKSCRSTR _BRKSCR;                                /* Break Status and Control Register; 0x0000FE0E */
/* FLBPR - macro for reading non volatile register         FLASH Block Protect Register; 0x0000FFCF */
/* Tip for register initialization in the user code:  const byte FLBPR_INIT @0x0000FFCF = <FLBPR_INITVAL>; */
/* MOR - macro for reading non volatile register           Mask Option Register; 0x0000FFD0 */
/* Tip for register initialization in the user code:  const byte MOR_INIT @0x0000FFD0 = <MOR_INITVAL>; */
volatile COPCTLSTR _COPCTL;                                /* COP Control Register; 0x0000FFFF */


/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile T1CNTSTR _T1CNT;                                  /* TIM1 Counter Register; 0x00000021 */
volatile T1MODSTR _T1MOD;                                  /* TIM1 Counter Modulo Register; 0x00000023 */
volatile T1CH0STR _T1CH0;                                  /* TIM1 Channel 0 Register; 0x00000026 */
volatile T1CH1STR _T1CH1;                                  /* TIM1 Channel 1 Register; 0x00000029 */
volatile T2CNTSTR _T2CNT;                                  /* TIM2 Counter Register; 0x00000031 */
volatile T2MODSTR _T2MOD;                                  /* TIM2 Counter Modulo Register; 0x00000033 */
volatile T2CH0STR _T2CH0;                                  /* TIM2 Channel 0 Register; 0x00000036 */
volatile T2CH1STR _T2CH1;                                  /* TIM2 Channel 1 Register; 0x00000039 */
volatile BRKSTR _BRK;                                      /* Break Address Register; 0x0000FE0C */

/*lint -restore */

/* EOF */