/* Based on CPU DB MC68HC908JB16_28, version 2.89.057 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908JB16/D Rev. 1.1 August 1, 2005 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x00000009 */ volatile T1SCSTR _T1SC; /* TIM Status and Control Register TSC; 0x0000000A */ volatile T1SC0STR _T1SC0; /* TIM Channel 0 Status and Control Register; 0x00000010 */ volatile T1SC1STR _T1SC1; /* TIM Channel 1 Status and Control Register; 0x00000013 */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register; 0x00000016 */ volatile KBIERSTR _KBIER; /* Keyboard Interrrupt Enable Register KBIER; 0x00000017 */ volatile UIR2STR _UIR2; /* USB Interrupt Register 2; 0x00000018 */ volatile UCR2STR _UCR2; /* USB Control Register 2; 0x00000019 */ volatile UCR3STR _UCR3; /* USB Control Register 3; 0x0000001A */ volatile UCR4STR _UCR4; /* USB Control Register 4; 0x0000001B */ volatile IOCRSTR _IOCR; /* IRQ Option Register; 0x0000001C */ volatile POCRSTR _POCR; /* Port Option Control Register; 0x0000001D */ volatile ISCRSTR _ISCR; /* IRQ Status and Control Register; 0x0000001E */ volatile CONFIGSTR _CONFIG; /* Configuration Register; 0x0000001F */ volatile UE0D0STR _UE0D0; /* USB Endpoint 0 Data Register 0; 0x00000020 */ volatile UE0D1STR _UE0D1; /* USB Endpoint 0 Data Register 1; 0x00000021 */ volatile UE0D2STR _UE0D2; /* USB Endpoint 0 Data Register 2; 0x00000022 */ volatile UE0D3STR _UE0D3; /* USB Endpoint 0 Data Register 3; 0x00000023 */ volatile UE0D4STR _UE0D4; /* USB Endpoint 0 Data Register 4; 0x00000024 */ volatile UE0D5STR _UE0D5; /* USB Endpoint 0 Data Register 5; 0x00000025 */ volatile UE0D6STR _UE0D6; /* USB Endpoint 0 Data Register 6; 0x00000026 */ volatile UE0D7STR _UE0D7; /* USB Endpoint 0 Data Register 7; 0x00000027 */ volatile UE1D0STR _UE1D0; /* USB Endpoint 1 Data Register 0; 0x00000028 */ volatile UE1D1STR _UE1D1; /* USB Endpoint 1 Data Register 1; 0x00000029 */ volatile UE1D2STR _UE1D2; /* USB Endpoint 1 Data Register 2; 0x0000002A */ volatile UE1D3STR _UE1D3; /* USB Endpoint 1 Data Register 3; 0x0000002B */ volatile UE1D4STR _UE1D4; /* USB Endpoint 1 Data Register 4; 0x0000002C */ volatile UE1D5STR _UE1D5; /* USB Endpoint 1 Data Register 5; 0x0000002D */ volatile UE1D6STR _UE1D6; /* USB Endpoint 1 Data Register 6; 0x0000002E */ volatile UE1D7STR _UE1D7; /* USB Endpoint 1 Data Register 7; 0x0000002F */ volatile UE2D0STR _UE2D0; /* USB Endpoint 2 Data Register 0; 0x00000030 */ volatile UE2D1STR _UE2D1; /* USB Endpoint 2 Data Register 1; 0x00000031 */ volatile UE2D2STR _UE2D2; /* USB Endpoint 2 Data Register 2; 0x00000032 */ volatile UE2D3STR _UE2D3; /* USB Endpoint 2 Data Register 3; 0x00000033 */ volatile UE2D4STR _UE2D4; /* USB Endpoint 2 Data Register 4; 0x00000034 */ volatile UE2D5STR _UE2D5; /* USB Endpoint 2 Data Register 5; 0x00000035 */ volatile UE2D6STR _UE2D6; /* USB Endpoint 2 Data Register 6; 0x00000036 */ volatile UE2D7STR _UE2D7; /* USB Endpoint 2 Data Register 7; 0x00000037 */ volatile UADDRSTR _UADDR; /* USB Address Register ; 0x00000038 */ volatile UIR0STR _UIR0; /* USB Interrupt Register 0; 0x00000039 */ volatile UIR1STR _UIR1; /* USB Interrupt Register 1; 0x0000003A */ volatile UCR0STR _UCR0; /* USB Control Register 0; 0x0000003B */ volatile UCR1STR _UCR1; /* USB Control Register 1; 0x0000003C */ volatile USR0STR _USR0; /* USB Status Register 0; 0x0000003D */ volatile USR1STR _USR1; /* USB Status Register 1; 0x0000003E */ volatile T2SCSTR _T2SC; /* TIM2 Status and Control Register TSC; 0x00000040 */ volatile T2SC0STR _T2SC0; /* TIM2 Channel 0 Status and Control Register; 0x00000046 */ volatile T2SC1STR _T2SC1; /* TIM2 Channel 1 Status and Control Register; 0x00000049 */ volatile PBWCSTR _PBWC; /* CGM Bandwidth Control Register; 0x00000051 */ volatile PVCRSTR _PVCR; /* VCO Control Register; 0x00000052 */ volatile PNRH1STR _PNRH1; /* PLL1 N & R Divider Select Register High; 0x00000053 */ volatile PNSL1STR _PNSL1; /* PLL1 N Divider Select Register Low; 0x00000054 */ volatile PRSL1STR _PRSL1; /* PLL1 R Divider Select Register Low; 0x00000055 */ volatile PNRH2STR _PNRH2; /* PLL2 N & R Divider Select Register High; 0x00000056 */ volatile PNSL2STR _PNSL2; /* PLL2 N Divider Select Register Low; 0x00000057 */ volatile PRSL2STR _PRSL2; /* PLL2 R Divider Select Register Low; 0x00000058 */ volatile PDCRSTR _PDCR; /* Phase Detector Control Register; 0x00000059 */ volatile SCC1STR _SCC1; /* SCI Control Register 1; 0x0000005A */ volatile SCC2STR _SCC2; /* SCI Control Register 2; 0x0000005B */ volatile SCC3STR _SCC3; /* SCI Control Register 3; 0x0000005C */ volatile SCS1STR _SCS1; /* SCI Status Register 1; 0x0000005D */ volatile SCS2STR _SCS2; /* SCI Status Register 2; 0x0000005E */ volatile SCDRSTR _SCDR; /* SCI Data Register; 0x0000005F */ volatile SCBRSTR _SCBR; /* SCI Baud Rate Register; 0x00000060 */ volatile BSRSTR _BSR; /* Break Status Register; 0x0000FE00 */ volatile RSRSTR _RSR; /* Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile INT1STR _INT1; /* Interrupt Status Register 1; 0x0000FE04 */ volatile INT2STR _INT2; /* Interrupt Status Register 2; 0x0000FE05 */ volatile FLCRSTR _FLCR; /* FLASH Control Register; 0x0000FE08 */ volatile FLBPRSTR _FLBPR; /* FLASH Block Protect Register; 0x0000FE09 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile T1CNTSTR _T1CNT; /* TIM Counter Register; 0x0000000C */ volatile T1MODSTR _T1MOD; /* TIM Counter Modulo Register; 0x0000000E */ volatile T1CH0STR _T1CH0; /* TIM Channel 0 Register; 0x00000011 */ volatile T1CH1STR _T1CH1; /* TIM Channel 1 Register; 0x00000014 */ volatile T2CNTSTR _T2CNT; /* TIM2 Counter Register; 0x00000042 */ volatile T2MODSTR _T2MOD; /* TIM2 Counter Modulo Register; 0x00000044 */ volatile T2CH0STR _T2CH0; /* TIM2 Channel 0 Register; 0x00000047 */ volatile T2CH1STR _T2CH1; /* TIM2 Channel 1 Register; 0x0000004A */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /*lint -restore */ /* EOF */