/* Based on CPU DB MC68HC908GZ60_64, version 2.87.092 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908GZ60 Rev. 6.0 04/2007 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile SCPSCSTR _SCPSC; /* ESCI Prescaler Register; 0x00000009 */ volatile SCIACTLSTR _SCIACTL; /* ESCI Arbiter Control Register; 0x0000000A */ volatile SCIADATSTR _SCIADAT; /* ESCI Arbiter Data Register; 0x0000000B */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x0000000C */ volatile PTAPUESTR _PTAPUE; /* Port A Input Pullup Enable Register; 0x0000000D */ volatile PTCPUESTR _PTCPUE; /* Port C Input Pullup Enable Register; 0x0000000E */ volatile PTDPUESTR _PTDPUE; /* Port D Input Pullup Enable Register; 0x0000000F */ volatile SPCRSTR _SPCR; /* SPI Control Register; 0x00000010 */ volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register; 0x00000011 */ volatile SPDRSTR _SPDR; /* SPI Data Register; 0x00000012 */ volatile SCC1STR _SCC1; /* ESCI Control Register 1; 0x00000013 */ volatile SCC2STR _SCC2; /* ESCI Control Register 2; 0x00000014 */ volatile SCC3STR _SCC3; /* ESCI Control Register 3; 0x00000015 */ volatile SCS1STR _SCS1; /* ESCI Status Register 1; 0x00000016 */ volatile SCS2STR _SCS2; /* ESCI Status Register 2; 0x00000017 */ volatile SCDRSTR _SCDR; /* ESCI Data Register; 0x00000018 */ volatile SCBRSTR _SCBR; /* ESCI Baud Rate Register; 0x00000019 */ volatile INTKBSCRSTR _INTKBSCR; /* Keyboard Status and Control Register; 0x0000001A */ volatile INTKBIERSTR _INTKBIER; /* Keyboard Interrupt Enable Register; 0x0000001B */ volatile TBCRSTR _TBCR; /* Timebase Control Register; 0x0000001C */ volatile INTSCRSTR _INTSCR; /* IRQ Status and Control Register; 0x0000001D */ volatile CONFIG2STR _CONFIG2; /* Configuration Register 2; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register; 0x0000001F */ volatile T1SCSTR _T1SC; /* TIM1 Status and Control Register; 0x00000020 */ volatile T1SC0STR _T1SC0; /* TIM1 Channel 0 Status and Control Register; 0x00000025 */ volatile T1SC1STR _T1SC1; /* TIM1 Channel 1 Status and Control Register; 0x00000028 */ volatile T2SCSTR _T2SC; /* TIM2 Status and Control Register; 0x0000002B */ volatile T2SC0STR _T2SC0; /* TIM2 Channel 0 Status and Control Register; 0x00000030 */ volatile T2SC1STR _T2SC1; /* TIM2 Channel 1 Status and Control Register; 0x00000033 */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x00000036 */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x00000037 */ volatile PMRSSTR _PMRS; /* PLL VCO Range Select Register; 0x0000003A */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x0000003C */ volatile ADCLKSTR _ADCLK; /* ADC Input Clock Register; 0x0000003F */ volatile PTFSTR _PTF; /* Port F Data Register; 0x00000440 */ volatile PTGSTR _PTG; /* Port G Data Register; 0x00000441 */ volatile DDRFSTR _DDRF; /* Data Direction Register F; 0x00000444 */ volatile DDRGSTR _DDRG; /* Data Direction Register G; 0x00000445 */ volatile INTKBIPRSTR _INTKBIPR; /* Keyboard Interrupt Polarity Register; 0x00000448 */ volatile T2SC2STR _T2SC2; /* TIM2 Channel 2 Status and Control Register; 0x00000456 */ volatile T2SC3STR _T2SC3; /* TIM2 Channel 3 Status and Control Register; 0x00000459 */ volatile T2SC4STR _T2SC4; /* TIM2 Channel 4 Status and Control Register; 0x0000045C */ volatile T2SC5STR _T2SC5; /* TIM2 Channel 5 Status and Control Register; 0x0000045F */ volatile CMCR0STR _CMCR0; /* Module Control Register 0; 0x00000500 */ volatile CMCR1STR _CMCR1; /* Module Control Register 1; 0x00000501 */ volatile CBTR0STR _CBTR0; /* Bus Timing Register 0; 0x00000502 */ volatile CBTR1STR _CBTR1; /* Bus Timing Register 1; 0x00000503 */ volatile CRFLGSTR _CRFLG; /* Receiver Flag Register; 0x00000504 */ volatile CRIERSTR _CRIER; /* Receiver Interrupt Enable Register; 0x00000505 */ volatile CTFLGSTR _CTFLG; /* Transmitter Flag Register; 0x00000506 */ volatile CTCRSTR _CTCR; /* Transmitter Control Register; 0x00000507 */ volatile CIDACSTR _CIDAC; /* Identifier Acceptance Control Register; 0x00000508 */ volatile CRXERRSTR _CRXERR; /* Receiver Error Counter Register; 0x0000050E */ volatile CTXERRSTR _CTXERR; /* Transmit Error Counter Register; 0x0000050F */ volatile REC_DSR0STR _REC_DSR0; /* Receive Buffer Data Segment Register 0; 0x00000544 */ volatile REC_DSR1STR _REC_DSR1; /* Receive Buffer Data Segment Register 1; 0x00000545 */ volatile REC_DSR2STR _REC_DSR2; /* Receive Buffer Data Segment Register 2; 0x00000546 */ volatile REC_DSR3STR _REC_DSR3; /* Receive Buffer Data Segment Register 3; 0x00000547 */ volatile REC_DSR4STR _REC_DSR4; /* Receive Buffer Data Segment Register 4; 0x00000548 */ volatile REC_DSR5STR _REC_DSR5; /* Receive Buffer Data Segment Register 5; 0x00000549 */ volatile REC_DSR6STR _REC_DSR6; /* Receive Buffer Data Segment Register 6; 0x0000054A */ volatile REC_DSR7STR _REC_DSR7; /* Receive Buffer Data Segment Register 7; 0x0000054B */ volatile REC_DLRSTR _REC_DLR; /* Receive Buffer Data Length Register; 0x0000054C */ volatile DSR00STR _DSR00; /* Transmit Buffer 0 Data Segment Register 0; 0x00000554 */ volatile DSR10STR _DSR10; /* Transmit Buffer 0 Data Segment Register 1; 0x00000555 */ volatile DSR20STR _DSR20; /* Transmit Buffer 0 Data Segment Register 2; 0x00000556 */ volatile DSR30STR _DSR30; /* Transmit Buffer 0 Data Segment Register 3; 0x00000557 */ volatile DSR40STR _DSR40; /* Transmit Buffer 0 Data Segment Register 4; 0x00000558 */ volatile DSR50STR _DSR50; /* Transmit Buffer 0 Data Segment Register 5; 0x00000559 */ volatile DSR60STR _DSR60; /* Transmit Buffer 0 Data Segment Register 6; 0x0000055A */ volatile DSR70STR _DSR70; /* Transmit Buffer 0 Data Segment Register 7; 0x0000055B */ volatile DLR0STR _DLR0; /* Transmit Buffer 0 Data Length Register; 0x0000055C */ volatile TBPR0STR _TBPR0; /* Transmit Buffer 0 Priority Register; 0x0000055D */ volatile DSR01STR _DSR01; /* Transmit Buffer 1 Data Segment Register 0; 0x00000564 */ volatile DSR11STR _DSR11; /* Transmit Buffer 1 Data Segment Register 1; 0x00000565 */ volatile DSR21STR _DSR21; /* Transmit Buffer 1 Data Segment Register 2; 0x00000566 */ volatile DSR31STR _DSR31; /* Transmit Buffer 1 Data Segment Register 3; 0x00000567 */ volatile DSR41STR _DSR41; /* Transmit Buffer 1 Data Segment Register 4; 0x00000568 */ volatile DSR51STR _DSR51; /* Transmit Buffer 1 Data Segment Register 5; 0x00000569 */ volatile DSR61STR _DSR61; /* Transmit Buffer 1 Data Segment Register 6; 0x0000056A */ volatile DSR71STR _DSR71; /* Transmit Buffer 1 Data Segment Register 7; 0x0000056B */ volatile DLR1STR _DLR1; /* Transmit Buffer 1 Data Length Register; 0x0000056C */ volatile TBPR1STR _TBPR1; /* Transmit Buffer 1 Priority Register; 0x0000056D */ volatile DSR02STR _DSR02; /* Transmit Buffer 2 Data Segment Register 0; 0x00000574 */ volatile DSR12STR _DSR12; /* Transmit Buffer 2 Data Segment Register 1; 0x00000575 */ volatile DSR22STR _DSR22; /* Transmit Buffer 2 Data Segment Register 2; 0x00000576 */ volatile DSR32STR _DSR32; /* Transmit Buffer 2 Data Segment Register 3; 0x00000577 */ volatile DSR42STR _DSR42; /* Transmit Buffer 2 Data Segment Register 4; 0x00000578 */ volatile DSR52STR _DSR52; /* Transmit Buffer 2 Data Segment Register 5; 0x00000579 */ volatile DSR62STR _DSR62; /* Transmit Buffer 2 Data Segment Register 6; 0x0000057A */ volatile DSR72STR _DSR72; /* Transmit Buffer 2 Data Segment Register 7; 0x0000057B */ volatile DLR2STR _DLR2; /* Transmit Buffer 2 Data Length Register; 0x0000057C */ volatile TBPR2STR _TBPR2; /* Transmit Buffer 2 Priority Register; 0x0000057D */ volatile BSRSTR _BSR; /* Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile INT1STR _INT1; /* Interrupt Status Register 1; 0x0000FE04 */ volatile INT2STR _INT2; /* Interrupt Status Register 2; 0x0000FE05 */ volatile INT3STR _INT3; /* Interrupt Status Register 3; 0x0000FE06 */ volatile INT4STR _INT4; /* Interrupt Status Register 4; 0x0000FE07 */ volatile FL2CRSTR _FL2CR; /* FLASH 2 Control Register; 0x0000FE08 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0B */ volatile LVISRSTR _LVISR; /* LVI Status Register; 0x0000FE0C */ /* FL1BPR - macro for reading non volatile register FLASH 1 Block Protect Register; 0x0000FF80 */ /* Tip for register initialization in the user code: const byte FL1BPR_INIT @0x0000FF80 = ; */ /* FL2BPR - macro for reading non volatile register FLASH 2 Block Protect Register; 0x0000FF81 */ /* Tip for register initialization in the user code: const byte FL2BPR_INIT @0x0000FF81 = ; */ volatile FL1CRSTR _FL1CR; /* FLASH 1 Control Register; 0x0000FF88 */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile T1CNTSTR _T1CNT; /* TIM1 Counter Register; 0x00000021 */ volatile T1MODSTR _T1MOD; /* TIM1 Counter Modulo Register; 0x00000023 */ volatile T1CH0STR _T1CH0; /* TIM1 Channel 0 Register; 0x00000026 */ volatile T1CH1STR _T1CH1; /* TIM1 Channel 1 Register; 0x00000029 */ volatile T2CNTSTR _T2CNT; /* TIM2 Counter Register; 0x0000002C */ volatile T2MODSTR _T2MOD; /* TIM2 Counter Modulo Register; 0x0000002E */ volatile T2CH0STR _T2CH0; /* TIM2 Channel 0 Register; 0x00000031 */ volatile T2CH1STR _T2CH1; /* TIM2 Channel 1 Register; 0x00000034 */ volatile PMSSTR _PMS; /* PLL Multiplier Select Register; 0x00000038 */ volatile ADRSTR _ADR; /* ADC Data Register; 0x0000003D */ volatile T2CH2STR _T2CH2; /* TIM2 Channel 2 Register; 0x00000457 */ volatile T2CH3STR _T2CH3; /* TIM2 Channel 3 Register; 0x0000045A */ volatile T2CH4STR _T2CH4; /* TIM2 Channel 4 Register; 0x0000045D */ volatile T2CH5STR _T2CH5; /* TIM2 Channel 5 Register; 0x00000460 */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE09 */ /* * * * * 32-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile CIDARSTR _CIDAR; /* Identifier Acceptance Register; 0x00000510 */ volatile CIDMRSTR _CIDMR; /* Identifier Mask Register; 0x00000514 */ volatile REC_IDRSTR _REC_IDR; /* Receive Buffer Identifier Register; 0x00000540 */ volatile IDR0STR _IDR0; /* Transmit Buffer 0 Identifier Register; 0x00000550 */ volatile IDR1STR _IDR1; /* Transmit Buffer 1 Identifier Register; 0x00000560 */ volatile IDR2STR _IDR2; /* Transmit Buffer 2 Identifier Register; 0x00000570 */ /*lint -restore */ /* EOF */