/* Based on CPU DB MC68HC908AZ60A, version 2.89.090 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908AZ60A Rev. 6 05/2006 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile PTFSTR _PTF; /* Port F Data Register; 0x00000009 */ volatile PTGSTR _PTG; /* Port G Data Register; 0x0000000A */ volatile PTHSTR _PTH; /* Port H Data Register; 0x0000000B */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x0000000C */ volatile DDRFSTR _DDRF; /* Data Direction Register F; 0x0000000D */ volatile DDRGSTR _DDRG; /* Data Direction Register G; 0x0000000E */ volatile DDRHSTR _DDRH; /* Data Direction Register H; 0x0000000F */ volatile SPCRSTR _SPCR; /* SPI Control Register; 0x00000010 */ volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register; 0x00000011 */ volatile SPDRSTR _SPDR; /* SPI Data Register; 0x00000012 */ volatile SCC1STR _SCC1; /* SCI Control Register 1; 0x00000013 */ volatile SCC2STR _SCC2; /* SCI Control Register 2; 0x00000014 */ volatile SCC3STR _SCC3; /* SCI Control Register 3; 0x00000015 */ volatile SCS1STR _SCS1; /* SCI Status Register 1; 0x00000016 */ volatile SCS2STR _SCS2; /* SCI Status Register 2; 0x00000017 */ volatile SCDRSTR _SCDR; /* SCI Data Register; 0x00000018 */ volatile SCBRSTR _SCBR; /* SCI Baud Rate Register; 0x00000019 */ volatile ISCRSTR _ISCR; /* IRQ Status and Control Register; 0x0000001A */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register; 0x0000001B */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x0000001C */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x0000001D */ volatile PPGSTR _PPG; /* PLL Programming Register; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register; 0x0000001F */ volatile TASCSTR _TASC; /* TIMA Status and Control Register; 0x00000020 */ volatile KBIERSTR _KBIER; /* Keyboard Interrupt Enable Register; 0x00000021 */ volatile TASC0STR _TASC0; /* TIMA Channel Status and Control Register; 0x00000026 */ volatile TASC1STR _TASC1; /* TIMA Channel Status and Control Register; 0x00000029 */ volatile TASC2STR _TASC2; /* TIMA Channel Status and Control Register; 0x0000002C */ volatile TASC3STR _TASC3; /* TIMA Channel Status and Control Register; 0x0000002F */ volatile TASC4STR _TASC4; /* TIMA Channel Status and Control Register; 0x00000032 */ volatile TASC5STR _TASC5; /* TIMA Channel Status and Control Register; 0x00000035 */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x00000038 */ volatile ADRSTR _ADR; /* ADC Data Register; 0x00000039 */ volatile ADICLKSTR _ADICLK; /* ADC Input Clock Register; 0x0000003A */ volatile TBSCRSTR _TBSCR; /* TIMB Status and Control Register; 0x00000040 */ volatile TBSC0STR _TBSC0; /* TIMB Channel Status and Control Register; 0x00000045 */ volatile TBSC1STR _TBSC1; /* IMB Channel Status and Control Register; 0x00000048 */ volatile PSCSTR _PSC; /* Timer Status & Control; 0x0000004B */ volatile CMCR0STR _CMCR0; /* Module Control Register 0; 0x00000500 */ volatile CMCR1STR _CMCR1; /* Module Control Register 1; 0x00000501 */ volatile CBTR0STR _CBTR0; /* Bus Timing Register 0; 0x00000502 */ volatile CBTR1STR _CBTR1; /* Bus Timing Register 1; 0x00000503 */ volatile CRFLGSTR _CRFLG; /* Receiver Flag Register; 0x00000504 */ volatile CRIERSTR _CRIER; /* Receiver Interrupt Enable Register; 0x00000505 */ volatile CTFLGSTR _CTFLG; /* Transmitter Flag Register; 0x00000506 */ volatile CTCRSTR _CTCR; /* Transmitter Control Register; 0x00000507 */ volatile CIDACSTR _CIDAC; /* Identifier Acceptance Control Register; 0x00000508 */ volatile CRXERRSTR _CRXERR; /* Receiver Error Counter Register; 0x0000050E */ volatile CTXERRSTR _CTXERR; /* Transmit Error Counter Register; 0x0000050F */ volatile REC_DSR0STR _REC_DSR0; /* Receive Buffer Data Segment Register 0; 0x00000544 */ volatile REC_DSR1STR _REC_DSR1; /* Receive Buffer Data Segment Register 1; 0x00000545 */ volatile REC_DSR2STR _REC_DSR2; /* Receive Buffer Data Segment Register 2; 0x00000546 */ volatile REC_DSR3STR _REC_DSR3; /* Receive Buffer Data Segment Register 3; 0x00000547 */ volatile REC_DSR4STR _REC_DSR4; /* Receive Buffer Data Segment Register 4; 0x00000548 */ volatile REC_DSR5STR _REC_DSR5; /* Receive Buffer Data Segment Register 5; 0x00000549 */ volatile REC_DSR6STR _REC_DSR6; /* Receive Buffer Data Segment Register 6; 0x0000054A */ volatile REC_DSR7STR _REC_DSR7; /* Receive Buffer Data Segment Register 7; 0x0000054B */ volatile REC_DLRSTR _REC_DLR; /* Receive Buffer Data Length Register; 0x0000054C */ volatile DSR00STR _DSR00; /* Transmit Buffer 0 Data Segment Register 0; 0x00000554 */ volatile DSR10STR _DSR10; /* Transmit Buffer 0 Data Segment Register 1; 0x00000555 */ volatile DSR20STR _DSR20; /* Transmit Buffer 0 Data Segment Register 2; 0x00000556 */ volatile DSR30STR _DSR30; /* Transmit Buffer 0 Data Segment Register 3; 0x00000557 */ volatile DSR40STR _DSR40; /* Transmit Buffer 0 Data Segment Register 4; 0x00000558 */ volatile DSR50STR _DSR50; /* Transmit Buffer 0 Data Segment Register 5; 0x00000559 */ volatile DSR60STR _DSR60; /* Transmit Buffer 0 Data Segment Register 6; 0x0000055A */ volatile DSR70STR _DSR70; /* Transmit Buffer 0 Data Segment Register 7; 0x0000055B */ volatile DLR0STR _DLR0; /* Transmit Buffer 0 Data Length Register; 0x0000055C */ volatile TBPR0STR _TBPR0; /* Transmit Buffer 0 Priority Register; 0x0000055D */ volatile DSR01STR _DSR01; /* Transmit Buffer 1 Data Segment Register 0; 0x00000564 */ volatile DSR11STR _DSR11; /* Transmit Buffer 1 Data Segment Register 1; 0x00000565 */ volatile DSR21STR _DSR21; /* Transmit Buffer 1 Data Segment Register 2; 0x00000566 */ volatile DSR31STR _DSR31; /* Transmit Buffer 1 Data Segment Register 3; 0x00000567 */ volatile DSR41STR _DSR41; /* Transmit Buffer 1 Data Segment Register 4; 0x00000568 */ volatile DSR51STR _DSR51; /* Transmit Buffer 1 Data Segment Register 5; 0x00000569 */ volatile DSR61STR _DSR61; /* Transmit Buffer 1 Data Segment Register 6; 0x0000056A */ volatile DSR71STR _DSR71; /* Transmit Buffer 1 Data Segment Register 7; 0x0000056B */ volatile DLR1STR _DLR1; /* Transmit Buffer 1 Data Length Register; 0x0000056C */ volatile TBPR1STR _TBPR1; /* Transmit Buffer 1 Priority Register; 0x0000056D */ volatile DSR02STR _DSR02; /* Transmit Buffer 2 Data Segment Register 0; 0x00000574 */ volatile DSR12STR _DSR12; /* Transmit Buffer 2 Data Segment Register 1; 0x00000575 */ volatile DSR22STR _DSR22; /* Transmit Buffer 2 Data Segment Register 2; 0x00000576 */ volatile DSR32STR _DSR32; /* Transmit Buffer 2 Data Segment Register 3; 0x00000577 */ volatile DSR42STR _DSR42; /* Transmit Buffer 2 Data Segment Register 4; 0x00000578 */ volatile DSR52STR _DSR52; /* Transmit Buffer 2 Data Segment Register 5; 0x00000579 */ volatile DSR62STR _DSR62; /* Transmit Buffer 2 Data Segment Register 6; 0x0000057A */ volatile DSR72STR _DSR72; /* Transmit Buffer 2 Data Segment Register 7; 0x0000057B */ volatile DLR2STR _DLR2; /* Transmit Buffer 2 Data Length Register; 0x0000057C */ volatile TBPR2STR _TBPR2; /* Transmit Buffer 2 Priority Register; 0x0000057D */ volatile SBSRSTR _SBSR; /* SIM Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile FL2CRSTR _FL2CR; /* FLASH2 Control Register; 0x0000FE08 */ volatile CONFIG2STR _CONFIG2; /* Configuration Register; 0x0000FE09 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile LVISRSTR _LVISR; /* LVI Status Register; 0x0000FE0F */ /* EE1DIVHNVR - macro for reading non volatile register EE1DIV Hi Non-volatile Register; 0x0000FE10 */ /* Tip for register initialization in the user code: const byte EE1DIVHNVR_INIT @0x0000FE10 = ; */ /* EE1DIVLNVR - macro for reading non volatile register EE1DIV Lo Non-volatile Register; 0x0000FE11 */ /* Tip for register initialization in the user code: const byte EE1DIVLNVR_INIT @0x0000FE11 = ; */ volatile EE1DIVHSTR _EE1DIVH; /* EE1DIV Divider High Register; 0x0000FE1A */ volatile EE1DIVLSTR _EE1DIVL; /* EE1DIV Divider Low Register; 0x0000FE1B */ /* EE1NVR - macro for reading non volatile register EEPROM1 Nonvolatile Register; 0x0000FE1C */ /* Tip for register initialization in the user code: const byte EE1NVR_INIT @0x0000FE1C = ; */ volatile EE1CRSTR _EE1CR; /* EEPROM1 Control Register; 0x0000FE1D */ volatile EE1ACRSTR _EE1ACR; /* EEPROM1 Array Control Register; 0x0000FE1F */ /* EE2DIVHNVR - macro for reading non volatile register EE2DIV Hi Non-volatile Register; 0x0000FF70 */ /* Tip for register initialization in the user code: const byte EE2DIVHNVR_INIT @0x0000FF70 = ; */ /* EE2DIVLNVR - macro for reading non volatile register EE2DIV Lo Non-volatile Register; 0x0000FF71 */ /* Tip for register initialization in the user code: const byte EE2DIVLNVR_INIT @0x0000FF71 = ; */ volatile EE2DIVHSTR _EE2DIVH; /* EE2DIV Divider High Register; 0x0000FF7A */ volatile EE2DIVLSTR _EE2DIVL; /* EE2DIV Divider Low Register; 0x0000FF7B */ /* EE2NVR - macro for reading non volatile register EEPROM2 Nonvolatile Register; 0x0000FF7C */ /* Tip for register initialization in the user code: const byte EE2NVR_INIT @0x0000FF7C = ; */ volatile EE2CRSTR _EE2CR; /* EEPROM2 Control Register; 0x0000FF7D */ volatile EE2ACRSTR _EE2ACR; /* EEPROM2 Array Control Register; 0x0000FF7F */ /* FL1BPR - macro for reading non volatile register FLASH1 Block Protect Register; 0x0000FF80 */ /* Tip for register initialization in the user code: const byte FL1BPR_INIT @0x0000FF80 = ; */ /* FL2BPR - macro for reading non volatile register FLASH2 Block Protect Register; 0x0000FF81 */ /* Tip for register initialization in the user code: const byte FL2BPR_INIT @0x0000FF81 = ; */ volatile FL1CRSTR _FL1CR; /* FLASH1 Control Register; 0x0000FF88 */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile TACNTSTR _TACNT; /* TIMA Counter Register; 0x00000022 */ volatile TAMODSTR _TAMOD; /* TIMA Counter Modulo Register; 0x00000024 */ volatile TACH0STR _TACH0; /* TIMA Channel Register; 0x00000027 */ volatile TACH1STR _TACH1; /* TIMA Channel Register; 0x0000002A */ volatile TACH2STR _TACH2; /* TIMA Channel Register; 0x0000002D */ volatile TACH3STR _TACH3; /* TIMA Channel Register; 0x00000030 */ volatile TACH4STR _TACH4; /* TIMA Channel Register; 0x00000033 */ volatile TACH5STR _TACH5; /* TIMA Channel Register; 0x00000036 */ volatile TBCNTSTR _TBCNT; /* TIMB Counter Register; 0x00000041 */ volatile TBMODSTR _TBMOD; /* TIMB Counter Modulo Register; 0x00000043 */ volatile TBCH0STR _TBCH0; /* TIMB Channel Register; 0x00000046 */ volatile TBCH1STR _TBCH1; /* TIMB Channel Register; 0x00000049 */ volatile PCNTSTR _PCNT; /* PIT Counter Register; 0x0000004C */ volatile PMODSTR _PMOD; /* PIT Counter Modulo Register; 0x0000004E */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /* * * * * 32-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile CIDARSTR _CIDAR; /* Identifier Acceptance Register; 0x00000510 */ volatile CIDMRSTR _CIDMR; /* Identifier Mask Register; 0x00000514 */ volatile REC_IDRSTR _REC_IDR; /* Receive Buffer Identifier Register; 0x00000540 */ volatile IDR0STR _IDR0; /* Transmit Buffer 0 Identifier Register; 0x00000550 */ volatile IDR1STR _IDR1; /* Transmit Buffer 1 Identifier Register; 0x00000560 */ volatile IDR2STR _IDR2; /* Transmit Buffer 2 Identifier Register; 0x00000570 */ /*lint -restore */ /* EOF */