/* Based on CPU DB MC68HC908AS60_64, version 2.89.024 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908AS60/D REV 1 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile PTFSTR _PTF; /* Port F Data Register; 0x00000009 */ volatile PTGSTR _PTG; /* Port G Data Register; 0x0000000A */ volatile PTHSTR _PTH; /* Port H Data Register; 0x0000000B */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x0000000C */ volatile DDRFSTR _DDRF; /* Data Direction Register F; 0x0000000D */ volatile DDRGSTR _DDRG; /* Data Direction Register G; 0x0000000E */ volatile DDRHSTR _DDRH; /* Data Direction Register H; 0x0000000F */ volatile SPCRSTR _SPCR; /* SPI Control Register; 0x00000010 */ volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register; 0x00000011 */ volatile SPDRSTR _SPDR; /* SPI Data Register; 0x00000012 */ volatile SCC1STR _SCC1; /* SCI Control Register 1; 0x00000013 */ volatile SCC2STR _SCC2; /* SCI Control Register 2; 0x00000014 */ volatile SCC3STR _SCC3; /* SCI Control Register 3; 0x00000015 */ volatile SCS1STR _SCS1; /* SCI Status Register 1; 0x00000016 */ volatile SCS2STR _SCS2; /* SCI Status Register 2; 0x00000017 */ volatile SCDRSTR _SCDR; /* SCI Data Register; 0x00000018 */ volatile SCBRSTR _SCBR; /* SCI Baud Rate Register; 0x00000019 */ volatile ISCRSTR _ISCR; /* IRQ Status and Control Register; 0x0000001A */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x0000001C */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x0000001D */ volatile PPGSTR _PPG; /* PLL Programming Register; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register; 0x0000001F */ volatile TASCSTR _TASC; /* TIMA Status and Control Register; 0x00000020 */ volatile TASC0STR _TASC0; /* TIMA Channel Status and Control Register; 0x00000026 */ volatile TASC1STR _TASC1; /* TIMA Channel Status and Control Register; 0x00000029 */ volatile TASC2STR _TASC2; /* TIMA Channel Status and Control Register; 0x0000002C */ volatile TASC3STR _TASC3; /* TIMA Channel Status and Control Register; 0x0000002F */ volatile TASC4STR _TASC4; /* TIMA Channel Status and Control Register; 0x00000032 */ volatile TASC5STR _TASC5; /* TIMA Channel Status and Control Register; 0x00000035 */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x00000038 */ volatile ADRSTR _ADR; /* ADC Data Register; 0x00000039 */ volatile ADICLKSTR _ADICLK; /* ADC Input Clock Register; 0x0000003A */ volatile BARDSTR _BARD; /* BDLC Analog and Roundtrip Delay Register; 0x0000003B */ volatile BCR1STR _BCR1; /* BDLC Control Register 1; 0x0000003C */ volatile BCR2STR _BCR2; /* BDLC Control Register 2; 0x0000003D */ volatile BSVRSTR _BSVR; /* BDLC State Vector Register; 0x0000003E */ volatile BDRSTR _BDR; /* BDLC Data Register; 0x0000003F */ volatile TSCSTR _TSC; /* Timer Status & Control; 0x0000004B */ volatile SBSRSTR _SBSR; /* SIM Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile FLCR1STR _FLCR1; /* FLASH1 Control Register; 0x0000FE0B */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile LVISRSTR _LVISR; /* LVI Status Register; 0x0000FE0F */ volatile FLCR2STR _FLCR2; /* FLASH2 Control Register; 0x0000FE11 */ /* EENVR2 - macro for reading non volatile register EEPROM2 Nonvolatile Register; 0x0000FE18 */ /* Tip for register initialization in the user code: const byte EENVR2_INIT @0x0000FE18 = ; */ volatile EECR2STR _EECR2; /* EEPROM2 Control Register; 0x0000FE19 */ volatile EEACR2STR _EEACR2; /* EEPROM2 Array Control Register; 0x0000FE1B */ /* EENVR1 - macro for reading non volatile register EEPROM1 Nonvolatile Register; 0x0000FE1C */ /* Tip for register initialization in the user code: const byte EENVR1_INIT @0x0000FE1C = ; */ volatile EECR1STR _EECR1; /* EEPROM1 Control Register; 0x0000FE1D */ volatile EEACR1STR _EEACR1; /* EEPROM1 Array Control Register; 0x0000FE1F */ /* FLBPR1 - macro for reading non volatile register FLASH1 Block Protect Register; 0x0000FF80 */ /* Tip for register initialization in the user code: const byte FLBPR1_INIT @0x0000FF80 = ; */ /* FLBPR2 - macro for reading non volatile register FLASH2 Block Protect Register; 0x0000FF81 */ /* Tip for register initialization in the user code: const byte FLBPR2_INIT @0x0000FF81 = ; */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile TACNTSTR _TACNT; /* TIMA Counter Register; 0x00000022 */ volatile TAMODSTR _TAMOD; /* TIMA Counter Modulo Register; 0x00000024 */ volatile TACH0STR _TACH0; /* TIMA Channel Register; 0x00000027 */ volatile TACH1STR _TACH1; /* TIMA Channel Register; 0x0000002A */ volatile TACH2STR _TACH2; /* TIMA Channel Register; 0x0000002D */ volatile TACH3STR _TACH3; /* TIMA Channel Register; 0x00000030 */ volatile TACH4STR _TACH4; /* TIMA Channel Register; 0x00000033 */ volatile TACH5STR _TACH5; /* TIMA Channel Register; 0x00000036 */ volatile TCNTSTR _TCNT; /* TIM Counter Register; 0x0000004C */ volatile TMODSTR _TMOD; /* TIM Counter Modulo Register; 0x0000004E */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /*lint -restore */ /* EOF */