/* Based on CPU DB MC68HC908AS32A, version 2.89.033 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908AS32A Rev. 2.0 05/2006 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile PTESTR _PTE; /* Port E Data Register; 0x00000008 */ volatile PTFSTR _PTF; /* Port F Data Register; 0x00000009 */ volatile DDRESTR _DDRE; /* Data Direction Register E; 0x0000000C */ volatile DDRFSTR _DDRF; /* Data Direction Register F; 0x0000000D */ volatile SPCRSTR _SPCR; /* SPI Control Register; 0x00000010 */ volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register; 0x00000011 */ volatile SPDRSTR _SPDR; /* SPI Data Register; 0x00000012 */ volatile SCC1STR _SCC1; /* SCI Control Register 1; 0x00000013 */ volatile SCC2STR _SCC2; /* SCI Control Register 2; 0x00000014 */ volatile SCC3STR _SCC3; /* SCI Control Register 3; 0x00000015 */ volatile SCS1STR _SCS1; /* SCI Status Register 1; 0x00000016 */ volatile SCS2STR _SCS2; /* SCI Status Register 2; 0x00000017 */ volatile SCDRSTR _SCDR; /* SCI Data Register; 0x00000018 */ volatile SCBRSTR _SCBR; /* SCI Baud Rate Register; 0x00000019 */ volatile ISCRSTR _ISCR; /* IRQ Status and Control Register; 0x0000001A */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x0000001C */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x0000001D */ volatile PPGSTR _PPG; /* PLL Programming Register; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register; 0x0000001F */ volatile TSCSTR _TSC; /* TIM Status and Control Register; 0x00000020 */ volatile TSC0STR _TSC0; /* TIM Channel Status and Control Register; 0x00000026 */ volatile TSC1STR _TSC1; /* TIM Channel Status and Control Register; 0x00000029 */ volatile TSC2STR _TSC2; /* TIM Channel Status and Control Register; 0x0000002C */ volatile TSC3STR _TSC3; /* TIM Channel Status and Control Register; 0x0000002F */ volatile TSC4STR _TSC4; /* TIM Channel Status and Control Register; 0x00000032 */ volatile TSC5STR _TSC5; /* TIM Channel Status and Control Register; 0x00000035 */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x00000038 */ volatile ADRSTR _ADR; /* ADC Data Register; 0x00000039 */ volatile ADICLKSTR _ADICLK; /* ADC Input Clock Register; 0x0000003A */ volatile BARDSTR _BARD; /* BDLC Analog and Roundtrip Delay Register; 0x0000003B */ volatile BCR1STR _BCR1; /* BDLC Control Register 1; 0x0000003C */ volatile BCR2STR _BCR2; /* BDLC Control Register 2; 0x0000003D */ volatile BSVRSTR _BSVR; /* BDLC State Vector Register; 0x0000003E */ volatile BDRSTR _BDR; /* BDLC Data Register; 0x0000003F */ volatile PSCSTR _PSC; /* Timer Status & Control; 0x0000004B */ volatile SBSRSTR _SBSR; /* SIM Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile CONFIG2STR _CONFIG2; /* Configuration Register; 0x0000FE09 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile LVISRSTR _LVISR; /* LVI Status Register; 0x0000FE0F */ /* EEDIVHNVR - macro for reading non volatile register EEDIV Hi Non-volatile Register; 0x0000FE10 */ /* Tip for register initialization in the user code: const byte EEDIVHNVR_INIT @0x0000FE10 = ; */ /* EEDIVLNVR - macro for reading non volatile register EEDIV Lo Non-volatile Register; 0x0000FE11 */ /* Tip for register initialization in the user code: const byte EEDIVLNVR_INIT @0x0000FE11 = ; */ volatile EEDIVHSTR _EEDIVH; /* EEDIV Divider High Register; 0x0000FE1A */ volatile EEDIVLSTR _EEDIVL; /* EEDIV Divider Low Register; 0x0000FE1B */ /* EENVR - macro for reading non volatile register EEPROM1 Nonvolatile Register; 0x0000FE1C */ /* Tip for register initialization in the user code: const byte EENVR_INIT @0x0000FE1C = ; */ volatile EECRSTR _EECR; /* EEPROM1 Control Register; 0x0000FE1D */ volatile EEACRSTR _EEACR; /* EEPROM1 Array Control Register; 0x0000FE1F */ /* FLBPR - macro for reading non volatile register FLASH Block Protect Register; 0x0000FF80 */ /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FF80 = ; */ volatile FLCRSTR _FLCR; /* FLASH Control Register; 0x0000FF88 */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile TCNTSTR _TCNT; /* TIM Counter Register; 0x00000022 */ volatile TMODSTR _TMOD; /* TIM Counter Modulo Register; 0x00000024 */ volatile TCH0STR _TCH0; /* TIM Channel Register; 0x00000027 */ volatile TCH1STR _TCH1; /* TIM Channel Register; 0x0000002A */ volatile TCH2STR _TCH2; /* TIM Channel Register; 0x0000002D */ volatile TCH3STR _TCH3; /* TIM Channel Register; 0x00000030 */ volatile TCH4STR _TCH4; /* TIM Channel Register; 0x00000033 */ volatile TCH5STR _TCH5; /* TIM Channel Register; 0x00000036 */ volatile PCNTSTR _PCNT; /* PIT Counter Register; 0x0000004C */ volatile PMODSTR _PMOD; /* PIT Counter Modulo Register; 0x0000004E */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /*lint -restore */ /* EOF */