/* Based on CPU DB MC68HC908AP64_48, version 2.89.111 (RegistersPrg V2.28) */ /* DataSheet : MC68HC908AP64 Rev. 4 1/2007 / MC68HC908AP64A Rev. 3 10/2007 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile PTASTR _PTA; /* Port A Data Register; 0x00000000 */ volatile PTBSTR _PTB; /* Port B Data Register; 0x00000001 */ volatile PTCSTR _PTC; /* Port C Data Register; 0x00000002 */ volatile PTDSTR _PTD; /* Port D Data Register; 0x00000003 */ volatile DDRASTR _DDRA; /* Data Direction Register A; 0x00000004 */ volatile DDRBSTR _DDRB; /* Data Direction Register B; 0x00000005 */ volatile DDRCSTR _DDRC; /* Data Direction Register C; 0x00000006 */ volatile DDRDSTR _DDRD; /* Data Direction Register D; 0x00000007 */ volatile LEDASTR _LEDA; /* Port-A LED Control; 0x0000000C */ volatile SPCRSTR _SPCR; /* SPI Control Register; 0x00000010 */ volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register; 0x00000011 */ volatile SPDRSTR _SPDR; /* SPI Data Register; 0x00000012 */ volatile SCC1STR _SCC1; /* SCI Control Register 1; 0x00000013 */ volatile SCC2STR _SCC2; /* SCI Control Register 2; 0x00000014 */ volatile SCC3STR _SCC3; /* SCI Control Register 3; 0x00000015 */ volatile SCS1STR _SCS1; /* SCI Status Register 1; 0x00000016 */ volatile SCS2STR _SCS2; /* SCI Status Register 2; 0x00000017 */ volatile SCDRSTR _SCDR; /* SCI Data Register; 0x00000018 */ volatile SCBRSTR _SCBR; /* SCI Baud Rate Register; 0x00000019 */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register; 0x0000001A */ volatile KBIERSTR _KBIER; /* Keyobard Interrupt Enable Register; 0x0000001B */ volatile INTSCR2STR _INTSCR2; /* IRQ2 Status and Control Register; 0x0000001C */ volatile CONFIG2STR _CONFIG2; /* Configuration Register 2; 0x0000001D */ volatile INTSCR1STR _INTSCR1; /* IRQ1 Status and Control Register; 0x0000001E */ volatile CONFIG1STR _CONFIG1; /* Configuration Register 1; 0x0000001F */ volatile T1SCSTR _T1SC; /* TIM1 Status and Control Register; 0x00000020 */ volatile T1SC0STR _T1SC0; /* TIM1 Channel 0 Status and Control Register; 0x00000025 */ volatile T1SC1STR _T1SC1; /* TIM1 Channel 1 Status and Control Register; 0x00000028 */ volatile T2SCSTR _T2SC; /* TIM2 Status and Control Register; 0x0000002B */ volatile T2SC0STR _T2SC0; /* TIM2 Channel 0 Status and Control Register; 0x00000030 */ volatile T2SC1STR _T2SC1; /* TIM2 Channel 1 Status and Control Register; 0x00000033 */ volatile PCTLSTR _PCTL; /* PLL Control Register; 0x00000036 */ volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register; 0x00000037 */ volatile PMRSSTR _PMRS; /* PLL VCO Range Select; 0x0000003A */ volatile PMDSSTR _PMDS; /* PLL Reference Divider Select Register; 0x0000003B */ volatile IRSCC1STR _IRSCC1; /* IRSCI Control Register 1; 0x00000040 */ volatile IRSCC2STR _IRSCC2; /* IRSCI Control Register 2; 0x00000041 */ volatile IRSCC3STR _IRSCC3; /* IRSCI Control Register 3; 0x00000042 */ volatile IRSCS1STR _IRSCS1; /* IRSCI Status Register 1; 0x00000043 */ volatile IRSCS2STR _IRSCS2; /* IRSCI Status Register 2; 0x00000044 */ volatile IRSCDRSTR _IRSCDR; /* IRSCI Data Register; 0x00000045 */ volatile IRSCBRSTR _IRSCBR; /* IRSCI Baud Rate Register; 0x00000046 */ volatile IRSCIRCRSTR _IRSCIRCR; /* IRSCI Infra-ref Control Register; 0x00000047 */ volatile MMADRSTR _MMADR; /* Multi-Master IIC Address Register; 0x00000048 */ volatile MMCR1STR _MMCR1; /* Multi-Master IIC Control Register 1; 0x00000049 */ volatile MMCR2STR _MMCR2; /* Multi-Master IIC Control Register 2; 0x0000004A */ volatile MMSRSTR _MMSR; /* Multi-Master IIC Status Register; 0x0000004B */ volatile MMDTRSTR _MMDTR; /* Multi-Master IIC Data Transmit Register; 0x0000004C */ volatile MMDRRSTR _MMDRR; /* Multi-Master IIC Data Receive Register; 0x0000004D */ volatile MMCRDRSTR _MMCRDR; /* Multi-Master IIC CRC Data Register; 0x0000004E */ volatile MMFDRSTR _MMFDR; /* Multi-Master IIC Frequency Divider Register; 0x0000004F */ volatile TBCRSTR _TBCR; /* Timebase Control Register; 0x00000051 */ volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register; 0x00000057 */ volatile ADICLKSTR _ADICLK; /* ADC Input Clock Register; 0x00000058 */ volatile ADR1LSTR _ADR1L; /* ADC Data Register Low 1; 0x0000005B */ volatile ADR2LSTR _ADR2L; /* ADC Data Register Low 2; 0x0000005C */ volatile ADR3LSTR _ADR3L; /* ADC Data Register Low 3; 0x0000005D */ volatile ADASCRSTR _ADASCR; /* ADC Auto-Scan Control Register; 0x0000005E */ volatile SBSRSTR _SBSR; /* SIM Break Status Register; 0x0000FE00 */ volatile SRSRSTR _SRSR; /* SIM Reset Status Register; 0x0000FE01 */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register; 0x0000FE03 */ volatile INT1STR _INT1; /* Interrupt Status Register 1; 0x0000FE04 */ volatile INT2STR _INT2; /* Interrupt Status Register 2; 0x0000FE05 */ volatile INT3STR _INT3; /* Interrupt Status Register 3; 0x0000FE06 */ volatile FLCRSTR _FLCR; /* FLASH Control Register; 0x0000FE08 */ volatile FLBPRSTR _FLBPR; /* FLASH Block Protect Register; 0x0000FE09 */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register; 0x0000FE0E */ volatile LVISRSTR _LVISR; /* LVI Status Register; 0x0000FE0F */ /* MOR - macro for reading non volatile register Mask Option Register; 0x0000FFCF */ /* Tip for register initialization in the user code: const byte MOR_INIT @0x0000FFCF = ; */ volatile COPCTLSTR _COPCTL; /* COP Control Register; 0x0000FFFF */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile T1CNTSTR _T1CNT; /* TIM1 Counter Register; 0x00000021 */ volatile T1MODSTR _T1MOD; /* TIM1 Counter Modulo Register; 0x00000023 */ volatile T1CH0STR _T1CH0; /* TIM1 Channel 0 Register; 0x00000026 */ volatile T1CH1STR _T1CH1; /* TIM1 Channel 1 Register; 0x00000029 */ volatile T2CNTSTR _T2CNT; /* TIM2 Counter Register; 0x0000002C */ volatile T2MODSTR _T2MOD; /* TIM2 Counter Modulo Register; 0x0000002E */ volatile T2CH0STR _T2CH0; /* TIM2 Channel 0 Register; 0x00000031 */ volatile T2CH1STR _T2CH1; /* TIM2 Channel 1 Register; 0x00000034 */ volatile PMSSTR _PMS; /* PLL Multiplier Select Register; 0x00000038 */ volatile ADR0STR _ADR0; /* ADC Data Register High; 0x00000059 */ volatile BRKSTR _BRK; /* Break Address Register; 0x0000FE0C */ /*lint -restore */ /* EOF */