/* Based on CPU DB MC9RS08SA12_32_SDIP, version 3.00.029 (RegistersPrg V2.28) */ /* ** ################################################################### ** Filename : mc9rs08sa12.h ** Processor : MC9RS08SA12C_32 ** FileFormat: V2.28 ** DataSheet : MC9RS08SA12 Rev. 1, Draft G 6/2007 ** Compiler : CodeWarrior compiler ** Date/Time : 27.5.2009, 10:23 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matchs with anouther bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC9RS08SA12_H #define _MC9RS08SA12_H #include /* Types definition */ typedef unsigned char byte; typedef unsigned int word; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() (void)(SRS = 0x00) #endif #endif /* __RESET_WATCHDOG */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** registers I/O map ****************/ /*** PTAD - Port A Data Register; 0x00000010 ***/ typedef union { byte Byte; struct { byte PTAD0 :1; /* Port A Data Register Bit 0 */ byte PTAD1 :1; /* Port A Data Register Bit 1 */ byte PTAD2 :1; /* Port A Data Register Bit 2 */ byte PTAD3 :1; /* Port A Data Register Bit 3 */ byte PTAD4 :1; /* Port A Data Register Bit 4 */ byte PTAD5 :1; /* Port A Data Register Bit 5 */ byte PTAD6 :1; /* Port A Data Register Bit 6 */ byte PTAD7 :1; /* Port A Data Register Bit 7 */ } Bits; } PTADSTR; extern volatile PTADSTR _PTAD @0x00000010; #define PTAD _PTAD.Byte #define PTAD_PTAD0 _PTAD.Bits.PTAD0 #define PTAD_PTAD1 _PTAD.Bits.PTAD1 #define PTAD_PTAD2 _PTAD.Bits.PTAD2 #define PTAD_PTAD3 _PTAD.Bits.PTAD3 #define PTAD_PTAD4 _PTAD.Bits.PTAD4 #define PTAD_PTAD5 _PTAD.Bits.PTAD5 #define PTAD_PTAD6 _PTAD.Bits.PTAD6 #define PTAD_PTAD7 _PTAD.Bits.PTAD7 #define PTAD_PTAD0_MASK 1 #define PTAD_PTAD1_MASK 2 #define PTAD_PTAD2_MASK 4 #define PTAD_PTAD3_MASK 8 #define PTAD_PTAD4_MASK 16 #define PTAD_PTAD5_MASK 32 #define PTAD_PTAD6_MASK 64 #define PTAD_PTAD7_MASK 128 /*** PTBD - Port B Data Register; 0x00000011 ***/ typedef union { byte Byte; struct { byte PTBD0 :1; /* Port B Data Register Bit 0 */ byte PTBD1 :1; /* Port B Data Register Bit 1 */ byte PTBD2 :1; /* Port B Data Register Bit 2 */ byte PTBD3 :1; /* Port B Data Register Bit 3 */ byte PTBD4 :1; /* Port B Data Register Bit 4 */ byte PTBD5 :1; /* Port B Data Register Bit 5 */ byte PTBD6 :1; /* Port B Data Register Bit 6 */ byte PTBD7 :1; /* Port B Data Register Bit 7 */ } Bits; } PTBDSTR; extern volatile PTBDSTR _PTBD @0x00000011; #define PTBD _PTBD.Byte #define PTBD_PTBD0 _PTBD.Bits.PTBD0 #define PTBD_PTBD1 _PTBD.Bits.PTBD1 #define PTBD_PTBD2 _PTBD.Bits.PTBD2 #define PTBD_PTBD3 _PTBD.Bits.PTBD3 #define PTBD_PTBD4 _PTBD.Bits.PTBD4 #define PTBD_PTBD5 _PTBD.Bits.PTBD5 #define PTBD_PTBD6 _PTBD.Bits.PTBD6 #define PTBD_PTBD7 _PTBD.Bits.PTBD7 #define PTBD_PTBD0_MASK 1 #define PTBD_PTBD1_MASK 2 #define PTBD_PTBD2_MASK 4 #define PTBD_PTBD3_MASK 8 #define PTBD_PTBD4_MASK 16 #define PTBD_PTBD5_MASK 32 #define PTBD_PTBD6_MASK 64 #define PTBD_PTBD7_MASK 128 /*** PTCD - Port C Data Register; 0x00000012 ***/ typedef union { byte Byte; struct { byte PTCD0 :1; /* Port C Data Register Bit 0 */ byte PTCD1 :1; /* Port C Data Register Bit 1 */ byte PTCD2 :1; /* Port C Data Register Bit 2 */ byte PTCD3 :1; /* Port C Data Register Bit 3 */ byte PTCD4 :1; /* Port C Data Register Bit 4 */ byte PTCD5 :1; /* Port C Data Register Bit 5 */ byte PTCD6 :1; /* Port C Data Register Bit 6 */ byte PTCD7 :1; /* Port C Data Register Bit 7 */ } Bits; } PTCDSTR; extern volatile PTCDSTR _PTCD @0x00000012; #define PTCD _PTCD.Byte #define PTCD_PTCD0 _PTCD.Bits.PTCD0 #define PTCD_PTCD1 _PTCD.Bits.PTCD1 #define PTCD_PTCD2 _PTCD.Bits.PTCD2 #define PTCD_PTCD3 _PTCD.Bits.PTCD3 #define PTCD_PTCD4 _PTCD.Bits.PTCD4 #define PTCD_PTCD5 _PTCD.Bits.PTCD5 #define PTCD_PTCD6 _PTCD.Bits.PTCD6 #define PTCD_PTCD7 _PTCD.Bits.PTCD7 #define PTCD_PTCD0_MASK 1 #define PTCD_PTCD1_MASK 2 #define PTCD_PTCD2_MASK 4 #define PTCD_PTCD3_MASK 8 #define PTCD_PTCD4_MASK 16 #define PTCD_PTCD5_MASK 32 #define PTCD_PTCD6_MASK 64 #define PTCD_PTCD7_MASK 128 /*** PTDD - Port D Data Register; 0x00000013 ***/ typedef union { byte Byte; struct { byte PTDD0 :1; /* Port D Data Register Bit 0 */ byte PTDD1 :1; /* Port D Data Register Bit 1 */ byte PTDD2 :1; /* Port D Data Register Bit 2 */ byte PTDD3 :1; /* Port D Data Register Bit 3 */ byte PTDD4 :1; /* Port D Data Register Bit 4 */ byte PTDD5 :1; /* Port D Data Register Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpPTDD :6; byte :1; byte :1; } MergedBits; } PTDDSTR; extern volatile PTDDSTR _PTDD @0x00000013; #define PTDD _PTDD.Byte #define PTDD_PTDD0 _PTDD.Bits.PTDD0 #define PTDD_PTDD1 _PTDD.Bits.PTDD1 #define PTDD_PTDD2 _PTDD.Bits.PTDD2 #define PTDD_PTDD3 _PTDD.Bits.PTDD3 #define PTDD_PTDD4 _PTDD.Bits.PTDD4 #define PTDD_PTDD5 _PTDD.Bits.PTDD5 #define PTDD_PTDD _PTDD.MergedBits.grpPTDD #define PTDD_PTDD0_MASK 1 #define PTDD_PTDD1_MASK 2 #define PTDD_PTDD2_MASK 4 #define PTDD_PTDD3_MASK 8 #define PTDD_PTDD4_MASK 16 #define PTDD_PTDD5_MASK 32 #define PTDD_PTDD_MASK 63 #define PTDD_PTDD_BITNUM 0 /*** KBISC - KBI Status and Control Register; 0x00000014 ***/ typedef union { byte Byte; struct { byte KBMOD :1; /* Keyboard Detection Mode */ byte KBIE :1; /* Keyboard Interrupt Enable */ byte KBACK :1; /* Keyboard Interrupt Acknowledge */ byte KBF :1; /* Keyboard Interrupt Flag */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBISCSTR; extern volatile KBISCSTR _KBISC @0x00000014; #define KBISC _KBISC.Byte #define KBISC_KBMOD _KBISC.Bits.KBMOD #define KBISC_KBIE _KBISC.Bits.KBIE #define KBISC_KBACK _KBISC.Bits.KBACK #define KBISC_KBF _KBISC.Bits.KBF #define KBISC_KBMOD_MASK 1 #define KBISC_KBIE_MASK 2 #define KBISC_KBACK_MASK 4 #define KBISC_KBF_MASK 8 /*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0x00000015 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select A for TPM Channel 0 */ byte MS0B :1; /* Mode Select B for TPM Channel 0 */ byte CH0IE :1; /* Channel 0 Interrupt Enable */ byte CH0F :1; /* Channel 0 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TPMC0SCSTR; extern volatile TPMC0SCSTR _TPMC0SC @0x00000015; #define TPMC0SC _TPMC0SC.Byte #define TPMC0SC_ELS0A _TPMC0SC.Bits.ELS0A #define TPMC0SC_ELS0B _TPMC0SC.Bits.ELS0B #define TPMC0SC_MS0A _TPMC0SC.Bits.MS0A #define TPMC0SC_MS0B _TPMC0SC.Bits.MS0B #define TPMC0SC_CH0IE _TPMC0SC.Bits.CH0IE #define TPMC0SC_CH0F _TPMC0SC.Bits.CH0F #define TPMC0SC_ELS0x _TPMC0SC.MergedBits.grpELS0x #define TPMC0SC_MS0x _TPMC0SC.MergedBits.grpMS0x #define TPMC0SC_ELS0A_MASK 4 #define TPMC0SC_ELS0B_MASK 8 #define TPMC0SC_MS0A_MASK 16 #define TPMC0SC_MS0B_MASK 32 #define TPMC0SC_CH0IE_MASK 64 #define TPMC0SC_CH0F_MASK 128 #define TPMC0SC_ELS0x_MASK 12 #define TPMC0SC_ELS0x_BITNUM 2 #define TPMC0SC_MS0x_MASK 48 #define TPMC0SC_MS0x_BITNUM 4 /*** TPMC0V - TPM Timer Channel 0 Value Register; 0x00000016 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMC0VH - TPM Timer Channel 0 Value Register High; 0x00000016 ***/ union { byte Byte; } TPMC0VHSTR; #define TPMC0VH _TPMC0V.Overlap_STR.TPMC0VHSTR.Byte /*** TPMC0VL - TPM Timer Channel 0 Value Register Low; 0x00000017 ***/ union { byte Byte; } TPMC0VLSTR; #define TPMC0VL _TPMC0V.Overlap_STR.TPMC0VLSTR.Byte } Overlap_STR; } TPMC0VSTR; extern volatile TPMC0VSTR _TPMC0V @0x00000016; #define TPMC0V _TPMC0V.Word /*** TPMC1SC - TPM Timer Channel 1 Status and Control Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select A for TPM Channel 1 */ byte MS1B :1; /* Mode Select B for TPM Channel 1 */ byte CH1IE :1; /* Channel 1 Interrupt Enable */ byte CH1F :1; /* Channel 1 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS1x :2; byte grpMS1x :2; byte :1; byte :1; } MergedBits; } TPMC1SCSTR; extern volatile TPMC1SCSTR _TPMC1SC @0x00000018; #define TPMC1SC _TPMC1SC.Byte #define TPMC1SC_ELS1A _TPMC1SC.Bits.ELS1A #define TPMC1SC_ELS1B _TPMC1SC.Bits.ELS1B #define TPMC1SC_MS1A _TPMC1SC.Bits.MS1A #define TPMC1SC_MS1B _TPMC1SC.Bits.MS1B #define TPMC1SC_CH1IE _TPMC1SC.Bits.CH1IE #define TPMC1SC_CH1F _TPMC1SC.Bits.CH1F #define TPMC1SC_ELS1x _TPMC1SC.MergedBits.grpELS1x #define TPMC1SC_MS1x _TPMC1SC.MergedBits.grpMS1x #define TPMC1SC_ELS1A_MASK 4 #define TPMC1SC_ELS1B_MASK 8 #define TPMC1SC_MS1A_MASK 16 #define TPMC1SC_MS1B_MASK 32 #define TPMC1SC_CH1IE_MASK 64 #define TPMC1SC_CH1F_MASK 128 #define TPMC1SC_ELS1x_MASK 12 #define TPMC1SC_ELS1x_BITNUM 2 #define TPMC1SC_MS1x_MASK 48 #define TPMC1SC_MS1x_BITNUM 4 /*** TPMC1V - TPM Timer Channel 1 Value Register; 0x00000019 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMC1VH - TPM Timer Channel 1 Value Register High; 0x00000019 ***/ union { byte Byte; } TPMC1VHSTR; #define TPMC1VH _TPMC1V.Overlap_STR.TPMC1VHSTR.Byte /*** TPMC1VL - TPM Timer Channel 1 Value Register Low; 0x0000001A ***/ union { byte Byte; } TPMC1VLSTR; #define TPMC1VL _TPMC1V.Overlap_STR.TPMC1VLSTR.Byte } Overlap_STR; } TPMC1VSTR; extern volatile TPMC1VSTR _TPMC1V @0x00000019; #define TPMC1V _TPMC1V.Word /*** ACMPSC - ACMP Status and Control Register; 0x0000001B ***/ typedef union { byte Byte; struct { byte ACMOD0 :1; /* Analog Comparator Mode Bit 0 */ byte ACMOD1 :1; /* Analog Comparator Mode Bit 1 */ byte ACOPE :1; /* Analog Comparator Output Pin Enable */ byte ACO :1; /* Analog Comparator Output */ byte ACIE :1; /* Analog Comparator Interrupt Enable */ byte ACF :1; /* Analog Comparator Flag */ byte ACBGS :1; /* Analog Comparator Bandgap Select */ byte ACME :1; /* Analog Comparator Module Enable */ } Bits; struct { byte grpACMOD :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ACMPSCSTR; extern volatile ACMPSCSTR _ACMPSC @0x0000001B; #define ACMPSC _ACMPSC.Byte #define ACMPSC_ACMOD0 _ACMPSC.Bits.ACMOD0 #define ACMPSC_ACMOD1 _ACMPSC.Bits.ACMOD1 #define ACMPSC_ACOPE _ACMPSC.Bits.ACOPE #define ACMPSC_ACO _ACMPSC.Bits.ACO #define ACMPSC_ACIE _ACMPSC.Bits.ACIE #define ACMPSC_ACF _ACMPSC.Bits.ACF #define ACMPSC_ACBGS _ACMPSC.Bits.ACBGS #define ACMPSC_ACME _ACMPSC.Bits.ACME #define ACMPSC_ACMOD _ACMPSC.MergedBits.grpACMOD #define ACMPSC_ACMOD0_MASK 1 #define ACMPSC_ACMOD1_MASK 2 #define ACMPSC_ACOPE_MASK 4 #define ACMPSC_ACO_MASK 8 #define ACMPSC_ACIE_MASK 16 #define ACMPSC_ACF_MASK 32 #define ACMPSC_ACBGS_MASK 64 #define ACMPSC_ACME_MASK 128 #define ACMPSC_ACMOD_MASK 3 #define ACMPSC_ACMOD_BITNUM 0 /*** ADCSC1 - Status and Control Register 1; 0x0000001C ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* Input Channel Select Bit 0 */ byte ADCH1 :1; /* Input Channel Select Bit 1 */ byte ADCH2 :1; /* Input Channel Select Bit 2 */ byte ADCH3 :1; /* Input Channel Select Bit 3 */ byte :1; byte ADCO :1; /* Continuous Conversion Enable - ADCO is used to enable continuous conversions */ byte AIEN :1; /* Interrupt Enable - AIEN is used to enable conversion complete interrupts. When COCO becomes set while AIEN is high, an interrupt is asserted */ byte COCO :1; /* Conversion Complete Flag - The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared whenever ADCSC1 is written or whenever ADCRL is read */ } Bits; struct { byte grpADCH :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADCSC1STR; extern volatile ADCSC1STR _ADCSC1 @0x0000001C; #define ADCSC1 _ADCSC1.Byte #define ADCSC1_ADCH0 _ADCSC1.Bits.ADCH0 #define ADCSC1_ADCH1 _ADCSC1.Bits.ADCH1 #define ADCSC1_ADCH2 _ADCSC1.Bits.ADCH2 #define ADCSC1_ADCH3 _ADCSC1.Bits.ADCH3 #define ADCSC1_ADCO _ADCSC1.Bits.ADCO #define ADCSC1_AIEN _ADCSC1.Bits.AIEN #define ADCSC1_COCO _ADCSC1.Bits.COCO #define ADCSC1_ADCH _ADCSC1.MergedBits.grpADCH #define ADCSC1_ADCH0_MASK 1 #define ADCSC1_ADCH1_MASK 2 #define ADCSC1_ADCH2_MASK 4 #define ADCSC1_ADCH3_MASK 8 #define ADCSC1_ADCO_MASK 32 #define ADCSC1_AIEN_MASK 64 #define ADCSC1_COCO_MASK 128 #define ADCSC1_ADCH_MASK 15 #define ADCSC1_ADCH_BITNUM 0 /*** ADCSC2 - Status and Control Register 2; 0x0000001D ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte ACFGT :1; /* Compare Function Greater Than Enable-ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. The compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value */ byte ACFE :1; /* Compare Function Enable - ACFE is used to enable the compare function */ byte ADTRG :1; /* Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion. Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input */ byte ADACT :1; /* Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted */ } Bits; } ADCSC2STR; extern volatile ADCSC2STR _ADCSC2 @0x0000001D; #define ADCSC2 _ADCSC2.Byte #define ADCSC2_ACFGT _ADCSC2.Bits.ACFGT #define ADCSC2_ACFE _ADCSC2.Bits.ACFE #define ADCSC2_ADTRG _ADCSC2.Bits.ADTRG #define ADCSC2_ADACT _ADCSC2.Bits.ADACT #define ADCSC2_ACFGT_MASK 16 #define ADCSC2_ACFE_MASK 32 #define ADCSC2_ADTRG_MASK 64 #define ADCSC2_ADACT_MASK 128 /*** ADCR - Data Result Low Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte ADR0 :1; /* ADC Result Data Bit 0 */ byte ADR1 :1; /* ADC Result Data Bit 1 */ byte ADR2 :1; /* ADC Result Data Bit 2 */ byte ADR3 :1; /* ADC Result Data Bit 3 */ byte ADR4 :1; /* ADC Result Data Bit 4 */ byte ADR5 :1; /* ADC Result Data Bit 5 */ byte ADR6 :1; /* ADC Result Data Bit 6 */ byte ADR7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADCRSTR; extern volatile ADCRSTR _ADCR @0x0000001E; #define ADCR _ADCR.Byte #define ADCR_ADR0 _ADCR.Bits.ADR0 #define ADCR_ADR1 _ADCR.Bits.ADR1 #define ADCR_ADR2 _ADCR.Bits.ADR2 #define ADCR_ADR3 _ADCR.Bits.ADR3 #define ADCR_ADR4 _ADCR.Bits.ADR4 #define ADCR_ADR5 _ADCR.Bits.ADR5 #define ADCR_ADR6 _ADCR.Bits.ADR6 #define ADCR_ADR7 _ADCR.Bits.ADR7 #define ADCR_ADR0_MASK 1 #define ADCR_ADR1_MASK 2 #define ADCR_ADR2_MASK 4 #define ADCR_ADR3_MASK 8 #define ADCR_ADR4_MASK 16 #define ADCR_ADR5_MASK 32 #define ADCR_ADR6_MASK 64 #define ADCR_ADR7_MASK 128 /*** PAGESEL - Page Select Register; 0x0000001F ***/ typedef union { byte Byte; struct { byte AD6 :1; /* Page Selector Bit 6 */ byte AD7 :1; /* Page Selector Bit 7 */ byte AD8 :1; /* Page Selector Bit 8 */ byte AD9 :1; /* Page Selector Bit 9 */ byte AD10 :1; /* Page Selector Bit 10 */ byte AD11 :1; /* Page Selector Bit 11 */ byte AD12 :1; /* Page Selector Bit 12 */ byte AD13 :1; /* Page Selector Bit 13 */ } Bits; } PAGESELSTR; extern volatile PAGESELSTR _PAGESEL @0x0000001F; #define PAGESEL _PAGESEL.Byte #define PAGESEL_AD6 _PAGESEL.Bits.AD6 #define PAGESEL_AD7 _PAGESEL.Bits.AD7 #define PAGESEL_AD8 _PAGESEL.Bits.AD8 #define PAGESEL_AD9 _PAGESEL.Bits.AD9 #define PAGESEL_AD10 _PAGESEL.Bits.AD10 #define PAGESEL_AD11 _PAGESEL.Bits.AD11 #define PAGESEL_AD12 _PAGESEL.Bits.AD12 #define PAGESEL_AD13 _PAGESEL.Bits.AD13 #define PAGESEL_AD6_MASK 1 #define PAGESEL_AD7_MASK 2 #define PAGESEL_AD8_MASK 4 #define PAGESEL_AD9_MASK 8 #define PAGESEL_AD10_MASK 16 #define PAGESEL_AD11_MASK 32 #define PAGESEL_AD12_MASK 64 #define PAGESEL_AD13_MASK 128 /*** MTIM1SC - MTIM Clock Configuration Register; 0x00000020 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte TSTP :1; /* MTIM Counter Stop */ byte TRST :1; /* MTIM Counter Reset */ byte TOIE :1; /* MTIM Overflow Interrupt Enable */ byte TOF :1; /* MTIM Overflow Flag */ } Bits; } MTIM1SCSTR; extern volatile MTIM1SCSTR _MTIM1SC @0x00000020; #define MTIM1SC _MTIM1SC.Byte #define MTIM1SC_TSTP _MTIM1SC.Bits.TSTP #define MTIM1SC_TRST _MTIM1SC.Bits.TRST #define MTIM1SC_TOIE _MTIM1SC.Bits.TOIE #define MTIM1SC_TOF _MTIM1SC.Bits.TOF #define MTIM1SC_TSTP_MASK 16 #define MTIM1SC_TRST_MASK 32 #define MTIM1SC_TOIE_MASK 64 #define MTIM1SC_TOF_MASK 128 /*** MTIM1CLK - MTIM Clock Configuration Register; 0x00000021 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Clock source Prescaler Bit 0 */ byte PS1 :1; /* Clock source Prescaler Bit 1 */ byte PS2 :1; /* Clock source Prescaler Bit 2 */ byte PS3 :1; /* Clock source Prescaler Bit 3 */ byte CLKS0 :1; /* Clock source Select Bit 0 */ byte CLKS1 :1; /* Clock source Select Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpPS :4; byte grpCLKS :2; byte :1; byte :1; } MergedBits; } MTIM1CLKSTR; extern volatile MTIM1CLKSTR _MTIM1CLK @0x00000021; #define MTIM1CLK _MTIM1CLK.Byte #define MTIM1CLK_PS0 _MTIM1CLK.Bits.PS0 #define MTIM1CLK_PS1 _MTIM1CLK.Bits.PS1 #define MTIM1CLK_PS2 _MTIM1CLK.Bits.PS2 #define MTIM1CLK_PS3 _MTIM1CLK.Bits.PS3 #define MTIM1CLK_CLKS0 _MTIM1CLK.Bits.CLKS0 #define MTIM1CLK_CLKS1 _MTIM1CLK.Bits.CLKS1 #define MTIM1CLK_PS _MTIM1CLK.MergedBits.grpPS #define MTIM1CLK_CLKS _MTIM1CLK.MergedBits.grpCLKS #define MTIM1CLK_PS0_MASK 1 #define MTIM1CLK_PS1_MASK 2 #define MTIM1CLK_PS2_MASK 4 #define MTIM1CLK_PS3_MASK 8 #define MTIM1CLK_CLKS0_MASK 16 #define MTIM1CLK_CLKS1_MASK 32 #define MTIM1CLK_PS_MASK 15 #define MTIM1CLK_PS_BITNUM 0 #define MTIM1CLK_CLKS_MASK 48 #define MTIM1CLK_CLKS_BITNUM 4 /*** MTIM1CNT - MTIM Counter Register; 0x00000022 ***/ typedef union { byte Byte; } MTIM1CNTSTR; extern volatile MTIM1CNTSTR _MTIM1CNT @0x00000022; #define MTIM1CNT _MTIM1CNT.Byte /*** MTIM1MOD - MTIM Modulo Register; 0x00000023 ***/ typedef union { byte Byte; } MTIM1MODSTR; extern volatile MTIM1MODSTR _MTIM1MOD @0x00000023; #define MTIM1MOD _MTIM1MOD.Byte /*** MTIM2SC - MTIM Clock Configuration Register; 0x00000024 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte TSTP :1; /* MTIM Counter Stop */ byte TRST :1; /* MTIM Counter Reset */ byte TOIE :1; /* MTIM Overflow Interrupt Enable */ byte TOF :1; /* MTIM Overflow Flag */ } Bits; } MTIM2SCSTR; extern volatile MTIM2SCSTR _MTIM2SC @0x00000024; #define MTIM2SC _MTIM2SC.Byte #define MTIM2SC_TSTP _MTIM2SC.Bits.TSTP #define MTIM2SC_TRST _MTIM2SC.Bits.TRST #define MTIM2SC_TOIE _MTIM2SC.Bits.TOIE #define MTIM2SC_TOF _MTIM2SC.Bits.TOF #define MTIM2SC_TSTP_MASK 16 #define MTIM2SC_TRST_MASK 32 #define MTIM2SC_TOIE_MASK 64 #define MTIM2SC_TOF_MASK 128 /*** MTIM2CLK - MTIM Clock Configuration Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Clock source Prescaler Bit 0 */ byte PS1 :1; /* Clock source Prescaler Bit 1 */ byte PS2 :1; /* Clock source Prescaler Bit 2 */ byte PS3 :1; /* Clock source Prescaler Bit 3 */ byte CLKS0 :1; /* Clock source Select Bit 0 */ byte CLKS1 :1; /* Clock source Select Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpPS :4; byte grpCLKS :2; byte :1; byte :1; } MergedBits; } MTIM2CLKSTR; extern volatile MTIM2CLKSTR _MTIM2CLK @0x00000025; #define MTIM2CLK _MTIM2CLK.Byte #define MTIM2CLK_PS0 _MTIM2CLK.Bits.PS0 #define MTIM2CLK_PS1 _MTIM2CLK.Bits.PS1 #define MTIM2CLK_PS2 _MTIM2CLK.Bits.PS2 #define MTIM2CLK_PS3 _MTIM2CLK.Bits.PS3 #define MTIM2CLK_CLKS0 _MTIM2CLK.Bits.CLKS0 #define MTIM2CLK_CLKS1 _MTIM2CLK.Bits.CLKS1 #define MTIM2CLK_PS _MTIM2CLK.MergedBits.grpPS #define MTIM2CLK_CLKS _MTIM2CLK.MergedBits.grpCLKS #define MTIM2CLK_PS0_MASK 1 #define MTIM2CLK_PS1_MASK 2 #define MTIM2CLK_PS2_MASK 4 #define MTIM2CLK_PS3_MASK 8 #define MTIM2CLK_CLKS0_MASK 16 #define MTIM2CLK_CLKS1_MASK 32 #define MTIM2CLK_PS_MASK 15 #define MTIM2CLK_PS_BITNUM 0 #define MTIM2CLK_CLKS_MASK 48 #define MTIM2CLK_CLKS_BITNUM 4 /*** MTIM2CNT - MTIM Counter Register; 0x00000026 ***/ typedef union { byte Byte; } MTIM2CNTSTR; extern volatile MTIM2CNTSTR _MTIM2CNT @0x00000026; #define MTIM2CNT _MTIM2CNT.Byte /*** MTIM2MOD - MTIM Modulo Register; 0x00000027 ***/ typedef union { byte Byte; } MTIM2MODSTR; extern volatile MTIM2MODSTR _MTIM2MOD @0x00000027; #define MTIM2MOD _MTIM2MOD.Byte /*** SCIBD - SCI Baud Rate Register; 0x00000028 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SCIBDH - SCI Baud Rate Register High; 0x00000028 ***/ union { byte Byte; struct { byte SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ byte SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ byte SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ byte SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ byte SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ byte :1; byte RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ byte LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { byte grpSBR_8 :5; byte :1; byte :1; byte :1; } MergedBits; } SCIBDHSTR; #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8 #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9 #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10 #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11 #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12 #define SCIBDH_RXEDGIE _SCIBD.Overlap_STR.SCIBDHSTR.Bits.RXEDGIE #define SCIBDH_LBKDIE _SCIBD.Overlap_STR.SCIBDHSTR.Bits.LBKDIE #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8 #define SCIBDH_SBR SCIBDH_SBR_8 #define SCIBDH_SBR8_MASK 1 #define SCIBDH_SBR9_MASK 2 #define SCIBDH_SBR10_MASK 4 #define SCIBDH_SBR11_MASK 8 #define SCIBDH_SBR12_MASK 16 #define SCIBDH_RXEDGIE_MASK 64 #define SCIBDH_LBKDIE_MASK 128 #define SCIBDH_SBR_8_MASK 31 #define SCIBDH_SBR_8_BITNUM 0 /*** SCIBDL - SCI Baud Rate Register Low; 0x00000029 ***/ union { byte Byte; struct { byte SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ byte SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ byte SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ byte SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ byte SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ byte SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ byte SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ byte SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ } Bits; } SCIBDLSTR; #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0 #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1 #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2 #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3 #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4 #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5 #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6 #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7 #define SCIBDL_SBR0_MASK 1 #define SCIBDL_SBR1_MASK 2 #define SCIBDL_SBR2_MASK 4 #define SCIBDL_SBR3_MASK 8 #define SCIBDL_SBR4_MASK 16 #define SCIBDL_SBR5_MASK 32 #define SCIBDL_SBR6_MASK 64 #define SCIBDL_SBR7_MASK 128 } Overlap_STR; } SCIBDSTR; extern volatile SCIBDSTR _SCIBD @0x00000028; #define SCIBD _SCIBD.Word /*** SCIC1 - SCI Control Register 1; 0x0000002A ***/ typedef union { byte Byte; struct { byte PT :1; /* Parity Type */ byte PE :1; /* Parity Enable */ byte ILT :1; /* Idle Line Type Select */ byte WAKE :1; /* Receiver Wakeup Method Select */ byte M :1; /* 9-Bit or 8-Bit Mode Select */ byte RSRC :1; /* Receiver Source Select */ byte SCISWAI :1; /* SCI Stops in Wait Mode */ byte LOOPS :1; /* Loop Mode Select */ } Bits; } SCIC1STR; extern volatile SCIC1STR _SCIC1 @0x0000002A; #define SCIC1 _SCIC1.Byte #define SCIC1_PT _SCIC1.Bits.PT #define SCIC1_PE _SCIC1.Bits.PE #define SCIC1_ILT _SCIC1.Bits.ILT #define SCIC1_WAKE _SCIC1.Bits.WAKE #define SCIC1_M _SCIC1.Bits.M #define SCIC1_RSRC _SCIC1.Bits.RSRC #define SCIC1_SCISWAI _SCIC1.Bits.SCISWAI #define SCIC1_LOOPS _SCIC1.Bits.LOOPS #define SCIC1_PT_MASK 1 #define SCIC1_PE_MASK 2 #define SCIC1_ILT_MASK 4 #define SCIC1_WAKE_MASK 8 #define SCIC1_M_MASK 16 #define SCIC1_RSRC_MASK 32 #define SCIC1_SCISWAI_MASK 64 #define SCIC1_LOOPS_MASK 128 /*** SCIC2 - SCI Control Register 2; 0x0000002B ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break */ byte RWU :1; /* Receiver Wakeup Control */ byte RE :1; /* Receiver Enable */ byte TE :1; /* Transmitter Enable */ byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */ byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */ byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */ byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */ } Bits; } SCIC2STR; extern volatile SCIC2STR _SCIC2 @0x0000002B; #define SCIC2 _SCIC2.Byte #define SCIC2_SBK _SCIC2.Bits.SBK #define SCIC2_RWU _SCIC2.Bits.RWU #define SCIC2_RE _SCIC2.Bits.RE #define SCIC2_TE _SCIC2.Bits.TE #define SCIC2_ILIE _SCIC2.Bits.ILIE #define SCIC2_RIE _SCIC2.Bits.RIE #define SCIC2_TCIE _SCIC2.Bits.TCIE #define SCIC2_TIE _SCIC2.Bits.TIE #define SCIC2_SBK_MASK 1 #define SCIC2_RWU_MASK 2 #define SCIC2_RE_MASK 4 #define SCIC2_TE_MASK 8 #define SCIC2_ILIE_MASK 16 #define SCIC2_RIE_MASK 32 #define SCIC2_TCIE_MASK 64 #define SCIC2_TIE_MASK 128 /*** SCIS1 - SCI Status Register 1; 0x0000002C ***/ typedef union { byte Byte; struct { byte PF :1; /* Parity Error Flag */ byte FE :1; /* Framing Error Flag */ byte NF :1; /* Noise Flag */ byte OR :1; /* Receiver Overrun Flag */ byte IDLE :1; /* Idle Line Flag */ byte RDRF :1; /* Receive Data Register Full Flag */ byte TC :1; /* Transmission Complete Flag */ byte TDRE :1; /* Transmit Data Register Empty Flag */ } Bits; } SCIS1STR; extern volatile SCIS1STR _SCIS1 @0x0000002C; #define SCIS1 _SCIS1.Byte #define SCIS1_PF _SCIS1.Bits.PF #define SCIS1_FE _SCIS1.Bits.FE #define SCIS1_NF _SCIS1.Bits.NF #define SCIS1_OR _SCIS1.Bits.OR #define SCIS1_IDLE _SCIS1.Bits.IDLE #define SCIS1_RDRF _SCIS1.Bits.RDRF #define SCIS1_TC _SCIS1.Bits.TC #define SCIS1_TDRE _SCIS1.Bits.TDRE #define SCIS1_PF_MASK 1 #define SCIS1_FE_MASK 2 #define SCIS1_NF_MASK 4 #define SCIS1_OR_MASK 8 #define SCIS1_IDLE_MASK 16 #define SCIS1_RDRF_MASK 32 #define SCIS1_TC_MASK 64 #define SCIS1_TDRE_MASK 128 /*** SCIS2 - SCI Status Register 2; 0x0000002D ***/ typedef union { byte Byte; struct { byte RAF :1; /* Receiver Active Flag */ byte LBKDE :1; /* LIN Break Detection Enable */ byte BRK13 :1; /* Break Character Generation Length */ byte RWUID :1; /* Receive Wake Up Idle Detect */ byte RXINV :1; /* Receive Data Inversion */ byte :1; byte RXEDGIF :1; /* RxD Pin Active Edge Interrupt Flag */ byte LBKDIF :1; /* LIN Break Detect Interrupt Flag */ } Bits; } SCIS2STR; extern volatile SCIS2STR _SCIS2 @0x0000002D; #define SCIS2 _SCIS2.Byte #define SCIS2_RAF _SCIS2.Bits.RAF #define SCIS2_LBKDE _SCIS2.Bits.LBKDE #define SCIS2_BRK13 _SCIS2.Bits.BRK13 #define SCIS2_RWUID _SCIS2.Bits.RWUID #define SCIS2_RXINV _SCIS2.Bits.RXINV #define SCIS2_RXEDGIF _SCIS2.Bits.RXEDGIF #define SCIS2_LBKDIF _SCIS2.Bits.LBKDIF #define SCIS2_RAF_MASK 1 #define SCIS2_LBKDE_MASK 2 #define SCIS2_BRK13_MASK 4 #define SCIS2_RWUID_MASK 8 #define SCIS2_RXINV_MASK 16 #define SCIS2_RXEDGIF_MASK 64 #define SCIS2_LBKDIF_MASK 128 /*** SCIC3 - SCI Control Register 3; 0x0000002E ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Parity Error Interrupt Enable */ byte FEIE :1; /* Framing Error Interrupt Enable */ byte NEIE :1; /* Noise Error Interrupt Enable */ byte ORIE :1; /* Overrun Interrupt Enable */ byte TXINV :1; /* Transmit Data Inversion */ byte TXDIR :1; /* TxD Pin Direction in Single-Wire Mode */ byte T8 :1; /* Ninth Data Bit for Transmitter */ byte R8 :1; /* Ninth Data Bit for Receiver */ } Bits; } SCIC3STR; extern volatile SCIC3STR _SCIC3 @0x0000002E; #define SCIC3 _SCIC3.Byte #define SCIC3_PEIE _SCIC3.Bits.PEIE #define SCIC3_FEIE _SCIC3.Bits.FEIE #define SCIC3_NEIE _SCIC3.Bits.NEIE #define SCIC3_ORIE _SCIC3.Bits.ORIE #define SCIC3_TXINV _SCIC3.Bits.TXINV #define SCIC3_TXDIR _SCIC3.Bits.TXDIR #define SCIC3_T8 _SCIC3.Bits.T8 #define SCIC3_R8 _SCIC3.Bits.R8 #define SCIC3_PEIE_MASK 1 #define SCIC3_FEIE_MASK 2 #define SCIC3_NEIE_MASK 4 #define SCIC3_ORIE_MASK 8 #define SCIC3_TXINV_MASK 16 #define SCIC3_TXDIR_MASK 32 #define SCIC3_T8_MASK 64 #define SCIC3_R8_MASK 128 /*** SCID - SCI Data Register; 0x0000002F ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCIDSTR; extern volatile SCIDSTR _SCID @0x0000002F; #define SCID _SCID.Byte #define SCID_R0_T0 _SCID.Bits.R0_T0 #define SCID_R1_T1 _SCID.Bits.R1_T1 #define SCID_R2_T2 _SCID.Bits.R2_T2 #define SCID_R3_T3 _SCID.Bits.R3_T3 #define SCID_R4_T4 _SCID.Bits.R4_T4 #define SCID_R5_T5 _SCID.Bits.R5_T5 #define SCID_R6_T6 _SCID.Bits.R6_T6 #define SCID_R7_T7 _SCID.Bits.R7_T7 #define SCID_R0_T0_MASK 1 #define SCID_R1_T1_MASK 2 #define SCID_R2_T2_MASK 4 #define SCID_R3_T3_MASK 8 #define SCID_R4_T4_MASK 16 #define SCID_R5_T5_MASK 32 #define SCID_R6_T6_MASK 64 #define SCID_R7_T7_MASK 128 /*** SRS - System Reset Status Register; 0x00000200 ***/ typedef union { byte Byte; struct { byte :1; byte LVD :1; /* Low Voltage Detect */ byte :1; byte ILAD :1; /* Illegal Address */ byte ILOP :1; /* Illegal Opcode */ byte COP :1; /* Computer Operating Properly (COP) Watchdog */ byte PIN :1; /* External Reset Pin */ byte POR :1; /* Power-On Reset */ } Bits; } SRSSTR; extern volatile SRSSTR _SRS @0x00000200; #define SRS _SRS.Byte #define SRS_LVD _SRS.Bits.LVD #define SRS_ILAD _SRS.Bits.ILAD #define SRS_ILOP _SRS.Bits.ILOP #define SRS_COP _SRS.Bits.COP #define SRS_PIN _SRS.Bits.PIN #define SRS_POR _SRS.Bits.POR #define SRS_LVD_MASK 2 #define SRS_ILAD_MASK 8 #define SRS_ILOP_MASK 16 #define SRS_COP_MASK 32 #define SRS_PIN_MASK 64 #define SRS_POR_MASK 128 /*** SOPT - System Options Register; 0x00000201 ***/ typedef union { byte Byte; struct { byte RSTPE :1; /* RESET Pin Enable */ byte BKGDPE :1; /* Background Debug Mode Pin Enable */ byte :1; byte :1; byte :1; byte STOPE :1; /* Stop Mode Enable */ byte COPT :1; /* COP Watchdog Timeout */ byte COPE :1; /* COP Watchdog Enable */ } Bits; } SOPTSTR; extern volatile SOPTSTR _SOPT @0x00000201; #define SOPT _SOPT.Byte #define SOPT_RSTPE _SOPT.Bits.RSTPE #define SOPT_BKGDPE _SOPT.Bits.BKGDPE #define SOPT_STOPE _SOPT.Bits.STOPE #define SOPT_COPT _SOPT.Bits.COPT #define SOPT_COPE _SOPT.Bits.COPE #define SOPT_RSTPE_MASK 1 #define SOPT_BKGDPE_MASK 2 #define SOPT_STOPE_MASK 32 #define SOPT_COPT_MASK 64 #define SOPT_COPE_MASK 128 /*** SIP1 - System Interrupt Pending Register; 0x00000202 ***/ typedef union { byte Byte; struct { byte RTI :1; /* Real-Time Interrupt Pending */ byte MTIM1 :1; /* Modulo Timer 1 Interrupt Pending */ byte MTIM2 :1; /* Modulo Timer 2 Interrupt Pending */ byte TPM :1; /* Timer/PWM Interrupt Pending */ byte ADC :1; /* ADC Interrupt Pending */ byte ACMP :1; /* Analog Comparator Interrupt Pending */ byte KBI :1; /* Keyboard Interrupt Pending */ byte SCI :1; /* SCI Interrupt Pending */ } Bits; struct { byte :1; byte grpMTIM_1 :2; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SIP1STR; extern volatile SIP1STR _SIP1 @0x00000202; #define SIP1 _SIP1.Byte #define SIP1_RTI _SIP1.Bits.RTI #define SIP1_MTIM1 _SIP1.Bits.MTIM1 #define SIP1_MTIM2 _SIP1.Bits.MTIM2 #define SIP1_TPM _SIP1.Bits.TPM #define SIP1_ADC _SIP1.Bits.ADC #define SIP1_ACMP _SIP1.Bits.ACMP #define SIP1_KBI _SIP1.Bits.KBI #define SIP1_SCI _SIP1.Bits.SCI #define SIP1_MTIM_1 _SIP1.MergedBits.grpMTIM_1 #define SIP1_MTIM SIP1_MTIM_1 #define SIP1_RTI_MASK 1 #define SIP1_MTIM1_MASK 2 #define SIP1_MTIM2_MASK 4 #define SIP1_TPM_MASK 8 #define SIP1_ADC_MASK 16 #define SIP1_ACMP_MASK 32 #define SIP1_KBI_MASK 64 #define SIP1_SCI_MASK 128 #define SIP1_MTIM_1_MASK 6 #define SIP1_MTIM_1_BITNUM 1 /*** SDID - System Device Identification Register; 0x00000206 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SDIDH - System Device Identification Register High; 0x00000206 ***/ union { byte Byte; struct { byte ID8 :1; /* Part Identification Number, bit 8 */ byte ID9 :1; /* Part Identification Number, bit 9 */ byte ID10 :1; /* Part Identification Number, bit 10 */ byte ID11 :1; /* Part Identification Number, bit 11 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpID_8 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SDIDHSTR; #define SDIDH _SDID.Overlap_STR.SDIDHSTR.Byte #define SDIDH_ID8 _SDID.Overlap_STR.SDIDHSTR.Bits.ID8 #define SDIDH_ID9 _SDID.Overlap_STR.SDIDHSTR.Bits.ID9 #define SDIDH_ID10 _SDID.Overlap_STR.SDIDHSTR.Bits.ID10 #define SDIDH_ID11 _SDID.Overlap_STR.SDIDHSTR.Bits.ID11 #define SDIDH_ID_8 _SDID.Overlap_STR.SDIDHSTR.MergedBits.grpID_8 #define SDIDH_ID SDIDH_ID_8 #define SDIDH_ID8_MASK 1 #define SDIDH_ID9_MASK 2 #define SDIDH_ID10_MASK 4 #define SDIDH_ID11_MASK 8 #define SDIDH_ID_8_MASK 15 #define SDIDH_ID_8_BITNUM 0 /*** SDIDL - System Device Identification Register Low; 0x00000207 ***/ union { byte Byte; struct { byte ID0 :1; /* Part Identification Number, bit 0 */ byte ID1 :1; /* Part Identification Number, bit 1 */ byte ID2 :1; /* Part Identification Number, bit 2 */ byte ID3 :1; /* Part Identification Number, bit 3 */ byte ID4 :1; /* Part Identification Number, bit 4 */ byte ID5 :1; /* Part Identification Number, bit 5 */ byte ID6 :1; /* Part Identification Number, bit 6 */ byte ID7 :1; /* Part Identification Number, bit 7 */ } Bits; } SDIDLSTR; #define SDIDL _SDID.Overlap_STR.SDIDLSTR.Byte #define SDIDL_ID0 _SDID.Overlap_STR.SDIDLSTR.Bits.ID0 #define SDIDL_ID1 _SDID.Overlap_STR.SDIDLSTR.Bits.ID1 #define SDIDL_ID2 _SDID.Overlap_STR.SDIDLSTR.Bits.ID2 #define SDIDL_ID3 _SDID.Overlap_STR.SDIDLSTR.Bits.ID3 #define SDIDL_ID4 _SDID.Overlap_STR.SDIDLSTR.Bits.ID4 #define SDIDL_ID5 _SDID.Overlap_STR.SDIDLSTR.Bits.ID5 #define SDIDL_ID6 _SDID.Overlap_STR.SDIDLSTR.Bits.ID6 #define SDIDL_ID7 _SDID.Overlap_STR.SDIDLSTR.Bits.ID7 #define SDIDL_ID0_MASK 1 #define SDIDL_ID1_MASK 2 #define SDIDL_ID2_MASK 4 #define SDIDL_ID3_MASK 8 #define SDIDL_ID4_MASK 16 #define SDIDL_ID5_MASK 32 #define SDIDL_ID6_MASK 64 #define SDIDL_ID7_MASK 128 } Overlap_STR; } SDIDSTR; extern volatile SDIDSTR _SDID @0x00000206; #define SDID _SDID.Word /*** SRTISC - System Real-Time Interrupt Status and Control Register; 0x00000208 ***/ typedef union { byte Byte; struct { byte RTIS0 :1; /* Real-Time Interrupt Delay Selects, bit 0 */ byte RTIS1 :1; /* Real-Time Interrupt Delay Selects, bit 1 */ byte RTIS2 :1; /* Real-Time Interrupt Delay Selects, bit 2 */ byte :1; byte RTIE :1; /* Real-Time Interrupt Enable */ byte RTICLKS :1; /* Real-Time Interrupt Clock Select */ byte RTIACK :1; /* Real-Time Interrupt Acknowledge */ byte RTIF :1; /* Real-Time Interrupt Flag */ } Bits; struct { byte grpRTIS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SRTISCSTR; extern volatile SRTISCSTR _SRTISC @0x00000208; #define SRTISC _SRTISC.Byte #define SRTISC_RTIS0 _SRTISC.Bits.RTIS0 #define SRTISC_RTIS1 _SRTISC.Bits.RTIS1 #define SRTISC_RTIS2 _SRTISC.Bits.RTIS2 #define SRTISC_RTIE _SRTISC.Bits.RTIE #define SRTISC_RTICLKS _SRTISC.Bits.RTICLKS #define SRTISC_RTIACK _SRTISC.Bits.RTIACK #define SRTISC_RTIF _SRTISC.Bits.RTIF #define SRTISC_RTIS _SRTISC.MergedBits.grpRTIS #define SRTISC_RTIS0_MASK 1 #define SRTISC_RTIS1_MASK 2 #define SRTISC_RTIS2_MASK 4 #define SRTISC_RTIE_MASK 16 #define SRTISC_RTICLKS_MASK 32 #define SRTISC_RTIACK_MASK 64 #define SRTISC_RTIF_MASK 128 #define SRTISC_RTIS_MASK 7 #define SRTISC_RTIS_BITNUM 0 /*** SPMSC1 - System Power Management Status and Control 1 Register; 0x00000209 ***/ typedef union { byte Byte; struct { byte BGBE :1; /* Bandgap Buffer Enable */ byte :1; byte LVDE :1; /* Low-Voltage Detect Enable */ byte LVDSE :1; /* Low-Voltage Detect Stop Enable */ byte LVDRE :1; /* Low-Voltage Detect Reset Enable */ byte LVDIE :1; /* Low-Voltage Detect Interrupt Enable */ byte LVDACK :1; /* Low-Voltage Detect Acknowledge */ byte LVDF :1; /* Low-Voltage Detect Flag */ } Bits; } SPMSC1STR; extern volatile SPMSC1STR _SPMSC1 @0x00000209; #define SPMSC1 _SPMSC1.Byte #define SPMSC1_BGBE _SPMSC1.Bits.BGBE #define SPMSC1_LVDE _SPMSC1.Bits.LVDE #define SPMSC1_LVDSE _SPMSC1.Bits.LVDSE #define SPMSC1_LVDRE _SPMSC1.Bits.LVDRE #define SPMSC1_LVDIE _SPMSC1.Bits.LVDIE #define SPMSC1_LVDACK _SPMSC1.Bits.LVDACK #define SPMSC1_LVDF _SPMSC1.Bits.LVDF #define SPMSC1_BGBE_MASK 1 #define SPMSC1_LVDE_MASK 4 #define SPMSC1_LVDSE_MASK 8 #define SPMSC1_LVDRE_MASK 16 #define SPMSC1_LVDIE_MASK 32 #define SPMSC1_LVDACK_MASK 64 #define SPMSC1_LVDF_MASK 128 /*** FOPT - Flash Options Register; 0x00000210 ***/ typedef union { byte Byte; struct { byte SECD :1; /* Security State Code */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } FOPTSTR; extern volatile FOPTSTR _FOPT @0x00000210; #define FOPT _FOPT.Byte #define FOPT_SECD _FOPT.Bits.SECD #define FOPT_SECD_MASK 1 /*** FLCR - Flash Control Register; 0x00000211 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte :1; byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High Voltage Enable */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x00000211; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** PTADD - Port A Data Direction Register; 0x00000220 ***/ typedef union { byte Byte; struct { byte PTADD0 :1; /* PTADD */ byte PTADD1 :1; /* PTADD */ byte PTADD2 :1; /* PTADD */ byte PTADD3 :1; /* PTADD */ byte :1; byte :1; byte PTADD6 :1; /* PTADD */ byte PTADD7 :1; /* PTADD */ } Bits; struct { byte grpPTADD :4; byte :1; byte :1; byte grpPTADD_6 :2; } MergedBits; } PTADDSTR; extern volatile PTADDSTR _PTADD @0x00000220; #define PTADD _PTADD.Byte #define PTADD_PTADD0 _PTADD.Bits.PTADD0 #define PTADD_PTADD1 _PTADD.Bits.PTADD1 #define PTADD_PTADD2 _PTADD.Bits.PTADD2 #define PTADD_PTADD3 _PTADD.Bits.PTADD3 #define PTADD_PTADD6 _PTADD.Bits.PTADD6 #define PTADD_PTADD7 _PTADD.Bits.PTADD7 #define PTADD_PTADD _PTADD.MergedBits.grpPTADD #define PTADD_PTADD_6 _PTADD.MergedBits.grpPTADD_6 #define PTADD_PTADD0_MASK 1 #define PTADD_PTADD1_MASK 2 #define PTADD_PTADD2_MASK 4 #define PTADD_PTADD3_MASK 8 #define PTADD_PTADD6_MASK 64 #define PTADD_PTADD7_MASK 128 #define PTADD_PTADD_MASK 15 #define PTADD_PTADD_BITNUM 0 #define PTADD_PTADD_6_MASK 192 #define PTADD_PTADD_6_BITNUM 6 /*** PTAPE - Port A Internal Pulling Device Enable Register; 0x00000221 ***/ typedef union { byte Byte; struct { byte PTAPE0 :1; /* Internal Pulling Device Enable for Port A Bit 0 */ byte PTAPE1 :1; /* Internal Pulling Device Enable for Port A Bit 1 */ byte PTAPE2 :1; /* Internal Pulling Device Enable for Port A Bit 2 */ byte PTAPE3 :1; /* Internal Pulling Device Enable for Port A Bit 3 */ byte :1; byte PTAPE5 :1; /* Internal Pulling Device Enable for Port A Bit 5 */ byte PTAPE6 :1; /* Internal Pulling Device Enable for Port A Bit 6 */ byte PTAPE7 :1; /* Internal Pulling Device Enable for Port A Bit 7 */ } Bits; struct { byte grpPTAPE :4; byte :1; byte grpPTAPE_5 :3; } MergedBits; } PTAPESTR; extern volatile PTAPESTR _PTAPE @0x00000221; #define PTAPE _PTAPE.Byte #define PTAPE_PTAPE0 _PTAPE.Bits.PTAPE0 #define PTAPE_PTAPE1 _PTAPE.Bits.PTAPE1 #define PTAPE_PTAPE2 _PTAPE.Bits.PTAPE2 #define PTAPE_PTAPE3 _PTAPE.Bits.PTAPE3 #define PTAPE_PTAPE5 _PTAPE.Bits.PTAPE5 #define PTAPE_PTAPE6 _PTAPE.Bits.PTAPE6 #define PTAPE_PTAPE7 _PTAPE.Bits.PTAPE7 #define PTAPE_PTAPE _PTAPE.MergedBits.grpPTAPE #define PTAPE_PTAPE_5 _PTAPE.MergedBits.grpPTAPE_5 #define PTAPE_PTAPE0_MASK 1 #define PTAPE_PTAPE1_MASK 2 #define PTAPE_PTAPE2_MASK 4 #define PTAPE_PTAPE3_MASK 8 #define PTAPE_PTAPE5_MASK 32 #define PTAPE_PTAPE6_MASK 64 #define PTAPE_PTAPE7_MASK 128 #define PTAPE_PTAPE_MASK 15 #define PTAPE_PTAPE_BITNUM 0 #define PTAPE_PTAPE_5_MASK 224 #define PTAPE_PTAPE_5_BITNUM 5 /*** PTAPUD - Port A Pullup/Pulldown Control Register; 0x00000222 ***/ typedef union { byte Byte; struct { byte PTAPUD0 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD1 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD2 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD3 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte :1; byte PTAPUD5 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD6 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD7 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ } Bits; struct { byte grpPTAPUD :4; byte :1; byte grpPTAPUD_5 :3; } MergedBits; } PTAPUDSTR; extern volatile PTAPUDSTR _PTAPUD @0x00000222; #define PTAPUD _PTAPUD.Byte #define PTAPUD_PTAPUD0 _PTAPUD.Bits.PTAPUD0 #define PTAPUD_PTAPUD1 _PTAPUD.Bits.PTAPUD1 #define PTAPUD_PTAPUD2 _PTAPUD.Bits.PTAPUD2 #define PTAPUD_PTAPUD3 _PTAPUD.Bits.PTAPUD3 #define PTAPUD_PTAPUD5 _PTAPUD.Bits.PTAPUD5 #define PTAPUD_PTAPUD6 _PTAPUD.Bits.PTAPUD6 #define PTAPUD_PTAPUD7 _PTAPUD.Bits.PTAPUD7 #define PTAPUD_PTAPUD _PTAPUD.MergedBits.grpPTAPUD #define PTAPUD_PTAPUD_5 _PTAPUD.MergedBits.grpPTAPUD_5 #define PTAPUD_PTAPUD0_MASK 1 #define PTAPUD_PTAPUD1_MASK 2 #define PTAPUD_PTAPUD2_MASK 4 #define PTAPUD_PTAPUD3_MASK 8 #define PTAPUD_PTAPUD5_MASK 32 #define PTAPUD_PTAPUD6_MASK 64 #define PTAPUD_PTAPUD7_MASK 128 #define PTAPUD_PTAPUD_MASK 15 #define PTAPUD_PTAPUD_BITNUM 0 #define PTAPUD_PTAPUD_5_MASK 224 #define PTAPUD_PTAPUD_5_BITNUM 5 /*** PTASE - Port A Output Slew Rate Control Enable Register; 0x00000223 ***/ typedef union { byte Byte; struct { byte PTASE0 :1; /* Output Slew Rate Enable for Port A Bit 0 */ byte PTASE1 :1; /* Output Slew Rate Enable for Port A Bit 1 */ byte PTASE2 :1; /* Output Slew Rate Enable for Port A Bit 2 */ byte PTASE3 :1; /* Output Slew Rate Enable for Port A Bit 3 */ byte PTASE4 :1; /* Output Slew Rate Enable for Port A Bit 4 */ byte :1; byte PTASE6 :1; /* Output Slew Rate Enable for Port A Bit 6 */ byte PTASE7 :1; /* Output Slew Rate Enable for Port A Bit 7 */ } Bits; struct { byte grpPTASE :5; byte :1; byte grpPTASE_6 :2; } MergedBits; } PTASESTR; extern volatile PTASESTR _PTASE @0x00000223; #define PTASE _PTASE.Byte #define PTASE_PTASE0 _PTASE.Bits.PTASE0 #define PTASE_PTASE1 _PTASE.Bits.PTASE1 #define PTASE_PTASE2 _PTASE.Bits.PTASE2 #define PTASE_PTASE3 _PTASE.Bits.PTASE3 #define PTASE_PTASE4 _PTASE.Bits.PTASE4 #define PTASE_PTASE6 _PTASE.Bits.PTASE6 #define PTASE_PTASE7 _PTASE.Bits.PTASE7 #define PTASE_PTASE _PTASE.MergedBits.grpPTASE #define PTASE_PTASE_6 _PTASE.MergedBits.grpPTASE_6 #define PTASE_PTASE0_MASK 1 #define PTASE_PTASE1_MASK 2 #define PTASE_PTASE2_MASK 4 #define PTASE_PTASE3_MASK 8 #define PTASE_PTASE4_MASK 16 #define PTASE_PTASE6_MASK 64 #define PTASE_PTASE7_MASK 128 #define PTASE_PTASE_MASK 31 #define PTASE_PTASE_BITNUM 0 #define PTASE_PTASE_6_MASK 192 #define PTASE_PTASE_6_BITNUM 6 /*** PTBDD - Port B Data Direction Register; 0x00000224 ***/ typedef union { byte Byte; struct { byte PTBDD0 :1; /* PTBDD */ byte PTBDD1 :1; /* PTBDD */ byte PTBDD2 :1; /* PTBDD */ byte PTBDD3 :1; /* PTBDD */ byte PTBDD4 :1; /* PTBDD */ byte PTBDD5 :1; /* PTBDD */ byte PTBDD6 :1; /* PTBDD */ byte PTBDD7 :1; /* PTBDD */ } Bits; } PTBDDSTR; extern volatile PTBDDSTR _PTBDD @0x00000224; #define PTBDD _PTBDD.Byte #define PTBDD_PTBDD0 _PTBDD.Bits.PTBDD0 #define PTBDD_PTBDD1 _PTBDD.Bits.PTBDD1 #define PTBDD_PTBDD2 _PTBDD.Bits.PTBDD2 #define PTBDD_PTBDD3 _PTBDD.Bits.PTBDD3 #define PTBDD_PTBDD4 _PTBDD.Bits.PTBDD4 #define PTBDD_PTBDD5 _PTBDD.Bits.PTBDD5 #define PTBDD_PTBDD6 _PTBDD.Bits.PTBDD6 #define PTBDD_PTBDD7 _PTBDD.Bits.PTBDD7 #define PTBDD_PTBDD0_MASK 1 #define PTBDD_PTBDD1_MASK 2 #define PTBDD_PTBDD2_MASK 4 #define PTBDD_PTBDD3_MASK 8 #define PTBDD_PTBDD4_MASK 16 #define PTBDD_PTBDD5_MASK 32 #define PTBDD_PTBDD6_MASK 64 #define PTBDD_PTBDD7_MASK 128 /*** PTBPE - Port B Internal Pulling Device Enable Register; 0x00000225 ***/ typedef union { byte Byte; struct { byte PTBPE0 :1; /* Internal Pulling Device Enable for Port B Bit 0 */ byte PTBPE1 :1; /* Internal Pulling Device Enable for Port B Bit 1 */ byte PTBPE2 :1; /* Internal Pulling Device Enable for Port B Bit 2 */ byte PTBPE3 :1; /* Internal Pulling Device Enable for Port B Bit 3 */ byte PTBPE4 :1; /* Internal Pulling Device Enable for Port B Bit 4 */ byte PTBPE5 :1; /* Internal Pulling Device Enable for Port B Bit 5 */ byte PTBPE6 :1; /* Internal Pulling Device Enable for Port B Bit 6 */ byte PTBPE7 :1; /* Internal Pulling Device Enable for Port B Bit 7 */ } Bits; } PTBPESTR; extern volatile PTBPESTR _PTBPE @0x00000225; #define PTBPE _PTBPE.Byte #define PTBPE_PTBPE0 _PTBPE.Bits.PTBPE0 #define PTBPE_PTBPE1 _PTBPE.Bits.PTBPE1 #define PTBPE_PTBPE2 _PTBPE.Bits.PTBPE2 #define PTBPE_PTBPE3 _PTBPE.Bits.PTBPE3 #define PTBPE_PTBPE4 _PTBPE.Bits.PTBPE4 #define PTBPE_PTBPE5 _PTBPE.Bits.PTBPE5 #define PTBPE_PTBPE6 _PTBPE.Bits.PTBPE6 #define PTBPE_PTBPE7 _PTBPE.Bits.PTBPE7 #define PTBPE_PTBPE0_MASK 1 #define PTBPE_PTBPE1_MASK 2 #define PTBPE_PTBPE2_MASK 4 #define PTBPE_PTBPE3_MASK 8 #define PTBPE_PTBPE4_MASK 16 #define PTBPE_PTBPE5_MASK 32 #define PTBPE_PTBPE6_MASK 64 #define PTBPE_PTBPE7_MASK 128 /*** PTBPUD - Port B Pullup/Pulldown Control Register; 0x00000226 ***/ typedef union { byte Byte; struct { byte PTBPUD0 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD1 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD2 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD3 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD4 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD5 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD6 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD7 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ } Bits; } PTBPUDSTR; extern volatile PTBPUDSTR _PTBPUD @0x00000226; #define PTBPUD _PTBPUD.Byte #define PTBPUD_PTBPUD0 _PTBPUD.Bits.PTBPUD0 #define PTBPUD_PTBPUD1 _PTBPUD.Bits.PTBPUD1 #define PTBPUD_PTBPUD2 _PTBPUD.Bits.PTBPUD2 #define PTBPUD_PTBPUD3 _PTBPUD.Bits.PTBPUD3 #define PTBPUD_PTBPUD4 _PTBPUD.Bits.PTBPUD4 #define PTBPUD_PTBPUD5 _PTBPUD.Bits.PTBPUD5 #define PTBPUD_PTBPUD6 _PTBPUD.Bits.PTBPUD6 #define PTBPUD_PTBPUD7 _PTBPUD.Bits.PTBPUD7 #define PTBPUD_PTBPUD0_MASK 1 #define PTBPUD_PTBPUD1_MASK 2 #define PTBPUD_PTBPUD2_MASK 4 #define PTBPUD_PTBPUD3_MASK 8 #define PTBPUD_PTBPUD4_MASK 16 #define PTBPUD_PTBPUD5_MASK 32 #define PTBPUD_PTBPUD6_MASK 64 #define PTBPUD_PTBPUD7_MASK 128 /*** PTBSE - Port B Output Slew Rate Control Enable Register; 0x00000227 ***/ typedef union { byte Byte; struct { byte PTBSE0 :1; /* Output Slew Rate Enable for Port B Bit 0 */ byte PTBSE1 :1; /* Output Slew Rate Enable for Port B Bit 1 */ byte PTBSE2 :1; /* Output Slew Rate Enable for Port B Bit 2 */ byte PTBSE3 :1; /* Output Slew Rate Enable for Port B Bit 3 */ byte PTBSE4 :1; /* Output Slew Rate Enable for Port B Bit 4 */ byte PTBSE5 :1; /* Output Slew Rate Enable for Port B Bit 5 */ byte PTBSE6 :1; /* Output Slew Rate Enable for Port B Bit 6 */ byte PTBSE7 :1; /* Output Slew Rate Enable for Port B Bit 7 */ } Bits; } PTBSESTR; extern volatile PTBSESTR _PTBSE @0x00000227; #define PTBSE _PTBSE.Byte #define PTBSE_PTBSE0 _PTBSE.Bits.PTBSE0 #define PTBSE_PTBSE1 _PTBSE.Bits.PTBSE1 #define PTBSE_PTBSE2 _PTBSE.Bits.PTBSE2 #define PTBSE_PTBSE3 _PTBSE.Bits.PTBSE3 #define PTBSE_PTBSE4 _PTBSE.Bits.PTBSE4 #define PTBSE_PTBSE5 _PTBSE.Bits.PTBSE5 #define PTBSE_PTBSE6 _PTBSE.Bits.PTBSE6 #define PTBSE_PTBSE7 _PTBSE.Bits.PTBSE7 #define PTBSE_PTBSE0_MASK 1 #define PTBSE_PTBSE1_MASK 2 #define PTBSE_PTBSE2_MASK 4 #define PTBSE_PTBSE3_MASK 8 #define PTBSE_PTBSE4_MASK 16 #define PTBSE_PTBSE5_MASK 32 #define PTBSE_PTBSE6_MASK 64 #define PTBSE_PTBSE7_MASK 128 /*** PTCDD - Port C Data Direction Register; 0x00000228 ***/ typedef union { byte Byte; struct { byte PTCDD0 :1; /* PTCDD */ byte PTCDD1 :1; /* PTCDD */ byte PTCDD2 :1; /* PTCDD */ byte PTCDD3 :1; /* PTCDD */ byte PTCDD4 :1; /* PTCDD */ byte PTCDD5 :1; /* PTCDD */ byte PTCDD6 :1; /* PTCDD */ byte PTCDD7 :1; /* PTCDD */ } Bits; } PTCDDSTR; extern volatile PTCDDSTR _PTCDD @0x00000228; #define PTCDD _PTCDD.Byte #define PTCDD_PTCDD0 _PTCDD.Bits.PTCDD0 #define PTCDD_PTCDD1 _PTCDD.Bits.PTCDD1 #define PTCDD_PTCDD2 _PTCDD.Bits.PTCDD2 #define PTCDD_PTCDD3 _PTCDD.Bits.PTCDD3 #define PTCDD_PTCDD4 _PTCDD.Bits.PTCDD4 #define PTCDD_PTCDD5 _PTCDD.Bits.PTCDD5 #define PTCDD_PTCDD6 _PTCDD.Bits.PTCDD6 #define PTCDD_PTCDD7 _PTCDD.Bits.PTCDD7 #define PTCDD_PTCDD0_MASK 1 #define PTCDD_PTCDD1_MASK 2 #define PTCDD_PTCDD2_MASK 4 #define PTCDD_PTCDD3_MASK 8 #define PTCDD_PTCDD4_MASK 16 #define PTCDD_PTCDD5_MASK 32 #define PTCDD_PTCDD6_MASK 64 #define PTCDD_PTCDD7_MASK 128 /*** PTCPE - Port C Internal Pulling Device Enable Register; 0x00000229 ***/ typedef union { byte Byte; struct { byte PTCPE0 :1; /* Internal Pulling Device Enable for Port C Bit 0 */ byte PTCPE1 :1; /* Internal Pulling Device Enable for Port C Bit 1 */ byte PTCPE2 :1; /* Internal Pulling Device Enable for Port C Bit 2 */ byte PTCPE3 :1; /* Internal Pulling Device Enable for Port C Bit 3 */ byte PTCPE4 :1; /* Internal Pulling Device Enable for Port C Bit 4 */ byte PTCPE5 :1; /* Internal Pulling Device Enable for Port C Bit 5 */ byte PTCPE6 :1; /* Internal Pulling Device Enable for Port C Bit 6 */ byte PTCPE7 :1; /* Internal Pulling Device Enable for Port C Bit 7 */ } Bits; } PTCPESTR; extern volatile PTCPESTR _PTCPE @0x00000229; #define PTCPE _PTCPE.Byte #define PTCPE_PTCPE0 _PTCPE.Bits.PTCPE0 #define PTCPE_PTCPE1 _PTCPE.Bits.PTCPE1 #define PTCPE_PTCPE2 _PTCPE.Bits.PTCPE2 #define PTCPE_PTCPE3 _PTCPE.Bits.PTCPE3 #define PTCPE_PTCPE4 _PTCPE.Bits.PTCPE4 #define PTCPE_PTCPE5 _PTCPE.Bits.PTCPE5 #define PTCPE_PTCPE6 _PTCPE.Bits.PTCPE6 #define PTCPE_PTCPE7 _PTCPE.Bits.PTCPE7 #define PTCPE_PTCPE0_MASK 1 #define PTCPE_PTCPE1_MASK 2 #define PTCPE_PTCPE2_MASK 4 #define PTCPE_PTCPE3_MASK 8 #define PTCPE_PTCPE4_MASK 16 #define PTCPE_PTCPE5_MASK 32 #define PTCPE_PTCPE6_MASK 64 #define PTCPE_PTCPE7_MASK 128 /*** PTCPUD - Port C Pullup/Pulldown Control Register; 0x0000022A ***/ typedef union { byte Byte; struct { byte PTCPUD0 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD1 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD2 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD3 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD4 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD5 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD6 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD7 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ } Bits; } PTCPUDSTR; extern volatile PTCPUDSTR _PTCPUD @0x0000022A; #define PTCPUD _PTCPUD.Byte #define PTCPUD_PTCPUD0 _PTCPUD.Bits.PTCPUD0 #define PTCPUD_PTCPUD1 _PTCPUD.Bits.PTCPUD1 #define PTCPUD_PTCPUD2 _PTCPUD.Bits.PTCPUD2 #define PTCPUD_PTCPUD3 _PTCPUD.Bits.PTCPUD3 #define PTCPUD_PTCPUD4 _PTCPUD.Bits.PTCPUD4 #define PTCPUD_PTCPUD5 _PTCPUD.Bits.PTCPUD5 #define PTCPUD_PTCPUD6 _PTCPUD.Bits.PTCPUD6 #define PTCPUD_PTCPUD7 _PTCPUD.Bits.PTCPUD7 #define PTCPUD_PTCPUD0_MASK 1 #define PTCPUD_PTCPUD1_MASK 2 #define PTCPUD_PTCPUD2_MASK 4 #define PTCPUD_PTCPUD3_MASK 8 #define PTCPUD_PTCPUD4_MASK 16 #define PTCPUD_PTCPUD5_MASK 32 #define PTCPUD_PTCPUD6_MASK 64 #define PTCPUD_PTCPUD7_MASK 128 /*** PTCSE - Port C Output Slew Rate Control Enable Register; 0x0000022B ***/ typedef union { byte Byte; struct { byte PTCSE0 :1; /* Output Slew Rate Enable for Port C Bit 0 */ byte PTCSE1 :1; /* Output Slew Rate Enable for Port C Bit 1 */ byte PTCSE2 :1; /* Output Slew Rate Enable for Port C Bit 2 */ byte PTCSE3 :1; /* Output Slew Rate Enable for Port C Bit 3 */ byte PTCSE4 :1; /* Output Slew Rate Enable for Port C Bit 4 */ byte PTCSE5 :1; /* Output Slew Rate Enable for Port C Bit 5 */ byte PTCSE6 :1; /* Output Slew Rate Enable for Port C Bit 6 */ byte PTCSE7 :1; /* Output Slew Rate Enable for Port C Bit 7 */ } Bits; } PTCSESTR; extern volatile PTCSESTR _PTCSE @0x0000022B; #define PTCSE _PTCSE.Byte #define PTCSE_PTCSE0 _PTCSE.Bits.PTCSE0 #define PTCSE_PTCSE1 _PTCSE.Bits.PTCSE1 #define PTCSE_PTCSE2 _PTCSE.Bits.PTCSE2 #define PTCSE_PTCSE3 _PTCSE.Bits.PTCSE3 #define PTCSE_PTCSE4 _PTCSE.Bits.PTCSE4 #define PTCSE_PTCSE5 _PTCSE.Bits.PTCSE5 #define PTCSE_PTCSE6 _PTCSE.Bits.PTCSE6 #define PTCSE_PTCSE7 _PTCSE.Bits.PTCSE7 #define PTCSE_PTCSE0_MASK 1 #define PTCSE_PTCSE1_MASK 2 #define PTCSE_PTCSE2_MASK 4 #define PTCSE_PTCSE3_MASK 8 #define PTCSE_PTCSE4_MASK 16 #define PTCSE_PTCSE5_MASK 32 #define PTCSE_PTCSE6_MASK 64 #define PTCSE_PTCSE7_MASK 128 /*** PTDDD - Port D Data Direction Register; 0x0000022C ***/ typedef union { byte Byte; struct { byte PTDDD0 :1; /* PTDDD */ byte PTDDD1 :1; /* PTDDD */ byte PTDDD2 :1; /* PTDDD */ byte PTDDD3 :1; /* PTDDD */ byte PTDDD4 :1; /* PTDDD */ byte PTDDD5 :1; /* PTDDD */ byte :1; byte :1; } Bits; struct { byte grpPTDDD :6; byte :1; byte :1; } MergedBits; } PTDDDSTR; extern volatile PTDDDSTR _PTDDD @0x0000022C; #define PTDDD _PTDDD.Byte #define PTDDD_PTDDD0 _PTDDD.Bits.PTDDD0 #define PTDDD_PTDDD1 _PTDDD.Bits.PTDDD1 #define PTDDD_PTDDD2 _PTDDD.Bits.PTDDD2 #define PTDDD_PTDDD3 _PTDDD.Bits.PTDDD3 #define PTDDD_PTDDD4 _PTDDD.Bits.PTDDD4 #define PTDDD_PTDDD5 _PTDDD.Bits.PTDDD5 #define PTDDD_PTDDD _PTDDD.MergedBits.grpPTDDD #define PTDDD_PTDDD0_MASK 1 #define PTDDD_PTDDD1_MASK 2 #define PTDDD_PTDDD2_MASK 4 #define PTDDD_PTDDD3_MASK 8 #define PTDDD_PTDDD4_MASK 16 #define PTDDD_PTDDD5_MASK 32 #define PTDDD_PTDDD_MASK 63 #define PTDDD_PTDDD_BITNUM 0 /*** PTDPE - Port D Internal Pulling Device Enable Register; 0x0000022D ***/ typedef union { byte Byte; struct { byte PTDPE0 :1; /* Internal Pulling Device Enable for Port D Bit 0 */ byte PTDPE1 :1; /* Internal Pulling Device Enable for Port D Bit 1 */ byte PTDPE2 :1; /* Internal Pulling Device Enable for Port D Bit 2 */ byte PTDPE3 :1; /* Internal Pulling Device Enable for Port D Bit 3 */ byte PTDPE4 :1; /* Internal Pulling Device Enable for Port D Bit 4 */ byte PTDPE5 :1; /* Internal Pulling Device Enable for Port D Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpPTDPE :6; byte :1; byte :1; } MergedBits; } PTDPESTR; extern volatile PTDPESTR _PTDPE @0x0000022D; #define PTDPE _PTDPE.Byte #define PTDPE_PTDPE0 _PTDPE.Bits.PTDPE0 #define PTDPE_PTDPE1 _PTDPE.Bits.PTDPE1 #define PTDPE_PTDPE2 _PTDPE.Bits.PTDPE2 #define PTDPE_PTDPE3 _PTDPE.Bits.PTDPE3 #define PTDPE_PTDPE4 _PTDPE.Bits.PTDPE4 #define PTDPE_PTDPE5 _PTDPE.Bits.PTDPE5 #define PTDPE_PTDPE _PTDPE.MergedBits.grpPTDPE #define PTDPE_PTDPE0_MASK 1 #define PTDPE_PTDPE1_MASK 2 #define PTDPE_PTDPE2_MASK 4 #define PTDPE_PTDPE3_MASK 8 #define PTDPE_PTDPE4_MASK 16 #define PTDPE_PTDPE5_MASK 32 #define PTDPE_PTDPE_MASK 63 #define PTDPE_PTDPE_BITNUM 0 /*** PTDPUD - Port D Pullup/Pulldown Control Register; 0x0000022E ***/ typedef union { byte Byte; struct { byte PTDPUD0 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD1 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD2 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD3 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD4 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD5 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte :1; byte :1; } Bits; struct { byte grpPTDPUD :6; byte :1; byte :1; } MergedBits; } PTDPUDSTR; extern volatile PTDPUDSTR _PTDPUD @0x0000022E; #define PTDPUD _PTDPUD.Byte #define PTDPUD_PTDPUD0 _PTDPUD.Bits.PTDPUD0 #define PTDPUD_PTDPUD1 _PTDPUD.Bits.PTDPUD1 #define PTDPUD_PTDPUD2 _PTDPUD.Bits.PTDPUD2 #define PTDPUD_PTDPUD3 _PTDPUD.Bits.PTDPUD3 #define PTDPUD_PTDPUD4 _PTDPUD.Bits.PTDPUD4 #define PTDPUD_PTDPUD5 _PTDPUD.Bits.PTDPUD5 #define PTDPUD_PTDPUD _PTDPUD.MergedBits.grpPTDPUD #define PTDPUD_PTDPUD0_MASK 1 #define PTDPUD_PTDPUD1_MASK 2 #define PTDPUD_PTDPUD2_MASK 4 #define PTDPUD_PTDPUD3_MASK 8 #define PTDPUD_PTDPUD4_MASK 16 #define PTDPUD_PTDPUD5_MASK 32 #define PTDPUD_PTDPUD_MASK 63 #define PTDPUD_PTDPUD_BITNUM 0 /*** PTDSE - Port D Output Slew Rate Control Enable Register; 0x0000022F ***/ typedef union { byte Byte; struct { byte PTDSE0 :1; /* Output Slew Rate Enable for Port D Bit 0 */ byte PTDSE1 :1; /* Output Slew Rate Enable for Port D Bit 1 */ byte PTDSE2 :1; /* Output Slew Rate Enable for Port D Bit 2 */ byte PTDSE3 :1; /* Output Slew Rate Enable for Port D Bit 3 */ byte PTDSE4 :1; /* Output Slew Rate Enable for Port D Bit 4 */ byte PTDSE5 :1; /* Output Slew Rate Enable for Port D Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpPTDSE :6; byte :1; byte :1; } MergedBits; } PTDSESTR; extern volatile PTDSESTR _PTDSE @0x0000022F; #define PTDSE _PTDSE.Byte #define PTDSE_PTDSE0 _PTDSE.Bits.PTDSE0 #define PTDSE_PTDSE1 _PTDSE.Bits.PTDSE1 #define PTDSE_PTDSE2 _PTDSE.Bits.PTDSE2 #define PTDSE_PTDSE3 _PTDSE.Bits.PTDSE3 #define PTDSE_PTDSE4 _PTDSE.Bits.PTDSE4 #define PTDSE_PTDSE5 _PTDSE.Bits.PTDSE5 #define PTDSE_PTDSE _PTDSE.MergedBits.grpPTDSE #define PTDSE_PTDSE0_MASK 1 #define PTDSE_PTDSE1_MASK 2 #define PTDSE_PTDSE2_MASK 4 #define PTDSE_PTDSE3_MASK 8 #define PTDSE_PTDSE4_MASK 16 #define PTDSE_PTDSE5_MASK 32 #define PTDSE_PTDSE_MASK 63 #define PTDSE_PTDSE_BITNUM 0 /*** TPMSC - TPM Status and Control Register; 0x00000230 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescale Divisor Select Bit 0 */ byte PS1 :1; /* Prescale Divisor Select Bit 1 */ byte PS2 :1; /* Prescale Divisor Select Bit 2 */ byte CLKSA :1; /* Clock Source Select A */ byte CLKSB :1; /* Clock Source Select B */ byte CPWMS :1; /* Center-Aligned PWM Select */ byte TOIE :1; /* Timer Overflow Interrupt Enable */ byte TOF :1; /* Timer Overflow Flag */ } Bits; struct { byte grpPS :3; byte grpCLKSx :2; byte :1; byte :1; byte :1; } MergedBits; } TPMSCSTR; extern volatile TPMSCSTR _TPMSC @0x00000230; #define TPMSC _TPMSC.Byte #define TPMSC_PS0 _TPMSC.Bits.PS0 #define TPMSC_PS1 _TPMSC.Bits.PS1 #define TPMSC_PS2 _TPMSC.Bits.PS2 #define TPMSC_CLKSA _TPMSC.Bits.CLKSA #define TPMSC_CLKSB _TPMSC.Bits.CLKSB #define TPMSC_CPWMS _TPMSC.Bits.CPWMS #define TPMSC_TOIE _TPMSC.Bits.TOIE #define TPMSC_TOF _TPMSC.Bits.TOF #define TPMSC_PS _TPMSC.MergedBits.grpPS #define TPMSC_CLKSx _TPMSC.MergedBits.grpCLKSx #define TPMSC_PS0_MASK 1 #define TPMSC_PS1_MASK 2 #define TPMSC_PS2_MASK 4 #define TPMSC_CLKSA_MASK 8 #define TPMSC_CLKSB_MASK 16 #define TPMSC_CPWMS_MASK 32 #define TPMSC_TOIE_MASK 64 #define TPMSC_TOF_MASK 128 #define TPMSC_PS_MASK 7 #define TPMSC_PS_BITNUM 0 #define TPMSC_CLKSx_MASK 24 #define TPMSC_CLKSx_BITNUM 3 /*** TPMCNT - TPM Timer Counter Register; 0x00000231 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMCNTH - TPM Timer Counter Register High; 0x00000231 ***/ union { byte Byte; } TPMCNTHSTR; #define TPMCNTH _TPMCNT.Overlap_STR.TPMCNTHSTR.Byte /*** TPMCNTL - TPM Timer Counter Register Low; 0x00000232 ***/ union { byte Byte; } TPMCNTLSTR; #define TPMCNTL _TPMCNT.Overlap_STR.TPMCNTLSTR.Byte } Overlap_STR; } TPMCNTSTR; extern volatile TPMCNTSTR _TPMCNT @0x00000231; #define TPMCNT _TPMCNT.Word /*** TPMMOD - TPM Timer Counter Modulo Register; 0x00000233 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMMODH - TPM Timer Counter Modulo Register High; 0x00000233 ***/ union { byte Byte; } TPMMODHSTR; #define TPMMODH _TPMMOD.Overlap_STR.TPMMODHSTR.Byte /*** TPMMODL - TPM Timer Counter Modulo Register Low; 0x00000234 ***/ union { byte Byte; } TPMMODLSTR; #define TPMMODL _TPMMOD.Overlap_STR.TPMMODLSTR.Byte } Overlap_STR; } TPMMODSTR; extern volatile TPMMODSTR _TPMMOD @0x00000233; #define TPMMOD _TPMMOD.Word /*** KBIPE - KBI Pin Enable Register; 0x00000235 ***/ typedef union { byte Byte; struct { byte KBIPE0 :1; /* Keyboard Pin Enable for KBI Port Bit 0 */ byte KBIPE1 :1; /* Keyboard Pin Enable for KBI Port Bit 1 */ byte KBIPE2 :1; /* Keyboard Pin Enable for KBI Port Bit 2 */ byte KBIPE3 :1; /* Keyboard Pin Enable for KBI Port Bit 3 */ byte KBIPE4 :1; /* Keyboard Pin Enable for KBI Port Bit 4 */ byte KBIPE5 :1; /* Keyboard Pin Enable for KBI Port Bit 5 */ byte KBIPE6 :1; /* Keyboard Pin Enable for KBI Port Bit 6 */ byte KBIPE7 :1; /* Keyboard Pin Enable for KBI Port Bit 7 */ } Bits; } KBIPESTR; extern volatile KBIPESTR _KBIPE @0x00000235; #define KBIPE _KBIPE.Byte #define KBIPE_KBIPE0 _KBIPE.Bits.KBIPE0 #define KBIPE_KBIPE1 _KBIPE.Bits.KBIPE1 #define KBIPE_KBIPE2 _KBIPE.Bits.KBIPE2 #define KBIPE_KBIPE3 _KBIPE.Bits.KBIPE3 #define KBIPE_KBIPE4 _KBIPE.Bits.KBIPE4 #define KBIPE_KBIPE5 _KBIPE.Bits.KBIPE5 #define KBIPE_KBIPE6 _KBIPE.Bits.KBIPE6 #define KBIPE_KBIPE7 _KBIPE.Bits.KBIPE7 #define KBIPE_KBIPE0_MASK 1 #define KBIPE_KBIPE1_MASK 2 #define KBIPE_KBIPE2_MASK 4 #define KBIPE_KBIPE3_MASK 8 #define KBIPE_KBIPE4_MASK 16 #define KBIPE_KBIPE5_MASK 32 #define KBIPE_KBIPE6_MASK 64 #define KBIPE_KBIPE7_MASK 128 /*** KBIES - KBI Edge Select Register; 0x00000236 ***/ typedef union { byte Byte; struct { byte KBEDG0 :1; /* Keyboard Edge Select Bit 0 */ byte KBEDG1 :1; /* Keyboard Edge Select Bit 1 */ byte KBEDG2 :1; /* Keyboard Edge Select Bit 2 */ byte KBEDG3 :1; /* Keyboard Edge Select Bit 3 */ byte KBEDG4 :1; /* Keyboard Edge Select Bit 4 */ byte KBEDG5 :1; /* Keyboard Edge Select Bit 5 */ byte KBEDG6 :1; /* Keyboard Edge Select Bit 6 */ byte KBEDG7 :1; /* Keyboard Edge Select Bit 7 */ } Bits; } KBIESSTR; extern volatile KBIESSTR _KBIES @0x00000236; #define KBIES _KBIES.Byte #define KBIES_KBEDG0 _KBIES.Bits.KBEDG0 #define KBIES_KBEDG1 _KBIES.Bits.KBEDG1 #define KBIES_KBEDG2 _KBIES.Bits.KBEDG2 #define KBIES_KBEDG3 _KBIES.Bits.KBEDG3 #define KBIES_KBEDG4 _KBIES.Bits.KBEDG4 #define KBIES_KBEDG5 _KBIES.Bits.KBEDG5 #define KBIES_KBEDG6 _KBIES.Bits.KBEDG6 #define KBIES_KBEDG7 _KBIES.Bits.KBEDG7 #define KBIES_KBEDG0_MASK 1 #define KBIES_KBEDG1_MASK 2 #define KBIES_KBEDG2_MASK 4 #define KBIES_KBEDG3_MASK 8 #define KBIES_KBEDG4_MASK 16 #define KBIES_KBEDG5_MASK 32 #define KBIES_KBEDG6_MASK 64 #define KBIES_KBEDG7_MASK 128 /*** ADCCV - Compare Value Low Register; 0x00000237 ***/ typedef union { byte Byte; struct { byte ADCV0 :1; /* Compare Function Value 0 */ byte ADCV1 :1; /* Compare Function Value 1 */ byte ADCV2 :1; /* Compare Function Value 2 */ byte ADCV3 :1; /* Compare Function Value 3 */ byte ADCV4 :1; /* Compare Function Value 4 */ byte ADCV5 :1; /* Compare Function Value 5 */ byte ADCV6 :1; /* Compare Function Value 6 */ byte ADCV7 :1; /* Compare Function Value 7 */ } Bits; } ADCCVSTR; extern volatile ADCCVSTR _ADCCV @0x00000237; #define ADCCV _ADCCV.Byte #define ADCCV_ADCV0 _ADCCV.Bits.ADCV0 #define ADCCV_ADCV1 _ADCCV.Bits.ADCV1 #define ADCCV_ADCV2 _ADCCV.Bits.ADCV2 #define ADCCV_ADCV3 _ADCCV.Bits.ADCV3 #define ADCCV_ADCV4 _ADCCV.Bits.ADCV4 #define ADCCV_ADCV5 _ADCCV.Bits.ADCV5 #define ADCCV_ADCV6 _ADCCV.Bits.ADCV6 #define ADCCV_ADCV7 _ADCCV.Bits.ADCV7 #define ADCCV_ADCV0_MASK 1 #define ADCCV_ADCV1_MASK 2 #define ADCCV_ADCV2_MASK 4 #define ADCCV_ADCV3_MASK 8 #define ADCCV_ADCV4_MASK 16 #define ADCCV_ADCV5_MASK 32 #define ADCCV_ADCV6_MASK 64 #define ADCCV_ADCV7_MASK 128 /*** ADCCFG - Configuration Register; 0x00000238 ***/ typedef union { byte Byte; struct { byte ADICLK0 :1; /* Input Clock Select Bit 0 */ byte ADICLK1 :1; /* Input Clock Select Bit 1 */ byte :1; byte :1; byte ADLSMP :1; /* Long Sample Time Configuration */ byte ADIV0 :1; /* Clock Divide Select Bit 0 */ byte ADIV1 :1; /* Clock Divide Select Bit 1 */ byte :1; } Bits; struct { byte grpADICLK :2; byte :1; byte :1; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADCCFGSTR; extern volatile ADCCFGSTR _ADCCFG @0x00000238; #define ADCCFG _ADCCFG.Byte #define ADCCFG_ADICLK0 _ADCCFG.Bits.ADICLK0 #define ADCCFG_ADICLK1 _ADCCFG.Bits.ADICLK1 #define ADCCFG_ADLSMP _ADCCFG.Bits.ADLSMP #define ADCCFG_ADIV0 _ADCCFG.Bits.ADIV0 #define ADCCFG_ADIV1 _ADCCFG.Bits.ADIV1 #define ADCCFG_ADICLK _ADCCFG.MergedBits.grpADICLK #define ADCCFG_ADIV _ADCCFG.MergedBits.grpADIV #define ADCCFG_ADICLK0_MASK 1 #define ADCCFG_ADICLK1_MASK 2 #define ADCCFG_ADLSMP_MASK 16 #define ADCCFG_ADIV0_MASK 32 #define ADCCFG_ADIV1_MASK 64 #define ADCCFG_ADICLK_MASK 3 #define ADCCFG_ADICLK_BITNUM 0 #define ADCCFG_ADIV_MASK 96 #define ADCCFG_ADIV_BITNUM 5 /*** APCTL1 - Pin Control 1 Register; 0x00000239 ***/ typedef union { byte Byte; struct { byte ADPC0 :1; /* ADC Pin Control 0 - ADPC0 is used to control the pin associated with channel AD0 */ byte ADPC1 :1; /* ADC Pin Control 1 - ADPC1 is used to control the pin associated with channel AD1 */ byte ADPC2 :1; /* ADC Pin Control 2 - ADPC2 is used to control the pin associated with channel AD2 */ byte ADPC3 :1; /* ADC Pin Control 3 - ADPC3 is used to control the pin associated with channel AD3 */ byte ADPC4 :1; /* ADC Pin Control 4 - ADPC4 is used to control the pin associated with channel AD4 */ byte ADPC5 :1; /* ADC Pin Control 5 - ADPC5 is used to control the pin associated with channel AD5 */ byte ADPC6 :1; /* ADC Pin Control 6 - ADPC6 is used to control the pin associated with channel AD6 */ byte ADPC7 :1; /* ADC Pin Control 7 - ADPC7 is used to control the pin associated with channel AD7 */ } Bits; } APCTL1STR; extern volatile APCTL1STR _APCTL1 @0x00000239; #define APCTL1 _APCTL1.Byte #define APCTL1_ADPC0 _APCTL1.Bits.ADPC0 #define APCTL1_ADPC1 _APCTL1.Bits.ADPC1 #define APCTL1_ADPC2 _APCTL1.Bits.ADPC2 #define APCTL1_ADPC3 _APCTL1.Bits.ADPC3 #define APCTL1_ADPC4 _APCTL1.Bits.ADPC4 #define APCTL1_ADPC5 _APCTL1.Bits.ADPC5 #define APCTL1_ADPC6 _APCTL1.Bits.ADPC6 #define APCTL1_ADPC7 _APCTL1.Bits.ADPC7 #define APCTL1_ADPC0_MASK 1 #define APCTL1_ADPC1_MASK 2 #define APCTL1_ADPC2_MASK 4 #define APCTL1_ADPC3_MASK 8 #define APCTL1_ADPC4_MASK 16 #define APCTL1_ADPC5_MASK 32 #define APCTL1_ADPC6_MASK 64 #define APCTL1_ADPC7_MASK 128 /*** APCTL2 - Pin Control 2 Register; 0x0000023A ***/ typedef union { byte Byte; struct { byte ADPC8 :1; /* ADC Pin Control 8 - ADPC8 is used to control the pin associated with channel AD8 */ byte ADPC9 :1; /* ADC Pin Control 9 - ADPC9 is used to control the pin associated with channel AD9 */ byte ADPC10 :1; /* ADC Pin Control 10 - ADPC10 is used to control the pin associated with channel AD10 */ byte ADPC11 :1; /* ADC Pin Control 11 - ADPC11 is used to control the pin associated with channel AD11 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADPC_8 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } APCTL2STR; extern volatile APCTL2STR _APCTL2 @0x0000023A; #define APCTL2 _APCTL2.Byte #define APCTL2_ADPC8 _APCTL2.Bits.ADPC8 #define APCTL2_ADPC9 _APCTL2.Bits.ADPC9 #define APCTL2_ADPC10 _APCTL2.Bits.ADPC10 #define APCTL2_ADPC11 _APCTL2.Bits.ADPC11 #define APCTL2_ADPC_8 _APCTL2.MergedBits.grpADPC_8 #define APCTL2_ADPC APCTL2_ADPC_8 #define APCTL2_ADPC8_MASK 1 #define APCTL2_ADPC9_MASK 2 #define APCTL2_ADPC10_MASK 4 #define APCTL2_ADPC11_MASK 8 #define APCTL2_ADPC_8_MASK 15 #define APCTL2_ADPC_8_BITNUM 0 /*** ICSC1 - ICS Control Register 1; 0x0000023C ***/ typedef union { byte Byte; struct { byte IREFSTEN :1; /* Internal Reference Stop Enable */ byte IRCLKEN :1; /* Internal Reference Clock Enable */ byte IREFS :1; /* Internal Reference Select */ byte RDIV :3; /* Reference Divider */ byte CLKS :2; /* Clock Source Select */ } Bits; } ICSC1STR; extern volatile ICSC1STR _ICSC1 @0x0000023C; #define ICSC1 _ICSC1.Byte #define ICSC1_IREFSTEN _ICSC1.Bits.IREFSTEN #define ICSC1_IRCLKEN _ICSC1.Bits.IRCLKEN #define ICSC1_IREFS _ICSC1.Bits.IREFS #define ICSC1_RDIV _ICSC1.Bits.RDIV #define ICSC1_CLKS _ICSC1.Bits.CLKS #define ICSC1_IREFSTEN_MASK 1 #define ICSC1_IRCLKEN_MASK 2 #define ICSC1_IREFS_MASK 4 #define ICSC1_RDIV_MASK 56 #define ICSC1_RDIV_BITNUM 3 #define ICSC1_CLKS_MASK 192 #define ICSC1_CLKS_BITNUM 6 /*** ICSC2 - ICS Control Register 2; 0x0000023D ***/ typedef union { byte Byte; struct { byte EREFSTEN :1; /* External Reference Stop Enable */ byte ERCLKEN :1; /* External Reference Enable */ byte EREFS :1; /* External Reference Select */ byte LP :1; /* Low Power Select */ byte HGO :1; /* High Gain Oscillator Select */ byte RANGE :1; /* Frequency Range Select */ byte BDIV :2; /* Bus Frequency Divider */ } Bits; } ICSC2STR; extern volatile ICSC2STR _ICSC2 @0x0000023D; #define ICSC2 _ICSC2.Byte #define ICSC2_EREFSTEN _ICSC2.Bits.EREFSTEN #define ICSC2_ERCLKEN _ICSC2.Bits.ERCLKEN #define ICSC2_EREFS _ICSC2.Bits.EREFS #define ICSC2_LP _ICSC2.Bits.LP #define ICSC2_HGO _ICSC2.Bits.HGO #define ICSC2_RANGE _ICSC2.Bits.RANGE #define ICSC2_BDIV _ICSC2.Bits.BDIV #define ICSC2_EREFSTEN_MASK 1 #define ICSC2_ERCLKEN_MASK 2 #define ICSC2_EREFS_MASK 4 #define ICSC2_LP_MASK 8 #define ICSC2_HGO_MASK 16 #define ICSC2_RANGE_MASK 32 #define ICSC2_BDIV_MASK 192 #define ICSC2_BDIV_BITNUM 6 /*** ICSTRM - ICS Trim Register; 0x0000023E ***/ typedef union { byte Byte; struct { byte TRIM :8; /* ICS Trim Setting */ } Bits; } ICSTRMSTR; extern volatile ICSTRMSTR _ICSTRM @0x0000023E; #define ICSTRM _ICSTRM.Byte #define ICSTRM_TRIM _ICSTRM.Bits.TRIM #define ICSTRM_TRIM_MASK 255 #define ICSTRM_TRIM_BITNUM 0 /*** ICSSC - ICS Status and Control Register; 0x0000023F ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte OSCINIT :1; /* OSC Initialization */ byte CLKST :2; /* Clock Mode Status */ byte :1; byte :1; byte :1; byte :1; } Bits; } ICSSCSTR; extern volatile ICSSCSTR _ICSSC @0x0000023F; #define ICSSC _ICSSC.Byte #define ICSSC_FTRIM _ICSSC.Bits.FTRIM #define ICSSC_OSCINIT _ICSSC.Bits.OSCINIT #define ICSSC_CLKST _ICSSC.Bits.CLKST #define ICSSC_FTRIM_MASK 1 #define ICSSC_OSCINIT_MASK 2 #define ICSSC_CLKST_MASK 12 #define ICSSC_CLKST_BITNUM 2 /*** NVICSTRM - Nonvolatile ICS Trim Register; 0x00003FFA ***/ typedef union { byte Byte; struct { byte TRIM :8; /* ICS Trim Setting */ } Bits; } NVICSTRMSTR; /* Tip for register initialization in the user code: const byte NVICSTRM_INIT @0x00003FFA = ; */ #define _NVICSTRM (*(const NVICSTRMSTR *__paged)CONVERT_TO_PAGED(0x00003FFA)) #define NVICSTRM _NVICSTRM.Byte #define NVICSTRM_TRIM _NVICSTRM.Bits.TRIM #define NVICSTRM_TRIM_MASK 255 #define NVICSTRM_TRIM_BITNUM 0 /*** NVFTRIM - Nonvolatile ICS Fine Trim; 0x00003FFB ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } NVFTRIMSTR; /* Tip for register initialization in the user code: const byte NVFTRIM_INIT @0x00003FFB = ; */ #define _NVFTRIM (*(const NVFTRIMSTR *__paged)CONVERT_TO_PAGED(0x00003FFB)) #define NVFTRIM _NVFTRIM.Byte #define NVFTRIM_FTRIM _NVFTRIM.Bits.FTRIM #define NVFTRIM_FTRIM_MASK 1 /*** NVOPT - Nonvolatile Flash Options Register; 0x00003FFC ***/ typedef union { byte Byte; struct { byte SECD :1; /* Security State Code */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } NVOPTSTR; /* Tip for register initialization in the user code: const byte NVOPT_INIT @0x00003FFC = ; */ #define _NVOPT (*(const NVOPTSTR *__paged)CONVERT_TO_PAGED(0x00003FFC)) #define NVOPT _NVOPT.Byte #define NVOPT_SECD _NVOPT.Bits.SECD #define NVOPT_SECD_MASK 1 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ #endif