/* Based on CPU DB MC9RS08LE4_28, version 3.00.012 (RegistersPrg V2.28) */ /* ** ################################################################### ** Filename : mc9rs08le4.h ** Processor : MC9RS08LE4CPC ** FileFormat: V2.28 ** DataSheet : MC9RS08LE4RM Rev. 1 9/2008 ** Compiler : CodeWarrior compiler ** Date/Time : 27.5.2009, 10:23 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - 25.08.2008, V3.00.0: ** - Renamed register PMCSC -> SPMSC1. ** - Removed registers LCDRVC, LCDPEN3, LCDBPEN3. ** - Removed bits LCDSUPPLY[BBYPASS,HREFSEL,CPSEL], ICSSC[IREFST]. ** - REASON: Bug-fix (#6457 in Issue Manager). ** ** File-Format-Revisions: ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matchs with anouther bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC9RS08LE4_H #define _MC9RS08LE4_H #include /* Types definition */ typedef unsigned char byte; typedef unsigned int word; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() (void)(SRS = 0x00) #endif #endif /* __RESET_WATCHDOG */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** registers I/O map ****************/ /*** ADCSC1 - Status and Control Register 1; 0x00000010 ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* Input Channel Select Bit 0 */ byte ADCH1 :1; /* Input Channel Select Bit 1 */ byte ADCH2 :1; /* Input Channel Select Bit 2 */ byte ADCH3 :1; /* Input Channel Select Bit 3 */ byte ADCH4 :1; /* Input Channel Select Bit 4 */ byte ADCO :1; /* Continuous Conversion Enable - ADCO is used to enable continuous conversions */ byte AIEN :1; /* Interrupt Enable - AIEN is used to enable conversion complete interrupts. When COCO becomes set while AIEN is high, an interrupt is asserted */ byte COCO :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADCSC1STR; extern volatile ADCSC1STR _ADCSC1 @0x00000010; #define ADCSC1 _ADCSC1.Byte #define ADCSC1_ADCH0 _ADCSC1.Bits.ADCH0 #define ADCSC1_ADCH1 _ADCSC1.Bits.ADCH1 #define ADCSC1_ADCH2 _ADCSC1.Bits.ADCH2 #define ADCSC1_ADCH3 _ADCSC1.Bits.ADCH3 #define ADCSC1_ADCH4 _ADCSC1.Bits.ADCH4 #define ADCSC1_ADCO _ADCSC1.Bits.ADCO #define ADCSC1_AIEN _ADCSC1.Bits.AIEN #define ADCSC1_COCO _ADCSC1.Bits.COCO #define ADCSC1_ADCH _ADCSC1.MergedBits.grpADCH #define ADCSC1_ADCH0_MASK 1 #define ADCSC1_ADCH1_MASK 2 #define ADCSC1_ADCH2_MASK 4 #define ADCSC1_ADCH3_MASK 8 #define ADCSC1_ADCH4_MASK 16 #define ADCSC1_ADCO_MASK 32 #define ADCSC1_AIEN_MASK 64 #define ADCSC1_COCO_MASK 128 #define ADCSC1_ADCH_MASK 31 #define ADCSC1_ADCH_BITNUM 0 /*** ADCSC2 - Status and Control Register 2; 0x00000011 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte ACFGT :1; /* Compare Function Greater Than Enable */ byte ACFE :1; /* Compare Function Enable - ACFE is used to enable the compare function */ byte ADTRG :1; /* Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion */ byte ADACT :1; /* Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted */ } Bits; } ADCSC2STR; extern volatile ADCSC2STR _ADCSC2 @0x00000011; #define ADCSC2 _ADCSC2.Byte #define ADCSC2_ACFGT _ADCSC2.Bits.ACFGT #define ADCSC2_ACFE _ADCSC2.Bits.ACFE #define ADCSC2_ADTRG _ADCSC2.Bits.ADTRG #define ADCSC2_ADACT _ADCSC2.Bits.ADACT #define ADCSC2_ACFGT_MASK 16 #define ADCSC2_ACFE_MASK 32 #define ADCSC2_ADTRG_MASK 64 #define ADCSC2_ADACT_MASK 128 /*** ADCR - Data Result Register; 0x00000012 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADCRH - Data Result High Register; 0x00000012 ***/ union { byte Byte; struct { byte ADR8 :1; /* ADC Result Data Bit 8 */ byte ADR9 :1; /* ADC Result Data Bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADR_8 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADCRHSTR; #define ADCRH _ADCR.Overlap_STR.ADCRHSTR.Byte #define ADCRH_ADR8 _ADCR.Overlap_STR.ADCRHSTR.Bits.ADR8 #define ADCRH_ADR9 _ADCR.Overlap_STR.ADCRHSTR.Bits.ADR9 #define ADCRH_ADR_8 _ADCR.Overlap_STR.ADCRHSTR.MergedBits.grpADR_8 #define ADCRH_ADR ADCRH_ADR_8 #define ADCRH_ADR8_MASK 1 #define ADCRH_ADR9_MASK 2 #define ADCRH_ADR_8_MASK 3 #define ADCRH_ADR_8_BITNUM 0 /*** ADCRL - Data Result Low Register; 0x00000013 ***/ union { byte Byte; struct { byte ADR0 :1; /* ADC Result Data Bit 0 */ byte ADR1 :1; /* ADC Result Data Bit 1 */ byte ADR2 :1; /* ADC Result Data Bit 2 */ byte ADR3 :1; /* ADC Result Data Bit 3 */ byte ADR4 :1; /* ADC Result Data Bit 4 */ byte ADR5 :1; /* ADC Result Data Bit 5 */ byte ADR6 :1; /* ADC Result Data Bit 6 */ byte ADR7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADCRLSTR; #define ADCRL _ADCR.Overlap_STR.ADCRLSTR.Byte #define ADCRL_ADR0 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR0 #define ADCRL_ADR1 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR1 #define ADCRL_ADR2 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR2 #define ADCRL_ADR3 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR3 #define ADCRL_ADR4 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR4 #define ADCRL_ADR5 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR5 #define ADCRL_ADR6 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR6 #define ADCRL_ADR7 _ADCR.Overlap_STR.ADCRLSTR.Bits.ADR7 #define ADCRL_ADR0_MASK 1 #define ADCRL_ADR1_MASK 2 #define ADCRL_ADR2_MASK 4 #define ADCRL_ADR3_MASK 8 #define ADCRL_ADR4_MASK 16 #define ADCRL_ADR5_MASK 32 #define ADCRL_ADR6_MASK 64 #define ADCRL_ADR7_MASK 128 } Overlap_STR; } ADCRSTR; extern volatile ADCRSTR _ADCR @0x00000012; #define ADCR _ADCR.Word /*** ADCCV - Compare Value Register; 0x00000014 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADCCVH - Compare Value High Register; 0x00000014 ***/ union { byte Byte; struct { byte ADCV8 :1; /* Compare Function Value 8 */ byte ADCV9 :1; /* Compare Function Value 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADCV_8 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADCCVHSTR; #define ADCCVH _ADCCV.Overlap_STR.ADCCVHSTR.Byte #define ADCCVH_ADCV8 _ADCCV.Overlap_STR.ADCCVHSTR.Bits.ADCV8 #define ADCCVH_ADCV9 _ADCCV.Overlap_STR.ADCCVHSTR.Bits.ADCV9 #define ADCCVH_ADCV_8 _ADCCV.Overlap_STR.ADCCVHSTR.MergedBits.grpADCV_8 #define ADCCVH_ADCV ADCCVH_ADCV_8 #define ADCCVH_ADCV8_MASK 1 #define ADCCVH_ADCV9_MASK 2 #define ADCCVH_ADCV_8_MASK 3 #define ADCCVH_ADCV_8_BITNUM 0 /*** ADCCVL - Compare Value Low Register; 0x00000015 ***/ union { byte Byte; struct { byte ADCV0 :1; /* Compare Function Value 0 */ byte ADCV1 :1; /* Compare Function Value 1 */ byte ADCV2 :1; /* Compare Function Value 2 */ byte ADCV3 :1; /* Compare Function Value 3 */ byte ADCV4 :1; /* Compare Function Value 4 */ byte ADCV5 :1; /* Compare Function Value 5 */ byte ADCV6 :1; /* Compare Function Value 6 */ byte ADCV7 :1; /* Compare Function Value 7 */ } Bits; } ADCCVLSTR; #define ADCCVL _ADCCV.Overlap_STR.ADCCVLSTR.Byte #define ADCCVL_ADCV0 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV0 #define ADCCVL_ADCV1 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV1 #define ADCCVL_ADCV2 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV2 #define ADCCVL_ADCV3 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV3 #define ADCCVL_ADCV4 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV4 #define ADCCVL_ADCV5 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV5 #define ADCCVL_ADCV6 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV6 #define ADCCVL_ADCV7 _ADCCV.Overlap_STR.ADCCVLSTR.Bits.ADCV7 #define ADCCVL_ADCV0_MASK 1 #define ADCCVL_ADCV1_MASK 2 #define ADCCVL_ADCV2_MASK 4 #define ADCCVL_ADCV3_MASK 8 #define ADCCVL_ADCV4_MASK 16 #define ADCCVL_ADCV5_MASK 32 #define ADCCVL_ADCV6_MASK 64 #define ADCCVL_ADCV7_MASK 128 } Overlap_STR; } ADCCVSTR; extern volatile ADCCVSTR _ADCCV @0x00000014; #define ADCCV _ADCCV.Word /*** ADCCFG - Configuration Register; 0x00000016 ***/ typedef union { byte Byte; struct { byte ADICLK0 :1; /* Input Clock Select Bit 0 */ byte ADICLK1 :1; /* Input Clock Select Bit 1 */ byte MODE0 :1; /* Conversion Mode Selection Bit 0 */ byte MODE1 :1; /* Conversion Mode Selection Bit 1 */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte ADIV0 :1; /* Clock Divide Select Bit 0 */ byte ADIV1 :1; /* Clock Divide Select Bit 1 */ byte ADLPC :1; /* Low Power Configuration */ } Bits; struct { byte grpADICLK :2; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADCCFGSTR; extern volatile ADCCFGSTR _ADCCFG @0x00000016; #define ADCCFG _ADCCFG.Byte #define ADCCFG_ADICLK0 _ADCCFG.Bits.ADICLK0 #define ADCCFG_ADICLK1 _ADCCFG.Bits.ADICLK1 #define ADCCFG_MODE0 _ADCCFG.Bits.MODE0 #define ADCCFG_MODE1 _ADCCFG.Bits.MODE1 #define ADCCFG_ADLSMP _ADCCFG.Bits.ADLSMP #define ADCCFG_ADIV0 _ADCCFG.Bits.ADIV0 #define ADCCFG_ADIV1 _ADCCFG.Bits.ADIV1 #define ADCCFG_ADLPC _ADCCFG.Bits.ADLPC #define ADCCFG_ADICLK _ADCCFG.MergedBits.grpADICLK #define ADCCFG_MODE _ADCCFG.MergedBits.grpMODE #define ADCCFG_ADIV _ADCCFG.MergedBits.grpADIV #define ADCCFG_ADICLK0_MASK 1 #define ADCCFG_ADICLK1_MASK 2 #define ADCCFG_MODE0_MASK 4 #define ADCCFG_MODE1_MASK 8 #define ADCCFG_ADLSMP_MASK 16 #define ADCCFG_ADIV0_MASK 32 #define ADCCFG_ADIV1_MASK 64 #define ADCCFG_ADLPC_MASK 128 #define ADCCFG_ADICLK_MASK 3 #define ADCCFG_ADICLK_BITNUM 0 #define ADCCFG_MODE_MASK 12 #define ADCCFG_MODE_BITNUM 2 #define ADCCFG_ADIV_MASK 96 #define ADCCFG_ADIV_BITNUM 5 /*** APCTL1 - Pin Control 1 Register; 0x00000017 ***/ typedef union { byte Byte; struct { byte ADPC0 :1; /* ADC Pin Control 0 - ADPC0 is used to control the pin associated with channel AD0 */ byte ADPC1 :1; /* ADC Pin Control 1 - ADPC1 is used to control the pin associated with channel AD1 */ byte ADPC2 :1; /* ADC Pin Control 2 - ADPC2 is used to control the pin associated with channel AD2 */ byte ADPC3 :1; /* ADC Pin Control 3 - ADPC3 is used to control the pin associated with channel AD3 */ byte ADPC4 :1; /* ADC Pin Control 4 - ADPC4 is used to control the pin associated with channel AD4 */ byte ADPC5 :1; /* ADC Pin Control 5 - ADPC5 is used to control the pin associated with channel AD5 */ byte ADPC6 :1; /* ADC Pin Control 6 - ADPC6 is used to control the pin associated with channel AD6 */ byte ADPC7 :1; /* ADC Pin Control 7 - ADPC7 is used to control the pin associated with channel AD7 */ } Bits; } APCTL1STR; extern volatile APCTL1STR _APCTL1 @0x00000017; #define APCTL1 _APCTL1.Byte #define APCTL1_ADPC0 _APCTL1.Bits.ADPC0 #define APCTL1_ADPC1 _APCTL1.Bits.ADPC1 #define APCTL1_ADPC2 _APCTL1.Bits.ADPC2 #define APCTL1_ADPC3 _APCTL1.Bits.ADPC3 #define APCTL1_ADPC4 _APCTL1.Bits.ADPC4 #define APCTL1_ADPC5 _APCTL1.Bits.ADPC5 #define APCTL1_ADPC6 _APCTL1.Bits.ADPC6 #define APCTL1_ADPC7 _APCTL1.Bits.ADPC7 #define APCTL1_ADPC0_MASK 1 #define APCTL1_ADPC1_MASK 2 #define APCTL1_ADPC2_MASK 4 #define APCTL1_ADPC3_MASK 8 #define APCTL1_ADPC4_MASK 16 #define APCTL1_ADPC5_MASK 32 #define APCTL1_ADPC6_MASK 64 #define APCTL1_ADPC7_MASK 128 /*** SRS - System Reset Status Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte :1; byte LVD :1; /* Low Voltage Detect */ byte :1; byte ILAD :1; /* Illegal Address */ byte ILOP :1; /* Illegal Opcode */ byte COP :1; /* Computer Operating Properly (COP) Watchdog */ byte PIN :1; /* External Reset Pin */ byte POR :1; /* Power-On Reset */ } Bits; } SRSSTR; extern volatile SRSSTR _SRS @0x00000018; #define SRS _SRS.Byte #define SRS_LVD _SRS.Bits.LVD #define SRS_ILAD _SRS.Bits.ILAD #define SRS_ILOP _SRS.Bits.ILOP #define SRS_COP _SRS.Bits.COP #define SRS_PIN _SRS.Bits.PIN #define SRS_POR _SRS.Bits.POR #define SRS_LVD_MASK 2 #define SRS_ILAD_MASK 8 #define SRS_ILOP_MASK 16 #define SRS_COP_MASK 32 #define SRS_PIN_MASK 64 #define SRS_POR_MASK 128 /*** SOPT - System Options Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte RSTPE :1; /* RESET Pin Enable */ byte BKGDPE :1; /* Background Debug Mode Pin Enable */ byte :1; byte :1; byte :1; byte STOPE :1; /* Stop Mode Enable */ byte COPT :1; /* COP Watchdog Timeout */ byte COPE :1; /* COP Watchdog Enable */ } Bits; } SOPTSTR; extern volatile SOPTSTR _SOPT @0x00000019; #define SOPT _SOPT.Byte #define SOPT_RSTPE _SOPT.Bits.RSTPE #define SOPT_BKGDPE _SOPT.Bits.BKGDPE #define SOPT_STOPE _SOPT.Bits.STOPE #define SOPT_COPT _SOPT.Bits.COPT #define SOPT_COPE _SOPT.Bits.COPE #define SOPT_RSTPE_MASK 1 #define SOPT_BKGDPE_MASK 2 #define SOPT_STOPE_MASK 32 #define SOPT_COPT_MASK 64 #define SOPT_COPE_MASK 128 /*** SIP1 - System Interrupt Pending Register 1; 0x0000001A ***/ typedef union { byte Byte; struct { byte RTI :1; /* Real-Time Interrupt Pending */ byte LCD :1; /* LCD Interrupt Pending */ byte KBI :1; /* KBI Interrupt Pending */ byte ADC :1; /* ADC Interrupt Pending */ byte SCIE :1; /* SCI Error Interrupt Pending */ byte SCIR :1; /* SCI Receive Interrupt Pending */ byte SCIT :1; /* SCI Transmit Interrupt Pending */ byte LVD :1; /* LVD Interrupt Pending */ } Bits; } SIP1STR; extern volatile SIP1STR _SIP1 @0x0000001A; #define SIP1 _SIP1.Byte #define SIP1_RTI _SIP1.Bits.RTI #define SIP1_LCD _SIP1.Bits.LCD #define SIP1_KBI _SIP1.Bits.KBI #define SIP1_ADC _SIP1.Bits.ADC #define SIP1_SCIE _SIP1.Bits.SCIE #define SIP1_SCIR _SIP1.Bits.SCIR #define SIP1_SCIT _SIP1.Bits.SCIT #define SIP1_LVD _SIP1.Bits.LVD #define SIP1_RTI_MASK 1 #define SIP1_LCD_MASK 2 #define SIP1_KBI_MASK 4 #define SIP1_ADC_MASK 8 #define SIP1_SCIE_MASK 16 #define SIP1_SCIR_MASK 32 #define SIP1_SCIT_MASK 64 #define SIP1_LVD_MASK 128 /*** SIP2 - System Interrupt Pending Register 2; 0x0000001B ***/ typedef union { byte Byte; struct { byte TPM1 :1; /* TPM1 Interrupt Pending */ byte TPM1CH0 :1; /* TPM1 Channel 0 Interrupt Pending */ byte TPM1CH1 :1; /* TPM1 Channel 1 Interrupt Pending */ byte :1; byte TPM2 :1; /* TPM2 Interrupt Pending */ byte TPM2CH0 :1; /* TPM2 Channel 0 Interrupt Pending */ byte TPM2CH1 :1; /* TPM2 Channel 1 Interrupt Pending */ byte :1; } Bits; struct { byte grpTPM_1 :1; byte grpTPM1CH :2; byte :1; byte grpTPM_2 :1; byte grpTPM2CH :2; byte :1; } MergedBits; } SIP2STR; extern volatile SIP2STR _SIP2 @0x0000001B; #define SIP2 _SIP2.Byte #define SIP2_TPM1 _SIP2.Bits.TPM1 #define SIP2_TPM1CH0 _SIP2.Bits.TPM1CH0 #define SIP2_TPM1CH1 _SIP2.Bits.TPM1CH1 #define SIP2_TPM2 _SIP2.Bits.TPM2 #define SIP2_TPM2CH0 _SIP2.Bits.TPM2CH0 #define SIP2_TPM2CH1 _SIP2.Bits.TPM2CH1 #define SIP2_TPM1CH _SIP2.MergedBits.grpTPM1CH #define SIP2_TPM2CH _SIP2.MergedBits.grpTPM2CH #define SIP2_TPM1_MASK 1 #define SIP2_TPM1CH0_MASK 2 #define SIP2_TPM1CH1_MASK 4 #define SIP2_TPM2_MASK 16 #define SIP2_TPM2CH0_MASK 32 #define SIP2_TPM2CH1_MASK 64 #define SIP2_TPM1CH_MASK 6 #define SIP2_TPM1CH_BITNUM 1 #define SIP2_TPM2CH_MASK 96 #define SIP2_TPM2CH_BITNUM 5 /*** KBISC - KBI Status and Control Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte KBMOD :1; /* Keyboard Detection Mode */ byte KBIE :1; /* Keyboard Interrupt Enable */ byte KBACK :1; /* Keyboard Interrupt Acknowledge */ byte KBF :1; /* Keyboard Interrupt Flag */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBISCSTR; extern volatile KBISCSTR _KBISC @0x0000001C; #define KBISC _KBISC.Byte #define KBISC_KBMOD _KBISC.Bits.KBMOD #define KBISC_KBIE _KBISC.Bits.KBIE #define KBISC_KBACK _KBISC.Bits.KBACK #define KBISC_KBF _KBISC.Bits.KBF #define KBISC_KBMOD_MASK 1 #define KBISC_KBIE_MASK 2 #define KBISC_KBACK_MASK 4 #define KBISC_KBF_MASK 8 /*** KBIPE - KBI Pin Enable Register; 0x0000001D ***/ typedef union { byte Byte; struct { byte KBIPE0 :1; /* Keyboard Pin Enable for KBI Port Bit 0 */ byte KBIPE1 :1; /* Keyboard Pin Enable for KBI Port Bit 1 */ byte KBIPE2 :1; /* Keyboard Pin Enable for KBI Port Bit 2 */ byte KBIPE3 :1; /* Keyboard Pin Enable for KBI Port Bit 3 */ byte KBIPE4 :1; /* Keyboard Pin Enable for KBI Port Bit 4 */ byte KBIPE5 :1; /* Keyboard Pin Enable for KBI Port Bit 5 */ byte KBIPE6 :1; /* Keyboard Pin Enable for KBI Port Bit 6 */ byte KBIPE7 :1; /* Keyboard Pin Enable for KBI Port Bit 7 */ } Bits; } KBIPESTR; extern volatile KBIPESTR _KBIPE @0x0000001D; #define KBIPE _KBIPE.Byte #define KBIPE_KBIPE0 _KBIPE.Bits.KBIPE0 #define KBIPE_KBIPE1 _KBIPE.Bits.KBIPE1 #define KBIPE_KBIPE2 _KBIPE.Bits.KBIPE2 #define KBIPE_KBIPE3 _KBIPE.Bits.KBIPE3 #define KBIPE_KBIPE4 _KBIPE.Bits.KBIPE4 #define KBIPE_KBIPE5 _KBIPE.Bits.KBIPE5 #define KBIPE_KBIPE6 _KBIPE.Bits.KBIPE6 #define KBIPE_KBIPE7 _KBIPE.Bits.KBIPE7 #define KBIPE_KBIPE0_MASK 1 #define KBIPE_KBIPE1_MASK 2 #define KBIPE_KBIPE2_MASK 4 #define KBIPE_KBIPE3_MASK 8 #define KBIPE_KBIPE4_MASK 16 #define KBIPE_KBIPE5_MASK 32 #define KBIPE_KBIPE6_MASK 64 #define KBIPE_KBIPE7_MASK 128 /*** KBIES - KBI Edge Select Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte KBEDG0 :1; /* Keyboard Edge Select Bit 0 */ byte KBEDG1 :1; /* Keyboard Edge Select Bit 1 */ byte KBEDG2 :1; /* Keyboard Edge Select Bit 2 */ byte KBEDG3 :1; /* Keyboard Edge Select Bit 3 */ byte KBEDG4 :1; /* Keyboard Edge Select Bit 4 */ byte KBEDG5 :1; /* Keyboard Edge Select Bit 5 */ byte KBEDG6 :1; /* Keyboard Edge Select Bit 6 */ byte KBEDG7 :1; /* Keyboard Edge Select Bit 7 */ } Bits; } KBIESSTR; extern volatile KBIESSTR _KBIES @0x0000001E; #define KBIES _KBIES.Byte #define KBIES_KBEDG0 _KBIES.Bits.KBEDG0 #define KBIES_KBEDG1 _KBIES.Bits.KBEDG1 #define KBIES_KBEDG2 _KBIES.Bits.KBEDG2 #define KBIES_KBEDG3 _KBIES.Bits.KBEDG3 #define KBIES_KBEDG4 _KBIES.Bits.KBEDG4 #define KBIES_KBEDG5 _KBIES.Bits.KBEDG5 #define KBIES_KBEDG6 _KBIES.Bits.KBEDG6 #define KBIES_KBEDG7 _KBIES.Bits.KBEDG7 #define KBIES_KBEDG0_MASK 1 #define KBIES_KBEDG1_MASK 2 #define KBIES_KBEDG2_MASK 4 #define KBIES_KBEDG3_MASK 8 #define KBIES_KBEDG4_MASK 16 #define KBIES_KBEDG5_MASK 32 #define KBIES_KBEDG6_MASK 64 #define KBIES_KBEDG7_MASK 128 /*** PAGESEL - Page Select Register; 0x0000001F ***/ typedef union { byte Byte; struct { byte AD6 :1; /* Page Selector Bit 6 */ byte AD7 :1; /* Page Selector Bit 7 */ byte AD8 :1; /* Page Selector Bit 8 */ byte AD9 :1; /* Page Selector Bit 9 */ byte AD10 :1; /* Page Selector Bit 10 */ byte AD11 :1; /* Page Selector Bit 11 */ byte AD12 :1; /* Page Selector Bit 12 */ byte AD13 :1; /* Page Selector Bit 13 */ } Bits; } PAGESELSTR; extern volatile PAGESELSTR _PAGESEL @0x0000001F; #define PAGESEL _PAGESEL.Byte #define PAGESEL_AD6 _PAGESEL.Bits.AD6 #define PAGESEL_AD7 _PAGESEL.Bits.AD7 #define PAGESEL_AD8 _PAGESEL.Bits.AD8 #define PAGESEL_AD9 _PAGESEL.Bits.AD9 #define PAGESEL_AD10 _PAGESEL.Bits.AD10 #define PAGESEL_AD11 _PAGESEL.Bits.AD11 #define PAGESEL_AD12 _PAGESEL.Bits.AD12 #define PAGESEL_AD13 _PAGESEL.Bits.AD13 #define PAGESEL_AD6_MASK 1 #define PAGESEL_AD7_MASK 2 #define PAGESEL_AD8_MASK 4 #define PAGESEL_AD9_MASK 8 #define PAGESEL_AD10_MASK 16 #define PAGESEL_AD11_MASK 32 #define PAGESEL_AD12_MASK 64 #define PAGESEL_AD13_MASK 128 /*** LCDWF0 - LCD Waveform Register 0; 0x00000020 ***/ typedef union { byte Byte; struct { byte BPALCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF0STR; extern volatile LCDWF0STR _LCDWF0 @0x00000020; #define LCDWF0 _LCDWF0.Byte #define LCDWF0_BPALCD0 _LCDWF0.Bits.BPALCD0 #define LCDWF0_BPBLCD0 _LCDWF0.Bits.BPBLCD0 #define LCDWF0_BPCLCD0 _LCDWF0.Bits.BPCLCD0 #define LCDWF0_BPDLCD0 _LCDWF0.Bits.BPDLCD0 #define LCDWF0_BPELCD0 _LCDWF0.Bits.BPELCD0 #define LCDWF0_BPFLCD0 _LCDWF0.Bits.BPFLCD0 #define LCDWF0_BPGLCD0 _LCDWF0.Bits.BPGLCD0 #define LCDWF0_BPHLCD0 _LCDWF0.Bits.BPHLCD0 /* LCDWF_ARR: Access 22 LCDWFx registers in an array */ #define LCDWF_ARR ((volatile byte *__paged) &LCDWF0) #define LCDWF0_BPALCD0_MASK 1 #define LCDWF0_BPBLCD0_MASK 2 #define LCDWF0_BPCLCD0_MASK 4 #define LCDWF0_BPDLCD0_MASK 8 #define LCDWF0_BPELCD0_MASK 16 #define LCDWF0_BPFLCD0_MASK 32 #define LCDWF0_BPGLCD0_MASK 64 #define LCDWF0_BPHLCD0_MASK 128 /*** LCDWF1 - LCD Waveform Register 1; 0x00000021 ***/ typedef union { byte Byte; struct { byte BPALCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF1STR; extern volatile LCDWF1STR _LCDWF1 @0x00000021; #define LCDWF1 _LCDWF1.Byte #define LCDWF1_BPALCD1 _LCDWF1.Bits.BPALCD1 #define LCDWF1_BPBLCD1 _LCDWF1.Bits.BPBLCD1 #define LCDWF1_BPCLCD1 _LCDWF1.Bits.BPCLCD1 #define LCDWF1_BPDLCD1 _LCDWF1.Bits.BPDLCD1 #define LCDWF1_BPELCD1 _LCDWF1.Bits.BPELCD1 #define LCDWF1_BPFLCD1 _LCDWF1.Bits.BPFLCD1 #define LCDWF1_BPGLCD1 _LCDWF1.Bits.BPGLCD1 #define LCDWF1_BPHLCD1 _LCDWF1.Bits.BPHLCD1 #define LCDWF1_BPALCD1_MASK 1 #define LCDWF1_BPBLCD1_MASK 2 #define LCDWF1_BPCLCD1_MASK 4 #define LCDWF1_BPDLCD1_MASK 8 #define LCDWF1_BPELCD1_MASK 16 #define LCDWF1_BPFLCD1_MASK 32 #define LCDWF1_BPGLCD1_MASK 64 #define LCDWF1_BPHLCD1_MASK 128 /*** LCDWF2 - LCD Waveform Register 2; 0x00000022 ***/ typedef union { byte Byte; struct { byte BPALCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF2STR; extern volatile LCDWF2STR _LCDWF2 @0x00000022; #define LCDWF2 _LCDWF2.Byte #define LCDWF2_BPALCD2 _LCDWF2.Bits.BPALCD2 #define LCDWF2_BPBLCD2 _LCDWF2.Bits.BPBLCD2 #define LCDWF2_BPCLCD2 _LCDWF2.Bits.BPCLCD2 #define LCDWF2_BPDLCD2 _LCDWF2.Bits.BPDLCD2 #define LCDWF2_BPELCD2 _LCDWF2.Bits.BPELCD2 #define LCDWF2_BPFLCD2 _LCDWF2.Bits.BPFLCD2 #define LCDWF2_BPGLCD2 _LCDWF2.Bits.BPGLCD2 #define LCDWF2_BPHLCD2 _LCDWF2.Bits.BPHLCD2 #define LCDWF2_BPALCD2_MASK 1 #define LCDWF2_BPBLCD2_MASK 2 #define LCDWF2_BPCLCD2_MASK 4 #define LCDWF2_BPDLCD2_MASK 8 #define LCDWF2_BPELCD2_MASK 16 #define LCDWF2_BPFLCD2_MASK 32 #define LCDWF2_BPGLCD2_MASK 64 #define LCDWF2_BPHLCD2_MASK 128 /*** LCDWF3 - LCD Waveform Register 3; 0x00000023 ***/ typedef union { byte Byte; struct { byte BPALCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF3STR; extern volatile LCDWF3STR _LCDWF3 @0x00000023; #define LCDWF3 _LCDWF3.Byte #define LCDWF3_BPALCD3 _LCDWF3.Bits.BPALCD3 #define LCDWF3_BPBLCD3 _LCDWF3.Bits.BPBLCD3 #define LCDWF3_BPCLCD3 _LCDWF3.Bits.BPCLCD3 #define LCDWF3_BPDLCD3 _LCDWF3.Bits.BPDLCD3 #define LCDWF3_BPELCD3 _LCDWF3.Bits.BPELCD3 #define LCDWF3_BPFLCD3 _LCDWF3.Bits.BPFLCD3 #define LCDWF3_BPGLCD3 _LCDWF3.Bits.BPGLCD3 #define LCDWF3_BPHLCD3 _LCDWF3.Bits.BPHLCD3 #define LCDWF3_BPALCD3_MASK 1 #define LCDWF3_BPBLCD3_MASK 2 #define LCDWF3_BPCLCD3_MASK 4 #define LCDWF3_BPDLCD3_MASK 8 #define LCDWF3_BPELCD3_MASK 16 #define LCDWF3_BPFLCD3_MASK 32 #define LCDWF3_BPGLCD3_MASK 64 #define LCDWF3_BPHLCD3_MASK 128 /*** LCDWF4 - LCD Waveform Register 4; 0x00000024 ***/ typedef union { byte Byte; struct { byte BPALCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF4STR; extern volatile LCDWF4STR _LCDWF4 @0x00000024; #define LCDWF4 _LCDWF4.Byte #define LCDWF4_BPALCD4 _LCDWF4.Bits.BPALCD4 #define LCDWF4_BPBLCD4 _LCDWF4.Bits.BPBLCD4 #define LCDWF4_BPCLCD4 _LCDWF4.Bits.BPCLCD4 #define LCDWF4_BPDLCD4 _LCDWF4.Bits.BPDLCD4 #define LCDWF4_BPELCD4 _LCDWF4.Bits.BPELCD4 #define LCDWF4_BPFLCD4 _LCDWF4.Bits.BPFLCD4 #define LCDWF4_BPGLCD4 _LCDWF4.Bits.BPGLCD4 #define LCDWF4_BPHLCD4 _LCDWF4.Bits.BPHLCD4 #define LCDWF4_BPALCD4_MASK 1 #define LCDWF4_BPBLCD4_MASK 2 #define LCDWF4_BPCLCD4_MASK 4 #define LCDWF4_BPDLCD4_MASK 8 #define LCDWF4_BPELCD4_MASK 16 #define LCDWF4_BPFLCD4_MASK 32 #define LCDWF4_BPGLCD4_MASK 64 #define LCDWF4_BPHLCD4_MASK 128 /*** LCDWF5 - LCD Waveform Register 5; 0x00000025 ***/ typedef union { byte Byte; struct { byte BPALCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF5STR; extern volatile LCDWF5STR _LCDWF5 @0x00000025; #define LCDWF5 _LCDWF5.Byte #define LCDWF5_BPALCD5 _LCDWF5.Bits.BPALCD5 #define LCDWF5_BPBLCD5 _LCDWF5.Bits.BPBLCD5 #define LCDWF5_BPCLCD5 _LCDWF5.Bits.BPCLCD5 #define LCDWF5_BPDLCD5 _LCDWF5.Bits.BPDLCD5 #define LCDWF5_BPELCD5 _LCDWF5.Bits.BPELCD5 #define LCDWF5_BPFLCD5 _LCDWF5.Bits.BPFLCD5 #define LCDWF5_BPGLCD5 _LCDWF5.Bits.BPGLCD5 #define LCDWF5_BPHLCD5 _LCDWF5.Bits.BPHLCD5 #define LCDWF5_BPALCD5_MASK 1 #define LCDWF5_BPBLCD5_MASK 2 #define LCDWF5_BPCLCD5_MASK 4 #define LCDWF5_BPDLCD5_MASK 8 #define LCDWF5_BPELCD5_MASK 16 #define LCDWF5_BPFLCD5_MASK 32 #define LCDWF5_BPGLCD5_MASK 64 #define LCDWF5_BPHLCD5_MASK 128 /*** LCDWF6 - LCD Waveform Register 6; 0x00000026 ***/ typedef union { byte Byte; struct { byte BPALCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF6STR; extern volatile LCDWF6STR _LCDWF6 @0x00000026; #define LCDWF6 _LCDWF6.Byte #define LCDWF6_BPALCD6 _LCDWF6.Bits.BPALCD6 #define LCDWF6_BPBLCD6 _LCDWF6.Bits.BPBLCD6 #define LCDWF6_BPCLCD6 _LCDWF6.Bits.BPCLCD6 #define LCDWF6_BPDLCD6 _LCDWF6.Bits.BPDLCD6 #define LCDWF6_BPELCD6 _LCDWF6.Bits.BPELCD6 #define LCDWF6_BPFLCD6 _LCDWF6.Bits.BPFLCD6 #define LCDWF6_BPGLCD6 _LCDWF6.Bits.BPGLCD6 #define LCDWF6_BPHLCD6 _LCDWF6.Bits.BPHLCD6 #define LCDWF6_BPALCD6_MASK 1 #define LCDWF6_BPBLCD6_MASK 2 #define LCDWF6_BPCLCD6_MASK 4 #define LCDWF6_BPDLCD6_MASK 8 #define LCDWF6_BPELCD6_MASK 16 #define LCDWF6_BPFLCD6_MASK 32 #define LCDWF6_BPGLCD6_MASK 64 #define LCDWF6_BPHLCD6_MASK 128 /*** LCDWF7 - LCD Waveform Register 7; 0x00000027 ***/ typedef union { byte Byte; struct { byte BPALCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF7STR; extern volatile LCDWF7STR _LCDWF7 @0x00000027; #define LCDWF7 _LCDWF7.Byte #define LCDWF7_BPALCD7 _LCDWF7.Bits.BPALCD7 #define LCDWF7_BPBLCD7 _LCDWF7.Bits.BPBLCD7 #define LCDWF7_BPCLCD7 _LCDWF7.Bits.BPCLCD7 #define LCDWF7_BPDLCD7 _LCDWF7.Bits.BPDLCD7 #define LCDWF7_BPELCD7 _LCDWF7.Bits.BPELCD7 #define LCDWF7_BPFLCD7 _LCDWF7.Bits.BPFLCD7 #define LCDWF7_BPGLCD7 _LCDWF7.Bits.BPGLCD7 #define LCDWF7_BPHLCD7 _LCDWF7.Bits.BPHLCD7 #define LCDWF7_BPALCD7_MASK 1 #define LCDWF7_BPBLCD7_MASK 2 #define LCDWF7_BPCLCD7_MASK 4 #define LCDWF7_BPDLCD7_MASK 8 #define LCDWF7_BPELCD7_MASK 16 #define LCDWF7_BPFLCD7_MASK 32 #define LCDWF7_BPGLCD7_MASK 64 #define LCDWF7_BPHLCD7_MASK 128 /*** LCDWF8 - LCD Waveform Register 8; 0x00000028 ***/ typedef union { byte Byte; struct { byte BPALCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF8STR; extern volatile LCDWF8STR _LCDWF8 @0x00000028; #define LCDWF8 _LCDWF8.Byte #define LCDWF8_BPALCD8 _LCDWF8.Bits.BPALCD8 #define LCDWF8_BPBLCD8 _LCDWF8.Bits.BPBLCD8 #define LCDWF8_BPCLCD8 _LCDWF8.Bits.BPCLCD8 #define LCDWF8_BPDLCD8 _LCDWF8.Bits.BPDLCD8 #define LCDWF8_BPELCD8 _LCDWF8.Bits.BPELCD8 #define LCDWF8_BPFLCD8 _LCDWF8.Bits.BPFLCD8 #define LCDWF8_BPGLCD8 _LCDWF8.Bits.BPGLCD8 #define LCDWF8_BPHLCD8 _LCDWF8.Bits.BPHLCD8 #define LCDWF8_BPALCD8_MASK 1 #define LCDWF8_BPBLCD8_MASK 2 #define LCDWF8_BPCLCD8_MASK 4 #define LCDWF8_BPDLCD8_MASK 8 #define LCDWF8_BPELCD8_MASK 16 #define LCDWF8_BPFLCD8_MASK 32 #define LCDWF8_BPGLCD8_MASK 64 #define LCDWF8_BPHLCD8_MASK 128 /*** LCDWF9 - LCD Waveform Register 9; 0x00000029 ***/ typedef union { byte Byte; struct { byte BPALCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF9STR; extern volatile LCDWF9STR _LCDWF9 @0x00000029; #define LCDWF9 _LCDWF9.Byte #define LCDWF9_BPALCD9 _LCDWF9.Bits.BPALCD9 #define LCDWF9_BPBLCD9 _LCDWF9.Bits.BPBLCD9 #define LCDWF9_BPCLCD9 _LCDWF9.Bits.BPCLCD9 #define LCDWF9_BPDLCD9 _LCDWF9.Bits.BPDLCD9 #define LCDWF9_BPELCD9 _LCDWF9.Bits.BPELCD9 #define LCDWF9_BPFLCD9 _LCDWF9.Bits.BPFLCD9 #define LCDWF9_BPGLCD9 _LCDWF9.Bits.BPGLCD9 #define LCDWF9_BPHLCD9 _LCDWF9.Bits.BPHLCD9 #define LCDWF9_BPALCD9_MASK 1 #define LCDWF9_BPBLCD9_MASK 2 #define LCDWF9_BPCLCD9_MASK 4 #define LCDWF9_BPDLCD9_MASK 8 #define LCDWF9_BPELCD9_MASK 16 #define LCDWF9_BPFLCD9_MASK 32 #define LCDWF9_BPGLCD9_MASK 64 #define LCDWF9_BPHLCD9_MASK 128 /*** LCDWF10 - LCD Waveform Register 10; 0x0000002A ***/ typedef union { byte Byte; struct { byte BPALCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF10STR; extern volatile LCDWF10STR _LCDWF10 @0x0000002A; #define LCDWF10 _LCDWF10.Byte #define LCDWF10_BPALCD10 _LCDWF10.Bits.BPALCD10 #define LCDWF10_BPBLCD10 _LCDWF10.Bits.BPBLCD10 #define LCDWF10_BPCLCD10 _LCDWF10.Bits.BPCLCD10 #define LCDWF10_BPDLCD10 _LCDWF10.Bits.BPDLCD10 #define LCDWF10_BPELCD10 _LCDWF10.Bits.BPELCD10 #define LCDWF10_BPFLCD10 _LCDWF10.Bits.BPFLCD10 #define LCDWF10_BPGLCD10 _LCDWF10.Bits.BPGLCD10 #define LCDWF10_BPHLCD10 _LCDWF10.Bits.BPHLCD10 #define LCDWF10_BPALCD10_MASK 1 #define LCDWF10_BPBLCD10_MASK 2 #define LCDWF10_BPCLCD10_MASK 4 #define LCDWF10_BPDLCD10_MASK 8 #define LCDWF10_BPELCD10_MASK 16 #define LCDWF10_BPFLCD10_MASK 32 #define LCDWF10_BPGLCD10_MASK 64 #define LCDWF10_BPHLCD10_MASK 128 /*** LCDWF11 - LCD Waveform Register 11; 0x0000002B ***/ typedef union { byte Byte; struct { byte BPALCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF11STR; extern volatile LCDWF11STR _LCDWF11 @0x0000002B; #define LCDWF11 _LCDWF11.Byte #define LCDWF11_BPALCD11 _LCDWF11.Bits.BPALCD11 #define LCDWF11_BPBLCD11 _LCDWF11.Bits.BPBLCD11 #define LCDWF11_BPCLCD11 _LCDWF11.Bits.BPCLCD11 #define LCDWF11_BPDLCD11 _LCDWF11.Bits.BPDLCD11 #define LCDWF11_BPELCD11 _LCDWF11.Bits.BPELCD11 #define LCDWF11_BPFLCD11 _LCDWF11.Bits.BPFLCD11 #define LCDWF11_BPGLCD11 _LCDWF11.Bits.BPGLCD11 #define LCDWF11_BPHLCD11 _LCDWF11.Bits.BPHLCD11 #define LCDWF11_BPALCD11_MASK 1 #define LCDWF11_BPBLCD11_MASK 2 #define LCDWF11_BPCLCD11_MASK 4 #define LCDWF11_BPDLCD11_MASK 8 #define LCDWF11_BPELCD11_MASK 16 #define LCDWF11_BPFLCD11_MASK 32 #define LCDWF11_BPGLCD11_MASK 64 #define LCDWF11_BPHLCD11_MASK 128 /*** LCDWF12 - LCD Waveform Register 12; 0x0000002C ***/ typedef union { byte Byte; struct { byte BPALCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF12STR; extern volatile LCDWF12STR _LCDWF12 @0x0000002C; #define LCDWF12 _LCDWF12.Byte #define LCDWF12_BPALCD12 _LCDWF12.Bits.BPALCD12 #define LCDWF12_BPBLCD12 _LCDWF12.Bits.BPBLCD12 #define LCDWF12_BPCLCD12 _LCDWF12.Bits.BPCLCD12 #define LCDWF12_BPDLCD12 _LCDWF12.Bits.BPDLCD12 #define LCDWF12_BPELCD12 _LCDWF12.Bits.BPELCD12 #define LCDWF12_BPFLCD12 _LCDWF12.Bits.BPFLCD12 #define LCDWF12_BPGLCD12 _LCDWF12.Bits.BPGLCD12 #define LCDWF12_BPHLCD12 _LCDWF12.Bits.BPHLCD12 #define LCDWF12_BPALCD12_MASK 1 #define LCDWF12_BPBLCD12_MASK 2 #define LCDWF12_BPCLCD12_MASK 4 #define LCDWF12_BPDLCD12_MASK 8 #define LCDWF12_BPELCD12_MASK 16 #define LCDWF12_BPFLCD12_MASK 32 #define LCDWF12_BPGLCD12_MASK 64 #define LCDWF12_BPHLCD12_MASK 128 /*** LCDWF13 - LCD Waveform Register 13; 0x0000002D ***/ typedef union { byte Byte; struct { byte BPALCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF13STR; extern volatile LCDWF13STR _LCDWF13 @0x0000002D; #define LCDWF13 _LCDWF13.Byte #define LCDWF13_BPALCD13 _LCDWF13.Bits.BPALCD13 #define LCDWF13_BPBLCD13 _LCDWF13.Bits.BPBLCD13 #define LCDWF13_BPCLCD13 _LCDWF13.Bits.BPCLCD13 #define LCDWF13_BPDLCD13 _LCDWF13.Bits.BPDLCD13 #define LCDWF13_BPELCD13 _LCDWF13.Bits.BPELCD13 #define LCDWF13_BPFLCD13 _LCDWF13.Bits.BPFLCD13 #define LCDWF13_BPGLCD13 _LCDWF13.Bits.BPGLCD13 #define LCDWF13_BPHLCD13 _LCDWF13.Bits.BPHLCD13 #define LCDWF13_BPALCD13_MASK 1 #define LCDWF13_BPBLCD13_MASK 2 #define LCDWF13_BPCLCD13_MASK 4 #define LCDWF13_BPDLCD13_MASK 8 #define LCDWF13_BPELCD13_MASK 16 #define LCDWF13_BPFLCD13_MASK 32 #define LCDWF13_BPGLCD13_MASK 64 #define LCDWF13_BPHLCD13_MASK 128 /*** LCDWF14 - LCD Waveform Register 14; 0x0000002E ***/ typedef union { byte Byte; struct { byte BPALCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF14STR; extern volatile LCDWF14STR _LCDWF14 @0x0000002E; #define LCDWF14 _LCDWF14.Byte #define LCDWF14_BPALCD14 _LCDWF14.Bits.BPALCD14 #define LCDWF14_BPBLCD14 _LCDWF14.Bits.BPBLCD14 #define LCDWF14_BPCLCD14 _LCDWF14.Bits.BPCLCD14 #define LCDWF14_BPDLCD14 _LCDWF14.Bits.BPDLCD14 #define LCDWF14_BPELCD14 _LCDWF14.Bits.BPELCD14 #define LCDWF14_BPFLCD14 _LCDWF14.Bits.BPFLCD14 #define LCDWF14_BPGLCD14 _LCDWF14.Bits.BPGLCD14 #define LCDWF14_BPHLCD14 _LCDWF14.Bits.BPHLCD14 #define LCDWF14_BPALCD14_MASK 1 #define LCDWF14_BPBLCD14_MASK 2 #define LCDWF14_BPCLCD14_MASK 4 #define LCDWF14_BPDLCD14_MASK 8 #define LCDWF14_BPELCD14_MASK 16 #define LCDWF14_BPFLCD14_MASK 32 #define LCDWF14_BPGLCD14_MASK 64 #define LCDWF14_BPHLCD14_MASK 128 /*** LCDWF15 - LCD Waveform Register 15; 0x0000002F ***/ typedef union { byte Byte; struct { byte BPALCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF15STR; extern volatile LCDWF15STR _LCDWF15 @0x0000002F; #define LCDWF15 _LCDWF15.Byte #define LCDWF15_BPALCD15 _LCDWF15.Bits.BPALCD15 #define LCDWF15_BPBLCD15 _LCDWF15.Bits.BPBLCD15 #define LCDWF15_BPCLCD15 _LCDWF15.Bits.BPCLCD15 #define LCDWF15_BPDLCD15 _LCDWF15.Bits.BPDLCD15 #define LCDWF15_BPELCD15 _LCDWF15.Bits.BPELCD15 #define LCDWF15_BPFLCD15 _LCDWF15.Bits.BPFLCD15 #define LCDWF15_BPGLCD15 _LCDWF15.Bits.BPGLCD15 #define LCDWF15_BPHLCD15 _LCDWF15.Bits.BPHLCD15 #define LCDWF15_BPALCD15_MASK 1 #define LCDWF15_BPBLCD15_MASK 2 #define LCDWF15_BPCLCD15_MASK 4 #define LCDWF15_BPDLCD15_MASK 8 #define LCDWF15_BPELCD15_MASK 16 #define LCDWF15_BPFLCD15_MASK 32 #define LCDWF15_BPGLCD15_MASK 64 #define LCDWF15_BPHLCD15_MASK 128 /*** LCDWF16 - LCD Waveform Register 16; 0x00000030 ***/ typedef union { byte Byte; struct { byte BPALCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF16STR; extern volatile LCDWF16STR _LCDWF16 @0x00000030; #define LCDWF16 _LCDWF16.Byte #define LCDWF16_BPALCD16 _LCDWF16.Bits.BPALCD16 #define LCDWF16_BPBLCD16 _LCDWF16.Bits.BPBLCD16 #define LCDWF16_BPCLCD16 _LCDWF16.Bits.BPCLCD16 #define LCDWF16_BPDLCD16 _LCDWF16.Bits.BPDLCD16 #define LCDWF16_BPELCD16 _LCDWF16.Bits.BPELCD16 #define LCDWF16_BPFLCD16 _LCDWF16.Bits.BPFLCD16 #define LCDWF16_BPGLCD16 _LCDWF16.Bits.BPGLCD16 #define LCDWF16_BPHLCD16 _LCDWF16.Bits.BPHLCD16 #define LCDWF16_BPALCD16_MASK 1 #define LCDWF16_BPBLCD16_MASK 2 #define LCDWF16_BPCLCD16_MASK 4 #define LCDWF16_BPDLCD16_MASK 8 #define LCDWF16_BPELCD16_MASK 16 #define LCDWF16_BPFLCD16_MASK 32 #define LCDWF16_BPGLCD16_MASK 64 #define LCDWF16_BPHLCD16_MASK 128 /*** LCDWF17 - LCD Waveform Register 17; 0x00000031 ***/ typedef union { byte Byte; struct { byte BPALCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF17STR; extern volatile LCDWF17STR _LCDWF17 @0x00000031; #define LCDWF17 _LCDWF17.Byte #define LCDWF17_BPALCD17 _LCDWF17.Bits.BPALCD17 #define LCDWF17_BPBLCD17 _LCDWF17.Bits.BPBLCD17 #define LCDWF17_BPCLCD17 _LCDWF17.Bits.BPCLCD17 #define LCDWF17_BPDLCD17 _LCDWF17.Bits.BPDLCD17 #define LCDWF17_BPELCD17 _LCDWF17.Bits.BPELCD17 #define LCDWF17_BPFLCD17 _LCDWF17.Bits.BPFLCD17 #define LCDWF17_BPGLCD17 _LCDWF17.Bits.BPGLCD17 #define LCDWF17_BPHLCD17 _LCDWF17.Bits.BPHLCD17 #define LCDWF17_BPALCD17_MASK 1 #define LCDWF17_BPBLCD17_MASK 2 #define LCDWF17_BPCLCD17_MASK 4 #define LCDWF17_BPDLCD17_MASK 8 #define LCDWF17_BPELCD17_MASK 16 #define LCDWF17_BPFLCD17_MASK 32 #define LCDWF17_BPGLCD17_MASK 64 #define LCDWF17_BPHLCD17_MASK 128 /*** LCDWF18 - LCD Waveform Register 18; 0x00000032 ***/ typedef union { byte Byte; struct { byte BPALCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF18STR; extern volatile LCDWF18STR _LCDWF18 @0x00000032; #define LCDWF18 _LCDWF18.Byte #define LCDWF18_BPALCD18 _LCDWF18.Bits.BPALCD18 #define LCDWF18_BPBLCD18 _LCDWF18.Bits.BPBLCD18 #define LCDWF18_BPCLCD18 _LCDWF18.Bits.BPCLCD18 #define LCDWF18_BPDLCD18 _LCDWF18.Bits.BPDLCD18 #define LCDWF18_BPELCD18 _LCDWF18.Bits.BPELCD18 #define LCDWF18_BPFLCD18 _LCDWF18.Bits.BPFLCD18 #define LCDWF18_BPGLCD18 _LCDWF18.Bits.BPGLCD18 #define LCDWF18_BPHLCD18 _LCDWF18.Bits.BPHLCD18 #define LCDWF18_BPALCD18_MASK 1 #define LCDWF18_BPBLCD18_MASK 2 #define LCDWF18_BPCLCD18_MASK 4 #define LCDWF18_BPDLCD18_MASK 8 #define LCDWF18_BPELCD18_MASK 16 #define LCDWF18_BPFLCD18_MASK 32 #define LCDWF18_BPGLCD18_MASK 64 #define LCDWF18_BPHLCD18_MASK 128 /*** LCDWF19 - LCD Waveform Register 19; 0x00000033 ***/ typedef union { byte Byte; struct { byte BPALCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF19STR; extern volatile LCDWF19STR _LCDWF19 @0x00000033; #define LCDWF19 _LCDWF19.Byte #define LCDWF19_BPALCD19 _LCDWF19.Bits.BPALCD19 #define LCDWF19_BPBLCD19 _LCDWF19.Bits.BPBLCD19 #define LCDWF19_BPCLCD19 _LCDWF19.Bits.BPCLCD19 #define LCDWF19_BPDLCD19 _LCDWF19.Bits.BPDLCD19 #define LCDWF19_BPELCD19 _LCDWF19.Bits.BPELCD19 #define LCDWF19_BPFLCD19 _LCDWF19.Bits.BPFLCD19 #define LCDWF19_BPGLCD19 _LCDWF19.Bits.BPGLCD19 #define LCDWF19_BPHLCD19 _LCDWF19.Bits.BPHLCD19 #define LCDWF19_BPALCD19_MASK 1 #define LCDWF19_BPBLCD19_MASK 2 #define LCDWF19_BPCLCD19_MASK 4 #define LCDWF19_BPDLCD19_MASK 8 #define LCDWF19_BPELCD19_MASK 16 #define LCDWF19_BPFLCD19_MASK 32 #define LCDWF19_BPGLCD19_MASK 64 #define LCDWF19_BPHLCD19_MASK 128 /*** LCDWF20 - LCD Waveform Register 20; 0x00000034 ***/ typedef union { byte Byte; struct { byte BPALCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF20STR; extern volatile LCDWF20STR _LCDWF20 @0x00000034; #define LCDWF20 _LCDWF20.Byte #define LCDWF20_BPALCD20 _LCDWF20.Bits.BPALCD20 #define LCDWF20_BPBLCD20 _LCDWF20.Bits.BPBLCD20 #define LCDWF20_BPCLCD20 _LCDWF20.Bits.BPCLCD20 #define LCDWF20_BPDLCD20 _LCDWF20.Bits.BPDLCD20 #define LCDWF20_BPELCD20 _LCDWF20.Bits.BPELCD20 #define LCDWF20_BPFLCD20 _LCDWF20.Bits.BPFLCD20 #define LCDWF20_BPGLCD20 _LCDWF20.Bits.BPGLCD20 #define LCDWF20_BPHLCD20 _LCDWF20.Bits.BPHLCD20 #define LCDWF20_BPALCD20_MASK 1 #define LCDWF20_BPBLCD20_MASK 2 #define LCDWF20_BPCLCD20_MASK 4 #define LCDWF20_BPDLCD20_MASK 8 #define LCDWF20_BPELCD20_MASK 16 #define LCDWF20_BPFLCD20_MASK 32 #define LCDWF20_BPGLCD20_MASK 64 #define LCDWF20_BPHLCD20_MASK 128 /*** LCDWF21 - LCD Waveform Register 21; 0x00000035 ***/ typedef union { byte Byte; struct { byte BPALCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF21STR; extern volatile LCDWF21STR _LCDWF21 @0x00000035; #define LCDWF21 _LCDWF21.Byte #define LCDWF21_BPALCD21 _LCDWF21.Bits.BPALCD21 #define LCDWF21_BPBLCD21 _LCDWF21.Bits.BPBLCD21 #define LCDWF21_BPCLCD21 _LCDWF21.Bits.BPCLCD21 #define LCDWF21_BPDLCD21 _LCDWF21.Bits.BPDLCD21 #define LCDWF21_BPELCD21 _LCDWF21.Bits.BPELCD21 #define LCDWF21_BPFLCD21 _LCDWF21.Bits.BPFLCD21 #define LCDWF21_BPGLCD21 _LCDWF21.Bits.BPGLCD21 #define LCDWF21_BPHLCD21 _LCDWF21.Bits.BPHLCD21 #define LCDWF21_BPALCD21_MASK 1 #define LCDWF21_BPBLCD21_MASK 2 #define LCDWF21_BPCLCD21_MASK 4 #define LCDWF21_BPDLCD21_MASK 8 #define LCDWF21_BPELCD21_MASK 16 #define LCDWF21_BPFLCD21_MASK 32 #define LCDWF21_BPGLCD21_MASK 64 #define LCDWF21_BPHLCD21_MASK 128 /*** LCDC0 - LCD Control Register 0; 0x00000040 ***/ typedef union { byte Byte; struct { byte DUTY0 :1; /* LCD Duty Select Bit 0 */ byte DUTY1 :1; /* LCD Duty Select Bit 1 */ byte DUTY2 :1; /* LCD Duty Select Bit 2 */ byte LCLK0 :1; /* LCD Clock Prescaler Bit 0 */ byte LCLK1 :1; /* LCD Clock Prescaler Bit 1 */ byte LCLK2 :1; /* LCD Clock Prescaler Bit 2 */ byte SOURCE :1; /* LCD Clock Source Select */ byte LCDEN :1; /* LCD Driver Enable */ } Bits; struct { byte grpDUTY :3; byte grpLCLK :3; byte :1; byte :1; } MergedBits; } LCDC0STR; extern volatile LCDC0STR _LCDC0 @0x00000040; #define LCDC0 _LCDC0.Byte #define LCDC0_DUTY0 _LCDC0.Bits.DUTY0 #define LCDC0_DUTY1 _LCDC0.Bits.DUTY1 #define LCDC0_DUTY2 _LCDC0.Bits.DUTY2 #define LCDC0_LCLK0 _LCDC0.Bits.LCLK0 #define LCDC0_LCLK1 _LCDC0.Bits.LCLK1 #define LCDC0_LCLK2 _LCDC0.Bits.LCLK2 #define LCDC0_SOURCE _LCDC0.Bits.SOURCE #define LCDC0_LCDEN _LCDC0.Bits.LCDEN /* LCDC_ARR: Access 2 LCDCx registers in an array */ #define LCDC_ARR ((volatile byte *__paged) &LCDC0) #define LCDC0_DUTY _LCDC0.MergedBits.grpDUTY #define LCDC0_LCLK _LCDC0.MergedBits.grpLCLK #define LCDC0_DUTY0_MASK 1 #define LCDC0_DUTY1_MASK 2 #define LCDC0_DUTY2_MASK 4 #define LCDC0_LCLK0_MASK 8 #define LCDC0_LCLK1_MASK 16 #define LCDC0_LCLK2_MASK 32 #define LCDC0_SOURCE_MASK 64 #define LCDC0_LCDEN_MASK 128 #define LCDC0_DUTY_MASK 7 #define LCDC0_DUTY_BITNUM 0 #define LCDC0_LCLK_MASK 56 #define LCDC0_LCLK_BITNUM 3 /*** LCDC1 - LCD Control Register 1; 0x00000041 ***/ typedef union { byte Byte; struct { byte LCDSTP :1; /* LCD Module Driver and Charge Pump Stop While in Stop2 or Stop3 Mode */ byte LCDWAI :1; /* LCD Module Driver and Charge Pump Stop While in Wait Mode */ byte FCDEN :1; /* Full Complementary Drive Enable */ byte :1; byte :1; byte :1; byte :1; byte LCDIEN :1; /* LCD Module Frame Frequency Interrupt Enable */ } Bits; } LCDC1STR; extern volatile LCDC1STR _LCDC1 @0x00000041; #define LCDC1 _LCDC1.Byte #define LCDC1_LCDSTP _LCDC1.Bits.LCDSTP #define LCDC1_LCDWAI _LCDC1.Bits.LCDWAI #define LCDC1_FCDEN _LCDC1.Bits.FCDEN #define LCDC1_LCDIEN _LCDC1.Bits.LCDIEN #define LCDC1_LCDSTP_MASK 1 #define LCDC1_LCDWAI_MASK 2 #define LCDC1_FCDEN_MASK 4 #define LCDC1_LCDIEN_MASK 128 /*** LCDSUPPLY - LCD Voltage Supply Register; 0x00000042 ***/ typedef union { byte Byte; struct { byte VSUPPLY0 :1; /* Voltage Supply Control Bit 0 */ byte VSUPPLY1 :1; /* Voltage Supply Control Bit 1 */ byte :1; byte :1; byte LADJ0 :1; /* LCD Module Load Adjust Bit 0 */ byte LADJ1 :1; /* LCD Module Load Adjust Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpVSUPPLY :2; byte :1; byte :1; byte grpLADJ :2; byte :1; byte :1; } MergedBits; } LCDSUPPLYSTR; extern volatile LCDSUPPLYSTR _LCDSUPPLY @0x00000042; #define LCDSUPPLY _LCDSUPPLY.Byte #define LCDSUPPLY_VSUPPLY0 _LCDSUPPLY.Bits.VSUPPLY0 #define LCDSUPPLY_VSUPPLY1 _LCDSUPPLY.Bits.VSUPPLY1 #define LCDSUPPLY_LADJ0 _LCDSUPPLY.Bits.LADJ0 #define LCDSUPPLY_LADJ1 _LCDSUPPLY.Bits.LADJ1 #define LCDSUPPLY_VSUPPLY _LCDSUPPLY.MergedBits.grpVSUPPLY #define LCDSUPPLY_LADJ _LCDSUPPLY.MergedBits.grpLADJ #define LCDSUPPLY_VSUPPLY0_MASK 1 #define LCDSUPPLY_VSUPPLY1_MASK 2 #define LCDSUPPLY_LADJ0_MASK 16 #define LCDSUPPLY_LADJ1_MASK 32 #define LCDSUPPLY_VSUPPLY_MASK 3 #define LCDSUPPLY_VSUPPLY_BITNUM 0 #define LCDSUPPLY_LADJ_MASK 48 #define LCDSUPPLY_LADJ_BITNUM 4 /*** LCDBCTL - LCD Blink Control Register; 0x00000044 ***/ typedef union { byte Byte; struct { byte BRATE0 :1; /* Blink-Rate Configuration Bit 0 */ byte BRATE1 :1; /* Blink-Rate Configuration Bit 1 */ byte BRATE2 :1; /* Blink-Rate Configuration Bit 2 */ byte BMODE :1; /* Blink Mode */ byte :1; byte BLANK :1; /* Blank Display Mode */ byte ALT :1; /* Alternate Display Mode */ byte BLINK :1; /* Blink Command */ } Bits; struct { byte grpBRATE :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDBCTLSTR; extern volatile LCDBCTLSTR _LCDBCTL @0x00000044; #define LCDBCTL _LCDBCTL.Byte #define LCDBCTL_BRATE0 _LCDBCTL.Bits.BRATE0 #define LCDBCTL_BRATE1 _LCDBCTL.Bits.BRATE1 #define LCDBCTL_BRATE2 _LCDBCTL.Bits.BRATE2 #define LCDBCTL_BMODE _LCDBCTL.Bits.BMODE #define LCDBCTL_BLANK _LCDBCTL.Bits.BLANK #define LCDBCTL_ALT _LCDBCTL.Bits.ALT #define LCDBCTL_BLINK _LCDBCTL.Bits.BLINK #define LCDBCTL_BRATE _LCDBCTL.MergedBits.grpBRATE #define LCDBCTL_BRATE0_MASK 1 #define LCDBCTL_BRATE1_MASK 2 #define LCDBCTL_BRATE2_MASK 4 #define LCDBCTL_BMODE_MASK 8 #define LCDBCTL_BLANK_MASK 32 #define LCDBCTL_ALT_MASK 64 #define LCDBCTL_BLINK_MASK 128 #define LCDBCTL_BRATE_MASK 7 #define LCDBCTL_BRATE_BITNUM 0 /*** LCDS - LCD Status Register; 0x00000045 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LCDIF :1; /* LCD Interrupt Flag */ } Bits; } LCDSSTR; extern volatile LCDSSTR _LCDS @0x00000045; #define LCDS _LCDS.Byte #define LCDS_LCDIF _LCDS.Bits.LCDIF #define LCDS_LCDIF_MASK 128 /*** PTAD - Port A Data Register; 0x00000046 ***/ typedef union { byte Byte; struct { byte PTAD0 :1; /* Port A Data Register Bit 0 */ byte PTAD1 :1; /* Port A Data Register Bit 1 */ byte PTAD2 :1; /* Port A Data Register Bit 2 */ byte PTAD3 :1; /* Port A Data Register Bit 3 */ byte PTAD4 :1; /* Port A Data Register Bit 4 */ byte PTAD5 :1; /* Port A Data Register Bit 5 */ byte PTAD6 :1; /* Port A Data Register Bit 6 */ byte PTAD7 :1; /* Port A Data Register Bit 7 */ } Bits; } PTADSTR; extern volatile PTADSTR _PTAD @0x00000046; #define PTAD _PTAD.Byte #define PTAD_PTAD0 _PTAD.Bits.PTAD0 #define PTAD_PTAD1 _PTAD.Bits.PTAD1 #define PTAD_PTAD2 _PTAD.Bits.PTAD2 #define PTAD_PTAD3 _PTAD.Bits.PTAD3 #define PTAD_PTAD4 _PTAD.Bits.PTAD4 #define PTAD_PTAD5 _PTAD.Bits.PTAD5 #define PTAD_PTAD6 _PTAD.Bits.PTAD6 #define PTAD_PTAD7 _PTAD.Bits.PTAD7 #define PTAD_PTAD0_MASK 1 #define PTAD_PTAD1_MASK 2 #define PTAD_PTAD2_MASK 4 #define PTAD_PTAD3_MASK 8 #define PTAD_PTAD4_MASK 16 #define PTAD_PTAD5_MASK 32 #define PTAD_PTAD6_MASK 64 #define PTAD_PTAD7_MASK 128 /*** PTADD - Port A Data Direction Register; 0x00000047 ***/ typedef union { byte Byte; struct { byte PTADD0 :1; /* PTADD */ byte PTADD1 :1; /* PTADD */ byte PTADD2 :1; /* PTADD */ byte PTADD3 :1; /* PTADD */ byte PTADD4 :1; /* PTADD */ byte PTADD5 :1; /* PTADD */ byte PTADD6 :1; /* PTADD */ byte PTADD7 :1; /* PTADD */ } Bits; } PTADDSTR; extern volatile PTADDSTR _PTADD @0x00000047; #define PTADD _PTADD.Byte #define PTADD_PTADD0 _PTADD.Bits.PTADD0 #define PTADD_PTADD1 _PTADD.Bits.PTADD1 #define PTADD_PTADD2 _PTADD.Bits.PTADD2 #define PTADD_PTADD3 _PTADD.Bits.PTADD3 #define PTADD_PTADD4 _PTADD.Bits.PTADD4 #define PTADD_PTADD5 _PTADD.Bits.PTADD5 #define PTADD_PTADD6 _PTADD.Bits.PTADD6 #define PTADD_PTADD7 _PTADD.Bits.PTADD7 #define PTADD_PTADD0_MASK 1 #define PTADD_PTADD1_MASK 2 #define PTADD_PTADD2_MASK 4 #define PTADD_PTADD3_MASK 8 #define PTADD_PTADD4_MASK 16 #define PTADD_PTADD5_MASK 32 #define PTADD_PTADD6_MASK 64 #define PTADD_PTADD7_MASK 128 /*** PTBD - Port B Data Register; 0x00000048 ***/ typedef union { byte Byte; struct { byte PTBD0 :1; /* Port B Data Register Bit 0 */ byte PTBD1 :1; /* Port B Data Register Bit 1 */ byte PTBD2 :1; /* Port B Data Register Bit 2 */ byte PTBD3 :1; /* Port B Data Register Bit 3 */ byte PTBD4 :1; /* Port B Data Register Bit 4 */ byte PTBD5 :1; /* Port B Data Register Bit 5 */ byte PTBD6 :1; /* Port B Data Register Bit 6 */ byte PTBD7 :1; /* Port B Data Register Bit 7 */ } Bits; } PTBDSTR; extern volatile PTBDSTR _PTBD @0x00000048; #define PTBD _PTBD.Byte #define PTBD_PTBD0 _PTBD.Bits.PTBD0 #define PTBD_PTBD1 _PTBD.Bits.PTBD1 #define PTBD_PTBD2 _PTBD.Bits.PTBD2 #define PTBD_PTBD3 _PTBD.Bits.PTBD3 #define PTBD_PTBD4 _PTBD.Bits.PTBD4 #define PTBD_PTBD5 _PTBD.Bits.PTBD5 #define PTBD_PTBD6 _PTBD.Bits.PTBD6 #define PTBD_PTBD7 _PTBD.Bits.PTBD7 #define PTBD_PTBD0_MASK 1 #define PTBD_PTBD1_MASK 2 #define PTBD_PTBD2_MASK 4 #define PTBD_PTBD3_MASK 8 #define PTBD_PTBD4_MASK 16 #define PTBD_PTBD5_MASK 32 #define PTBD_PTBD6_MASK 64 #define PTBD_PTBD7_MASK 128 /*** PTBDD - Port B Data Direction Register; 0x00000049 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte PTBDD2 :1; /* PTBDD */ byte PTBDD3 :1; /* PTBDD */ byte PTBDD4 :1; /* PTBDD */ byte PTBDD5 :1; /* PTBDD */ byte PTBDD6 :1; /* PTBDD */ byte PTBDD7 :1; /* PTBDD */ } Bits; struct { byte :1; byte :1; byte grpPTBDD_2 :6; } MergedBits; } PTBDDSTR; extern volatile PTBDDSTR _PTBDD @0x00000049; #define PTBDD _PTBDD.Byte #define PTBDD_PTBDD2 _PTBDD.Bits.PTBDD2 #define PTBDD_PTBDD3 _PTBDD.Bits.PTBDD3 #define PTBDD_PTBDD4 _PTBDD.Bits.PTBDD4 #define PTBDD_PTBDD5 _PTBDD.Bits.PTBDD5 #define PTBDD_PTBDD6 _PTBDD.Bits.PTBDD6 #define PTBDD_PTBDD7 _PTBDD.Bits.PTBDD7 #define PTBDD_PTBDD_2 _PTBDD.MergedBits.grpPTBDD_2 #define PTBDD_PTBDD2_MASK 4 #define PTBDD_PTBDD3_MASK 8 #define PTBDD_PTBDD4_MASK 16 #define PTBDD_PTBDD5_MASK 32 #define PTBDD_PTBDD6_MASK 64 #define PTBDD_PTBDD7_MASK 128 #define PTBDD_PTBDD_2_MASK 252 #define PTBDD_PTBDD_2_BITNUM 2 /*** PTCD - Port C Data Register; 0x0000004A ***/ typedef union { byte Byte; struct { byte PTCD0 :1; /* Port C Data Register Bit 0 */ byte PTCD1 :1; /* Port C Data Register Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTCD :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTCDSTR; extern volatile PTCDSTR _PTCD @0x0000004A; #define PTCD _PTCD.Byte #define PTCD_PTCD0 _PTCD.Bits.PTCD0 #define PTCD_PTCD1 _PTCD.Bits.PTCD1 #define PTCD_PTCD _PTCD.MergedBits.grpPTCD #define PTCD_PTCD0_MASK 1 #define PTCD_PTCD1_MASK 2 #define PTCD_PTCD_MASK 3 #define PTCD_PTCD_BITNUM 0 /*** PTCDD - Port C Data Direction Register; 0x0000004B ***/ typedef union { byte Byte; struct { byte PTCDD0 :1; /* PTCDD */ byte PTCDD1 :1; /* PTCDD */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTCDD :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTCDDSTR; extern volatile PTCDDSTR _PTCDD @0x0000004B; #define PTCDD _PTCDD.Byte #define PTCDD_PTCDD0 _PTCDD.Bits.PTCDD0 #define PTCDD_PTCDD1 _PTCDD.Bits.PTCDD1 #define PTCDD_PTCDD _PTCDD.MergedBits.grpPTCDD #define PTCDD_PTCDD0_MASK 1 #define PTCDD_PTCDD1_MASK 2 #define PTCDD_PTCDD_MASK 3 #define PTCDD_PTCDD_BITNUM 0 /*** PTDD - Port D Data Register; 0x0000004C ***/ typedef union { byte Byte; struct { byte PTDD0 :1; /* Port D Data Register Bit 0 */ byte PTDD1 :1; /* Port D Data Register Bit 1 */ byte PTDD2 :1; /* Port D Data Register Bit 2 */ byte PTDD3 :1; /* Port D Data Register Bit 3 */ byte PTDD4 :1; /* Port D Data Register Bit 4 */ byte PTDD5 :1; /* Port D Data Register Bit 5 */ byte PTDD6 :1; /* Port D Data Register Bit 6 */ byte PTDD7 :1; /* Port D Data Register Bit 7 */ } Bits; } PTDDSTR; extern volatile PTDDSTR _PTDD @0x0000004C; #define PTDD _PTDD.Byte #define PTDD_PTDD0 _PTDD.Bits.PTDD0 #define PTDD_PTDD1 _PTDD.Bits.PTDD1 #define PTDD_PTDD2 _PTDD.Bits.PTDD2 #define PTDD_PTDD3 _PTDD.Bits.PTDD3 #define PTDD_PTDD4 _PTDD.Bits.PTDD4 #define PTDD_PTDD5 _PTDD.Bits.PTDD5 #define PTDD_PTDD6 _PTDD.Bits.PTDD6 #define PTDD_PTDD7 _PTDD.Bits.PTDD7 #define PTDD_PTDD0_MASK 1 #define PTDD_PTDD1_MASK 2 #define PTDD_PTDD2_MASK 4 #define PTDD_PTDD3_MASK 8 #define PTDD_PTDD4_MASK 16 #define PTDD_PTDD5_MASK 32 #define PTDD_PTDD6_MASK 64 #define PTDD_PTDD7_MASK 128 /*** PTDDD - Port D Data Direction Register; 0x0000004D ***/ typedef union { byte Byte; struct { byte PTDDD0 :1; /* PTDDD */ byte PTDDD1 :1; /* PTDDD */ byte PTDDD2 :1; /* PTDDD */ byte PTDDD3 :1; /* PTDDD */ byte PTDDD4 :1; /* PTDDD */ byte PTDDD5 :1; /* PTDDD */ byte PTDDD6 :1; /* PTDDD */ byte PTDDD7 :1; /* PTDDD */ } Bits; } PTDDDSTR; extern volatile PTDDDSTR _PTDDD @0x0000004D; #define PTDDD _PTDDD.Byte #define PTDDD_PTDDD0 _PTDDD.Bits.PTDDD0 #define PTDDD_PTDDD1 _PTDDD.Bits.PTDDD1 #define PTDDD_PTDDD2 _PTDDD.Bits.PTDDD2 #define PTDDD_PTDDD3 _PTDDD.Bits.PTDDD3 #define PTDDD_PTDDD4 _PTDDD.Bits.PTDDD4 #define PTDDD_PTDDD5 _PTDDD.Bits.PTDDD5 #define PTDDD_PTDDD6 _PTDDD.Bits.PTDDD6 #define PTDDD_PTDDD7 _PTDDD.Bits.PTDDD7 #define PTDDD_PTDDD0_MASK 1 #define PTDDD_PTDDD1_MASK 2 #define PTDDD_PTDDD2_MASK 4 #define PTDDD_PTDDD3_MASK 8 #define PTDDD_PTDDD4_MASK 16 #define PTDDD_PTDDD5_MASK 32 #define PTDDD_PTDDD6_MASK 64 #define PTDDD_PTDDD7_MASK 128 /*** PTAPE - Port A Internal Pulling Device Enable Register; 0x00000200 ***/ typedef union { byte Byte; struct { byte PTAPE0 :1; /* Internal Pulling Device Enable for Port A Bit 0 */ byte PTAPE1 :1; /* Internal Pulling Device Enable for Port A Bit 1 */ byte PTAPE2 :1; /* Internal Pulling Device Enable for Port A Bit 2 */ byte PTAPE3 :1; /* Internal Pulling Device Enable for Port A Bit 3 */ byte PTAPE4 :1; /* Internal Pulling Device Enable for Port A Bit 4 */ byte PTAPE5 :1; /* Internal Pulling Device Enable for Port A Bit 5 */ byte PTAPE6 :1; /* Internal Pulling Device Enable for Port A Bit 6 */ byte PTAPE7 :1; /* Internal Pulling Device Enable for Port A Bit 7 */ } Bits; } PTAPESTR; extern volatile PTAPESTR _PTAPE @0x00000200; #define PTAPE _PTAPE.Byte #define PTAPE_PTAPE0 _PTAPE.Bits.PTAPE0 #define PTAPE_PTAPE1 _PTAPE.Bits.PTAPE1 #define PTAPE_PTAPE2 _PTAPE.Bits.PTAPE2 #define PTAPE_PTAPE3 _PTAPE.Bits.PTAPE3 #define PTAPE_PTAPE4 _PTAPE.Bits.PTAPE4 #define PTAPE_PTAPE5 _PTAPE.Bits.PTAPE5 #define PTAPE_PTAPE6 _PTAPE.Bits.PTAPE6 #define PTAPE_PTAPE7 _PTAPE.Bits.PTAPE7 #define PTAPE_PTAPE0_MASK 1 #define PTAPE_PTAPE1_MASK 2 #define PTAPE_PTAPE2_MASK 4 #define PTAPE_PTAPE3_MASK 8 #define PTAPE_PTAPE4_MASK 16 #define PTAPE_PTAPE5_MASK 32 #define PTAPE_PTAPE6_MASK 64 #define PTAPE_PTAPE7_MASK 128 /*** PTAPUD - Port A Pullup/Pulldown Control Register; 0x00000201 ***/ typedef union { byte Byte; struct { byte PTAPUD0 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD1 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD2 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD3 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD4 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD5 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD6 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ byte PTAPUD7 :1; /* Pullup/Pulldown Device Control for Port A Bit 0 */ } Bits; } PTAPUDSTR; extern volatile PTAPUDSTR _PTAPUD @0x00000201; #define PTAPUD _PTAPUD.Byte #define PTAPUD_PTAPUD0 _PTAPUD.Bits.PTAPUD0 #define PTAPUD_PTAPUD1 _PTAPUD.Bits.PTAPUD1 #define PTAPUD_PTAPUD2 _PTAPUD.Bits.PTAPUD2 #define PTAPUD_PTAPUD3 _PTAPUD.Bits.PTAPUD3 #define PTAPUD_PTAPUD4 _PTAPUD.Bits.PTAPUD4 #define PTAPUD_PTAPUD5 _PTAPUD.Bits.PTAPUD5 #define PTAPUD_PTAPUD6 _PTAPUD.Bits.PTAPUD6 #define PTAPUD_PTAPUD7 _PTAPUD.Bits.PTAPUD7 #define PTAPUD_PTAPUD0_MASK 1 #define PTAPUD_PTAPUD1_MASK 2 #define PTAPUD_PTAPUD2_MASK 4 #define PTAPUD_PTAPUD3_MASK 8 #define PTAPUD_PTAPUD4_MASK 16 #define PTAPUD_PTAPUD5_MASK 32 #define PTAPUD_PTAPUD6_MASK 64 #define PTAPUD_PTAPUD7_MASK 128 /*** PTADS - Port A Drive Strength Selection Register; 0x00000202 ***/ typedef union { byte Byte; struct { byte PTADS0 :1; /* Output Drive Strength Selection for Port A Bit 0 */ byte PTADS1 :1; /* Output Drive Strength Selection for Port A Bit 1 */ byte PTADS2 :1; /* Output Drive Strength Selection for Port A Bit 2 */ byte PTADS3 :1; /* Output Drive Strength Selection for Port A Bit 3 */ byte PTADS4 :1; /* Output Drive Strength Selection for Port A Bit 4 */ byte PTADS5 :1; /* Output Drive Strength Selection for Port A Bit 5 */ byte PTADS6 :1; /* Output Drive Strength Selection for Port A Bit 6 */ byte PTADS7 :1; /* Output Drive Strength Selection for Port A Bit 7 */ } Bits; } PTADSSTR; extern volatile PTADSSTR _PTADS @0x00000202; #define PTADS _PTADS.Byte #define PTADS_PTADS0 _PTADS.Bits.PTADS0 #define PTADS_PTADS1 _PTADS.Bits.PTADS1 #define PTADS_PTADS2 _PTADS.Bits.PTADS2 #define PTADS_PTADS3 _PTADS.Bits.PTADS3 #define PTADS_PTADS4 _PTADS.Bits.PTADS4 #define PTADS_PTADS5 _PTADS.Bits.PTADS5 #define PTADS_PTADS6 _PTADS.Bits.PTADS6 #define PTADS_PTADS7 _PTADS.Bits.PTADS7 #define PTADS_PTADS0_MASK 1 #define PTADS_PTADS1_MASK 2 #define PTADS_PTADS2_MASK 4 #define PTADS_PTADS3_MASK 8 #define PTADS_PTADS4_MASK 16 #define PTADS_PTADS5_MASK 32 #define PTADS_PTADS6_MASK 64 #define PTADS_PTADS7_MASK 128 /*** PTASE - Port A Output Slew Rate Control Enable Register; 0x00000203 ***/ typedef union { byte Byte; struct { byte PTASE0 :1; /* Output Slew Rate Enable for Port A Bit 0 */ byte PTASE1 :1; /* Output Slew Rate Enable for Port A Bit 1 */ byte PTASE2 :1; /* Output Slew Rate Enable for Port A Bit 2 */ byte PTASE3 :1; /* Output Slew Rate Enable for Port A Bit 3 */ byte PTASE4 :1; /* Output Slew Rate Enable for Port A Bit 4 */ byte PTASE5 :1; /* Output Slew Rate Enable for Port A Bit 5 */ byte PTASE6 :1; /* Output Slew Rate Enable for Port A Bit 6 */ byte PTASE7 :1; /* Output Slew Rate Enable for Port A Bit 7 */ } Bits; } PTASESTR; extern volatile PTASESTR _PTASE @0x00000203; #define PTASE _PTASE.Byte #define PTASE_PTASE0 _PTASE.Bits.PTASE0 #define PTASE_PTASE1 _PTASE.Bits.PTASE1 #define PTASE_PTASE2 _PTASE.Bits.PTASE2 #define PTASE_PTASE3 _PTASE.Bits.PTASE3 #define PTASE_PTASE4 _PTASE.Bits.PTASE4 #define PTASE_PTASE5 _PTASE.Bits.PTASE5 #define PTASE_PTASE6 _PTASE.Bits.PTASE6 #define PTASE_PTASE7 _PTASE.Bits.PTASE7 #define PTASE_PTASE0_MASK 1 #define PTASE_PTASE1_MASK 2 #define PTASE_PTASE2_MASK 4 #define PTASE_PTASE3_MASK 8 #define PTASE_PTASE4_MASK 16 #define PTASE_PTASE5_MASK 32 #define PTASE_PTASE6_MASK 64 #define PTASE_PTASE7_MASK 128 /*** PTBPE - Port B Internal Pulling Device Enable Register; 0x00000204 ***/ typedef union { byte Byte; struct { byte PTBPE0 :1; /* Internal Pulling Device Enable for Port B Bit 0 */ byte :1; byte PTBPE2 :1; /* Internal Pulling Device Enable for Port B Bit 2 */ byte PTBPE3 :1; /* Internal Pulling Device Enable for Port B Bit 3 */ byte PTBPE4 :1; /* Internal Pulling Device Enable for Port B Bit 4 */ byte PTBPE5 :1; /* Internal Pulling Device Enable for Port B Bit 5 */ byte PTBPE6 :1; /* Internal Pulling Device Enable for Port B Bit 6 */ byte PTBPE7 :1; /* Internal Pulling Device Enable for Port B Bit 7 */ } Bits; struct { byte grpPTBPE :1; byte :1; byte grpPTBPE_2 :6; } MergedBits; } PTBPESTR; extern volatile PTBPESTR _PTBPE @0x00000204; #define PTBPE _PTBPE.Byte #define PTBPE_PTBPE0 _PTBPE.Bits.PTBPE0 #define PTBPE_PTBPE2 _PTBPE.Bits.PTBPE2 #define PTBPE_PTBPE3 _PTBPE.Bits.PTBPE3 #define PTBPE_PTBPE4 _PTBPE.Bits.PTBPE4 #define PTBPE_PTBPE5 _PTBPE.Bits.PTBPE5 #define PTBPE_PTBPE6 _PTBPE.Bits.PTBPE6 #define PTBPE_PTBPE7 _PTBPE.Bits.PTBPE7 #define PTBPE_PTBPE_2 _PTBPE.MergedBits.grpPTBPE_2 #define PTBPE_PTBPE0_MASK 1 #define PTBPE_PTBPE2_MASK 4 #define PTBPE_PTBPE3_MASK 8 #define PTBPE_PTBPE4_MASK 16 #define PTBPE_PTBPE5_MASK 32 #define PTBPE_PTBPE6_MASK 64 #define PTBPE_PTBPE7_MASK 128 #define PTBPE_PTBPE_2_MASK 252 #define PTBPE_PTBPE_2_BITNUM 2 /*** PTBPUD - Port B Pullup/Pulldown Control Register; 0x00000205 ***/ typedef union { byte Byte; struct { byte PTBPUD0 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte :1; byte PTBPUD2 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD3 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD4 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD5 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD6 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ byte PTBPUD7 :1; /* Pullup/Pulldown Device Control for Port B Bit 0 */ } Bits; struct { byte grpPTBPUD :1; byte :1; byte grpPTBPUD_2 :6; } MergedBits; } PTBPUDSTR; extern volatile PTBPUDSTR _PTBPUD @0x00000205; #define PTBPUD _PTBPUD.Byte #define PTBPUD_PTBPUD0 _PTBPUD.Bits.PTBPUD0 #define PTBPUD_PTBPUD2 _PTBPUD.Bits.PTBPUD2 #define PTBPUD_PTBPUD3 _PTBPUD.Bits.PTBPUD3 #define PTBPUD_PTBPUD4 _PTBPUD.Bits.PTBPUD4 #define PTBPUD_PTBPUD5 _PTBPUD.Bits.PTBPUD5 #define PTBPUD_PTBPUD6 _PTBPUD.Bits.PTBPUD6 #define PTBPUD_PTBPUD7 _PTBPUD.Bits.PTBPUD7 #define PTBPUD_PTBPUD_2 _PTBPUD.MergedBits.grpPTBPUD_2 #define PTBPUD_PTBPUD0_MASK 1 #define PTBPUD_PTBPUD2_MASK 4 #define PTBPUD_PTBPUD3_MASK 8 #define PTBPUD_PTBPUD4_MASK 16 #define PTBPUD_PTBPUD5_MASK 32 #define PTBPUD_PTBPUD6_MASK 64 #define PTBPUD_PTBPUD7_MASK 128 #define PTBPUD_PTBPUD_2_MASK 252 #define PTBPUD_PTBPUD_2_BITNUM 2 /*** PTBDS - Port B Drive Strength Selection Register; 0x00000206 ***/ typedef union { byte Byte; struct { byte :1; byte PTBDS1 :1; /* Output Drive Strength Selection for Port B Bit 1 */ byte PTBDS2 :1; /* Output Drive Strength Selection for Port B Bit 2 */ byte PTBDS3 :1; /* Output Drive Strength Selection for Port B Bit 3 */ byte PTBDS4 :1; /* Output Drive Strength Selection for Port B Bit 4 */ byte PTBDS5 :1; /* Output Drive Strength Selection for Port B Bit 5 */ byte PTBDS6 :1; /* Output Drive Strength Selection for Port B Bit 6 */ byte PTBDS7 :1; /* Output Drive Strength Selection for Port B Bit 7 */ } Bits; struct { byte :1; byte grpPTBDS_1 :7; } MergedBits; } PTBDSSTR; extern volatile PTBDSSTR _PTBDS @0x00000206; #define PTBDS _PTBDS.Byte #define PTBDS_PTBDS1 _PTBDS.Bits.PTBDS1 #define PTBDS_PTBDS2 _PTBDS.Bits.PTBDS2 #define PTBDS_PTBDS3 _PTBDS.Bits.PTBDS3 #define PTBDS_PTBDS4 _PTBDS.Bits.PTBDS4 #define PTBDS_PTBDS5 _PTBDS.Bits.PTBDS5 #define PTBDS_PTBDS6 _PTBDS.Bits.PTBDS6 #define PTBDS_PTBDS7 _PTBDS.Bits.PTBDS7 #define PTBDS_PTBDS_1 _PTBDS.MergedBits.grpPTBDS_1 #define PTBDS_PTBDS1_MASK 2 #define PTBDS_PTBDS2_MASK 4 #define PTBDS_PTBDS3_MASK 8 #define PTBDS_PTBDS4_MASK 16 #define PTBDS_PTBDS5_MASK 32 #define PTBDS_PTBDS6_MASK 64 #define PTBDS_PTBDS7_MASK 128 #define PTBDS_PTBDS_1_MASK 254 #define PTBDS_PTBDS_1_BITNUM 1 /*** PTBSE - Port B Output Slew Rate Control Enable Register; 0x00000207 ***/ typedef union { byte Byte; struct { byte :1; byte PTBSE1 :1; /* Output Slew Rate Enable for Port B Bit 1 */ byte PTBSE2 :1; /* Output Slew Rate Enable for Port B Bit 2 */ byte PTBSE3 :1; /* Output Slew Rate Enable for Port B Bit 3 */ byte PTBSE4 :1; /* Output Slew Rate Enable for Port B Bit 4 */ byte PTBSE5 :1; /* Output Slew Rate Enable for Port B Bit 5 */ byte PTBSE6 :1; /* Output Slew Rate Enable for Port B Bit 6 */ byte PTBSE7 :1; /* Output Slew Rate Enable for Port B Bit 7 */ } Bits; struct { byte :1; byte grpPTBSE_1 :7; } MergedBits; } PTBSESTR; extern volatile PTBSESTR _PTBSE @0x00000207; #define PTBSE _PTBSE.Byte #define PTBSE_PTBSE1 _PTBSE.Bits.PTBSE1 #define PTBSE_PTBSE2 _PTBSE.Bits.PTBSE2 #define PTBSE_PTBSE3 _PTBSE.Bits.PTBSE3 #define PTBSE_PTBSE4 _PTBSE.Bits.PTBSE4 #define PTBSE_PTBSE5 _PTBSE.Bits.PTBSE5 #define PTBSE_PTBSE6 _PTBSE.Bits.PTBSE6 #define PTBSE_PTBSE7 _PTBSE.Bits.PTBSE7 #define PTBSE_PTBSE_1 _PTBSE.MergedBits.grpPTBSE_1 #define PTBSE_PTBSE1_MASK 2 #define PTBSE_PTBSE2_MASK 4 #define PTBSE_PTBSE3_MASK 8 #define PTBSE_PTBSE4_MASK 16 #define PTBSE_PTBSE5_MASK 32 #define PTBSE_PTBSE6_MASK 64 #define PTBSE_PTBSE7_MASK 128 #define PTBSE_PTBSE_1_MASK 254 #define PTBSE_PTBSE_1_BITNUM 1 /*** PTCPE - Port C Internal Pulling Device Enable Register; 0x00000208 ***/ typedef union { byte Byte; struct { byte PTCPE0 :1; /* Internal Pulling Device Enable for Port C Bit 0 */ byte PTCPE1 :1; /* Internal Pulling Device Enable for Port C Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTCPE :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTCPESTR; extern volatile PTCPESTR _PTCPE @0x00000208; #define PTCPE _PTCPE.Byte #define PTCPE_PTCPE0 _PTCPE.Bits.PTCPE0 #define PTCPE_PTCPE1 _PTCPE.Bits.PTCPE1 #define PTCPE_PTCPE _PTCPE.MergedBits.grpPTCPE #define PTCPE_PTCPE0_MASK 1 #define PTCPE_PTCPE1_MASK 2 #define PTCPE_PTCPE_MASK 3 #define PTCPE_PTCPE_BITNUM 0 /*** PTCPUD - Port C Pullup/Pulldown Control Register; 0x00000209 ***/ typedef union { byte Byte; struct { byte PTCPUD0 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte PTCPUD1 :1; /* Pullup/Pulldown Device Control for Port C Bit 0 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTCPUD :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTCPUDSTR; extern volatile PTCPUDSTR _PTCPUD @0x00000209; #define PTCPUD _PTCPUD.Byte #define PTCPUD_PTCPUD0 _PTCPUD.Bits.PTCPUD0 #define PTCPUD_PTCPUD1 _PTCPUD.Bits.PTCPUD1 #define PTCPUD_PTCPUD _PTCPUD.MergedBits.grpPTCPUD #define PTCPUD_PTCPUD0_MASK 1 #define PTCPUD_PTCPUD1_MASK 2 #define PTCPUD_PTCPUD_MASK 3 #define PTCPUD_PTCPUD_BITNUM 0 /*** PTCDS - Port C Drive Strength Selection Register; 0x0000020A ***/ typedef union { byte Byte; struct { byte PTCDS0 :1; /* Output Drive Strength Selection for Port C Bit 0 */ byte PTCDS1 :1; /* Output Drive Strength Selection for Port C Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTCDS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTCDSSTR; extern volatile PTCDSSTR _PTCDS @0x0000020A; #define PTCDS _PTCDS.Byte #define PTCDS_PTCDS0 _PTCDS.Bits.PTCDS0 #define PTCDS_PTCDS1 _PTCDS.Bits.PTCDS1 #define PTCDS_PTCDS _PTCDS.MergedBits.grpPTCDS #define PTCDS_PTCDS0_MASK 1 #define PTCDS_PTCDS1_MASK 2 #define PTCDS_PTCDS_MASK 3 #define PTCDS_PTCDS_BITNUM 0 /*** PTCSE - Port C Output Slew Rate Control Enable Register; 0x0000020B ***/ typedef union { byte Byte; struct { byte PTCSE0 :1; /* Output Slew Rate Enable for Port C Bit 0 */ byte PTCSE1 :1; /* Output Slew Rate Enable for Port C Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTCSE :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTCSESTR; extern volatile PTCSESTR _PTCSE @0x0000020B; #define PTCSE _PTCSE.Byte #define PTCSE_PTCSE0 _PTCSE.Bits.PTCSE0 #define PTCSE_PTCSE1 _PTCSE.Bits.PTCSE1 #define PTCSE_PTCSE _PTCSE.MergedBits.grpPTCSE #define PTCSE_PTCSE0_MASK 1 #define PTCSE_PTCSE1_MASK 2 #define PTCSE_PTCSE_MASK 3 #define PTCSE_PTCSE_BITNUM 0 /*** PTDPE - Port D Internal Pulling Device Enable Register; 0x0000020C ***/ typedef union { byte Byte; struct { byte PTDPE0 :1; /* Internal Pulling Device Enable for Port D Bit 0 */ byte PTDPE1 :1; /* Internal Pulling Device Enable for Port D Bit 1 */ byte PTDPE2 :1; /* Internal Pulling Device Enable for Port D Bit 2 */ byte PTDPE3 :1; /* Internal Pulling Device Enable for Port D Bit 3 */ byte PTDPE4 :1; /* Internal Pulling Device Enable for Port D Bit 4 */ byte PTDPE5 :1; /* Internal Pulling Device Enable for Port D Bit 5 */ byte PTDPE6 :1; /* Internal Pulling Device Enable for Port D Bit 6 */ byte PTDPE7 :1; /* Internal Pulling Device Enable for Port D Bit 7 */ } Bits; } PTDPESTR; extern volatile PTDPESTR _PTDPE @0x0000020C; #define PTDPE _PTDPE.Byte #define PTDPE_PTDPE0 _PTDPE.Bits.PTDPE0 #define PTDPE_PTDPE1 _PTDPE.Bits.PTDPE1 #define PTDPE_PTDPE2 _PTDPE.Bits.PTDPE2 #define PTDPE_PTDPE3 _PTDPE.Bits.PTDPE3 #define PTDPE_PTDPE4 _PTDPE.Bits.PTDPE4 #define PTDPE_PTDPE5 _PTDPE.Bits.PTDPE5 #define PTDPE_PTDPE6 _PTDPE.Bits.PTDPE6 #define PTDPE_PTDPE7 _PTDPE.Bits.PTDPE7 #define PTDPE_PTDPE0_MASK 1 #define PTDPE_PTDPE1_MASK 2 #define PTDPE_PTDPE2_MASK 4 #define PTDPE_PTDPE3_MASK 8 #define PTDPE_PTDPE4_MASK 16 #define PTDPE_PTDPE5_MASK 32 #define PTDPE_PTDPE6_MASK 64 #define PTDPE_PTDPE7_MASK 128 /*** PTDPUD - Port D Pullup/Pulldown Control Register; 0x0000020D ***/ typedef union { byte Byte; struct { byte PTDPUD0 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD1 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD2 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD3 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD4 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD5 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD6 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ byte PTDPUD7 :1; /* Pullup/Pulldown Device Control for Port D Bit 0 */ } Bits; } PTDPUDSTR; extern volatile PTDPUDSTR _PTDPUD @0x0000020D; #define PTDPUD _PTDPUD.Byte #define PTDPUD_PTDPUD0 _PTDPUD.Bits.PTDPUD0 #define PTDPUD_PTDPUD1 _PTDPUD.Bits.PTDPUD1 #define PTDPUD_PTDPUD2 _PTDPUD.Bits.PTDPUD2 #define PTDPUD_PTDPUD3 _PTDPUD.Bits.PTDPUD3 #define PTDPUD_PTDPUD4 _PTDPUD.Bits.PTDPUD4 #define PTDPUD_PTDPUD5 _PTDPUD.Bits.PTDPUD5 #define PTDPUD_PTDPUD6 _PTDPUD.Bits.PTDPUD6 #define PTDPUD_PTDPUD7 _PTDPUD.Bits.PTDPUD7 #define PTDPUD_PTDPUD0_MASK 1 #define PTDPUD_PTDPUD1_MASK 2 #define PTDPUD_PTDPUD2_MASK 4 #define PTDPUD_PTDPUD3_MASK 8 #define PTDPUD_PTDPUD4_MASK 16 #define PTDPUD_PTDPUD5_MASK 32 #define PTDPUD_PTDPUD6_MASK 64 #define PTDPUD_PTDPUD7_MASK 128 /*** PTDDS - Port D Drive Strength Selection Register; 0x0000020E ***/ typedef union { byte Byte; struct { byte PTDDS0 :1; /* Output Drive Strength Selection for Port D Bit 0 */ byte PTDDS1 :1; /* Output Drive Strength Selection for Port D Bit 1 */ byte PTDDS2 :1; /* Output Drive Strength Selection for Port D Bit 2 */ byte PTDDS3 :1; /* Output Drive Strength Selection for Port D Bit 3 */ byte PTDDS4 :1; /* Output Drive Strength Selection for Port D Bit 4 */ byte PTDDS5 :1; /* Output Drive Strength Selection for Port D Bit 5 */ byte PTDDS6 :1; /* Output Drive Strength Selection for Port D Bit 6 */ byte PTDDS7 :1; /* Output Drive Strength Selection for Port D Bit 7 */ } Bits; } PTDDSSTR; extern volatile PTDDSSTR _PTDDS @0x0000020E; #define PTDDS _PTDDS.Byte #define PTDDS_PTDDS0 _PTDDS.Bits.PTDDS0 #define PTDDS_PTDDS1 _PTDDS.Bits.PTDDS1 #define PTDDS_PTDDS2 _PTDDS.Bits.PTDDS2 #define PTDDS_PTDDS3 _PTDDS.Bits.PTDDS3 #define PTDDS_PTDDS4 _PTDDS.Bits.PTDDS4 #define PTDDS_PTDDS5 _PTDDS.Bits.PTDDS5 #define PTDDS_PTDDS6 _PTDDS.Bits.PTDDS6 #define PTDDS_PTDDS7 _PTDDS.Bits.PTDDS7 #define PTDDS_PTDDS0_MASK 1 #define PTDDS_PTDDS1_MASK 2 #define PTDDS_PTDDS2_MASK 4 #define PTDDS_PTDDS3_MASK 8 #define PTDDS_PTDDS4_MASK 16 #define PTDDS_PTDDS5_MASK 32 #define PTDDS_PTDDS6_MASK 64 #define PTDDS_PTDDS7_MASK 128 /*** PTDSE - Port D Output Slew Rate Control Enable Register; 0x0000020F ***/ typedef union { byte Byte; struct { byte PTDSE0 :1; /* Output Slew Rate Enable for Port D Bit 0 */ byte PTDSE1 :1; /* Output Slew Rate Enable for Port D Bit 1 */ byte PTDSE2 :1; /* Output Slew Rate Enable for Port D Bit 2 */ byte PTDSE3 :1; /* Output Slew Rate Enable for Port D Bit 3 */ byte PTDSE4 :1; /* Output Slew Rate Enable for Port D Bit 4 */ byte PTDSE5 :1; /* Output Slew Rate Enable for Port D Bit 5 */ byte PTDSE6 :1; /* Output Slew Rate Enable for Port D Bit 6 */ byte PTDSE7 :1; /* Output Slew Rate Enable for Port D Bit 7 */ } Bits; } PTDSESTR; extern volatile PTDSESTR _PTDSE @0x0000020F; #define PTDSE _PTDSE.Byte #define PTDSE_PTDSE0 _PTDSE.Bits.PTDSE0 #define PTDSE_PTDSE1 _PTDSE.Bits.PTDSE1 #define PTDSE_PTDSE2 _PTDSE.Bits.PTDSE2 #define PTDSE_PTDSE3 _PTDSE.Bits.PTDSE3 #define PTDSE_PTDSE4 _PTDSE.Bits.PTDSE4 #define PTDSE_PTDSE5 _PTDSE.Bits.PTDSE5 #define PTDSE_PTDSE6 _PTDSE.Bits.PTDSE6 #define PTDSE_PTDSE7 _PTDSE.Bits.PTDSE7 #define PTDSE_PTDSE0_MASK 1 #define PTDSE_PTDSE1_MASK 2 #define PTDSE_PTDSE2_MASK 4 #define PTDSE_PTDSE3_MASK 8 #define PTDSE_PTDSE4_MASK 16 #define PTDSE_PTDSE5_MASK 32 #define PTDSE_PTDSE6_MASK 64 #define PTDSE_PTDSE7_MASK 128 /*** SCIBD - SCI Baud Rate Register; 0x00000210 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SCIBDH - SCI Baud Rate Register High; 0x00000210 ***/ union { byte Byte; struct { byte SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ byte SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ byte SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ byte SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ byte SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ byte :1; byte RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ byte LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { byte grpSBR_8 :5; byte :1; byte :1; byte :1; } MergedBits; } SCIBDHSTR; #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8 #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9 #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10 #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11 #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12 #define SCIBDH_RXEDGIE _SCIBD.Overlap_STR.SCIBDHSTR.Bits.RXEDGIE #define SCIBDH_LBKDIE _SCIBD.Overlap_STR.SCIBDHSTR.Bits.LBKDIE #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8 #define SCIBDH_SBR SCIBDH_SBR_8 #define SCIBDH_SBR8_MASK 1 #define SCIBDH_SBR9_MASK 2 #define SCIBDH_SBR10_MASK 4 #define SCIBDH_SBR11_MASK 8 #define SCIBDH_SBR12_MASK 16 #define SCIBDH_RXEDGIE_MASK 64 #define SCIBDH_LBKDIE_MASK 128 #define SCIBDH_SBR_8_MASK 31 #define SCIBDH_SBR_8_BITNUM 0 /*** SCIBDL - SCI Baud Rate Register Low; 0x00000211 ***/ union { byte Byte; struct { byte SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ byte SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ byte SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ byte SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ byte SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ byte SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ byte SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ byte SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ } Bits; } SCIBDLSTR; #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0 #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1 #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2 #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3 #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4 #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5 #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6 #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7 #define SCIBDL_SBR0_MASK 1 #define SCIBDL_SBR1_MASK 2 #define SCIBDL_SBR2_MASK 4 #define SCIBDL_SBR3_MASK 8 #define SCIBDL_SBR4_MASK 16 #define SCIBDL_SBR5_MASK 32 #define SCIBDL_SBR6_MASK 64 #define SCIBDL_SBR7_MASK 128 } Overlap_STR; } SCIBDSTR; extern volatile SCIBDSTR _SCIBD @0x00000210; #define SCIBD _SCIBD.Word /*** SCIC1 - SCI Control Register 1; 0x00000212 ***/ typedef union { byte Byte; struct { byte PT :1; /* Parity Type */ byte PE :1; /* Parity Enable */ byte ILT :1; /* Idle Line Type Select */ byte WAKE :1; /* Receiver Wakeup Method Select */ byte M :1; /* 9-Bit or 8-Bit Mode Select */ byte RSRC :1; /* Receiver Source Select */ byte SCISWAI :1; /* SCI Stops in Wait Mode */ byte LOOPS :1; /* Loop Mode Select */ } Bits; } SCIC1STR; extern volatile SCIC1STR _SCIC1 @0x00000212; #define SCIC1 _SCIC1.Byte #define SCIC1_PT _SCIC1.Bits.PT #define SCIC1_PE _SCIC1.Bits.PE #define SCIC1_ILT _SCIC1.Bits.ILT #define SCIC1_WAKE _SCIC1.Bits.WAKE #define SCIC1_M _SCIC1.Bits.M #define SCIC1_RSRC _SCIC1.Bits.RSRC #define SCIC1_SCISWAI _SCIC1.Bits.SCISWAI #define SCIC1_LOOPS _SCIC1.Bits.LOOPS #define SCIC1_PT_MASK 1 #define SCIC1_PE_MASK 2 #define SCIC1_ILT_MASK 4 #define SCIC1_WAKE_MASK 8 #define SCIC1_M_MASK 16 #define SCIC1_RSRC_MASK 32 #define SCIC1_SCISWAI_MASK 64 #define SCIC1_LOOPS_MASK 128 /*** SCIC2 - SCI Control Register 2; 0x00000213 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break */ byte RWU :1; /* Receiver Wakeup Control */ byte RE :1; /* Receiver Enable */ byte TE :1; /* Transmitter Enable */ byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */ byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */ byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */ byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */ } Bits; } SCIC2STR; extern volatile SCIC2STR _SCIC2 @0x00000213; #define SCIC2 _SCIC2.Byte #define SCIC2_SBK _SCIC2.Bits.SBK #define SCIC2_RWU _SCIC2.Bits.RWU #define SCIC2_RE _SCIC2.Bits.RE #define SCIC2_TE _SCIC2.Bits.TE #define SCIC2_ILIE _SCIC2.Bits.ILIE #define SCIC2_RIE _SCIC2.Bits.RIE #define SCIC2_TCIE _SCIC2.Bits.TCIE #define SCIC2_TIE _SCIC2.Bits.TIE #define SCIC2_SBK_MASK 1 #define SCIC2_RWU_MASK 2 #define SCIC2_RE_MASK 4 #define SCIC2_TE_MASK 8 #define SCIC2_ILIE_MASK 16 #define SCIC2_RIE_MASK 32 #define SCIC2_TCIE_MASK 64 #define SCIC2_TIE_MASK 128 /*** SCIS1 - SCI Status Register 1; 0x00000214 ***/ typedef union { byte Byte; struct { byte PF :1; /* Parity Error Flag */ byte FE :1; /* Framing Error Flag */ byte NF :1; /* Noise Flag */ byte OR :1; /* Receiver Overrun Flag */ byte IDLE :1; /* Idle Line Flag */ byte RDRF :1; /* Receive Data Register Full Flag */ byte TC :1; /* Transmission Complete Flag */ byte TDRE :1; /* Transmit Data Register Empty Flag */ } Bits; } SCIS1STR; extern volatile SCIS1STR _SCIS1 @0x00000214; #define SCIS1 _SCIS1.Byte #define SCIS1_PF _SCIS1.Bits.PF #define SCIS1_FE _SCIS1.Bits.FE #define SCIS1_NF _SCIS1.Bits.NF #define SCIS1_OR _SCIS1.Bits.OR #define SCIS1_IDLE _SCIS1.Bits.IDLE #define SCIS1_RDRF _SCIS1.Bits.RDRF #define SCIS1_TC _SCIS1.Bits.TC #define SCIS1_TDRE _SCIS1.Bits.TDRE #define SCIS1_PF_MASK 1 #define SCIS1_FE_MASK 2 #define SCIS1_NF_MASK 4 #define SCIS1_OR_MASK 8 #define SCIS1_IDLE_MASK 16 #define SCIS1_RDRF_MASK 32 #define SCIS1_TC_MASK 64 #define SCIS1_TDRE_MASK 128 /*** SCIS2 - SCI Status Register 2; 0x00000215 ***/ typedef union { byte Byte; struct { byte RAF :1; /* Receiver Active Flag */ byte LBKDE :1; /* LIN Break Detection Enable */ byte BRK13 :1; /* Break Character Generation Length */ byte RWUID :1; /* Receive Wake Up Idle Detect */ byte RXINV :1; /* Receive Data Inversion */ byte :1; byte RXEDGIF :1; /* RxD Pin Active Edge Interrupt Flag */ byte LBKDIF :1; /* LIN Break Detect Interrupt Flag */ } Bits; } SCIS2STR; extern volatile SCIS2STR _SCIS2 @0x00000215; #define SCIS2 _SCIS2.Byte #define SCIS2_RAF _SCIS2.Bits.RAF #define SCIS2_LBKDE _SCIS2.Bits.LBKDE #define SCIS2_BRK13 _SCIS2.Bits.BRK13 #define SCIS2_RWUID _SCIS2.Bits.RWUID #define SCIS2_RXINV _SCIS2.Bits.RXINV #define SCIS2_RXEDGIF _SCIS2.Bits.RXEDGIF #define SCIS2_LBKDIF _SCIS2.Bits.LBKDIF #define SCIS2_RAF_MASK 1 #define SCIS2_LBKDE_MASK 2 #define SCIS2_BRK13_MASK 4 #define SCIS2_RWUID_MASK 8 #define SCIS2_RXINV_MASK 16 #define SCIS2_RXEDGIF_MASK 64 #define SCIS2_LBKDIF_MASK 128 /*** SCIC3 - SCI Control Register 3; 0x00000216 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Parity Error Interrupt Enable */ byte FEIE :1; /* Framing Error Interrupt Enable */ byte NEIE :1; /* Noise Error Interrupt Enable */ byte ORIE :1; /* Overrun Interrupt Enable */ byte TXINV :1; /* Transmit Data Inversion */ byte TXDIR :1; /* TxD Pin Direction in Single-Wire Mode */ byte T8 :1; /* Ninth Data Bit for Transmitter */ byte R8 :1; /* Ninth Data Bit for Receiver */ } Bits; } SCIC3STR; extern volatile SCIC3STR _SCIC3 @0x00000216; #define SCIC3 _SCIC3.Byte #define SCIC3_PEIE _SCIC3.Bits.PEIE #define SCIC3_FEIE _SCIC3.Bits.FEIE #define SCIC3_NEIE _SCIC3.Bits.NEIE #define SCIC3_ORIE _SCIC3.Bits.ORIE #define SCIC3_TXINV _SCIC3.Bits.TXINV #define SCIC3_TXDIR _SCIC3.Bits.TXDIR #define SCIC3_T8 _SCIC3.Bits.T8 #define SCIC3_R8 _SCIC3.Bits.R8 #define SCIC3_PEIE_MASK 1 #define SCIC3_FEIE_MASK 2 #define SCIC3_NEIE_MASK 4 #define SCIC3_ORIE_MASK 8 #define SCIC3_TXINV_MASK 16 #define SCIC3_TXDIR_MASK 32 #define SCIC3_T8_MASK 64 #define SCIC3_R8_MASK 128 /*** SCID - SCI Data Register; 0x00000217 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCIDSTR; extern volatile SCIDSTR _SCID @0x00000217; #define SCID _SCID.Byte #define SCID_R0_T0 _SCID.Bits.R0_T0 #define SCID_R1_T1 _SCID.Bits.R1_T1 #define SCID_R2_T2 _SCID.Bits.R2_T2 #define SCID_R3_T3 _SCID.Bits.R3_T3 #define SCID_R4_T4 _SCID.Bits.R4_T4 #define SCID_R5_T5 _SCID.Bits.R5_T5 #define SCID_R6_T6 _SCID.Bits.R6_T6 #define SCID_R7_T7 _SCID.Bits.R7_T7 #define SCID_R0_T0_MASK 1 #define SCID_R1_T1_MASK 2 #define SCID_R2_T2_MASK 4 #define SCID_R3_T3_MASK 8 #define SCID_R4_T4_MASK 16 #define SCID_R5_T5_MASK 32 #define SCID_R6_T6_MASK 64 #define SCID_R7_T7_MASK 128 /*** SDID - System Device Identification Register; 0x0000021A ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SDIDH - System Device Identification Register High; 0x0000021A ***/ union { byte Byte; struct { byte ID8 :1; /* Part Identification Number, bit 8 */ byte ID9 :1; /* Part Identification Number, bit 9 */ byte ID10 :1; /* Part Identification Number, bit 10 */ byte ID11 :1; /* Part Identification Number, bit 11 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpID_8 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SDIDHSTR; #define SDIDH _SDID.Overlap_STR.SDIDHSTR.Byte #define SDIDH_ID8 _SDID.Overlap_STR.SDIDHSTR.Bits.ID8 #define SDIDH_ID9 _SDID.Overlap_STR.SDIDHSTR.Bits.ID9 #define SDIDH_ID10 _SDID.Overlap_STR.SDIDHSTR.Bits.ID10 #define SDIDH_ID11 _SDID.Overlap_STR.SDIDHSTR.Bits.ID11 #define SDIDH_ID_8 _SDID.Overlap_STR.SDIDHSTR.MergedBits.grpID_8 #define SDIDH_ID SDIDH_ID_8 #define SDIDH_ID8_MASK 1 #define SDIDH_ID9_MASK 2 #define SDIDH_ID10_MASK 4 #define SDIDH_ID11_MASK 8 #define SDIDH_ID_8_MASK 15 #define SDIDH_ID_8_BITNUM 0 /*** SDIDL - System Device Identification Register Low; 0x0000021B ***/ union { byte Byte; struct { byte ID0 :1; /* Part Identification Number, bit 0 */ byte ID1 :1; /* Part Identification Number, bit 1 */ byte ID2 :1; /* Part Identification Number, bit 2 */ byte ID3 :1; /* Part Identification Number, bit 3 */ byte ID4 :1; /* Part Identification Number, bit 4 */ byte ID5 :1; /* Part Identification Number, bit 5 */ byte ID6 :1; /* Part Identification Number, bit 6 */ byte ID7 :1; /* Part Identification Number, bit 7 */ } Bits; } SDIDLSTR; #define SDIDL _SDID.Overlap_STR.SDIDLSTR.Byte #define SDIDL_ID0 _SDID.Overlap_STR.SDIDLSTR.Bits.ID0 #define SDIDL_ID1 _SDID.Overlap_STR.SDIDLSTR.Bits.ID1 #define SDIDL_ID2 _SDID.Overlap_STR.SDIDLSTR.Bits.ID2 #define SDIDL_ID3 _SDID.Overlap_STR.SDIDLSTR.Bits.ID3 #define SDIDL_ID4 _SDID.Overlap_STR.SDIDLSTR.Bits.ID4 #define SDIDL_ID5 _SDID.Overlap_STR.SDIDLSTR.Bits.ID5 #define SDIDL_ID6 _SDID.Overlap_STR.SDIDLSTR.Bits.ID6 #define SDIDL_ID7 _SDID.Overlap_STR.SDIDLSTR.Bits.ID7 #define SDIDL_ID0_MASK 1 #define SDIDL_ID1_MASK 2 #define SDIDL_ID2_MASK 4 #define SDIDL_ID3_MASK 8 #define SDIDL_ID4_MASK 16 #define SDIDL_ID5_MASK 32 #define SDIDL_ID6_MASK 64 #define SDIDL_ID7_MASK 128 } Overlap_STR; } SDIDSTR; extern volatile SDIDSTR _SDID @0x0000021A; #define SDID _SDID.Word /*** SRTISC - System Real-Time Interrupt Status and Control Register; 0x0000021C ***/ typedef union { byte Byte; struct { byte RTIS0 :1; /* Real-Time Interrupt Delay Selects, bit 0 */ byte RTIS1 :1; /* Real-Time Interrupt Delay Selects, bit 1 */ byte RTIS2 :1; /* Real-Time Interrupt Delay Selects, bit 2 */ byte :1; byte RTIE :1; /* Real-Time Interrupt Enable */ byte RTICLKS :1; /* Real-Time Interrupt Clock Select */ byte RTIACK :1; /* Real-Time Interrupt Acknowledge */ byte RTIF :1; /* Real-Time Interrupt Flag */ } Bits; struct { byte grpRTIS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SRTISCSTR; extern volatile SRTISCSTR _SRTISC @0x0000021C; #define SRTISC _SRTISC.Byte #define SRTISC_RTIS0 _SRTISC.Bits.RTIS0 #define SRTISC_RTIS1 _SRTISC.Bits.RTIS1 #define SRTISC_RTIS2 _SRTISC.Bits.RTIS2 #define SRTISC_RTIE _SRTISC.Bits.RTIE #define SRTISC_RTICLKS _SRTISC.Bits.RTICLKS #define SRTISC_RTIACK _SRTISC.Bits.RTIACK #define SRTISC_RTIF _SRTISC.Bits.RTIF #define SRTISC_RTIS _SRTISC.MergedBits.grpRTIS #define SRTISC_RTIS0_MASK 1 #define SRTISC_RTIS1_MASK 2 #define SRTISC_RTIS2_MASK 4 #define SRTISC_RTIE_MASK 16 #define SRTISC_RTICLKS_MASK 32 #define SRTISC_RTIACK_MASK 64 #define SRTISC_RTIF_MASK 128 #define SRTISC_RTIS_MASK 7 #define SRTISC_RTIS_BITNUM 0 /*** SPMSC1 - System Power Management Status and Control Register; 0x0000021D ***/ typedef union { byte Byte; struct { byte BGBE :1; /* Bandgap Buffer Enable */ byte :1; byte LVDE :1; /* Low-Voltage Detect Enable */ byte LVDSE :1; /* Low-Voltage Detect Stop Enable */ byte LVDRE :1; /* Low-Voltage Detect Reset Enable */ byte LVDIE :1; /* Low-Voltage Detect Interrupt Enable */ byte LVDACK :1; /* Low-Voltage Detect Acknowledge */ byte LVDF :1; /* Low-Voltage Detect Flag */ } Bits; } SPMSC1STR; extern volatile SPMSC1STR _SPMSC1 @0x0000021D; #define SPMSC1 _SPMSC1.Byte #define SPMSC1_BGBE _SPMSC1.Bits.BGBE #define SPMSC1_LVDE _SPMSC1.Bits.LVDE #define SPMSC1_LVDSE _SPMSC1.Bits.LVDSE #define SPMSC1_LVDRE _SPMSC1.Bits.LVDRE #define SPMSC1_LVDIE _SPMSC1.Bits.LVDIE #define SPMSC1_LVDACK _SPMSC1.Bits.LVDACK #define SPMSC1_LVDF _SPMSC1.Bits.LVDF #define SPMSC1_BGBE_MASK 1 #define SPMSC1_LVDE_MASK 4 #define SPMSC1_LVDSE_MASK 8 #define SPMSC1_LVDRE_MASK 16 #define SPMSC1_LVDIE_MASK 32 #define SPMSC1_LVDACK_MASK 64 #define SPMSC1_LVDF_MASK 128 /*** TPM1SC - TPM1 Status and Control Register; 0x00000220 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescale Divisor Select Bit 0 */ byte PS1 :1; /* Prescale Divisor Select Bit 1 */ byte PS2 :1; /* Prescale Divisor Select Bit 2 */ byte CLKSA :1; /* Clock Source Select A */ byte CLKSB :1; /* Clock Source Select B */ byte CPWMS :1; /* Center-Aligned PWM Select */ byte TOIE :1; /* Timer Overflow Interrupt Enable */ byte TOF :1; /* Timer Overflow Flag */ } Bits; struct { byte grpPS :3; byte grpCLKSx :2; byte :1; byte :1; byte :1; } MergedBits; } TPM1SCSTR; extern volatile TPM1SCSTR _TPM1SC @0x00000220; #define TPM1SC _TPM1SC.Byte #define TPM1SC_PS0 _TPM1SC.Bits.PS0 #define TPM1SC_PS1 _TPM1SC.Bits.PS1 #define TPM1SC_PS2 _TPM1SC.Bits.PS2 #define TPM1SC_CLKSA _TPM1SC.Bits.CLKSA #define TPM1SC_CLKSB _TPM1SC.Bits.CLKSB #define TPM1SC_CPWMS _TPM1SC.Bits.CPWMS #define TPM1SC_TOIE _TPM1SC.Bits.TOIE #define TPM1SC_TOF _TPM1SC.Bits.TOF #define TPM1SC_PS _TPM1SC.MergedBits.grpPS #define TPM1SC_CLKSx _TPM1SC.MergedBits.grpCLKSx #define TPM1SC_PS0_MASK 1 #define TPM1SC_PS1_MASK 2 #define TPM1SC_PS2_MASK 4 #define TPM1SC_CLKSA_MASK 8 #define TPM1SC_CLKSB_MASK 16 #define TPM1SC_CPWMS_MASK 32 #define TPM1SC_TOIE_MASK 64 #define TPM1SC_TOF_MASK 128 #define TPM1SC_PS_MASK 7 #define TPM1SC_PS_BITNUM 0 #define TPM1SC_CLKSx_MASK 24 #define TPM1SC_CLKSx_BITNUM 3 /*** TPM1CNT - TPM1 Timer Counter Register; 0x00000221 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM1CNTH - TPM1 Timer Counter Register High; 0x00000221 ***/ union { byte Byte; } TPM1CNTHSTR; #define TPM1CNTH _TPM1CNT.Overlap_STR.TPM1CNTHSTR.Byte /*** TPM1CNTL - TPM1 Timer Counter Register Low; 0x00000222 ***/ union { byte Byte; } TPM1CNTLSTR; #define TPM1CNTL _TPM1CNT.Overlap_STR.TPM1CNTLSTR.Byte } Overlap_STR; } TPM1CNTSTR; extern volatile TPM1CNTSTR _TPM1CNT @0x00000221; #define TPM1CNT _TPM1CNT.Word /*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0x00000223 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0x00000223 ***/ union { byte Byte; } TPM1MODHSTR; #define TPM1MODH _TPM1MOD.Overlap_STR.TPM1MODHSTR.Byte /*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0x00000224 ***/ union { byte Byte; } TPM1MODLSTR; #define TPM1MODL _TPM1MOD.Overlap_STR.TPM1MODLSTR.Byte } Overlap_STR; } TPM1MODSTR; extern volatile TPM1MODSTR _TPM1MOD @0x00000223; #define TPM1MOD _TPM1MOD.Word /*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000225 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select A for TPM Channel 0 */ byte MS0B :1; /* Mode Select B for TPM Channel 0 */ byte CH0IE :1; /* Channel 0 Interrupt Enable */ byte CH0F :1; /* Channel 0 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TPM1C0SCSTR; extern volatile TPM1C0SCSTR _TPM1C0SC @0x00000225; #define TPM1C0SC _TPM1C0SC.Byte #define TPM1C0SC_ELS0A _TPM1C0SC.Bits.ELS0A #define TPM1C0SC_ELS0B _TPM1C0SC.Bits.ELS0B #define TPM1C0SC_MS0A _TPM1C0SC.Bits.MS0A #define TPM1C0SC_MS0B _TPM1C0SC.Bits.MS0B #define TPM1C0SC_CH0IE _TPM1C0SC.Bits.CH0IE #define TPM1C0SC_CH0F _TPM1C0SC.Bits.CH0F #define TPM1C0SC_ELS0x _TPM1C0SC.MergedBits.grpELS0x #define TPM1C0SC_MS0x _TPM1C0SC.MergedBits.grpMS0x #define TPM1C0SC_ELS0A_MASK 4 #define TPM1C0SC_ELS0B_MASK 8 #define TPM1C0SC_MS0A_MASK 16 #define TPM1C0SC_MS0B_MASK 32 #define TPM1C0SC_CH0IE_MASK 64 #define TPM1C0SC_CH0F_MASK 128 #define TPM1C0SC_ELS0x_MASK 12 #define TPM1C0SC_ELS0x_BITNUM 2 #define TPM1C0SC_MS0x_MASK 48 #define TPM1C0SC_MS0x_BITNUM 4 /*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0x00000226 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM1C0VH - TPM1 Timer Channel 0 Value Register High; 0x00000226 ***/ union { byte Byte; } TPM1C0VHSTR; #define TPM1C0VH _TPM1C0V.Overlap_STR.TPM1C0VHSTR.Byte /*** TPM1C0VL - TPM1 Timer Channel 0 Value Register Low; 0x00000227 ***/ union { byte Byte; } TPM1C0VLSTR; #define TPM1C0VL _TPM1C0V.Overlap_STR.TPM1C0VLSTR.Byte } Overlap_STR; } TPM1C0VSTR; extern volatile TPM1C0VSTR _TPM1C0V @0x00000226; #define TPM1C0V _TPM1C0V.Word /*** TPM1C1SC - TPM1 Timer Channel 1 Status and Control Register; 0x00000228 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select A for TPM Channel 1 */ byte MS1B :1; /* Mode Select B for TPM Channel 1 */ byte CH1IE :1; /* Channel 1 Interrupt Enable */ byte CH1F :1; /* Channel 1 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS1x :2; byte grpMS1x :2; byte :1; byte :1; } MergedBits; } TPM1C1SCSTR; extern volatile TPM1C1SCSTR _TPM1C1SC @0x00000228; #define TPM1C1SC _TPM1C1SC.Byte #define TPM1C1SC_ELS1A _TPM1C1SC.Bits.ELS1A #define TPM1C1SC_ELS1B _TPM1C1SC.Bits.ELS1B #define TPM1C1SC_MS1A _TPM1C1SC.Bits.MS1A #define TPM1C1SC_MS1B _TPM1C1SC.Bits.MS1B #define TPM1C1SC_CH1IE _TPM1C1SC.Bits.CH1IE #define TPM1C1SC_CH1F _TPM1C1SC.Bits.CH1F #define TPM1C1SC_ELS1x _TPM1C1SC.MergedBits.grpELS1x #define TPM1C1SC_MS1x _TPM1C1SC.MergedBits.grpMS1x #define TPM1C1SC_ELS1A_MASK 4 #define TPM1C1SC_ELS1B_MASK 8 #define TPM1C1SC_MS1A_MASK 16 #define TPM1C1SC_MS1B_MASK 32 #define TPM1C1SC_CH1IE_MASK 64 #define TPM1C1SC_CH1F_MASK 128 #define TPM1C1SC_ELS1x_MASK 12 #define TPM1C1SC_ELS1x_BITNUM 2 #define TPM1C1SC_MS1x_MASK 48 #define TPM1C1SC_MS1x_BITNUM 4 /*** TPM1C1V - TPM1 Timer Channel 1 Value Register; 0x00000229 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM1C1VH - TPM1 Timer Channel 1 Value Register High; 0x00000229 ***/ union { byte Byte; } TPM1C1VHSTR; #define TPM1C1VH _TPM1C1V.Overlap_STR.TPM1C1VHSTR.Byte /*** TPM1C1VL - TPM1 Timer Channel 1 Value Register Low; 0x0000022A ***/ union { byte Byte; } TPM1C1VLSTR; #define TPM1C1VL _TPM1C1V.Overlap_STR.TPM1C1VLSTR.Byte } Overlap_STR; } TPM1C1VSTR; extern volatile TPM1C1VSTR _TPM1C1V @0x00000229; #define TPM1C1V _TPM1C1V.Word /*** ICSC1 - ICS Control Register 1; 0x0000022C ***/ typedef union { byte Byte; struct { byte IREFSTEN :1; /* Internal Reference Stop Enable */ byte IRCLKEN :1; /* Internal Reference Clock Enable */ byte IREFS :1; /* Internal Reference Select */ byte RDIV :3; /* Reference Divider */ byte CLKS :2; /* Clock Source Select */ } Bits; } ICSC1STR; extern volatile ICSC1STR _ICSC1 @0x0000022C; #define ICSC1 _ICSC1.Byte #define ICSC1_IREFSTEN _ICSC1.Bits.IREFSTEN #define ICSC1_IRCLKEN _ICSC1.Bits.IRCLKEN #define ICSC1_IREFS _ICSC1.Bits.IREFS #define ICSC1_RDIV _ICSC1.Bits.RDIV #define ICSC1_CLKS _ICSC1.Bits.CLKS #define ICSC1_IREFSTEN_MASK 1 #define ICSC1_IRCLKEN_MASK 2 #define ICSC1_IREFS_MASK 4 #define ICSC1_RDIV_MASK 56 #define ICSC1_RDIV_BITNUM 3 #define ICSC1_CLKS_MASK 192 #define ICSC1_CLKS_BITNUM 6 /*** ICSC2 - ICS Control Register 2; 0x0000022D ***/ typedef union { byte Byte; struct { byte EREFSTEN :1; /* External Reference Stop Enable */ byte ERCLKEN :1; /* External Reference Enable */ byte EREFS :1; /* External Reference Select */ byte LP :1; /* Low Power Select */ byte HGO :1; /* High Gain Oscillator Select */ byte RANGE :1; /* Frequency Range Select */ byte BDIV :2; /* Bus Frequency Divider */ } Bits; } ICSC2STR; extern volatile ICSC2STR _ICSC2 @0x0000022D; #define ICSC2 _ICSC2.Byte #define ICSC2_EREFSTEN _ICSC2.Bits.EREFSTEN #define ICSC2_ERCLKEN _ICSC2.Bits.ERCLKEN #define ICSC2_EREFS _ICSC2.Bits.EREFS #define ICSC2_LP _ICSC2.Bits.LP #define ICSC2_HGO _ICSC2.Bits.HGO #define ICSC2_RANGE _ICSC2.Bits.RANGE #define ICSC2_BDIV _ICSC2.Bits.BDIV #define ICSC2_EREFSTEN_MASK 1 #define ICSC2_ERCLKEN_MASK 2 #define ICSC2_EREFS_MASK 4 #define ICSC2_LP_MASK 8 #define ICSC2_HGO_MASK 16 #define ICSC2_RANGE_MASK 32 #define ICSC2_BDIV_MASK 192 #define ICSC2_BDIV_BITNUM 6 /*** ICSTRM - ICS Trim Register; 0x0000022E ***/ typedef union { byte Byte; struct { byte TRIM :8; /* ICS Trim Setting */ } Bits; } ICSTRMSTR; extern volatile ICSTRMSTR _ICSTRM @0x0000022E; #define ICSTRM _ICSTRM.Byte #define ICSTRM_TRIM _ICSTRM.Bits.TRIM #define ICSTRM_TRIM_MASK 255 #define ICSTRM_TRIM_BITNUM 0 /*** ICSSC - ICS Status and Control Register; 0x0000022F ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte OSCINIT :1; /* OSC Initialization */ byte CLKST :2; /* Clock Mode Status */ byte :1; byte :1; byte :1; byte :1; } Bits; } ICSSCSTR; extern volatile ICSSCSTR _ICSSC @0x0000022F; #define ICSSC _ICSSC.Byte #define ICSSC_FTRIM _ICSSC.Bits.FTRIM #define ICSSC_OSCINIT _ICSSC.Bits.OSCINIT #define ICSSC_CLKST _ICSSC.Bits.CLKST #define ICSSC_FTRIM_MASK 1 #define ICSSC_OSCINIT_MASK 2 #define ICSSC_CLKST_MASK 12 #define ICSSC_CLKST_BITNUM 2 /*** TPM2SC - TPM2 Status and Control Register; 0x00000230 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescale Divisor Select Bit 0 */ byte PS1 :1; /* Prescale Divisor Select Bit 1 */ byte PS2 :1; /* Prescale Divisor Select Bit 2 */ byte CLKSA :1; /* Clock Source Select A */ byte CLKSB :1; /* Clock Source Select B */ byte CPWMS :1; /* Center-Aligned PWM Select */ byte TOIE :1; /* Timer Overflow Interrupt Enable */ byte TOF :1; /* Timer Overflow Flag */ } Bits; struct { byte grpPS :3; byte grpCLKSx :2; byte :1; byte :1; byte :1; } MergedBits; } TPM2SCSTR; extern volatile TPM2SCSTR _TPM2SC @0x00000230; #define TPM2SC _TPM2SC.Byte #define TPM2SC_PS0 _TPM2SC.Bits.PS0 #define TPM2SC_PS1 _TPM2SC.Bits.PS1 #define TPM2SC_PS2 _TPM2SC.Bits.PS2 #define TPM2SC_CLKSA _TPM2SC.Bits.CLKSA #define TPM2SC_CLKSB _TPM2SC.Bits.CLKSB #define TPM2SC_CPWMS _TPM2SC.Bits.CPWMS #define TPM2SC_TOIE _TPM2SC.Bits.TOIE #define TPM2SC_TOF _TPM2SC.Bits.TOF #define TPM2SC_PS _TPM2SC.MergedBits.grpPS #define TPM2SC_CLKSx _TPM2SC.MergedBits.grpCLKSx #define TPM2SC_PS0_MASK 1 #define TPM2SC_PS1_MASK 2 #define TPM2SC_PS2_MASK 4 #define TPM2SC_CLKSA_MASK 8 #define TPM2SC_CLKSB_MASK 16 #define TPM2SC_CPWMS_MASK 32 #define TPM2SC_TOIE_MASK 64 #define TPM2SC_TOF_MASK 128 #define TPM2SC_PS_MASK 7 #define TPM2SC_PS_BITNUM 0 #define TPM2SC_CLKSx_MASK 24 #define TPM2SC_CLKSx_BITNUM 3 /*** TPM2CNT - TPM2 Timer Counter Register; 0x00000231 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM2CNTH - TPM2 Timer Counter Register High; 0x00000231 ***/ union { byte Byte; } TPM2CNTHSTR; #define TPM2CNTH _TPM2CNT.Overlap_STR.TPM2CNTHSTR.Byte /*** TPM2CNTL - TPM2 Timer Counter Register Low; 0x00000232 ***/ union { byte Byte; } TPM2CNTLSTR; #define TPM2CNTL _TPM2CNT.Overlap_STR.TPM2CNTLSTR.Byte } Overlap_STR; } TPM2CNTSTR; extern volatile TPM2CNTSTR _TPM2CNT @0x00000231; #define TPM2CNT _TPM2CNT.Word /*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000233 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0x00000233 ***/ union { byte Byte; } TPM2MODHSTR; #define TPM2MODH _TPM2MOD.Overlap_STR.TPM2MODHSTR.Byte /*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0x00000234 ***/ union { byte Byte; } TPM2MODLSTR; #define TPM2MODL _TPM2MOD.Overlap_STR.TPM2MODLSTR.Byte } Overlap_STR; } TPM2MODSTR; extern volatile TPM2MODSTR _TPM2MOD @0x00000233; #define TPM2MOD _TPM2MOD.Word /*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0x00000235 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select A for TPM Channel 0 */ byte MS0B :1; /* Mode Select B for TPM Channel 0 */ byte CH0IE :1; /* Channel 0 Interrupt Enable */ byte CH0F :1; /* Channel 0 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TPM2C0SCSTR; extern volatile TPM2C0SCSTR _TPM2C0SC @0x00000235; #define TPM2C0SC _TPM2C0SC.Byte #define TPM2C0SC_ELS0A _TPM2C0SC.Bits.ELS0A #define TPM2C0SC_ELS0B _TPM2C0SC.Bits.ELS0B #define TPM2C0SC_MS0A _TPM2C0SC.Bits.MS0A #define TPM2C0SC_MS0B _TPM2C0SC.Bits.MS0B #define TPM2C0SC_CH0IE _TPM2C0SC.Bits.CH0IE #define TPM2C0SC_CH0F _TPM2C0SC.Bits.CH0F #define TPM2C0SC_ELS0x _TPM2C0SC.MergedBits.grpELS0x #define TPM2C0SC_MS0x _TPM2C0SC.MergedBits.grpMS0x #define TPM2C0SC_ELS0A_MASK 4 #define TPM2C0SC_ELS0B_MASK 8 #define TPM2C0SC_MS0A_MASK 16 #define TPM2C0SC_MS0B_MASK 32 #define TPM2C0SC_CH0IE_MASK 64 #define TPM2C0SC_CH0F_MASK 128 #define TPM2C0SC_ELS0x_MASK 12 #define TPM2C0SC_ELS0x_BITNUM 2 #define TPM2C0SC_MS0x_MASK 48 #define TPM2C0SC_MS0x_BITNUM 4 /*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0x00000236 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0x00000236 ***/ union { byte Byte; } TPM2C0VHSTR; #define TPM2C0VH _TPM2C0V.Overlap_STR.TPM2C0VHSTR.Byte /*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0x00000237 ***/ union { byte Byte; } TPM2C0VLSTR; #define TPM2C0VL _TPM2C0V.Overlap_STR.TPM2C0VLSTR.Byte } Overlap_STR; } TPM2C0VSTR; extern volatile TPM2C0VSTR _TPM2C0V @0x00000236; #define TPM2C0V _TPM2C0V.Word /*** TPM2C1SC - TPM2 Timer Channel 1 Status and Control Register; 0x00000238 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select A for TPM Channel 1 */ byte MS1B :1; /* Mode Select B for TPM Channel 1 */ byte CH1IE :1; /* Channel 1 Interrupt Enable */ byte CH1F :1; /* Channel 1 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS1x :2; byte grpMS1x :2; byte :1; byte :1; } MergedBits; } TPM2C1SCSTR; extern volatile TPM2C1SCSTR _TPM2C1SC @0x00000238; #define TPM2C1SC _TPM2C1SC.Byte #define TPM2C1SC_ELS1A _TPM2C1SC.Bits.ELS1A #define TPM2C1SC_ELS1B _TPM2C1SC.Bits.ELS1B #define TPM2C1SC_MS1A _TPM2C1SC.Bits.MS1A #define TPM2C1SC_MS1B _TPM2C1SC.Bits.MS1B #define TPM2C1SC_CH1IE _TPM2C1SC.Bits.CH1IE #define TPM2C1SC_CH1F _TPM2C1SC.Bits.CH1F #define TPM2C1SC_ELS1x _TPM2C1SC.MergedBits.grpELS1x #define TPM2C1SC_MS1x _TPM2C1SC.MergedBits.grpMS1x #define TPM2C1SC_ELS1A_MASK 4 #define TPM2C1SC_ELS1B_MASK 8 #define TPM2C1SC_MS1A_MASK 16 #define TPM2C1SC_MS1B_MASK 32 #define TPM2C1SC_CH1IE_MASK 64 #define TPM2C1SC_CH1F_MASK 128 #define TPM2C1SC_ELS1x_MASK 12 #define TPM2C1SC_ELS1x_BITNUM 2 #define TPM2C1SC_MS1x_MASK 48 #define TPM2C1SC_MS1x_BITNUM 4 /*** TPM2C1V - TPM2 Timer Channel 1 Value Register; 0x00000239 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPM2C1VH - TPM2 Timer Channel 1 Value Register High; 0x00000239 ***/ union { byte Byte; } TPM2C1VHSTR; #define TPM2C1VH _TPM2C1V.Overlap_STR.TPM2C1VHSTR.Byte /*** TPM2C1VL - TPM2 Timer Channel 1 Value Register Low; 0x0000023A ***/ union { byte Byte; } TPM2C1VLSTR; #define TPM2C1VL _TPM2C1V.Overlap_STR.TPM2C1VLSTR.Byte } Overlap_STR; } TPM2C1VSTR; extern volatile TPM2C1VSTR _TPM2C1V @0x00000239; #define TPM2C1V _TPM2C1V.Word /*** FOPT - Flash Options Register; 0x0000023C ***/ typedef union { byte Byte; struct { byte SECD :1; /* Security State Code */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } FOPTSTR; extern volatile FOPTSTR _FOPT @0x0000023C; #define FOPT _FOPT.Byte #define FOPT_SECD _FOPT.Bits.SECD #define FOPT_SECD_MASK 1 /*** FLCR - Flash Control Register; 0x0000023D ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte :1; byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High Voltage Enable */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000023D; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** LCDPEN0 - LCD Pin Enable Register 0; 0x00000240 ***/ typedef union { byte Byte; struct { byte PEN0 :1; /* Enable LCD pin 0 for LCD operation */ byte PEN1 :1; /* Enable LCD pin 1 for LCD operation */ byte PEN2 :1; /* Enable LCD pin 2 for LCD operation */ byte PEN3 :1; /* Enable LCD pin 3 for LCD operation */ byte PEN4 :1; /* Enable LCD pin 4 for LCD operation */ byte PEN5 :1; /* Enable LCD pin 5 for LCD operation */ byte PEN6 :1; /* Enable LCD pin 6 for LCD operation */ byte PEN7 :1; /* Enable LCD pin 7 for LCD operation */ } Bits; } LCDPEN0STR; extern volatile LCDPEN0STR _LCDPEN0 @0x00000240; #define LCDPEN0 _LCDPEN0.Byte #define LCDPEN0_PEN0 _LCDPEN0.Bits.PEN0 #define LCDPEN0_PEN1 _LCDPEN0.Bits.PEN1 #define LCDPEN0_PEN2 _LCDPEN0.Bits.PEN2 #define LCDPEN0_PEN3 _LCDPEN0.Bits.PEN3 #define LCDPEN0_PEN4 _LCDPEN0.Bits.PEN4 #define LCDPEN0_PEN5 _LCDPEN0.Bits.PEN5 #define LCDPEN0_PEN6 _LCDPEN0.Bits.PEN6 #define LCDPEN0_PEN7 _LCDPEN0.Bits.PEN7 /* LCDPEN_ARR: Access 3 LCDPENx registers in an array */ #define LCDPEN_ARR ((volatile byte *__paged) &LCDPEN0) #define LCDPEN0_PEN0_MASK 1 #define LCDPEN0_PEN1_MASK 2 #define LCDPEN0_PEN2_MASK 4 #define LCDPEN0_PEN3_MASK 8 #define LCDPEN0_PEN4_MASK 16 #define LCDPEN0_PEN5_MASK 32 #define LCDPEN0_PEN6_MASK 64 #define LCDPEN0_PEN7_MASK 128 /*** LCDPEN1 - LCD Pin Enable Register 1; 0x00000241 ***/ typedef union { byte Byte; struct { byte PEN8 :1; /* Enable LCD pin 8 for LCD operation */ byte PEN9 :1; /* Enable LCD pin 9 for LCD operation */ byte PEN10 :1; /* Enable LCD pin 10 for LCD operation */ byte PEN11 :1; /* Enable LCD pin 11 for LCD operation */ byte PEN12 :1; /* Enable LCD pin 12 for LCD operation */ byte PEN13 :1; /* Enable LCD pin 13 for LCD operation */ byte PEN14 :1; /* Enable LCD pin 14 for LCD operation */ byte PEN15 :1; /* Enable LCD pin 15 for LCD operation */ } Bits; } LCDPEN1STR; extern volatile LCDPEN1STR _LCDPEN1 @0x00000241; #define LCDPEN1 _LCDPEN1.Byte #define LCDPEN1_PEN8 _LCDPEN1.Bits.PEN8 #define LCDPEN1_PEN9 _LCDPEN1.Bits.PEN9 #define LCDPEN1_PEN10 _LCDPEN1.Bits.PEN10 #define LCDPEN1_PEN11 _LCDPEN1.Bits.PEN11 #define LCDPEN1_PEN12 _LCDPEN1.Bits.PEN12 #define LCDPEN1_PEN13 _LCDPEN1.Bits.PEN13 #define LCDPEN1_PEN14 _LCDPEN1.Bits.PEN14 #define LCDPEN1_PEN15 _LCDPEN1.Bits.PEN15 #define LCDPEN1_PEN8_MASK 1 #define LCDPEN1_PEN9_MASK 2 #define LCDPEN1_PEN10_MASK 4 #define LCDPEN1_PEN11_MASK 8 #define LCDPEN1_PEN12_MASK 16 #define LCDPEN1_PEN13_MASK 32 #define LCDPEN1_PEN14_MASK 64 #define LCDPEN1_PEN15_MASK 128 /*** LCDPEN2 - LCD Pin Enable Register 2; 0x00000242 ***/ typedef union { byte Byte; struct { byte PEN16 :1; /* Enable LCD pin 16 for LCD operation */ byte PEN17 :1; /* Enable LCD pin 17 for LCD operation */ byte PEN18 :1; /* Enable LCD pin 18 for LCD operation */ byte PEN19 :1; /* Enable LCD pin 19 for LCD operation */ byte PEN20 :1; /* Enable LCD pin 20 for LCD operation */ byte PEN21 :1; /* Enable LCD pin 21 for LCD operation */ byte :1; byte :1; } Bits; struct { byte grpPEN_16 :6; byte :1; byte :1; } MergedBits; } LCDPEN2STR; extern volatile LCDPEN2STR _LCDPEN2 @0x00000242; #define LCDPEN2 _LCDPEN2.Byte #define LCDPEN2_PEN16 _LCDPEN2.Bits.PEN16 #define LCDPEN2_PEN17 _LCDPEN2.Bits.PEN17 #define LCDPEN2_PEN18 _LCDPEN2.Bits.PEN18 #define LCDPEN2_PEN19 _LCDPEN2.Bits.PEN19 #define LCDPEN2_PEN20 _LCDPEN2.Bits.PEN20 #define LCDPEN2_PEN21 _LCDPEN2.Bits.PEN21 #define LCDPEN2_PEN_16 _LCDPEN2.MergedBits.grpPEN_16 #define LCDPEN2_PEN LCDPEN2_PEN_16 #define LCDPEN2_PEN16_MASK 1 #define LCDPEN2_PEN17_MASK 2 #define LCDPEN2_PEN18_MASK 4 #define LCDPEN2_PEN19_MASK 8 #define LCDPEN2_PEN20_MASK 16 #define LCDPEN2_PEN21_MASK 32 #define LCDPEN2_PEN_16_MASK 63 #define LCDPEN2_PEN_16_BITNUM 0 /*** LCDBPEN0 - LCD Backplane Enable Register 0; 0x00000248 ***/ typedef union { byte Byte; struct { byte BPEN0 :1; /* Enable LCD pin 0 to operate as an LCD backplane or an LCD frontplane */ byte BPEN1 :1; /* Enable LCD pin 1 to operate as an LCD backplane or an LCD frontplane */ byte BPEN2 :1; /* Enable LCD pin 2 to operate as an LCD backplane or an LCD frontplane */ byte BPEN3 :1; /* Enable LCD pin 3 to operate as an LCD backplane or an LCD frontplane */ byte BPEN4 :1; /* Enable LCD pin 4 to operate as an LCD backplane or an LCD frontplane */ byte BPEN5 :1; /* Enable LCD pin 5 to operate as an LCD backplane or an LCD frontplane */ byte BPEN6 :1; /* Enable LCD pin 6 to operate as an LCD backplane or an LCD frontplane */ byte BPEN7 :1; /* Enable LCD pin 7 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN0STR; extern volatile LCDBPEN0STR _LCDBPEN0 @0x00000248; #define LCDBPEN0 _LCDBPEN0.Byte #define LCDBPEN0_BPEN0 _LCDBPEN0.Bits.BPEN0 #define LCDBPEN0_BPEN1 _LCDBPEN0.Bits.BPEN1 #define LCDBPEN0_BPEN2 _LCDBPEN0.Bits.BPEN2 #define LCDBPEN0_BPEN3 _LCDBPEN0.Bits.BPEN3 #define LCDBPEN0_BPEN4 _LCDBPEN0.Bits.BPEN4 #define LCDBPEN0_BPEN5 _LCDBPEN0.Bits.BPEN5 #define LCDBPEN0_BPEN6 _LCDBPEN0.Bits.BPEN6 #define LCDBPEN0_BPEN7 _LCDBPEN0.Bits.BPEN7 /* LCDBPEN_ARR: Access 3 LCDBPENx registers in an array */ #define LCDBPEN_ARR ((volatile byte *__paged) &LCDBPEN0) #define LCDBPEN0_BPEN0_MASK 1 #define LCDBPEN0_BPEN1_MASK 2 #define LCDBPEN0_BPEN2_MASK 4 #define LCDBPEN0_BPEN3_MASK 8 #define LCDBPEN0_BPEN4_MASK 16 #define LCDBPEN0_BPEN5_MASK 32 #define LCDBPEN0_BPEN6_MASK 64 #define LCDBPEN0_BPEN7_MASK 128 /*** LCDBPEN1 - LCD Backplane Enable Register 1; 0x00000249 ***/ typedef union { byte Byte; struct { byte BPEN8 :1; /* Enable LCD pin 8 to operate as an LCD backplane or an LCD frontplane */ byte BPEN9 :1; /* Enable LCD pin 9 to operate as an LCD backplane or an LCD frontplane */ byte BPEN10 :1; /* Enable LCD pin 10 to operate as an LCD backplane or an LCD frontplane */ byte BPEN11 :1; /* Enable LCD pin 11 to operate as an LCD backplane or an LCD frontplane */ byte BPEN12 :1; /* Enable LCD pin 12 to operate as an LCD backplane or an LCD frontplane */ byte BPEN13 :1; /* Enable LCD pin 13 to operate as an LCD backplane or an LCD frontplane */ byte BPEN14 :1; /* Enable LCD pin 14 to operate as an LCD backplane or an LCD frontplane */ byte BPEN15 :1; /* Enable LCD pin 15 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN1STR; extern volatile LCDBPEN1STR _LCDBPEN1 @0x00000249; #define LCDBPEN1 _LCDBPEN1.Byte #define LCDBPEN1_BPEN8 _LCDBPEN1.Bits.BPEN8 #define LCDBPEN1_BPEN9 _LCDBPEN1.Bits.BPEN9 #define LCDBPEN1_BPEN10 _LCDBPEN1.Bits.BPEN10 #define LCDBPEN1_BPEN11 _LCDBPEN1.Bits.BPEN11 #define LCDBPEN1_BPEN12 _LCDBPEN1.Bits.BPEN12 #define LCDBPEN1_BPEN13 _LCDBPEN1.Bits.BPEN13 #define LCDBPEN1_BPEN14 _LCDBPEN1.Bits.BPEN14 #define LCDBPEN1_BPEN15 _LCDBPEN1.Bits.BPEN15 #define LCDBPEN1_BPEN8_MASK 1 #define LCDBPEN1_BPEN9_MASK 2 #define LCDBPEN1_BPEN10_MASK 4 #define LCDBPEN1_BPEN11_MASK 8 #define LCDBPEN1_BPEN12_MASK 16 #define LCDBPEN1_BPEN13_MASK 32 #define LCDBPEN1_BPEN14_MASK 64 #define LCDBPEN1_BPEN15_MASK 128 /*** LCDBPEN2 - LCD Backplane Enable Register 2; 0x0000024A ***/ typedef union { byte Byte; struct { byte BPEN16 :1; /* Enable LCD pin 16 to operate as an LCD backplane or an LCD frontplane */ byte BPEN17 :1; /* Enable LCD pin 17 to operate as an LCD backplane or an LCD frontplane */ byte BPEN18 :1; /* Enable LCD pin 18 to operate as an LCD backplane or an LCD frontplane */ byte BPEN19 :1; /* Enable LCD pin 19 to operate as an LCD backplane or an LCD frontplane */ byte BPEN20 :1; /* Enable LCD pin 20 to operate as an LCD backplane or an LCD frontplane */ byte BPEN21 :1; /* Enable LCD pin 21 to operate as an LCD backplane or an LCD frontplane */ byte :1; byte :1; } Bits; struct { byte grpBPEN_16 :6; byte :1; byte :1; } MergedBits; } LCDBPEN2STR; extern volatile LCDBPEN2STR _LCDBPEN2 @0x0000024A; #define LCDBPEN2 _LCDBPEN2.Byte #define LCDBPEN2_BPEN16 _LCDBPEN2.Bits.BPEN16 #define LCDBPEN2_BPEN17 _LCDBPEN2.Bits.BPEN17 #define LCDBPEN2_BPEN18 _LCDBPEN2.Bits.BPEN18 #define LCDBPEN2_BPEN19 _LCDBPEN2.Bits.BPEN19 #define LCDBPEN2_BPEN20 _LCDBPEN2.Bits.BPEN20 #define LCDBPEN2_BPEN21 _LCDBPEN2.Bits.BPEN21 #define LCDBPEN2_BPEN_16 _LCDBPEN2.MergedBits.grpBPEN_16 #define LCDBPEN2_BPEN LCDBPEN2_BPEN_16 #define LCDBPEN2_BPEN16_MASK 1 #define LCDBPEN2_BPEN17_MASK 2 #define LCDBPEN2_BPEN18_MASK 4 #define LCDBPEN2_BPEN19_MASK 8 #define LCDBPEN2_BPEN20_MASK 16 #define LCDBPEN2_BPEN21_MASK 32 #define LCDBPEN2_BPEN_16_MASK 63 #define LCDBPEN2_BPEN_16_BITNUM 0 /*** NVICSTRM - Nonvolatile ICS Trim Register; 0x00003FFA ***/ typedef union { byte Byte; struct { byte TRIM :8; /* ICS Trim Setting */ } Bits; } NVICSTRMSTR; /* Tip for register initialization in the user code: const byte NVICSTRM_INIT @0x00003FFA = ; */ #define _NVICSTRM (*(const NVICSTRMSTR *__paged)CONVERT_TO_PAGED(0x00003FFA)) #define NVICSTRM _NVICSTRM.Byte #define NVICSTRM_TRIM _NVICSTRM.Bits.TRIM #define NVICSTRM_TRIM_MASK 255 #define NVICSTRM_TRIM_BITNUM 0 /*** NVFTRIM - Nonvolatile ICS Fine Trim; 0x00003FFB ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } NVFTRIMSTR; /* Tip for register initialization in the user code: const byte NVFTRIM_INIT @0x00003FFB = ; */ #define _NVFTRIM (*(const NVFTRIMSTR *__paged)CONVERT_TO_PAGED(0x00003FFB)) #define NVFTRIM _NVFTRIM.Byte #define NVFTRIM_FTRIM _NVFTRIM.Bits.FTRIM #define NVFTRIM_FTRIM_MASK 1 /*** NVOPT - Nonvolatile Flash Options Register; 0x00003FFC ***/ typedef union { byte Byte; struct { byte SECD :1; /* Security State Code */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } NVOPTSTR; /* Tip for register initialization in the user code: const byte NVOPT_INIT @0x00003FFC = ; */ #define _NVOPT (*(const NVOPTSTR *__paged)CONVERT_TO_PAGED(0x00003FFC)) #define NVOPT _NVOPT.Byte #define NVOPT_SECD _NVOPT.Bits.SECD #define NVOPT_SECD_MASK 1 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 25.8.2008 13:29:57 */ #define LCDSUPPLY_BBYPASS This_symb_has_been_depreciated #define LCDSUPPLY_HREFSEL This_symb_has_been_depreciated #define LCDSUPPLY_CPSEL This_symb_has_been_depreciated #define LCDSUPPLY_BBYPASS_MASK This_symb_has_been_depreciated #define LCDSUPPLY_HREFSEL_MASK This_symb_has_been_depreciated #define LCDSUPPLY_CPSEL_MASK This_symb_has_been_depreciated #define LCDRVC This_symb_has_been_depreciated #define LCDRVC_RVTRIM0 This_symb_has_been_depreciated #define LCDRVC_RVTRIM1 This_symb_has_been_depreciated #define LCDRVC_RVTRIM2 This_symb_has_been_depreciated #define LCDRVC_RVTRIM3 This_symb_has_been_depreciated #define LCDRVC_RVEN This_symb_has_been_depreciated #define LCDRVC_RVTRIM This_symb_has_been_depreciated #define LCDRVC_RVTRIM0_MASK This_symb_has_been_depreciated #define LCDRVC_RVTRIM1_MASK This_symb_has_been_depreciated #define LCDRVC_RVTRIM2_MASK This_symb_has_been_depreciated #define LCDRVC_RVTRIM3_MASK This_symb_has_been_depreciated #define LCDRVC_RVEN_MASK This_symb_has_been_depreciated #define LCDRVC_RVTRIM_MASK This_symb_has_been_depreciated #define LCDRVC_RVTRIM_BITNUM This_symb_has_been_depreciated #define ICSSC_IREFST This_symb_has_been_depreciated #define ICSSC_IREFST_MASK This_symb_has_been_depreciated #define LCDPEN3 This_symb_has_been_depreciated #define LCDBPEN3 This_symb_has_been_depreciated /* **** 28.8.2008 9:56:31 */ #define PMCSC SPMSC1 #define PMCSC_BGBE SPMSC1_BGBE #define PMCSC_LVDE SPMSC1_LVDE #define PMCSC_LVDSE SPMSC1_LVDSE #define PMCSC_LVDRE SPMSC1_LVDRE #define PMCSC_LVDIE SPMSC1_LVDIE #define PMCSC_LVDACK SPMSC1_LVDACK #define PMCSC_LVDF SPMSC1_LVDF #define PMCSC_BGBE_MASK SPMSC1_BGBE_MASK #define PMCSC_LVDE_MASK SPMSC1_LVDE_MASK #define PMCSC_LVDSE_MASK SPMSC1_LVDSE_MASK #define PMCSC_LVDRE_MASK SPMSC1_LVDRE_MASK #define PMCSC_LVDIE_MASK SPMSC1_LVDIE_MASK #define PMCSC_LVDACK_MASK SPMSC1_LVDACK_MASK #define PMCSC_LVDF_MASK SPMSC1_LVDF_MASK #endif