/* Based on CPU DB MC68HC908QL4_P_DW, version 2.87.100 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908ql4.h ** Processor : MC68HC908QL4CDW ** FileFormat: V2.30 ** DataSheet : MC68HC908QL4 Rev. 4 12/2004 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:09 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908QL4_H #define _MC68HC908QL4_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_ADC 16 #define VectorNumber_KBI 15 #define VectorNumber_Reserved2 14 #define VectorNumber_Reserved3 13 #define VectorNumber_Reserved4 12 #define VectorNumber_Reserved5 11 #define VectorNumber_SLIC 10 #define VectorNumber_Reserved7 9 #define VectorNumber_Reserved8 8 #define VectorNumber_Reserved9 7 #define VectorNumber_TIMOvr 6 #define VectorNumber_TIMCH1 5 #define VectorNumber_TIMCH0 4 #define VectorNumber_Reserved13 3 #define VectorNumber_IRQ 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_ADC 0x0000FFDE #define INT_KBI 0x0000FFE0 #define Reserved2 0x0000FFE2 #define Reserved3 0x0000FFE4 #define Reserved4 0x0000FFE6 #define Reserved5 0x0000FFE8 #define INT_SLIC 0x0000FFEA #define Reserved7 0x0000FFEC #define Reserved8 0x0000FFEE #define Reserved9 0x0000FFF0 #define INT_TIMOvr 0x0000FFF2 #define INT_TIMCH1 0x0000FFF4 #define INT_TIMCH0 0x0000FFF6 #define Reserved13 0x0000FFF8 #define INT_IRQ 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte AWUL :1; /* Auto Wake-up Latch Data Bit */ byte :1; } Bits; struct { byte grpPTA :6; byte :1; byte :1; } MergedBits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_AWUL _PTA.Bits.AWUL #define PTA_PTA _PTA.MergedBits.grpPTA #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_AWUL_MASK 64 #define PTA_PTA_MASK 63 #define PTA_PTA_BITNUM 0 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte :1; byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpDDRA :2; byte :1; byte grpDDRA_3 :3; byte :1; byte :1; } MergedBits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA _DDRA.MergedBits.grpDDRA #define DDRA_DDRA_3 _DDRA.MergedBits.grpDDRA_3 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA_MASK 3 #define DDRA_DDRA_BITNUM 0 #define DDRA_DDRA_3_MASK 56 #define DDRA_DDRA_3_BITNUM 3 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** PTAPUE - Input Pull-Up Enable Register PTAPUE; 0x0000000B ***/ typedef union { byte Byte; struct { byte PTAPUE0 :1; /* Pull-Up Enable bit 0, Port A */ byte PTAPUE1 :1; /* Pull-Up Enable bit 1, Port A */ byte PTAPUE2 :1; /* Pull-Up Enable bit 2, Port A */ byte PTAPUE3 :1; /* Pull-Up Enable bit 3, Port A */ byte PTAPUE4 :1; /* Pull-Up Enable bit 4, Port A */ byte PTAPUE5 :1; /* Pull-Up Enable bit 5, Port A */ byte :1; byte OSC2EN :1; /* Enable PTA4 on OSC2 Pin */ } Bits; struct { byte grpPTAPUE :6; byte :1; byte :1; } MergedBits; } PTAPUESTR; extern volatile PTAPUESTR _PTAPUE @0x0000000B; #define PTAPUE _PTAPUE.Byte #define PTAPUE_PTAPUE0 _PTAPUE.Bits.PTAPUE0 #define PTAPUE_PTAPUE1 _PTAPUE.Bits.PTAPUE1 #define PTAPUE_PTAPUE2 _PTAPUE.Bits.PTAPUE2 #define PTAPUE_PTAPUE3 _PTAPUE.Bits.PTAPUE3 #define PTAPUE_PTAPUE4 _PTAPUE.Bits.PTAPUE4 #define PTAPUE_PTAPUE5 _PTAPUE.Bits.PTAPUE5 #define PTAPUE_OSC2EN _PTAPUE.Bits.OSC2EN #define PTAPUE_PTAPUE _PTAPUE.MergedBits.grpPTAPUE #define PTAPUE_PTAPUE0_MASK 1 #define PTAPUE_PTAPUE1_MASK 2 #define PTAPUE_PTAPUE2_MASK 4 #define PTAPUE_PTAPUE3_MASK 8 #define PTAPUE_PTAPUE4_MASK 16 #define PTAPUE_PTAPUE5_MASK 32 #define PTAPUE_OSC2EN_MASK 128 #define PTAPUE_PTAPUE_MASK 63 #define PTAPUE_PTAPUE_BITNUM 0 /*** PTBPUE - Input Pull-Up Enable Register PTBPUE; 0x0000000C ***/ typedef union { byte Byte; struct { byte PTBPUE0 :1; /* Pull-Up Enable bit 0, Port B */ byte PTBPUE1 :1; /* Pull-Up Enable bit 1, Port B */ byte PTBPUE2 :1; /* Pull-Up Enable bit 2, Port B */ byte PTBPUE3 :1; /* Pull-Up Enable bit 3, Port B */ byte PTBPUE4 :1; /* Pull-Up Enable bit 4, Port B */ byte PTBPUE5 :1; /* Pull-Up Enable bit 5, Port B */ byte PTBPUE6 :1; /* Pull-Up Enable bit 6, Port B */ byte PTBPUE7 :1; /* Pull-Up Enable bit 7, Port B */ } Bits; } PTBPUESTR; extern volatile PTBPUESTR _PTBPUE @0x0000000C; #define PTBPUE _PTBPUE.Byte #define PTBPUE_PTBPUE0 _PTBPUE.Bits.PTBPUE0 #define PTBPUE_PTBPUE1 _PTBPUE.Bits.PTBPUE1 #define PTBPUE_PTBPUE2 _PTBPUE.Bits.PTBPUE2 #define PTBPUE_PTBPUE3 _PTBPUE.Bits.PTBPUE3 #define PTBPUE_PTBPUE4 _PTBPUE.Bits.PTBPUE4 #define PTBPUE_PTBPUE5 _PTBPUE.Bits.PTBPUE5 #define PTBPUE_PTBPUE6 _PTBPUE.Bits.PTBPUE6 #define PTBPUE_PTBPUE7 _PTBPUE.Bits.PTBPUE7 #define PTBPUE_PTBPUE0_MASK 1 #define PTBPUE_PTBPUE1_MASK 2 #define PTBPUE_PTBPUE2_MASK 4 #define PTBPUE_PTBPUE3_MASK 8 #define PTBPUE_PTBPUE4_MASK 16 #define PTBPUE_PTBPUE5_MASK 32 #define PTBPUE_PTBPUE6_MASK 64 #define PTBPUE_PTBPUE7_MASK 128 /*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */ byte IMASKK :1; /* Keyboard Interrupt Mask Bit */ byte ACKK :1; /* Keyboard Acknowledge Bit */ byte KEYF :1; /* Keyboard Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBSCRSTR; extern volatile KBSCRSTR _KBSCR @0x0000001A; #define KBSCR _KBSCR.Byte #define KBSCR_MODEK _KBSCR.Bits.MODEK #define KBSCR_IMASKK _KBSCR.Bits.IMASKK #define KBSCR_ACKK _KBSCR.Bits.ACKK #define KBSCR_KEYF _KBSCR.Bits.KEYF #define KBSCR_MODEK_MASK 1 #define KBSCR_IMASKK_MASK 2 #define KBSCR_ACKK_MASK 4 #define KBSCR_KEYF_MASK 8 /*** KBIER - Keyboard Interrrupt Enable Register KBIER; 0x0000001B ***/ typedef union { byte Byte; struct { byte KBIE0 :1; /* Keyboard Interrupt Enable Bit 0 */ byte KBIE1 :1; /* Keyboard Interrupt Enable Bit 1 */ byte KBIE2 :1; /* Keyboard Interrupt Enable Bit 2 */ byte KBIE3 :1; /* Keyboard Interrupt Enable Bit 3 */ byte KBIE4 :1; /* Keyboard Interrupt Enable Bit 4 */ byte KBIE5 :1; /* Keyboard Interrupt Enable Bit 5 */ byte AWUIE :1; /* Auto Wake-up Interrupt Enable Bit */ byte :1; } Bits; struct { byte grpKBIE :6; byte :1; byte :1; } MergedBits; } KBIERSTR; extern volatile KBIERSTR _KBIER @0x0000001B; #define KBIER _KBIER.Byte #define KBIER_KBIE0 _KBIER.Bits.KBIE0 #define KBIER_KBIE1 _KBIER.Bits.KBIE1 #define KBIER_KBIE2 _KBIER.Bits.KBIE2 #define KBIER_KBIE3 _KBIER.Bits.KBIE3 #define KBIER_KBIE4 _KBIER.Bits.KBIE4 #define KBIER_KBIE5 _KBIER.Bits.KBIE5 #define KBIER_AWUIE _KBIER.Bits.AWUIE #define KBIER_KBIE _KBIER.MergedBits.grpKBIE #define KBIER_KBIE0_MASK 1 #define KBIER_KBIE1_MASK 2 #define KBIER_KBIE2_MASK 4 #define KBIER_KBIE3_MASK 8 #define KBIER_KBIE4_MASK 16 #define KBIER_KBIE5_MASK 32 #define KBIER_AWUIE_MASK 64 #define KBIER_KBIE_MASK 63 #define KBIER_KBIE_BITNUM 0 /*** KBIPR - Keyboard Interrupt Polarity Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte KBIP0 :1; /* Keyboard Interrupt Polarity Bit 0 */ byte KBIP1 :1; /* Keyboard Interrupt Polarity Bit 1 */ byte KBIP2 :1; /* Keyboard Interrupt Polarity Bit 2 */ byte KBIP3 :1; /* Keyboard Interrupt Polarity Bit 3 */ byte KBIP4 :1; /* Keyboard Interrupt Polarity Bit 4 */ byte KBIP5 :1; /* Keyboard Interrupt Polarity Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpKBIP :6; byte :1; byte :1; } MergedBits; } KBIPRSTR; extern volatile KBIPRSTR _KBIPR @0x0000001C; #define KBIPR _KBIPR.Byte #define KBIPR_KBIP0 _KBIPR.Bits.KBIP0 #define KBIPR_KBIP1 _KBIPR.Bits.KBIP1 #define KBIPR_KBIP2 _KBIPR.Bits.KBIP2 #define KBIPR_KBIP3 _KBIPR.Bits.KBIP3 #define KBIPR_KBIP4 _KBIPR.Bits.KBIP4 #define KBIPR_KBIP5 _KBIPR.Bits.KBIP5 #define KBIPR_KBIP _KBIPR.MergedBits.grpKBIP #define KBIPR_KBIP0_MASK 1 #define KBIPR_KBIP1_MASK 2 #define KBIPR_KBIP2_MASK 4 #define KBIPR_KBIP3_MASK 8 #define KBIPR_KBIP4_MASK 16 #define KBIPR_KBIP5_MASK 32 #define KBIPR_KBIP_MASK 63 #define KBIPR_KBIP_BITNUM 0 /*** INTSCR - IRQ Status and Control Register; 0x0000001D ***/ typedef union { byte Byte; struct { byte MODE :1; /* IRQ Edge/Level Select Bit */ byte IMASK :1; /* IRQ Interrupt Mask Bit */ byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */ byte IRQF :1; /* IRQ Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } INTSCRSTR; extern volatile INTSCRSTR _INTSCR @0x0000001D; #define INTSCR _INTSCR.Byte #define INTSCR_MODE _INTSCR.Bits.MODE #define INTSCR_IMASK _INTSCR.Bits.IMASK #define INTSCR_ACK _INTSCR.Bits.ACK #define INTSCR_IRQF _INTSCR.Bits.IRQF #define INTSCR_MODE_MASK 1 #define INTSCR_IMASK_MASK 2 #define INTSCR_ACK_MASK 4 #define INTSCR_IRQF_MASK 8 /*** CONFIG2 - Configuration Register 2; 0x0000001E ***/ typedef union { byte Byte; struct { byte RSTEN :1; /* RST Pin Function Selection */ byte OSCENINSTOP :1; /* Oscillator Enable in Stop Mode Bit */ byte :1; byte :1; byte :1; byte :1; byte IRQEN :1; /* IRQ Pin Function Selection Bit */ byte IRQPUD :1; /* IRQ Pin Pullup Control Bit */ } Bits; } CONFIG2STR; extern volatile CONFIG2STR _CONFIG2 @0x0000001E; #define CONFIG2 _CONFIG2.Byte #define CONFIG2_RSTEN _CONFIG2.Bits.RSTEN #define CONFIG2_OSCENINSTOP _CONFIG2.Bits.OSCENINSTOP #define CONFIG2_IRQEN _CONFIG2.Bits.IRQEN #define CONFIG2_IRQPUD _CONFIG2.Bits.IRQPUD #define CONFIG2_RSTEN_MASK 1 #define CONFIG2_OSCENINSTOP_MASK 2 #define CONFIG2_IRQEN_MASK 64 #define CONFIG2_IRQPUD_MASK 128 /*** CONFIG1 - Configuration Register 1; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte SSREC :1; /* Short Stop Recovery Bit */ byte LVITRIP :1; /* LVI Trip Point Selection Bit */ byte LVIPWRD :1; /* Low Voltage Inhibit Power Disable Bit */ byte LVIRSTD :1; /* Low Voltage Inhibit Reset Disable Bit */ byte LVISTOP :1; /* LVI Enable in Stop Mode Bit */ byte COPRS :1; /* COP Reset Period Selection Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVITRIP _CONFIG1.Bits.LVITRIP #define CONFIG1_LVIPWRD _CONFIG1.Bits.LVIPWRD #define CONFIG1_LVIRSTD _CONFIG1.Bits.LVIRSTD #define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP #define CONFIG1_COPRS _CONFIG1.Bits.COPRS #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_SSREC_MASK 4 #define CONFIG1_LVITRIP_MASK 8 #define CONFIG1_LVIPWRD_MASK 16 #define CONFIG1_LVIRSTD_MASK 32 #define CONFIG1_LVISTOP_MASK 64 #define CONFIG1_COPRS_MASK 128 /*** TSC - TIM Status and Control Register TSC; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM Reset Bit */ byte TSTOP :1; /* TIM Stop Bit */ byte TOIE :1; /* TIM Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TSCSTR; extern volatile TSCSTR _TSC @0x00000020; #define TSC _TSC.Byte #define TSC_PS0 _TSC.Bits.PS0 #define TSC_PS1 _TSC.Bits.PS1 #define TSC_PS2 _TSC.Bits.PS2 #define TSC_TRST _TSC.Bits.TRST #define TSC_TSTOP _TSC.Bits.TSTOP #define TSC_TOIE _TSC.Bits.TOIE #define TSC_TOF _TSC.Bits.TOF #define TSC_PS _TSC.MergedBits.grpPS #define TSC_PS0_MASK 1 #define TSC_PS1_MASK 2 #define TSC_PS2_MASK 4 #define TSC_TRST_MASK 16 #define TSC_TSTOP_MASK 32 #define TSC_TOIE_MASK 64 #define TSC_TOF_MASK 128 #define TSC_PS_MASK 7 #define TSC_PS_BITNUM 0 /*** TCNT - TIM Counter Register; 0x00000021 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCNTH - TIM Counter Register High; 0x00000021 ***/ union { byte Byte; } TCNTHSTR; #define TCNTH _TCNT.Overlap_STR.TCNTHSTR.Byte /*** TCNTL - TIM Counter Register Low; 0x00000022 ***/ union { byte Byte; } TCNTLSTR; #define TCNTL _TCNT.Overlap_STR.TCNTLSTR.Byte } Overlap_STR; } TCNTSTR; extern volatile TCNTSTR _TCNT @0x00000021; #define TCNT _TCNT.Word /*** TMOD - TIM Counter Modulo Register; 0x00000023 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TMODH - TIM Counter Modulo Register High; 0x00000023 ***/ union { byte Byte; } TMODHSTR; #define TMODH _TMOD.Overlap_STR.TMODHSTR.Byte /*** TMODL - TIM Counter Modulo Register Low; 0x00000024 ***/ union { byte Byte; } TMODLSTR; #define TMODL _TMOD.Overlap_STR.TMODLSTR.Byte } Overlap_STR; } TMODSTR; extern volatile TMODSTR _TMOD @0x00000023; #define TMOD _TMOD.Word /*** TSC0 - TIM Channel 0 Status and Control Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TSC0STR; extern volatile TSC0STR _TSC0 @0x00000025; #define TSC0 _TSC0.Byte #define TSC0_CH0MAX _TSC0.Bits.CH0MAX #define TSC0_TOV0 _TSC0.Bits.TOV0 #define TSC0_ELS0A _TSC0.Bits.ELS0A #define TSC0_ELS0B _TSC0.Bits.ELS0B #define TSC0_MS0A _TSC0.Bits.MS0A #define TSC0_MS0B _TSC0.Bits.MS0B #define TSC0_CH0IE _TSC0.Bits.CH0IE #define TSC0_CH0F _TSC0.Bits.CH0F #define TSC0_ELS0x _TSC0.MergedBits.grpELS0x #define TSC0_MS0x _TSC0.MergedBits.grpMS0x #define TSC0_CH0MAX_MASK 1 #define TSC0_TOV0_MASK 2 #define TSC0_ELS0A_MASK 4 #define TSC0_ELS0B_MASK 8 #define TSC0_MS0A_MASK 16 #define TSC0_MS0B_MASK 32 #define TSC0_CH0IE_MASK 64 #define TSC0_CH0F_MASK 128 #define TSC0_ELS0x_MASK 12 #define TSC0_ELS0x_BITNUM 2 #define TSC0_MS0x_MASK 48 #define TSC0_MS0x_BITNUM 4 /*** TCH0 - TIM Channel 0 Register; 0x00000026 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCH0H - TIM Channel 0 Register High; 0x00000026 ***/ union { byte Byte; } TCH0HSTR; #define TCH0H _TCH0.Overlap_STR.TCH0HSTR.Byte /*** TCH0L - TIM Channel 0 Register Low; 0x00000027 ***/ union { byte Byte; } TCH0LSTR; #define TCH0L _TCH0.Overlap_STR.TCH0LSTR.Byte } Overlap_STR; } TCH0STR; extern volatile TCH0STR _TCH0 @0x00000026; #define TCH0 _TCH0.Word /*** TSC1 - TIM Channel 1 Status and Control Register; 0x00000028 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } TSC1STR; extern volatile TSC1STR _TSC1 @0x00000028; #define TSC1 _TSC1.Byte #define TSC1_CH1MAX _TSC1.Bits.CH1MAX #define TSC1_TOV1 _TSC1.Bits.TOV1 #define TSC1_ELS1A _TSC1.Bits.ELS1A #define TSC1_ELS1B _TSC1.Bits.ELS1B #define TSC1_MS1A _TSC1.Bits.MS1A #define TSC1_CH1IE _TSC1.Bits.CH1IE #define TSC1_CH1F _TSC1.Bits.CH1F #define TSC1_ELS1x _TSC1.MergedBits.grpELS1x #define TSC1_CH1MAX_MASK 1 #define TSC1_TOV1_MASK 2 #define TSC1_ELS1A_MASK 4 #define TSC1_ELS1B_MASK 8 #define TSC1_MS1A_MASK 16 #define TSC1_CH1IE_MASK 64 #define TSC1_CH1F_MASK 128 #define TSC1_ELS1x_MASK 12 #define TSC1_ELS1x_BITNUM 2 /*** TCH1 - TIM Channel 1 Register; 0x00000029 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCH1H - TIM Channel 1 Register High; 0x00000029 ***/ union { byte Byte; } TCH1HSTR; #define TCH1H _TCH1.Overlap_STR.TCH1HSTR.Byte /*** TCH1L - TIM Channel 1 Register Low; 0x0000002A ***/ union { byte Byte; } TCH1LSTR; #define TCH1L _TCH1.Overlap_STR.TCH1LSTR.Byte } Overlap_STR; } TCH1STR; extern volatile TCH1STR _TCH1 @0x00000029; #define TCH1 _TCH1.Word /*** OSCSC - Oscillator Status and Control Register; 0x00000036 ***/ typedef union { byte Byte; struct { byte ECGST :1; /* External Clock Status Bit */ byte ECGON :1; /* External Clock Generator On Bit */ byte ECFS0 :1; /* External Clock Frequency Select Bit 0 */ byte ECFS1 :1; /* External Clock Frequency Select Bit 1 */ byte ICFS0 :1; /* Internal Clock Frequency Select Bit 0 */ byte ICFS1 :1; /* Internal Clock Frequency Select Bit 1 */ byte OSCOPT0 :1; /* OSC Option Bit 0 */ byte OSCOPT1 :1; /* OSC Option Bit 1 */ } Bits; struct { byte :1; byte :1; byte grpECFS :2; byte grpICFS :2; byte grpOSCOPT :2; } MergedBits; } OSCSCSTR; extern volatile OSCSCSTR _OSCSC @0x00000036; #define OSCSC _OSCSC.Byte #define OSCSC_ECGST _OSCSC.Bits.ECGST #define OSCSC_ECGON _OSCSC.Bits.ECGON #define OSCSC_ECFS0 _OSCSC.Bits.ECFS0 #define OSCSC_ECFS1 _OSCSC.Bits.ECFS1 #define OSCSC_ICFS0 _OSCSC.Bits.ICFS0 #define OSCSC_ICFS1 _OSCSC.Bits.ICFS1 #define OSCSC_OSCOPT0 _OSCSC.Bits.OSCOPT0 #define OSCSC_OSCOPT1 _OSCSC.Bits.OSCOPT1 #define OSCSC_ECFS _OSCSC.MergedBits.grpECFS #define OSCSC_ICFS _OSCSC.MergedBits.grpICFS #define OSCSC_OSCOPT _OSCSC.MergedBits.grpOSCOPT #define OSCSC_ECGST_MASK 1 #define OSCSC_ECGON_MASK 2 #define OSCSC_ECFS0_MASK 4 #define OSCSC_ECFS1_MASK 8 #define OSCSC_ICFS0_MASK 16 #define OSCSC_ICFS1_MASK 32 #define OSCSC_OSCOPT0_MASK 64 #define OSCSC_OSCOPT1_MASK 128 #define OSCSC_ECFS_MASK 12 #define OSCSC_ECFS_BITNUM 2 #define OSCSC_ICFS_MASK 48 #define OSCSC_ICFS_BITNUM 4 #define OSCSC_OSCOPT_MASK 192 #define OSCSC_OSCOPT_BITNUM 6 /*** OSCTRIM - Oscillator Trim Register; 0x00000038 ***/ typedef union { byte Byte; struct { byte TRIM0 :1; /* Oscillator Trim Bit 0 */ byte TRIM1 :1; /* Oscillator Trim Bit 1 */ byte TRIM2 :1; /* Oscillator Trim Bit 2 */ byte TRIM3 :1; /* Oscillator Trim Bit 3 */ byte TRIM4 :1; /* Oscillator Trim Bit 4 */ byte TRIM5 :1; /* Oscillator Trim Bit 5 */ byte TRIM6 :1; /* Oscillator Trim Bit 6 */ byte TRIM7 :1; /* Oscillator Trim Bit 7 */ } Bits; } OSCTRIMSTR; extern volatile OSCTRIMSTR _OSCTRIM @0x00000038; #define OSCTRIM _OSCTRIM.Byte #define OSCTRIM_TRIM0 _OSCTRIM.Bits.TRIM0 #define OSCTRIM_TRIM1 _OSCTRIM.Bits.TRIM1 #define OSCTRIM_TRIM2 _OSCTRIM.Bits.TRIM2 #define OSCTRIM_TRIM3 _OSCTRIM.Bits.TRIM3 #define OSCTRIM_TRIM4 _OSCTRIM.Bits.TRIM4 #define OSCTRIM_TRIM5 _OSCTRIM.Bits.TRIM5 #define OSCTRIM_TRIM6 _OSCTRIM.Bits.TRIM6 #define OSCTRIM_TRIM7 _OSCTRIM.Bits.TRIM7 #define OSCTRIM_TRIM0_MASK 1 #define OSCTRIM_TRIM1_MASK 2 #define OSCTRIM_TRIM2_MASK 4 #define OSCTRIM_TRIM3_MASK 8 #define OSCTRIM_TRIM4_MASK 16 #define OSCTRIM_TRIM5_MASK 32 #define OSCTRIM_TRIM6_MASK 64 #define OSCTRIM_TRIM7_MASK 128 /*** ADSCR - ADC10 Status and Control Register; 0x0000003C ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC10 Channel Select Bit 0 */ byte ADCH1 :1; /* ADC10 Channel Select Bit 1 */ byte ADCH2 :1; /* ADC10 Channel Select Bit 2 */ byte ADCH3 :1; /* ADC10 Channel Select Bit 3 */ byte ADCH4 :1; /* ADC10 Channel Select Bit 4 */ byte ADCO :1; /* ADC10 Continuous Conversion Bit */ byte AIEN :1; /* ADC10 Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x0000003C; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADR - ADC10 Data Register - Right-justified; 0x0000003D ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADRH - ADC10 Data Register High - Right-justified mode; 0x0000003D ***/ union { byte Byte; struct { byte AD8 :1; /* ADC10 Data Bit 8 */ byte AD9 :1; /* ADC10 Data Bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpAD_8 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADRHSTR; #define ADRH _ADR.Overlap_STR.ADRHSTR.Byte #define ADRH_AD8 _ADR.Overlap_STR.ADRHSTR.Bits.AD8 #define ADRH_AD9 _ADR.Overlap_STR.ADRHSTR.Bits.AD9 #define ADRH_AD_8 _ADR.Overlap_STR.ADRHSTR.MergedBits.grpAD_8 #define ADRH_AD ADRH_AD_8 #define ADRH_AD8_MASK 1 #define ADRH_AD9_MASK 2 #define ADRH_AD_8_MASK 3 #define ADRH_AD_8_BITNUM 0 /*** ADRL - ADC10 Data Register Low - Right-justified mode; 0x0000003E ***/ union { byte Byte; struct { byte AD0 :1; /* ADC10 Data Bit 0 */ byte AD1 :1; /* ADC10 Data Bit 1 */ byte AD2 :1; /* ADC10 Data Bit 2 */ byte AD3 :1; /* ADC10 Data Bit 3 */ byte AD4 :1; /* ADC10 Data Bit 4 */ byte AD5 :1; /* ADC10 Data Bit 5 */ byte AD6 :1; /* ADC10 Data Bit 6 */ byte AD7 :1; /* ADC10 Data Bit 7 */ } Bits; } ADRLSTR; #define ADRL _ADR.Overlap_STR.ADRLSTR.Byte #define ADRL_AD0 _ADR.Overlap_STR.ADRLSTR.Bits.AD0 #define ADRL_AD1 _ADR.Overlap_STR.ADRLSTR.Bits.AD1 #define ADRL_AD2 _ADR.Overlap_STR.ADRLSTR.Bits.AD2 #define ADRL_AD3 _ADR.Overlap_STR.ADRLSTR.Bits.AD3 #define ADRL_AD4 _ADR.Overlap_STR.ADRLSTR.Bits.AD4 #define ADRL_AD5 _ADR.Overlap_STR.ADRLSTR.Bits.AD5 #define ADRL_AD6 _ADR.Overlap_STR.ADRLSTR.Bits.AD6 #define ADRL_AD7 _ADR.Overlap_STR.ADRLSTR.Bits.AD7 #define ADRL_AD0_MASK 1 #define ADRL_AD1_MASK 2 #define ADRL_AD2_MASK 4 #define ADRL_AD3_MASK 8 #define ADRL_AD4_MASK 16 #define ADRL_AD5_MASK 32 #define ADRL_AD6_MASK 64 #define ADRL_AD7_MASK 128 } Overlap_STR; } ADRSTR; extern volatile ADRSTR _ADR @0x0000003D; #define ADR _ADR.Word /*** ADCLK - ADC Input Clock Register; 0x0000003F ***/ typedef union { byte Byte; struct { byte ACLKEN :1; /* Asynchronous Clock Source Enable */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte MODE0 :1; /* 10- or 8-Bit or External-Triggered Mode Selection Bit 0 */ byte MODE1 :1; /* 10- or 8-Bit or External-Triggered Mode Selection Bit 1 */ byte ADICLK :1; /* Input Clock Select Bit */ byte ADIV0 :1; /* ADC10 Clock Divider Bit 0 */ byte ADIV1 :1; /* ADC10 Clock Divider Bit 1 */ byte ADLPC :1; /* ADC10 Low-Power Configuration Bit */ } Bits; struct { byte :1; byte :1; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADCLKSTR; extern volatile ADCLKSTR _ADCLK @0x0000003F; #define ADCLK _ADCLK.Byte #define ADCLK_ACLKEN _ADCLK.Bits.ACLKEN #define ADCLK_ADLSMP _ADCLK.Bits.ADLSMP #define ADCLK_MODE0 _ADCLK.Bits.MODE0 #define ADCLK_MODE1 _ADCLK.Bits.MODE1 #define ADCLK_ADICLK _ADCLK.Bits.ADICLK #define ADCLK_ADIV0 _ADCLK.Bits.ADIV0 #define ADCLK_ADIV1 _ADCLK.Bits.ADIV1 #define ADCLK_ADLPC _ADCLK.Bits.ADLPC #define ADCLK_MODE _ADCLK.MergedBits.grpMODE #define ADCLK_ADIV _ADCLK.MergedBits.grpADIV #define ADCLK_ACLKEN_MASK 1 #define ADCLK_ADLSMP_MASK 2 #define ADCLK_MODE0_MASK 4 #define ADCLK_MODE1_MASK 8 #define ADCLK_ADICLK_MASK 16 #define ADCLK_ADIV0_MASK 32 #define ADCLK_ADIV1_MASK 64 #define ADCLK_ADLPC_MASK 128 #define ADCLK_MODE_MASK 12 #define ADCLK_MODE_BITNUM 2 #define ADCLK_ADIV_MASK 96 #define ADCLK_ADIV_BITNUM 5 /*** SLCC1 - SLIC Control Register 1; 0x00000040 ***/ typedef union { byte Byte; struct { byte SLCIE :1; /* SLIC Interrupt Enable */ byte IMSG :1; /* SLIC Ignore Message Bit */ byte TXABRT :1; /* Transmit Abort Message */ byte WAKETX :1; /* Transmit Wakeup Symbol */ byte :1; byte INITREQ :1; /* Initialization Request */ byte :1; byte :1; } Bits; } SLCC1STR; extern volatile SLCC1STR _SLCC1 @0x00000040; #define SLCC1 _SLCC1.Byte #define SLCC1_SLCIE _SLCC1.Bits.SLCIE #define SLCC1_IMSG _SLCC1.Bits.IMSG #define SLCC1_TXABRT _SLCC1.Bits.TXABRT #define SLCC1_WAKETX _SLCC1.Bits.WAKETX #define SLCC1_INITREQ _SLCC1.Bits.INITREQ #define SLCC1_SLCIE_MASK 1 #define SLCC1_IMSG_MASK 2 #define SLCC1_TXABRT_MASK 4 #define SLCC1_WAKETX_MASK 8 #define SLCC1_INITREQ_MASK 32 /*** SLCC2 - SLIC Control Register 2; 0x00000041 ***/ typedef union { byte Byte; struct { byte SLCE :1; /* SLIC Module Enable */ byte :1; byte BTM :1; /* UART Byte Transfer Mode */ byte SLCWCM :1; /* SLIC Wait Clock Mode */ byte :1; byte :1; byte :1; byte :1; } Bits; } SLCC2STR; extern volatile SLCC2STR _SLCC2 @0x00000041; #define SLCC2 _SLCC2.Byte #define SLCC2_SLCE _SLCC2.Bits.SLCE #define SLCC2_BTM _SLCC2.Bits.BTM #define SLCC2_SLCWCM _SLCC2.Bits.SLCWCM #define SLCC2_SLCE_MASK 1 #define SLCC2_BTM_MASK 4 #define SLCC2_SLCWCM_MASK 8 /*** SLCS - SLIC Status Register; 0x00000042 ***/ typedef union { byte Byte; struct { byte SLCF :1; /* SLIC Interrupt Flag */ byte :1; byte :1; byte :1; byte :1; byte INITACK :1; /* Initialization Mode Acknowledge */ byte :1; byte SLCACT :1; /* SLIC Active (Oscillator Trim Blocking Semaphore) */ } Bits; } SLCSSTR; extern volatile SLCSSTR _SLCS @0x00000042; #define SLCS _SLCS.Byte #define SLCS_SLCF _SLCS.Bits.SLCF #define SLCS_INITACK _SLCS.Bits.INITACK #define SLCS_SLCACT _SLCS.Bits.SLCACT #define SLCS_SLCF_MASK 1 #define SLCS_INITACK_MASK 32 #define SLCS_SLCACT_MASK 128 /*** SLCP - SLIC Prescale Register; 0x00000043 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte RXFP0 :1; /* Digital Receive Filter Clock Prescaler Bit 0 */ byte RXFP1 :1; /* Digital Receive Filter Clock Prescaler Bit 1 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte grpRXFP :2; } MergedBits; } SLCPSTR; extern volatile SLCPSTR _SLCP @0x00000043; #define SLCP _SLCP.Byte #define SLCP_RXFP0 _SLCP.Bits.RXFP0 #define SLCP_RXFP1 _SLCP.Bits.RXFP1 #define SLCP_RXFP _SLCP.MergedBits.grpRXFP #define SLCP_RXFP0_MASK 64 #define SLCP_RXFP1_MASK 128 #define SLCP_RXFP_MASK 192 #define SLCP_RXFP_BITNUM 6 /*** SLCBT - SLIC Bit Time Register; 0x00000044 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SLCBTH - SLIC Bit Time Register High; 0x00000044 ***/ union { byte Byte; struct { byte BT8 :1; /* SLIC Bit Time Register Bit 8 */ byte BT9 :1; /* SLIC Bit Time Register Bit 9 */ byte BT10 :1; /* SLIC Bit Time Register Bit 10 */ byte BT11 :1; /* SLIC Bit Time Register Bit 11 */ byte BT12 :1; /* SLIC Bit Time Register Bit 12 */ byte :1; byte :1; byte :1; } Bits; struct { byte grpBT_8 :5; byte :1; byte :1; byte :1; } MergedBits; } SLCBTHSTR; #define SLCBTH _SLCBT.Overlap_STR.SLCBTHSTR.Byte #define SLCBTH_BT8 _SLCBT.Overlap_STR.SLCBTHSTR.Bits.BT8 #define SLCBTH_BT9 _SLCBT.Overlap_STR.SLCBTHSTR.Bits.BT9 #define SLCBTH_BT10 _SLCBT.Overlap_STR.SLCBTHSTR.Bits.BT10 #define SLCBTH_BT11 _SLCBT.Overlap_STR.SLCBTHSTR.Bits.BT11 #define SLCBTH_BT12 _SLCBT.Overlap_STR.SLCBTHSTR.Bits.BT12 #define SLCBTH_BT_8 _SLCBT.Overlap_STR.SLCBTHSTR.MergedBits.grpBT_8 #define SLCBTH_BT SLCBTH_BT_8 #define SLCBTH_BT8_MASK 1 #define SLCBTH_BT9_MASK 2 #define SLCBTH_BT10_MASK 4 #define SLCBTH_BT11_MASK 8 #define SLCBTH_BT12_MASK 16 #define SLCBTH_BT_8_MASK 31 #define SLCBTH_BT_8_BITNUM 0 /*** SLCBTL - SLIC Bit Time Register Low; 0x00000045 ***/ union { byte Byte; struct { byte :1; byte BT1 :1; /* SLIC Bit Time Register Bit 1 */ byte BT2 :1; /* SLIC Bit Time Register Bit 2 */ byte BT3 :1; /* SLIC Bit Time Register Bit 3 */ byte BT4 :1; /* SLIC Bit Time Register Bit 4 */ byte BT5 :1; /* SLIC Bit Time Register Bit 5 */ byte BT6 :1; /* SLIC Bit Time Register Bit 6 */ byte BT7 :1; /* SLIC Bit Time Register Bit 7 */ } Bits; struct { byte :1; byte grpBT_1 :7; } MergedBits; } SLCBTLSTR; #define SLCBTL _SLCBT.Overlap_STR.SLCBTLSTR.Byte #define SLCBTL_BT1 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT1 #define SLCBTL_BT2 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT2 #define SLCBTL_BT3 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT3 #define SLCBTL_BT4 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT4 #define SLCBTL_BT5 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT5 #define SLCBTL_BT6 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT6 #define SLCBTL_BT7 _SLCBT.Overlap_STR.SLCBTLSTR.Bits.BT7 #define SLCBTL_BT_1 _SLCBT.Overlap_STR.SLCBTLSTR.MergedBits.grpBT_1 #define SLCBTL_BT SLCBTL_BT_1 #define SLCBTL_BT1_MASK 2 #define SLCBTL_BT2_MASK 4 #define SLCBTL_BT3_MASK 8 #define SLCBTL_BT4_MASK 16 #define SLCBTL_BT5_MASK 32 #define SLCBTL_BT6_MASK 64 #define SLCBTL_BT7_MASK 128 #define SLCBTL_BT_1_MASK 254 #define SLCBTL_BT_1_BITNUM 1 } Overlap_STR; } SLCBTSTR; extern volatile SLCBTSTR _SLCBT @0x00000044; #define SLCBT _SLCBT.Word /*** SLCSV - SLIC State Vector Register; 0x00000046 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte I0 :1; /* Interrupt State Vector Bit 0 */ byte I1 :1; /* Interrupt State Vector Bit 1 */ byte I2 :1; /* Interrupt State Vector Bit 2 */ byte I3 :1; /* Interrupt State Vector Bit 3 */ byte :1; byte :1; } Bits; struct { byte :1; byte :1; byte grpI :4; byte :1; byte :1; } MergedBits; } SLCSVSTR; extern volatile SLCSVSTR _SLCSV @0x00000046; #define SLCSV _SLCSV.Byte #define SLCSV_I0 _SLCSV.Bits.I0 #define SLCSV_I1 _SLCSV.Bits.I1 #define SLCSV_I2 _SLCSV.Bits.I2 #define SLCSV_I3 _SLCSV.Bits.I3 #define SLCSV_I _SLCSV.MergedBits.grpI #define SLCSV_I0_MASK 4 #define SLCSV_I1_MASK 8 #define SLCSV_I2_MASK 16 #define SLCSV_I3_MASK 32 #define SLCSV_I_MASK 60 #define SLCSV_I_BITNUM 2 /*** SLCDLC - SLIC Data Length Code Register; 0x00000047 ***/ typedef union { byte Byte; struct { byte DLC0 :1; /* Data Length Control Bit 0 */ byte DLC1 :1; /* Data Length Control Bit 1 */ byte DLC2 :1; /* Data Length Control Bit 2 */ byte DLC3 :1; /* Data Length Control Bit 3 */ byte DLC4 :1; /* Data Length Control Bit 4 */ byte DLC5 :1; /* Data Length Control Bit 5 */ byte CHKMOD :1; /* LIN Checksum Mode */ byte TXGO :1; /* SLIC Transmit Go */ } Bits; struct { byte grpDLC :6; byte :1; byte :1; } MergedBits; } SLCDLCSTR; extern volatile SLCDLCSTR _SLCDLC @0x00000047; #define SLCDLC _SLCDLC.Byte #define SLCDLC_DLC0 _SLCDLC.Bits.DLC0 #define SLCDLC_DLC1 _SLCDLC.Bits.DLC1 #define SLCDLC_DLC2 _SLCDLC.Bits.DLC2 #define SLCDLC_DLC3 _SLCDLC.Bits.DLC3 #define SLCDLC_DLC4 _SLCDLC.Bits.DLC4 #define SLCDLC_DLC5 _SLCDLC.Bits.DLC5 #define SLCDLC_CHKMOD _SLCDLC.Bits.CHKMOD #define SLCDLC_TXGO _SLCDLC.Bits.TXGO #define SLCDLC_DLC _SLCDLC.MergedBits.grpDLC #define SLCDLC_DLC0_MASK 1 #define SLCDLC_DLC1_MASK 2 #define SLCDLC_DLC2_MASK 4 #define SLCDLC_DLC3_MASK 8 #define SLCDLC_DLC4_MASK 16 #define SLCDLC_DLC5_MASK 32 #define SLCDLC_CHKMOD_MASK 64 #define SLCDLC_TXGO_MASK 128 #define SLCDLC_DLC_MASK 63 #define SLCDLC_DLC_BITNUM 0 /*** SLCID - SLIC Identifier Register; 0x00000048 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Identifier Bit 0 */ byte R1_T1 :1; /* SLIC Identifier Bit 1 */ byte R2_T2 :1; /* SLIC Identifier Bit 2 */ byte R3_T3 :1; /* SLIC Identifier Bit 3 */ byte R4_T4 :1; /* SLIC Identifier Bit 4 */ byte R5_T5 :1; /* SLIC Identifier Bit 5 */ byte R6_T6 :1; /* SLIC Identifier Bit 6 */ byte R7_T7 :1; /* SLIC Identifier Bit 7 */ } Bits; } SLCIDSTR; extern volatile SLCIDSTR _SLCID @0x00000048; #define SLCID _SLCID.Byte #define SLCID_R0_T0 _SLCID.Bits.R0_T0 #define SLCID_R1_T1 _SLCID.Bits.R1_T1 #define SLCID_R2_T2 _SLCID.Bits.R2_T2 #define SLCID_R3_T3 _SLCID.Bits.R3_T3 #define SLCID_R4_T4 _SLCID.Bits.R4_T4 #define SLCID_R5_T5 _SLCID.Bits.R5_T5 #define SLCID_R6_T6 _SLCID.Bits.R6_T6 #define SLCID_R7_T7 _SLCID.Bits.R7_T7 #define SLCID_R0_T0_MASK 1 #define SLCID_R1_T1_MASK 2 #define SLCID_R2_T2_MASK 4 #define SLCID_R3_T3_MASK 8 #define SLCID_R4_T4_MASK 16 #define SLCID_R5_T5_MASK 32 #define SLCID_R6_T6_MASK 64 #define SLCID_R7_T7_MASK 128 /*** SLCD7 - SLIC Data Register 7; 0x00000049 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD7STR; extern volatile SLCD7STR _SLCD7 @0x00000049; #define SLCD7 _SLCD7.Byte #define SLCD7_R0_T0 _SLCD7.Bits.R0_T0 #define SLCD7_R1_T1 _SLCD7.Bits.R1_T1 #define SLCD7_R2_T2 _SLCD7.Bits.R2_T2 #define SLCD7_R3_T3 _SLCD7.Bits.R3_T3 #define SLCD7_R4_T4 _SLCD7.Bits.R4_T4 #define SLCD7_R5_T5 _SLCD7.Bits.R5_T5 #define SLCD7_R6_T6 _SLCD7.Bits.R6_T6 #define SLCD7_R7_T7 _SLCD7.Bits.R7_T7 #define SLCD7_R0_T0_MASK 1 #define SLCD7_R1_T1_MASK 2 #define SLCD7_R2_T2_MASK 4 #define SLCD7_R3_T3_MASK 8 #define SLCD7_R4_T4_MASK 16 #define SLCD7_R5_T5_MASK 32 #define SLCD7_R6_T6_MASK 64 #define SLCD7_R7_T7_MASK 128 /*** SLCD6 - SLIC Data Register 6; 0x0000004A ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD6STR; extern volatile SLCD6STR _SLCD6 @0x0000004A; #define SLCD6 _SLCD6.Byte #define SLCD6_R0_T0 _SLCD6.Bits.R0_T0 #define SLCD6_R1_T1 _SLCD6.Bits.R1_T1 #define SLCD6_R2_T2 _SLCD6.Bits.R2_T2 #define SLCD6_R3_T3 _SLCD6.Bits.R3_T3 #define SLCD6_R4_T4 _SLCD6.Bits.R4_T4 #define SLCD6_R5_T5 _SLCD6.Bits.R5_T5 #define SLCD6_R6_T6 _SLCD6.Bits.R6_T6 #define SLCD6_R7_T7 _SLCD6.Bits.R7_T7 #define SLCD6_R0_T0_MASK 1 #define SLCD6_R1_T1_MASK 2 #define SLCD6_R2_T2_MASK 4 #define SLCD6_R3_T3_MASK 8 #define SLCD6_R4_T4_MASK 16 #define SLCD6_R5_T5_MASK 32 #define SLCD6_R6_T6_MASK 64 #define SLCD6_R7_T7_MASK 128 /*** SLCD5 - SLIC Data Register 5; 0x0000004B ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD5STR; extern volatile SLCD5STR _SLCD5 @0x0000004B; #define SLCD5 _SLCD5.Byte #define SLCD5_R0_T0 _SLCD5.Bits.R0_T0 #define SLCD5_R1_T1 _SLCD5.Bits.R1_T1 #define SLCD5_R2_T2 _SLCD5.Bits.R2_T2 #define SLCD5_R3_T3 _SLCD5.Bits.R3_T3 #define SLCD5_R4_T4 _SLCD5.Bits.R4_T4 #define SLCD5_R5_T5 _SLCD5.Bits.R5_T5 #define SLCD5_R6_T6 _SLCD5.Bits.R6_T6 #define SLCD5_R7_T7 _SLCD5.Bits.R7_T7 #define SLCD5_R0_T0_MASK 1 #define SLCD5_R1_T1_MASK 2 #define SLCD5_R2_T2_MASK 4 #define SLCD5_R3_T3_MASK 8 #define SLCD5_R4_T4_MASK 16 #define SLCD5_R5_T5_MASK 32 #define SLCD5_R6_T6_MASK 64 #define SLCD5_R7_T7_MASK 128 /*** SLCD4 - SLIC Data Register 4; 0x0000004C ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD4STR; extern volatile SLCD4STR _SLCD4 @0x0000004C; #define SLCD4 _SLCD4.Byte #define SLCD4_R0_T0 _SLCD4.Bits.R0_T0 #define SLCD4_R1_T1 _SLCD4.Bits.R1_T1 #define SLCD4_R2_T2 _SLCD4.Bits.R2_T2 #define SLCD4_R3_T3 _SLCD4.Bits.R3_T3 #define SLCD4_R4_T4 _SLCD4.Bits.R4_T4 #define SLCD4_R5_T5 _SLCD4.Bits.R5_T5 #define SLCD4_R6_T6 _SLCD4.Bits.R6_T6 #define SLCD4_R7_T7 _SLCD4.Bits.R7_T7 #define SLCD4_R0_T0_MASK 1 #define SLCD4_R1_T1_MASK 2 #define SLCD4_R2_T2_MASK 4 #define SLCD4_R3_T3_MASK 8 #define SLCD4_R4_T4_MASK 16 #define SLCD4_R5_T5_MASK 32 #define SLCD4_R6_T6_MASK 64 #define SLCD4_R7_T7_MASK 128 /*** SLCD3 - SLIC Data Register 3; 0x0000004D ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD3STR; extern volatile SLCD3STR _SLCD3 @0x0000004D; #define SLCD3 _SLCD3.Byte #define SLCD3_R0_T0 _SLCD3.Bits.R0_T0 #define SLCD3_R1_T1 _SLCD3.Bits.R1_T1 #define SLCD3_R2_T2 _SLCD3.Bits.R2_T2 #define SLCD3_R3_T3 _SLCD3.Bits.R3_T3 #define SLCD3_R4_T4 _SLCD3.Bits.R4_T4 #define SLCD3_R5_T5 _SLCD3.Bits.R5_T5 #define SLCD3_R6_T6 _SLCD3.Bits.R6_T6 #define SLCD3_R7_T7 _SLCD3.Bits.R7_T7 #define SLCD3_R0_T0_MASK 1 #define SLCD3_R1_T1_MASK 2 #define SLCD3_R2_T2_MASK 4 #define SLCD3_R3_T3_MASK 8 #define SLCD3_R4_T4_MASK 16 #define SLCD3_R5_T5_MASK 32 #define SLCD3_R6_T6_MASK 64 #define SLCD3_R7_T7_MASK 128 /*** SLCD2 - SLIC Data Register 2; 0x0000004E ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD2STR; extern volatile SLCD2STR _SLCD2 @0x0000004E; #define SLCD2 _SLCD2.Byte #define SLCD2_R0_T0 _SLCD2.Bits.R0_T0 #define SLCD2_R1_T1 _SLCD2.Bits.R1_T1 #define SLCD2_R2_T2 _SLCD2.Bits.R2_T2 #define SLCD2_R3_T3 _SLCD2.Bits.R3_T3 #define SLCD2_R4_T4 _SLCD2.Bits.R4_T4 #define SLCD2_R5_T5 _SLCD2.Bits.R5_T5 #define SLCD2_R6_T6 _SLCD2.Bits.R6_T6 #define SLCD2_R7_T7 _SLCD2.Bits.R7_T7 #define SLCD2_R0_T0_MASK 1 #define SLCD2_R1_T1_MASK 2 #define SLCD2_R2_T2_MASK 4 #define SLCD2_R3_T3_MASK 8 #define SLCD2_R4_T4_MASK 16 #define SLCD2_R5_T5_MASK 32 #define SLCD2_R6_T6_MASK 64 #define SLCD2_R7_T7_MASK 128 /*** SLCD1 - SLIC Data Register 1; 0x0000004F ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD1STR; extern volatile SLCD1STR _SLCD1 @0x0000004F; #define SLCD1 _SLCD1.Byte #define SLCD1_R0_T0 _SLCD1.Bits.R0_T0 #define SLCD1_R1_T1 _SLCD1.Bits.R1_T1 #define SLCD1_R2_T2 _SLCD1.Bits.R2_T2 #define SLCD1_R3_T3 _SLCD1.Bits.R3_T3 #define SLCD1_R4_T4 _SLCD1.Bits.R4_T4 #define SLCD1_R5_T5 _SLCD1.Bits.R5_T5 #define SLCD1_R6_T6 _SLCD1.Bits.R6_T6 #define SLCD1_R7_T7 _SLCD1.Bits.R7_T7 #define SLCD1_R0_T0_MASK 1 #define SLCD1_R1_T1_MASK 2 #define SLCD1_R2_T2_MASK 4 #define SLCD1_R3_T3_MASK 8 #define SLCD1_R4_T4_MASK 16 #define SLCD1_R5_T5_MASK 32 #define SLCD1_R6_T6_MASK 64 #define SLCD1_R7_T7_MASK 128 /*** SLCD0 - SLIC Data Register 0; 0x00000050 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* SLIC Data Bit 0 */ byte R1_T1 :1; /* SLIC Data Bit 1 */ byte R2_T2 :1; /* SLIC Data Bit 2 */ byte R3_T3 :1; /* SLIC Data Bit 3 */ byte R4_T4 :1; /* SLIC Data Bit 4 */ byte R5_T5 :1; /* SLIC Data Bit 5 */ byte R6_T6 :1; /* SLIC Data Bit 6 */ byte R7_T7 :1; /* SLIC Data Bit 7 */ } Bits; } SLCD0STR; extern volatile SLCD0STR _SLCD0 @0x00000050; #define SLCD0 _SLCD0.Byte #define SLCD0_R0_T0 _SLCD0.Bits.R0_T0 #define SLCD0_R1_T1 _SLCD0.Bits.R1_T1 #define SLCD0_R2_T2 _SLCD0.Bits.R2_T2 #define SLCD0_R3_T3 _SLCD0.Bits.R3_T3 #define SLCD0_R4_T4 _SLCD0.Bits.R4_T4 #define SLCD0_R5_T5 _SLCD0.Bits.R5_T5 #define SLCD0_R6_T6 _SLCD0.Bits.R6_T6 #define SLCD0_R7_T7 _SLCD0.Bits.R7_T7 #define SLCD0_R0_T0_MASK 1 #define SLCD0_R1_T1_MASK 2 #define SLCD0_R2_T2_MASK 4 #define SLCD0_R3_T3_MASK 8 #define SLCD0_R4_T4_MASK 16 #define SLCD0_R5_T5_MASK 32 #define SLCD0_R6_T6_MASK 64 #define SLCD0_R7_T7_MASK 128 /*** BSR - Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte SBSW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } BSRSTR; extern volatile BSRSTR _BSR @0x0000FE00; #define BSR _BSR.Byte #define BSR_SBSW _BSR.Bits.SBSW #define BSR_SBSW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte MODRST :1; /* Monitor Mode Entry Module Reset bit */ byte ILAD :1; /* Illegal Address Reset Bit (opcode fetches only) */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_LVI _SRSR.Bits.LVI #define SRSR_MODRST _SRSR.Bits.MODRST #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_PIN _SRSR.Bits.PIN #define SRSR_POR _SRSR.Bits.POR #define SRSR_LVI_MASK 2 #define SRSR_MODRST_MASK 4 #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_PIN_MASK 64 #define SRSR_POR_MASK 128 /*** BRKAR - Break Auxiliary Register; 0x0000FE02 ***/ typedef union { byte Byte; struct { byte BDCOP :1; /* Break Disable COP Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } BRKARSTR; extern volatile BRKARSTR _BRKAR @0x0000FE02; #define BRKAR _BRKAR.Byte #define BRKAR_BDCOP _BRKAR.Bits.BDCOP #define BRKAR_BDCOP_MASK 1 /*** BFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } BFCRSTR; extern volatile BFCRSTR _BFCR @0x0000FE03; #define BFCR _BFCR.Byte #define BFCR_BCFE _BFCR.Bits.BCFE #define BFCR_BCFE_MASK 128 /*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte IF1 :1; /* Interrupt Flag 1 */ byte :1; byte IF3 :1; /* Interrupt Flag 3 */ byte IF4 :1; /* Interrupt Flag 4 */ byte IF5 :1; /* Interrupt Flag 5 */ byte IF6 :1; /* Interrupt Flag 6 */ } Bits; struct { byte :1; byte :1; byte grpIF_1 :1; byte :1; byte grpIF_3 :4; } MergedBits; } INT1STR; extern volatile INT1STR _INT1 @0x0000FE04; #define INT1 _INT1.Byte #define INT1_IF1 _INT1.Bits.IF1 #define INT1_IF3 _INT1.Bits.IF3 #define INT1_IF4 _INT1.Bits.IF4 #define INT1_IF5 _INT1.Bits.IF5 #define INT1_IF6 _INT1.Bits.IF6 #define INT1_IF_3 _INT1.MergedBits.grpIF_3 #define INT1_IF INT1_IF_3 #define INT1_IF1_MASK 4 #define INT1_IF3_MASK 16 #define INT1_IF4_MASK 32 #define INT1_IF5_MASK 64 #define INT1_IF6_MASK 128 #define INT1_IF_3_MASK 240 #define INT1_IF_3_BITNUM 4 /*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/ typedef union { byte Byte; struct { byte IF7 :1; /* Interrupt Flag 7 */ byte IF8 :1; /* Interrupt Flag 8 */ byte IF9 :1; /* Interrupt Flag 9 */ byte IF10 :1; /* Interrupt Flag 10 */ byte IF11 :1; /* Interrupt Flag 11 */ byte IF12 :1; /* Interrupt Flag 12 */ byte IF13 :1; /* Interrupt Flag 13 */ byte IF14 :1; /* Interrupt Flag 14 */ } Bits; } INT2STR; extern volatile INT2STR _INT2 @0x0000FE05; #define INT2 _INT2.Byte #define INT2_IF7 _INT2.Bits.IF7 #define INT2_IF8 _INT2.Bits.IF8 #define INT2_IF9 _INT2.Bits.IF9 #define INT2_IF10 _INT2.Bits.IF10 #define INT2_IF11 _INT2.Bits.IF11 #define INT2_IF12 _INT2.Bits.IF12 #define INT2_IF13 _INT2.Bits.IF13 #define INT2_IF14 _INT2.Bits.IF14 #define INT2_IF7_MASK 1 #define INT2_IF8_MASK 2 #define INT2_IF9_MASK 4 #define INT2_IF10_MASK 8 #define INT2_IF11_MASK 16 #define INT2_IF12_MASK 32 #define INT2_IF13_MASK 64 #define INT2_IF14_MASK 128 /*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/ typedef union { byte Byte; struct { byte IF15 :1; /* Interrupt Flag 15 */ byte IF16 :1; /* Interrupt Flag 16 */ byte IF17 :1; /* Interrupt Flag 17 */ byte IF18 :1; /* Interrupt Flag 18 */ byte IF19 :1; /* Interrupt Flag 19 */ byte IF20 :1; /* Interrupt Flag 20 */ byte IF21 :1; /* Interrupt Flag 21 */ byte IF22 :1; /* Interrupt Flag 22 */ } Bits; } INT3STR; extern volatile INT3STR _INT3 @0x0000FE06; #define INT3 _INT3.Byte #define INT3_IF15 _INT3.Bits.IF15 #define INT3_IF16 _INT3.Bits.IF16 #define INT3_IF17 _INT3.Bits.IF17 #define INT3_IF18 _INT3.Bits.IF18 #define INT3_IF19 _INT3.Bits.IF19 #define INT3_IF20 _INT3.Bits.IF20 #define INT3_IF21 _INT3.Bits.IF21 #define INT3_IF22 _INT3.Bits.IF22 #define INT3_IF15_MASK 1 #define INT3_IF16_MASK 2 #define INT3_IF17_MASK 4 #define INT3_IF18_MASK 8 #define INT3_IF19_MASK 16 #define INT3_IF20_MASK 32 #define INT3_IF21_MASK 64 #define INT3_IF22_MASK 128 /*** FLCR - FLASH Control Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000FE08; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_ERASE _FLCR.Bits.ERASE #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_ERASE_MASK 2 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** BRK - Break Address Register; 0x0000FE09 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register High; 0x0000FE09 ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Register Bit 8 */ byte BIT9 :1; /* Break Address Register Bit 9 */ byte BIT10 :1; /* Break Address Register Bit 10 */ byte BIT11 :1; /* Break Address Register Bit 11 */ byte BIT12 :1; /* Break Address Register Bit 12 */ byte BIT13 :1; /* Break Address Register Bit 13 */ byte BIT14 :1; /* Break Address Register Bit 14 */ byte BIT15 :1; /* Break Address Register Bit 15 */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register Low; 0x0000FE0A ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Register Bit 0 */ byte BIT1 :1; /* Break Address Register Bit 1 */ byte BIT2 :1; /* Break Address Register Bit 2 */ byte BIT3 :1; /* Break Address Register Bit 3 */ byte BIT4 :1; /* Break Address Register Bit 4 */ byte BIT5 :1; /* Break Address Register Bit 5 */ byte BIT6 :1; /* Break Address Register Bit 6 */ byte BIT7 :1; /* Break Address Register Bit 7 */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE09; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0B ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0B; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** LVISR - LVI Status Register; 0x0000FE0C ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LVIOUT :1; /* LVI Output Bit */ } Bits; } LVISRSTR; extern volatile LVISRSTR _LVISR @0x0000FE0C; #define LVISR _LVISR.Byte #define LVISR_LVIOUT _LVISR.Bits.LVIOUT #define LVISR_LVIOUT_MASK 128 /*** FLBPR - FLASH Block Protect Register; 0x0000FFBE ***/ typedef union { byte Byte; struct { byte :1; byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte BPR4 :1; /* Block Protect Register Bit 4 */ byte BPR5 :1; /* Block Protect Register Bit 5 */ byte BPR6 :1; /* Block Protect Register Bit 6 */ byte BPR7 :1; /* Block Protect Register Bit 7 */ } Bits; struct { byte :1; byte grpBPR_1 :7; } MergedBits; } FLBPRSTR; /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FFBE = ; */ #define _FLBPR (*(const FLBPRSTR * __far)0x0000FFBE) #define FLBPR _FLBPR.Byte #define FLBPR_BPR1 _FLBPR.Bits.BPR1 #define FLBPR_BPR2 _FLBPR.Bits.BPR2 #define FLBPR_BPR3 _FLBPR.Bits.BPR3 #define FLBPR_BPR4 _FLBPR.Bits.BPR4 #define FLBPR_BPR5 _FLBPR.Bits.BPR5 #define FLBPR_BPR6 _FLBPR.Bits.BPR6 #define FLBPR_BPR7 _FLBPR.Bits.BPR7 #define FLBPR_BPR_1 _FLBPR.MergedBits.grpBPR_1 #define FLBPR_BPR FLBPR_BPR_1 #define FLBPR_BPR1_MASK 2 #define FLBPR_BPR2_MASK 4 #define FLBPR_BPR3_MASK 8 #define FLBPR_BPR4_MASK 16 #define FLBPR_BPR5_MASK 32 #define FLBPR_BPR6_MASK 64 #define FLBPR_BPR7_MASK 128 #define FLBPR_BPR_1_MASK 254 #define FLBPR_BPR_1_BITNUM 1 /*** Optional - Internal Oscillator Trim; 0x0000FFC0 ***/ typedef union { byte Byte; struct { byte TRIM0 :1; /* ICG Trim Factor Bit 0 */ byte TRIM1 :1; /* ICG Trim Factor Bit 1 */ byte TRIM2 :1; /* ICG Trim Factor Bit 2 */ byte TRIM3 :1; /* ICG Trim Factor Bit 3 */ byte TRIM4 :1; /* ICG Trim Factor Bit 4 */ byte TRIM5 :1; /* ICG Trim Factor Bit 5 */ byte TRIM6 :1; /* ICG Trim Factor Bit 6 */ byte TRIM7 :1; /* ICG Trim Factor Bit 7 */ } Bits; } OptionalSTR; /* Tip for register initialization in the user code: const byte Optional_INIT @0x0000FFC0 = ; */ #define _Optional (*(const OptionalSTR * __far)0x0000FFC0) #define Optional _Optional.Byte #define Optional_TRIM0 _Optional.Bits.TRIM0 #define Optional_TRIM1 _Optional.Bits.TRIM1 #define Optional_TRIM2 _Optional.Bits.TRIM2 #define Optional_TRIM3 _Optional.Bits.TRIM3 #define Optional_TRIM4 _Optional.Bits.TRIM4 #define Optional_TRIM5 _Optional.Bits.TRIM5 #define Optional_TRIM6 _Optional.Bits.TRIM6 #define Optional_TRIM7 _Optional.Bits.TRIM7 #define Optional_TRIM0_MASK 1 #define Optional_TRIM1_MASK 2 #define Optional_TRIM2_MASK 4 #define Optional_TRIM3_MASK 8 #define Optional_TRIM4_MASK 16 #define Optional_TRIM5_MASK 32 #define Optional_TRIM6_MASK 64 #define Optional_TRIM7_MASK 128 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------------------------------- Exceptions in bit names of timer status and control registers due to backward compatibility with previous releases */ #define TSC0_CHxMAX _TSC0.Bits.CH0MAX #define TSC0_TOVx _TSC0.Bits.TOV0 #define TSC0_ELSxA _TSC0.Bits.ELS0A #define TSC0_ELSxB _TSC0.Bits.ELS0B #define TSC0_MSxA _TSC0.Bits.MS0A #define TSC0_MSxB _TSC0.Bits.MS0B #define TSC0_CHxIE _TSC0.Bits.CH0IE #define TSC0_CHxF _TSC0.Bits.CH0F #define TSC1_CHxMAX _TSC1.Bits.CH1MAX #define TSC1_TOVx _TSC1.Bits.TOV1 #define TSC1_ELSxA _TSC1.Bits.ELS1A #define TSC1_ELSxB _TSC1.Bits.ELS1B #define TSC1_MSxA _TSC1.Bits.MS1A #define TSC1_CHxIE _TSC1.Bits.CH1IE #define TSC1_CHxF _TSC1.Bits.CH1F /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 12:42:43 */ #define TCH_ARR This_symb_has_been_depreciated #endif