/* Based on CPU DB MC68HC908LV8_52, version 2.89.078 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908lv8.h ** Processor : MC68HC908LV8CFA ** FileFormat: V2.30 ** DataSheet : MC68HC908LV8 Rev. 2 12/2005 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:09 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908LV8_H #define _MC68HC908LV8_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_ADC 18 #define VectorNumber_KBD 17 #define VectorNumber_Reserved2 16 #define VectorNumber_Reserved3 15 #define VectorNumber_Reserved4 14 #define VectorNumber_Reserved5 13 #define VectorNumber_Reserved6 12 #define VectorNumber_Reserved7 11 #define VectorNumber_TIM2Ovr 10 #define VectorNumber_TIM2CH1 9 #define VectorNumber_TIM2CH0 8 #define VectorNumber_TIM1Ovr 7 #define VectorNumber_TIM1CH1 6 #define VectorNumber_TIM1CH0 5 #define VectorNumber_PLL 4 #define VectorNumber_LVI 3 #define VectorNumber_IRQ 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_ADC 0x0000FFDA #define INT_KBD 0x0000FFDC #define Reserved2 0x0000FFDE #define Reserved3 0x0000FFE0 #define Reserved4 0x0000FFE2 #define Reserved5 0x0000FFE4 #define Reserved6 0x0000FFE6 #define Reserved7 0x0000FFE8 #define INT_TIM2Ovr 0x0000FFEA #define INT_TIM2CH1 0x0000FFEC #define INT_TIM2CH0 0x0000FFEE #define INT_TIM1Ovr 0x0000FFF0 #define INT_TIM1CH1 0x0000FFF2 #define INT_TIM1CH0 0x0000FFF4 #define INT_PLL 0x0000FFF6 #define INT_LVI 0x0000FFF8 #define INT_IRQ 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte PTA6 :1; /* Port A Data Bit 6 */ byte PTA7 :1; /* Port A Data Bit 7 */ } Bits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_PTA6 _PTA.Bits.PTA6 #define PTA_PTA7 _PTA.Bits.PTA7 #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_PTA6_MASK 64 #define PTA_PTA7_MASK 128 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** PTC - Port C Data Register; 0x00000002 ***/ typedef union { byte Byte; struct { byte PTC0 :1; /* Port C Data Bit 0 */ byte PTC1 :1; /* Port C Data Bit 1 */ byte PTC2 :1; /* Port C Data Bit 2 */ byte PTC3 :1; /* Port C Data Bit 3 */ byte PTC4 :1; /* Port C Data Bit 4 */ byte PTC5 :1; /* Port C Data Bit 5 */ byte PTC6 :1; /* Port C Data Bit 6 */ byte PTC7 :1; /* Port C Data Bit 7 */ } Bits; } PTCSTR; extern volatile PTCSTR _PTC @0x00000002; #define PTC _PTC.Byte #define PTC_PTC0 _PTC.Bits.PTC0 #define PTC_PTC1 _PTC.Bits.PTC1 #define PTC_PTC2 _PTC.Bits.PTC2 #define PTC_PTC3 _PTC.Bits.PTC3 #define PTC_PTC4 _PTC.Bits.PTC4 #define PTC_PTC5 _PTC.Bits.PTC5 #define PTC_PTC6 _PTC.Bits.PTC6 #define PTC_PTC7 _PTC.Bits.PTC7 #define PTC_PTC0_MASK 1 #define PTC_PTC1_MASK 2 #define PTC_PTC2_MASK 4 #define PTC_PTC3_MASK 8 #define PTC_PTC4_MASK 16 #define PTC_PTC5_MASK 32 #define PTC_PTC6_MASK 64 #define PTC_PTC7_MASK 128 /*** PTD - Port D Data Register; 0x00000003 ***/ typedef union { byte Byte; struct { byte PTD0 :1; /* Port D Data Bit 0 */ byte PTD1 :1; /* Port D Data Bit 1 */ byte PTD2 :1; /* Port D Data Bit 2 */ byte PTD3 :1; /* Port D Data Bit 3 */ byte PTD4 :1; /* Port D Data Bit 4 */ byte PTD5 :1; /* Port D Data Bit 5 */ byte PTD6 :1; /* Port D Data Bit 6 */ byte PTD7 :1; /* Port D Data Bit 7 */ } Bits; } PTDSTR; extern volatile PTDSTR _PTD @0x00000003; #define PTD _PTD.Byte #define PTD_PTD0 _PTD.Bits.PTD0 #define PTD_PTD1 _PTD.Bits.PTD1 #define PTD_PTD2 _PTD.Bits.PTD2 #define PTD_PTD3 _PTD.Bits.PTD3 #define PTD_PTD4 _PTD.Bits.PTD4 #define PTD_PTD5 _PTD.Bits.PTD5 #define PTD_PTD6 _PTD.Bits.PTD6 #define PTD_PTD7 _PTD.Bits.PTD7 #define PTD_PTD0_MASK 1 #define PTD_PTD1_MASK 2 #define PTD_PTD2_MASK 4 #define PTD_PTD3_MASK 8 #define PTD_PTD4_MASK 16 #define PTD_PTD5_MASK 32 #define PTD_PTD6_MASK 64 #define PTD_PTD7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte DDRA6 :1; /* Data Direction Register A Bit 6 */ byte DDRA7 :1; /* Data Direction Register A Bit 7 */ } Bits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA6 _DDRA.Bits.DDRA6 #define DDRA_DDRA7 _DDRA.Bits.DDRA7 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA6_MASK 64 #define DDRA_DDRA7_MASK 128 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** DDRC - Data Direction Register C; 0x00000006 ***/ typedef union { byte Byte; struct { byte DDRC0 :1; /* Data Direction Register C Bit 0 */ byte DDRC1 :1; /* Data Direction Register C Bit 1 */ byte DDRC2 :1; /* Data Direction Register C Bit 2 */ byte DDRC3 :1; /* Data Direction Register C Bit 3 */ byte DDRC4 :1; /* Data Direction Register C Bit 4 */ byte DDRC5 :1; /* Data Direction Register C Bit 5 */ byte DDRC6 :1; /* Data Direction Register C Bit 6 */ byte DDRC7 :1; /* Data Direction Register C Bit 7 */ } Bits; } DDRCSTR; extern volatile DDRCSTR _DDRC @0x00000006; #define DDRC _DDRC.Byte #define DDRC_DDRC0 _DDRC.Bits.DDRC0 #define DDRC_DDRC1 _DDRC.Bits.DDRC1 #define DDRC_DDRC2 _DDRC.Bits.DDRC2 #define DDRC_DDRC3 _DDRC.Bits.DDRC3 #define DDRC_DDRC4 _DDRC.Bits.DDRC4 #define DDRC_DDRC5 _DDRC.Bits.DDRC5 #define DDRC_DDRC6 _DDRC.Bits.DDRC6 #define DDRC_DDRC7 _DDRC.Bits.DDRC7 #define DDRC_DDRC0_MASK 1 #define DDRC_DDRC1_MASK 2 #define DDRC_DDRC2_MASK 4 #define DDRC_DDRC3_MASK 8 #define DDRC_DDRC4_MASK 16 #define DDRC_DDRC5_MASK 32 #define DDRC_DDRC6_MASK 64 #define DDRC_DDRC7_MASK 128 /*** DDRD - Data Direction Register D; 0x00000007 ***/ typedef union { byte Byte; struct { byte DDRD0 :1; /* Data Direction Register D Bit 0 */ byte DDRD1 :1; /* Data Direction Register D Bit 1 */ byte DDRD2 :1; /* Data Direction Register D Bit 2 */ byte DDRD3 :1; /* Data Direction Register D Bit 3 */ byte DDRD4 :1; /* Data Direction Register D Bit 4 */ byte DDRD5 :1; /* Data Direction Register D Bit 5 */ byte DDRD6 :1; /* Data Direction Register D Bit 6 */ byte DDRD7 :1; /* Data Direction Register D Bit 7 */ } Bits; } DDRDSTR; extern volatile DDRDSTR _DDRD @0x00000007; #define DDRD _DDRD.Byte #define DDRD_DDRD0 _DDRD.Bits.DDRD0 #define DDRD_DDRD1 _DDRD.Bits.DDRD1 #define DDRD_DDRD2 _DDRD.Bits.DDRD2 #define DDRD_DDRD3 _DDRD.Bits.DDRD3 #define DDRD_DDRD4 _DDRD.Bits.DDRD4 #define DDRD_DDRD5 _DDRD.Bits.DDRD5 #define DDRD_DDRD6 _DDRD.Bits.DDRD6 #define DDRD_DDRD7 _DDRD.Bits.DDRD7 #define DDRD_DDRD0_MASK 1 #define DDRD_DDRD1_MASK 2 #define DDRD_DDRD2_MASK 4 #define DDRD_DDRD3_MASK 8 #define DDRD_DDRD4_MASK 16 #define DDRD_DDRD5_MASK 32 #define DDRD_DDRD6_MASK 64 #define DDRD_DDRD7_MASK 128 /*** DDRE - Data Direction Register E; 0x00000008 ***/ typedef union { byte Byte; struct { byte DDRE0 :1; /* Data Direction Register E Bit 0 */ byte DDRE1 :1; /* Data Direction Register E Bit 1 */ byte DDRE2 :1; /* Data Direction Register E Bit 2 */ byte DDRE3 :1; /* Data Direction Register E Bit 3 */ byte DDRE4 :1; /* Data Direction Register E Bit 4 */ byte DDRE5 :1; /* Data Direction Register E Bit 5 */ byte DDRE6 :1; /* Data Direction Register E Bit 6 */ byte DDRE7 :1; /* Data Direction Register E Bit 7 */ } Bits; } DDRESTR; extern volatile DDRESTR _DDRE @0x00000008; #define DDRE _DDRE.Byte #define DDRE_DDRE0 _DDRE.Bits.DDRE0 #define DDRE_DDRE1 _DDRE.Bits.DDRE1 #define DDRE_DDRE2 _DDRE.Bits.DDRE2 #define DDRE_DDRE3 _DDRE.Bits.DDRE3 #define DDRE_DDRE4 _DDRE.Bits.DDRE4 #define DDRE_DDRE5 _DDRE.Bits.DDRE5 #define DDRE_DDRE6 _DDRE.Bits.DDRE6 #define DDRE_DDRE7 _DDRE.Bits.DDRE7 #define DDRE_DDRE0_MASK 1 #define DDRE_DDRE1_MASK 2 #define DDRE_DDRE2_MASK 4 #define DDRE_DDRE3_MASK 8 #define DDRE_DDRE4_MASK 16 #define DDRE_DDRE5_MASK 32 #define DDRE_DDRE6_MASK 64 #define DDRE_DDRE7_MASK 128 /*** PTE - Port E Data Register; 0x00000009 ***/ typedef union { byte Byte; struct { byte PTE0 :1; /* Port E Data Bit 0 */ byte PTE1 :1; /* Port E Data Bit 1 */ byte PTE2 :1; /* Port E Data Bit 2 */ byte PTE3 :1; /* Port E Data Bit 3 */ byte PTE4 :1; /* Port E Data Bit 4 */ byte PTE5 :1; /* Port E Data Bit 5 */ byte PTE6 :1; /* Port E Data Bit 6 */ byte PTE7 :1; /* Port E Data Bit 7 */ } Bits; } PTESTR; extern volatile PTESTR _PTE @0x00000009; #define PTE _PTE.Byte #define PTE_PTE0 _PTE.Bits.PTE0 #define PTE_PTE1 _PTE.Bits.PTE1 #define PTE_PTE2 _PTE.Bits.PTE2 #define PTE_PTE3 _PTE.Bits.PTE3 #define PTE_PTE4 _PTE.Bits.PTE4 #define PTE_PTE5 _PTE.Bits.PTE5 #define PTE_PTE6 _PTE.Bits.PTE6 #define PTE_PTE7 _PTE.Bits.PTE7 #define PTE_PTE0_MASK 1 #define PTE_PTE1_MASK 2 #define PTE_PTE2_MASK 4 #define PTE_PTE3_MASK 8 #define PTE_PTE4_MASK 16 #define PTE_PTE5_MASK 32 #define PTE_PTE6_MASK 64 #define PTE_PTE7_MASK 128 /*** HDB - Port B High Current Drive Control Register; 0x0000000C ***/ typedef union { byte Byte; struct { byte PPI1CLKS0 :1; /* PPI1 Clock Source Select Bit 0 */ byte PPI1CLKS1 :1; /* PPI1 Clock Source Select Bit 1 */ byte HDB2 :1; /* Port B LED Drive Enable Bit 2 */ byte HDB3 :1; /* Port B LED Drive Enable Bit 3 */ byte HDB4 :1; /* Port B LED Drive Enable Bit 4 */ byte HDB5 :1; /* Port B LED Drive Enable Bit 5 */ byte PPI1L :1; /* PPI1 Pending for Acknowledgement */ byte :1; } Bits; struct { byte grpPPI1CLKS :2; byte grpHDB_2 :4; byte :1; byte :1; } MergedBits; } HDBSTR; extern volatile HDBSTR _HDB @0x0000000C; #define HDB _HDB.Byte #define HDB_PPI1CLKS0 _HDB.Bits.PPI1CLKS0 #define HDB_PPI1CLKS1 _HDB.Bits.PPI1CLKS1 #define HDB_HDB2 _HDB.Bits.HDB2 #define HDB_HDB3 _HDB.Bits.HDB3 #define HDB_HDB4 _HDB.Bits.HDB4 #define HDB_HDB5 _HDB.Bits.HDB5 #define HDB_PPI1L _HDB.Bits.PPI1L #define HDB_PPI1CLKS _HDB.MergedBits.grpPPI1CLKS #define HDB_HDB_2 _HDB.MergedBits.grpHDB_2 #define HDB_PPI1CLKS0_MASK 1 #define HDB_PPI1CLKS1_MASK 2 #define HDB_HDB2_MASK 4 #define HDB_HDB3_MASK 8 #define HDB_HDB4_MASK 16 #define HDB_HDB5_MASK 32 #define HDB_PPI1L_MASK 64 #define HDB_PPI1CLKS_MASK 3 #define HDB_PPI1CLKS_BITNUM 0 #define HDB_HDB_2_MASK 60 #define HDB_HDB_2_BITNUM 2 /*** KBSCR - Keyboard Status and Control Register; 0x0000001B ***/ typedef union { byte Byte; struct { byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */ byte IMASKK :1; /* Keyboard Interrupt Mask Bit */ byte ACKK :1; /* Keyboard Acknowledge Bit */ byte KEYF :1; /* Keyboard Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBSCRSTR; extern volatile KBSCRSTR _KBSCR @0x0000001B; #define KBSCR _KBSCR.Byte #define KBSCR_MODEK _KBSCR.Bits.MODEK #define KBSCR_IMASKK _KBSCR.Bits.IMASKK #define KBSCR_ACKK _KBSCR.Bits.ACKK #define KBSCR_KEYF _KBSCR.Bits.KEYF #define KBSCR_MODEK_MASK 1 #define KBSCR_IMASKK_MASK 2 #define KBSCR_ACKK_MASK 4 #define KBSCR_KEYF_MASK 8 /*** KBIER - Keyobard Interrupt Enable Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte KBIE0 :1; /* Keyboard Interrut Enable Bit */ byte KBIE1 :1; /* Keyboard Interrut Enable Bit */ byte KBIE2 :1; /* Keyboard Interrut Enable Bit */ byte KBIE3 :1; /* Keyboard Interrut Enable Bit */ byte PPI1IE0 :1; /* PPI1 Interrupt Period Select Bit 0 */ byte PPI1IE1 :1; /* PPI1 Interrupt Period Select Bit 1 */ byte PPI1IE2 :1; /* PPI1 Interrupt Period Select Bit 2 */ byte :1; } Bits; struct { byte grpKBIE :4; byte grpPPI1IE :3; byte :1; } MergedBits; } KBIERSTR; extern volatile KBIERSTR _KBIER @0x0000001C; #define KBIER _KBIER.Byte #define KBIER_KBIE0 _KBIER.Bits.KBIE0 #define KBIER_KBIE1 _KBIER.Bits.KBIE1 #define KBIER_KBIE2 _KBIER.Bits.KBIE2 #define KBIER_KBIE3 _KBIER.Bits.KBIE3 #define KBIER_PPI1IE0 _KBIER.Bits.PPI1IE0 #define KBIER_PPI1IE1 _KBIER.Bits.PPI1IE1 #define KBIER_PPI1IE2 _KBIER.Bits.PPI1IE2 #define KBIER_KBIE _KBIER.MergedBits.grpKBIE #define KBIER_PPI1IE _KBIER.MergedBits.grpPPI1IE #define KBIER_KBIE0_MASK 1 #define KBIER_KBIE1_MASK 2 #define KBIER_KBIE2_MASK 4 #define KBIER_KBIE3_MASK 8 #define KBIER_PPI1IE0_MASK 16 #define KBIER_PPI1IE1_MASK 32 #define KBIER_PPI1IE2_MASK 64 #define KBIER_KBIE_MASK 15 #define KBIER_KBIE_BITNUM 0 #define KBIER_PPI1IE_MASK 112 #define KBIER_PPI1IE_BITNUM 4 /*** CONFIG2 - Configuration Register 2; 0x0000001D ***/ typedef union { byte Byte; struct { byte LVISEL0 :1; /* LVI Operating Mode Selection 0 */ byte LVISEL1 :1; /* LVI Operating Mode Selection 1 */ byte PCEL :1; /* Port C Enable Low Nibble */ byte PCEH :1; /* Port C Enable High Nibble */ byte PDE :1; /* Port D Enable for LCD Drive */ byte PEE :1; /* Port E Enable for LCD Drive */ byte :1; byte STOP_XCLKEN :1; /* Crystal Oscillator Stop Mode Enable */ } Bits; struct { byte grpLVISEL :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } CONFIG2STR; extern volatile CONFIG2STR _CONFIG2 @0x0000001D; #define CONFIG2 _CONFIG2.Byte #define CONFIG2_LVISEL0 _CONFIG2.Bits.LVISEL0 #define CONFIG2_LVISEL1 _CONFIG2.Bits.LVISEL1 #define CONFIG2_PCEL _CONFIG2.Bits.PCEL #define CONFIG2_PCEH _CONFIG2.Bits.PCEH #define CONFIG2_PDE _CONFIG2.Bits.PDE #define CONFIG2_PEE _CONFIG2.Bits.PEE #define CONFIG2_STOP_XCLKEN _CONFIG2.Bits.STOP_XCLKEN #define CONFIG2_LVISEL _CONFIG2.MergedBits.grpLVISEL #define CONFIG2_LVISEL0_MASK 1 #define CONFIG2_LVISEL1_MASK 2 #define CONFIG2_PCEL_MASK 4 #define CONFIG2_PCEH_MASK 8 #define CONFIG2_PDE_MASK 16 #define CONFIG2_PEE_MASK 32 #define CONFIG2_STOP_XCLKEN_MASK 128 #define CONFIG2_LVISEL_MASK 3 #define CONFIG2_LVISEL_BITNUM 0 /*** INTSCR - IRQ Status and Control Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte MODE :1; /* IRQ Edge/Level Select Bit */ byte IMASK :1; /* IRQ Interrupt Mask Bit */ byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */ byte IRQF :1; /* IRQ Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } INTSCRSTR; extern volatile INTSCRSTR _INTSCR @0x0000001E; #define INTSCR _INTSCR.Byte #define INTSCR_MODE _INTSCR.Bits.MODE #define INTSCR_IMASK _INTSCR.Bits.IMASK #define INTSCR_ACK _INTSCR.Bits.ACK #define INTSCR_IRQF _INTSCR.Bits.IRQF #define INTSCR_MODE_MASK 1 #define INTSCR_IMASK_MASK 2 #define INTSCR_ACK_MASK 4 #define INTSCR_IRQF_MASK 8 /*** CONFIG1 - Configuration Register 2; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte SSREC :1; /* Short Stop Recovery Bit */ byte :1; byte LVIPWRD :1; /* LVI Power Disable Bit */ byte LVIRSTD :1; /* LVI Reset Disable Bit */ byte LVISTOP :1; /* LVI Enable in Stop Mode Bit */ byte COPRS :1; /* COP rate Select Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVIPWRD _CONFIG1.Bits.LVIPWRD #define CONFIG1_LVIRSTD _CONFIG1.Bits.LVIRSTD #define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP #define CONFIG1_COPRS _CONFIG1.Bits.COPRS #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_SSREC_MASK 4 #define CONFIG1_LVIPWRD_MASK 16 #define CONFIG1_LVIRSTD_MASK 32 #define CONFIG1_LVISTOP_MASK 64 #define CONFIG1_COPRS_MASK 128 /*** T1SC - TIM1 Status and Control Register; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM1 Reset Bit */ byte TSTOP :1; /* TIM1 Stop Bit */ byte TOIE :1; /* TIM1 Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM1 Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } T1SCSTR; extern volatile T1SCSTR _T1SC @0x00000020; #define T1SC _T1SC.Byte #define T1SC_PS0 _T1SC.Bits.PS0 #define T1SC_PS1 _T1SC.Bits.PS1 #define T1SC_PS2 _T1SC.Bits.PS2 #define T1SC_TRST _T1SC.Bits.TRST #define T1SC_TSTOP _T1SC.Bits.TSTOP #define T1SC_TOIE _T1SC.Bits.TOIE #define T1SC_TOF _T1SC.Bits.TOF #define T1SC_PS _T1SC.MergedBits.grpPS #define T1SC_PS0_MASK 1 #define T1SC_PS1_MASK 2 #define T1SC_PS2_MASK 4 #define T1SC_TRST_MASK 16 #define T1SC_TSTOP_MASK 32 #define T1SC_TOIE_MASK 64 #define T1SC_TOF_MASK 128 #define T1SC_PS_MASK 7 #define T1SC_PS_BITNUM 0 /*** T1CNT - TIM1 Counter Register; 0x00000021 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CNTH - TIM1 Counter Register; 0x00000021 ***/ union { byte Byte; } T1CNTHSTR; #define T1CNTH _T1CNT.Overlap_STR.T1CNTHSTR.Byte /*** T1CNTL - TIM1 Counter Register; 0x00000022 ***/ union { byte Byte; } T1CNTLSTR; #define T1CNTL _T1CNT.Overlap_STR.T1CNTLSTR.Byte } Overlap_STR; } T1CNTSTR; extern volatile T1CNTSTR _T1CNT @0x00000021; #define T1CNT _T1CNT.Word /*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1MODH - TIM1 Counter Modulo Register; 0x00000023 ***/ union { byte Byte; } T1MODHSTR; #define T1MODH _T1MOD.Overlap_STR.T1MODHSTR.Byte /*** T1MODL - TIM1 Counter Modulo Register; 0x00000024 ***/ union { byte Byte; } T1MODLSTR; #define T1MODL _T1MOD.Overlap_STR.T1MODLSTR.Byte } Overlap_STR; } T1MODSTR; extern volatile T1MODSTR _T1MOD @0x00000023; #define T1MOD _T1MOD.Word /*** T1SC0 - TIM1 Channel Status and Control Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit */ byte ELS0B :1; /* Edge/Level Select Bit */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } T1SC0STR; extern volatile T1SC0STR _T1SC0 @0x00000025; #define T1SC0 _T1SC0.Byte #define T1SC0_CH0MAX _T1SC0.Bits.CH0MAX #define T1SC0_TOV0 _T1SC0.Bits.TOV0 #define T1SC0_ELS0A _T1SC0.Bits.ELS0A #define T1SC0_ELS0B _T1SC0.Bits.ELS0B #define T1SC0_MS0A _T1SC0.Bits.MS0A #define T1SC0_MS0B _T1SC0.Bits.MS0B #define T1SC0_CH0IE _T1SC0.Bits.CH0IE #define T1SC0_CH0F _T1SC0.Bits.CH0F #define T1SC0_ELS0x _T1SC0.MergedBits.grpELS0x #define T1SC0_MS0x _T1SC0.MergedBits.grpMS0x #define T1SC0_CH0MAX_MASK 1 #define T1SC0_TOV0_MASK 2 #define T1SC0_ELS0A_MASK 4 #define T1SC0_ELS0B_MASK 8 #define T1SC0_MS0A_MASK 16 #define T1SC0_MS0B_MASK 32 #define T1SC0_CH0IE_MASK 64 #define T1SC0_CH0F_MASK 128 #define T1SC0_ELS0x_MASK 12 #define T1SC0_ELS0x_BITNUM 2 #define T1SC0_MS0x_MASK 48 #define T1SC0_MS0x_BITNUM 4 /*** T1CH0 - TIM1 Channel Register; 0x00000026 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CH0H - TIM1 Channel Register; 0x00000026 ***/ union { byte Byte; } T1CH0HSTR; #define T1CH0H _T1CH0.Overlap_STR.T1CH0HSTR.Byte /*** T1CH0L - TIM1 Channel Register; 0x00000027 ***/ union { byte Byte; } T1CH0LSTR; #define T1CH0L _T1CH0.Overlap_STR.T1CH0LSTR.Byte } Overlap_STR; } T1CH0STR; extern volatile T1CH0STR _T1CH0 @0x00000026; #define T1CH0 _T1CH0.Word /*** T1SC1 - TIM1 Channel Status and Control Register; 0x00000028 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit */ byte ELS1B :1; /* Edge/Level Select Bit */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } T1SC1STR; extern volatile T1SC1STR _T1SC1 @0x00000028; #define T1SC1 _T1SC1.Byte #define T1SC1_CH1MAX _T1SC1.Bits.CH1MAX #define T1SC1_TOV1 _T1SC1.Bits.TOV1 #define T1SC1_ELS1A _T1SC1.Bits.ELS1A #define T1SC1_ELS1B _T1SC1.Bits.ELS1B #define T1SC1_MS1A _T1SC1.Bits.MS1A #define T1SC1_CH1IE _T1SC1.Bits.CH1IE #define T1SC1_CH1F _T1SC1.Bits.CH1F #define T1SC1_ELS1x _T1SC1.MergedBits.grpELS1x #define T1SC1_CH1MAX_MASK 1 #define T1SC1_TOV1_MASK 2 #define T1SC1_ELS1A_MASK 4 #define T1SC1_ELS1B_MASK 8 #define T1SC1_MS1A_MASK 16 #define T1SC1_CH1IE_MASK 64 #define T1SC1_CH1F_MASK 128 #define T1SC1_ELS1x_MASK 12 #define T1SC1_ELS1x_BITNUM 2 /*** T1CH1 - TIM1 Channel Register; 0x00000029 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CH1H - TIM1 Channel Register; 0x00000029 ***/ union { byte Byte; } T1CH1HSTR; #define T1CH1H _T1CH1.Overlap_STR.T1CH1HSTR.Byte /*** T1CH1L - TIM1 Channel Register; 0x0000002A ***/ union { byte Byte; } T1CH1LSTR; #define T1CH1L _T1CH1.Overlap_STR.T1CH1LSTR.Byte } Overlap_STR; } T1CH1STR; extern volatile T1CH1STR _T1CH1 @0x00000029; #define T1CH1 _T1CH1.Word /*** T2SC - TIM2 Status and Control Register; 0x0000002B ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit */ byte PS1 :1; /* Prescaler Select Bit */ byte PS2 :1; /* Prescaler Select Bit */ byte :1; byte TRST :1; /* TIM2 Reset Bit */ byte TSTOP :1; /* TIM2 Stop Bit */ byte TOIE :1; /* TIM2 Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM2 Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } T2SCSTR; extern volatile T2SCSTR _T2SC @0x0000002B; #define T2SC _T2SC.Byte #define T2SC_PS0 _T2SC.Bits.PS0 #define T2SC_PS1 _T2SC.Bits.PS1 #define T2SC_PS2 _T2SC.Bits.PS2 #define T2SC_TRST _T2SC.Bits.TRST #define T2SC_TSTOP _T2SC.Bits.TSTOP #define T2SC_TOIE _T2SC.Bits.TOIE #define T2SC_TOF _T2SC.Bits.TOF #define T2SC_PS _T2SC.MergedBits.grpPS #define T2SC_PS0_MASK 1 #define T2SC_PS1_MASK 2 #define T2SC_PS2_MASK 4 #define T2SC_TRST_MASK 16 #define T2SC_TSTOP_MASK 32 #define T2SC_TOIE_MASK 64 #define T2SC_TOF_MASK 128 #define T2SC_PS_MASK 7 #define T2SC_PS_BITNUM 0 /*** T2CNT - TIM2 Counter Register; 0x0000002C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CNTH - TIM2 Counter Register; 0x0000002C ***/ union { byte Byte; } T2CNTHSTR; #define T2CNTH _T2CNT.Overlap_STR.T2CNTHSTR.Byte /*** T2CNTL - TIM2 Counter Register; 0x0000002D ***/ union { byte Byte; } T2CNTLSTR; #define T2CNTL _T2CNT.Overlap_STR.T2CNTLSTR.Byte } Overlap_STR; } T2CNTSTR; extern volatile T2CNTSTR _T2CNT @0x0000002C; #define T2CNT _T2CNT.Word /*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2MODH - TIM2 Counter Modulo Register; 0x0000002E ***/ union { byte Byte; } T2MODHSTR; #define T2MODH _T2MOD.Overlap_STR.T2MODHSTR.Byte /*** T2MODL - TIM2 Counter Modulo Register; 0x0000002F ***/ union { byte Byte; } T2MODLSTR; #define T2MODL _T2MOD.Overlap_STR.T2MODLSTR.Byte } Overlap_STR; } T2MODSTR; extern volatile T2MODSTR _T2MOD @0x0000002E; #define T2MOD _T2MOD.Word /*** T2SC0 - TIM2 Channel Status and Control Register; 0x00000030 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit */ byte ELS0B :1; /* Edge/Level Select Bit */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } T2SC0STR; extern volatile T2SC0STR _T2SC0 @0x00000030; #define T2SC0 _T2SC0.Byte #define T2SC0_CH0MAX _T2SC0.Bits.CH0MAX #define T2SC0_TOV0 _T2SC0.Bits.TOV0 #define T2SC0_ELS0A _T2SC0.Bits.ELS0A #define T2SC0_ELS0B _T2SC0.Bits.ELS0B #define T2SC0_MS0A _T2SC0.Bits.MS0A #define T2SC0_MS0B _T2SC0.Bits.MS0B #define T2SC0_CH0IE _T2SC0.Bits.CH0IE #define T2SC0_CH0F _T2SC0.Bits.CH0F #define T2SC0_ELS0x _T2SC0.MergedBits.grpELS0x #define T2SC0_MS0x _T2SC0.MergedBits.grpMS0x #define T2SC0_CH0MAX_MASK 1 #define T2SC0_TOV0_MASK 2 #define T2SC0_ELS0A_MASK 4 #define T2SC0_ELS0B_MASK 8 #define T2SC0_MS0A_MASK 16 #define T2SC0_MS0B_MASK 32 #define T2SC0_CH0IE_MASK 64 #define T2SC0_CH0F_MASK 128 #define T2SC0_ELS0x_MASK 12 #define T2SC0_ELS0x_BITNUM 2 #define T2SC0_MS0x_MASK 48 #define T2SC0_MS0x_BITNUM 4 /*** T2CH0 - TIM2 Channel Register; 0x00000031 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CH0H - TIM2 Channel Register; 0x00000031 ***/ union { byte Byte; } T2CH0HSTR; #define T2CH0H _T2CH0.Overlap_STR.T2CH0HSTR.Byte /*** T2CH0L - TIM2 Channel Register; 0x00000032 ***/ union { byte Byte; } T2CH0LSTR; #define T2CH0L _T2CH0.Overlap_STR.T2CH0LSTR.Byte } Overlap_STR; } T2CH0STR; extern volatile T2CH0STR _T2CH0 @0x00000031; #define T2CH0 _T2CH0.Word /*** T2SC1 - TIM2 Channel Status and Control Register; 0x00000033 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit */ byte ELS1B :1; /* Edge/Level Select Bit */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } T2SC1STR; extern volatile T2SC1STR _T2SC1 @0x00000033; #define T2SC1 _T2SC1.Byte #define T2SC1_CH1MAX _T2SC1.Bits.CH1MAX #define T2SC1_TOV1 _T2SC1.Bits.TOV1 #define T2SC1_ELS1A _T2SC1.Bits.ELS1A #define T2SC1_ELS1B _T2SC1.Bits.ELS1B #define T2SC1_MS1A _T2SC1.Bits.MS1A #define T2SC1_CH1IE _T2SC1.Bits.CH1IE #define T2SC1_CH1F _T2SC1.Bits.CH1F #define T2SC1_ELS1x _T2SC1.MergedBits.grpELS1x #define T2SC1_CH1MAX_MASK 1 #define T2SC1_TOV1_MASK 2 #define T2SC1_ELS1A_MASK 4 #define T2SC1_ELS1B_MASK 8 #define T2SC1_MS1A_MASK 16 #define T2SC1_CH1IE_MASK 64 #define T2SC1_CH1F_MASK 128 #define T2SC1_ELS1x_MASK 12 #define T2SC1_ELS1x_BITNUM 2 /*** T2CH1 - TIM2 Channel Register; 0x00000034 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CH1H - TIM2 Channel Register; 0x00000034 ***/ union { byte Byte; } T2CH1HSTR; #define T2CH1H _T2CH1.Overlap_STR.T2CH1HSTR.Byte /*** T2CH1L - TIM2 Channel Register; 0x00000035 ***/ union { byte Byte; } T2CH1LSTR; #define T2CH1L _T2CH1.Overlap_STR.T2CH1LSTR.Byte } Overlap_STR; } T2CH1STR; extern volatile T2CH1STR _T2CH1 @0x00000034; #define T2CH1 _T2CH1.Word /*** PCTL - PLL Bandwidth Control Register; 0x00000036 ***/ typedef union { byte Byte; struct { byte VPR0 :1; /* VCO Power-of-Two Range Select Bits */ byte VPR1 :1; /* VCO Power-of-Two Range Select Bits */ byte PRE0 :1; /* Prescaler Program Bits */ byte PRE1 :1; /* Prescaler Program Bits */ byte BCS :1; /* Base Clock Select Bit */ byte PLLON :1; /* PLL On Bit */ byte PLLF :1; /* PLL Flag Bit */ byte PLLIE :1; /* PLL Interrupt Enable Bit */ } Bits; struct { byte grpVPR :2; byte grpPRE :2; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PCTLSTR; extern volatile PCTLSTR _PCTL @0x00000036; #define PCTL _PCTL.Byte #define PCTL_VPR0 _PCTL.Bits.VPR0 #define PCTL_VPR1 _PCTL.Bits.VPR1 #define PCTL_PRE0 _PCTL.Bits.PRE0 #define PCTL_PRE1 _PCTL.Bits.PRE1 #define PCTL_BCS _PCTL.Bits.BCS #define PCTL_PLLON _PCTL.Bits.PLLON #define PCTL_PLLF _PCTL.Bits.PLLF #define PCTL_PLLIE _PCTL.Bits.PLLIE #define PCTL_VPR _PCTL.MergedBits.grpVPR #define PCTL_PRE _PCTL.MergedBits.grpPRE #define PCTL_VPR0_MASK 1 #define PCTL_VPR1_MASK 2 #define PCTL_PRE0_MASK 4 #define PCTL_PRE1_MASK 8 #define PCTL_BCS_MASK 16 #define PCTL_PLLON_MASK 32 #define PCTL_PLLF_MASK 64 #define PCTL_PLLIE_MASK 128 #define PCTL_VPR_MASK 3 #define PCTL_VPR_BITNUM 0 #define PCTL_PRE_MASK 12 #define PCTL_PRE_BITNUM 2 /*** PBWC - PLL Bandwidth Control Register; 0x00000037 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte ACQ :1; /* Automatic Bandwidth Control Bit */ byte LOCK :1; /* Lock Indicator Bit */ byte AUTO :1; /* Acquisiton Mode Bit */ } Bits; } PBWCSTR; extern volatile PBWCSTR _PBWC @0x00000037; #define PBWC _PBWC.Byte #define PBWC_ACQ _PBWC.Bits.ACQ #define PBWC_LOCK _PBWC.Bits.LOCK #define PBWC_AUTO _PBWC.Bits.AUTO #define PBWC_ACQ_MASK 32 #define PBWC_LOCK_MASK 64 #define PBWC_AUTO_MASK 128 /*** PMS - PLL Multiplier Select Register; 0x00000038 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** PMSH - PLL Multiplier Select Register High; 0x00000038 ***/ union { byte Byte; struct { byte MUL8 :1; /* PLL Multiplier Select Bit */ byte MUL9 :1; /* PLL Multiplier Select Bit */ byte MUL10 :1; /* PLL Multiplier Select Bit */ byte MUL11 :1; /* PLL Multiplier Select Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpMUL_8 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PMSHSTR; #define PMSH _PMS.Overlap_STR.PMSHSTR.Byte #define PMSH_MUL8 _PMS.Overlap_STR.PMSHSTR.Bits.MUL8 #define PMSH_MUL9 _PMS.Overlap_STR.PMSHSTR.Bits.MUL9 #define PMSH_MUL10 _PMS.Overlap_STR.PMSHSTR.Bits.MUL10 #define PMSH_MUL11 _PMS.Overlap_STR.PMSHSTR.Bits.MUL11 #define PMSH_MUL_8 _PMS.Overlap_STR.PMSHSTR.MergedBits.grpMUL_8 #define PMSH_MUL PMSH_MUL_8 #define PMSH_MUL8_MASK 1 #define PMSH_MUL9_MASK 2 #define PMSH_MUL10_MASK 4 #define PMSH_MUL11_MASK 8 #define PMSH_MUL_8_MASK 15 #define PMSH_MUL_8_BITNUM 0 /*** PMSL - PLL Multiplier Select Register Low; 0x00000039 ***/ union { byte Byte; struct { byte MUL0 :1; /* PLL Multiplier Select Bit */ byte MUL1 :1; /* PLL Multiplier Select Bit */ byte MUL2 :1; /* PLL Multiplier Select Bit */ byte MUL3 :1; /* PLL Multiplier Select Bit */ byte MUL4 :1; /* PLL Multiplier Select Bit */ byte MUL5 :1; /* PLL Multiplier Select Bit */ byte MUL6 :1; /* PLL Multiplier Select Bit */ byte MUL7 :1; /* PLL Multiplier Select Bit */ } Bits; } PMSLSTR; #define PMSL _PMS.Overlap_STR.PMSLSTR.Byte #define PMSL_MUL0 _PMS.Overlap_STR.PMSLSTR.Bits.MUL0 #define PMSL_MUL1 _PMS.Overlap_STR.PMSLSTR.Bits.MUL1 #define PMSL_MUL2 _PMS.Overlap_STR.PMSLSTR.Bits.MUL2 #define PMSL_MUL3 _PMS.Overlap_STR.PMSLSTR.Bits.MUL3 #define PMSL_MUL4 _PMS.Overlap_STR.PMSLSTR.Bits.MUL4 #define PMSL_MUL5 _PMS.Overlap_STR.PMSLSTR.Bits.MUL5 #define PMSL_MUL6 _PMS.Overlap_STR.PMSLSTR.Bits.MUL6 #define PMSL_MUL7 _PMS.Overlap_STR.PMSLSTR.Bits.MUL7 #define PMSL_MUL0_MASK 1 #define PMSL_MUL1_MASK 2 #define PMSL_MUL2_MASK 4 #define PMSL_MUL3_MASK 8 #define PMSL_MUL4_MASK 16 #define PMSL_MUL5_MASK 32 #define PMSL_MUL6_MASK 64 #define PMSL_MUL7_MASK 128 } Overlap_STR; } PMSSTR; extern volatile PMSSTR _PMS @0x00000038; #define PMS _PMS.Word /*** PMRS - PLL VCO Range Select; 0x0000003A ***/ typedef union { byte Byte; struct { byte VRS0 :1; /* VCO Range Select Bit */ byte VRS1 :1; /* VCO Range Select Bit */ byte VRS2 :1; /* VCO Range Select Bit */ byte VRS3 :1; /* VCO Range Select Bit */ byte VRS4 :1; /* VCO Range Select Bit */ byte VRS5 :1; /* VCO Range Select Bit */ byte VRS6 :1; /* VCO Range Select Bit */ byte VRS7 :1; /* VCO Range Select Bit */ } Bits; } PMRSSTR; extern volatile PMRSSTR _PMRS @0x0000003A; #define PMRS _PMRS.Byte #define PMRS_VRS0 _PMRS.Bits.VRS0 #define PMRS_VRS1 _PMRS.Bits.VRS1 #define PMRS_VRS2 _PMRS.Bits.VRS2 #define PMRS_VRS3 _PMRS.Bits.VRS3 #define PMRS_VRS4 _PMRS.Bits.VRS4 #define PMRS_VRS5 _PMRS.Bits.VRS5 #define PMRS_VRS6 _PMRS.Bits.VRS6 #define PMRS_VRS7 _PMRS.Bits.VRS7 #define PMRS_VRS0_MASK 1 #define PMRS_VRS1_MASK 2 #define PMRS_VRS2_MASK 4 #define PMRS_VRS3_MASK 8 #define PMRS_VRS4_MASK 16 #define PMRS_VRS5_MASK 32 #define PMRS_VRS6_MASK 64 #define PMRS_VRS7_MASK 128 /*** PMDS - PLL Reference Divider Select Register; 0x0000003B ***/ typedef union { byte Byte; struct { byte RDS0 :1; /* Reference Divider Select Bit */ byte RDS1 :1; /* Reference Divider Select Bit */ byte RDS2 :1; /* Reference Divider Select Bit */ byte RDS3 :1; /* Reference Divider Select Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpRDS :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PMDSSTR; extern volatile PMDSSTR _PMDS @0x0000003B; #define PMDS _PMDS.Byte #define PMDS_RDS0 _PMDS.Bits.RDS0 #define PMDS_RDS1 _PMDS.Bits.RDS1 #define PMDS_RDS2 _PMDS.Bits.RDS2 #define PMDS_RDS3 _PMDS.Bits.RDS3 #define PMDS_RDS _PMDS.MergedBits.grpRDS #define PMDS_RDS0_MASK 1 #define PMDS_RDS1_MASK 2 #define PMDS_RDS2_MASK 4 #define PMDS_RDS3_MASK 8 #define PMDS_RDS_MASK 15 #define PMDS_RDS_BITNUM 0 /*** ADCSC - ADC Status and Control Register; 0x0000003C ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADCSCSTR; extern volatile ADCSCSTR _ADCSC @0x0000003C; #define ADCSC _ADCSC.Byte #define ADCSC_ADCH0 _ADCSC.Bits.ADCH0 #define ADCSC_ADCH1 _ADCSC.Bits.ADCH1 #define ADCSC_ADCH2 _ADCSC.Bits.ADCH2 #define ADCSC_ADCH3 _ADCSC.Bits.ADCH3 #define ADCSC_ADCH4 _ADCSC.Bits.ADCH4 #define ADCSC_ADCO _ADCSC.Bits.ADCO #define ADCSC_AIEN _ADCSC.Bits.AIEN #define ADCSC_COCO _ADCSC.Bits.COCO #define ADCSC_ADCH _ADCSC.MergedBits.grpADCH #define ADCSC_ADCH0_MASK 1 #define ADCSC_ADCH1_MASK 2 #define ADCSC_ADCH2_MASK 4 #define ADCSC_ADCH3_MASK 8 #define ADCSC_ADCH4_MASK 16 #define ADCSC_ADCO_MASK 32 #define ADCSC_AIEN_MASK 64 #define ADCSC_COCO_MASK 128 #define ADCSC_ADCH_MASK 31 #define ADCSC_ADCH_BITNUM 0 /*** ADR - ADC Data Register; 0x0000003D ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADRH - ADC Data Register High; 0x0000003D ***/ union { byte Byte; struct { byte BIT8 :1; /* ADC Data Bit 8 */ byte BIT9 :1; /* ADC Data Bit 9 */ byte BIT10 :1; /* ADC Data Bit 10 */ byte BIT11 :1; /* ADC Data Bit 11 */ byte BIT12 :1; /* ADC Data Bit 12 */ byte BIT13 :1; /* ADC Data Bit 13 */ byte BIT14 :1; /* ADC Data Bit 14 */ byte BIT15 :1; /* ADC Data Bit 15 */ } Bits; } ADRHSTR; #define ADRH _ADR.Overlap_STR.ADRHSTR.Byte #define ADRH_BIT8 _ADR.Overlap_STR.ADRHSTR.Bits.BIT8 #define ADRH_BIT9 _ADR.Overlap_STR.ADRHSTR.Bits.BIT9 #define ADRH_BIT10 _ADR.Overlap_STR.ADRHSTR.Bits.BIT10 #define ADRH_BIT11 _ADR.Overlap_STR.ADRHSTR.Bits.BIT11 #define ADRH_BIT12 _ADR.Overlap_STR.ADRHSTR.Bits.BIT12 #define ADRH_BIT13 _ADR.Overlap_STR.ADRHSTR.Bits.BIT13 #define ADRH_BIT14 _ADR.Overlap_STR.ADRHSTR.Bits.BIT14 #define ADRH_BIT15 _ADR.Overlap_STR.ADRHSTR.Bits.BIT15 #define ADRH_BIT8_MASK 1 #define ADRH_BIT9_MASK 2 #define ADRH_BIT10_MASK 4 #define ADRH_BIT11_MASK 8 #define ADRH_BIT12_MASK 16 #define ADRH_BIT13_MASK 32 #define ADRH_BIT14_MASK 64 #define ADRH_BIT15_MASK 128 /*** ADRL - ADC Data Register Low; 0x0000003E ***/ union { byte Byte; struct { byte BIT0 :1; /* ADC Data Bit 0 */ byte BIT1 :1; /* ADC Data Bit 1 */ byte BIT2 :1; /* ADC Data Bit 2 */ byte BIT3 :1; /* ADC Data Bit 3 */ byte BIT4 :1; /* ADC Data Bit 4 */ byte BIT5 :1; /* ADC Data Bit 5 */ byte BIT6 :1; /* ADC Data Bit 6 */ byte BIT7 :1; /* ADC Data Bit 7 */ } Bits; } ADRLSTR; #define ADRL _ADR.Overlap_STR.ADRLSTR.Byte #define ADRL_BIT0 _ADR.Overlap_STR.ADRLSTR.Bits.BIT0 #define ADRL_BIT1 _ADR.Overlap_STR.ADRLSTR.Bits.BIT1 #define ADRL_BIT2 _ADR.Overlap_STR.ADRLSTR.Bits.BIT2 #define ADRL_BIT3 _ADR.Overlap_STR.ADRLSTR.Bits.BIT3 #define ADRL_BIT4 _ADR.Overlap_STR.ADRLSTR.Bits.BIT4 #define ADRL_BIT5 _ADR.Overlap_STR.ADRLSTR.Bits.BIT5 #define ADRL_BIT6 _ADR.Overlap_STR.ADRLSTR.Bits.BIT6 #define ADRL_BIT7 _ADR.Overlap_STR.ADRLSTR.Bits.BIT7 #define ADRL_BIT0_MASK 1 #define ADRL_BIT1_MASK 2 #define ADRL_BIT2_MASK 4 #define ADRL_BIT3_MASK 8 #define ADRL_BIT4_MASK 16 #define ADRL_BIT5_MASK 32 #define ADRL_BIT6_MASK 64 #define ADRL_BIT7_MASK 128 } Overlap_STR; } ADRSTR; extern volatile ADRSTR _ADR @0x0000003D; #define ADR _ADR.Word /*** ADCLK - ADC Input Clock Register; 0x0000003F ***/ typedef union { byte Byte; struct { byte ACLKEN :1; /* Asynchronous Clock Source Enable */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte MODE0 :1; /* Modes of Result Justification Bit 0 */ byte MODE1 :1; /* Modes of Result Justification Bit 1 */ byte ADICLK :1; /* ADC10 Input Clock Register Bit */ byte ADIV0 :1; /* ADC10 Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC10 Clock Prescaler Bit 1 */ byte ADLPC :1; /* ADC10 Low-Power Configuration Bit */ } Bits; struct { byte :1; byte :1; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADCLKSTR; extern volatile ADCLKSTR _ADCLK @0x0000003F; #define ADCLK _ADCLK.Byte #define ADCLK_ACLKEN _ADCLK.Bits.ACLKEN #define ADCLK_ADLSMP _ADCLK.Bits.ADLSMP #define ADCLK_MODE0 _ADCLK.Bits.MODE0 #define ADCLK_MODE1 _ADCLK.Bits.MODE1 #define ADCLK_ADICLK _ADCLK.Bits.ADICLK #define ADCLK_ADIV0 _ADCLK.Bits.ADIV0 #define ADCLK_ADIV1 _ADCLK.Bits.ADIV1 #define ADCLK_ADLPC _ADCLK.Bits.ADLPC #define ADCLK_MODE _ADCLK.MergedBits.grpMODE #define ADCLK_ADIV _ADCLK.MergedBits.grpADIV #define ADCLK_ACLKEN_MASK 1 #define ADCLK_ADLSMP_MASK 2 #define ADCLK_MODE0_MASK 4 #define ADCLK_MODE1_MASK 8 #define ADCLK_ADICLK_MASK 16 #define ADCLK_ADIV0_MASK 32 #define ADCLK_ADIV1_MASK 64 #define ADCLK_ADLPC_MASK 128 #define ADCLK_MODE_MASK 12 #define ADCLK_MODE_BITNUM 2 #define ADCLK_ADIV_MASK 96 #define ADCLK_ADIV_BITNUM 5 /*** LCDCLK - LCD Clock Register; 0x0000004F ***/ typedef union { byte Byte; struct { byte LCLK0 :1; /* LCD Waweform Base Clock Select 0 */ byte LCLK1 :1; /* LCD Waweform Base Clock Select 1 */ byte LCLK2 :1; /* LCD Waweform Base Clock Select 2 */ byte DUTY0 :1; /* Duty Cycle Select Bit 0 */ byte DUTY1 :1; /* Duty Cycle Select Bit 1 */ byte FCCLT0 :1; /* Fast Charde Duty Cycle Select Bit 0 */ byte FCCLT1 :1; /* Fast Charde Duty Cycle Select Bit 1 */ byte :1; } Bits; struct { byte grpLCLK :3; byte grpDUTY :2; byte grpFCCLT :2; byte :1; } MergedBits; } LCDCLKSTR; extern volatile LCDCLKSTR _LCDCLK @0x0000004F; #define LCDCLK _LCDCLK.Byte #define LCDCLK_LCLK0 _LCDCLK.Bits.LCLK0 #define LCDCLK_LCLK1 _LCDCLK.Bits.LCLK1 #define LCDCLK_LCLK2 _LCDCLK.Bits.LCLK2 #define LCDCLK_DUTY0 _LCDCLK.Bits.DUTY0 #define LCDCLK_DUTY1 _LCDCLK.Bits.DUTY1 #define LCDCLK_FCCLT0 _LCDCLK.Bits.FCCLT0 #define LCDCLK_FCCLT1 _LCDCLK.Bits.FCCLT1 #define LCDCLK_LCLK _LCDCLK.MergedBits.grpLCLK #define LCDCLK_DUTY _LCDCLK.MergedBits.grpDUTY #define LCDCLK_FCCLT _LCDCLK.MergedBits.grpFCCLT #define LCDCLK_LCLK0_MASK 1 #define LCDCLK_LCLK1_MASK 2 #define LCDCLK_LCLK2_MASK 4 #define LCDCLK_DUTY0_MASK 8 #define LCDCLK_DUTY1_MASK 16 #define LCDCLK_FCCLT0_MASK 32 #define LCDCLK_FCCLT1_MASK 64 #define LCDCLK_LCLK_MASK 7 #define LCDCLK_LCLK_BITNUM 0 #define LCDCLK_DUTY_MASK 24 #define LCDCLK_DUTY_BITNUM 3 #define LCDCLK_FCCLT_MASK 96 #define LCDCLK_FCCLT_BITNUM 5 /*** LCDCR - LCD Control Register; 0x00000051 ***/ typedef union { byte Byte; struct { byte LCCON0 :1; /* LCD Contrast Control Bit 0 */ byte LCCON1 :1; /* LCD Contrast Control Bit 1 */ byte LCCON2 :1; /* LCD Contrast Control Bit 2 */ byte LCCON3 :1; /* LCD Contrast Control Bit 3 */ byte LC :1; /* Low Current */ byte FC :1; /* Fast Charge */ byte :1; byte LCDE :1; /* LCD Enable */ } Bits; struct { byte grpLCCON :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDCRSTR; extern volatile LCDCRSTR _LCDCR @0x00000051; #define LCDCR _LCDCR.Byte #define LCDCR_LCCON0 _LCDCR.Bits.LCCON0 #define LCDCR_LCCON1 _LCDCR.Bits.LCCON1 #define LCDCR_LCCON2 _LCDCR.Bits.LCCON2 #define LCDCR_LCCON3 _LCDCR.Bits.LCCON3 #define LCDCR_LC _LCDCR.Bits.LC #define LCDCR_FC _LCDCR.Bits.FC #define LCDCR_LCDE _LCDCR.Bits.LCDE #define LCDCR_LCCON _LCDCR.MergedBits.grpLCCON #define LCDCR_LCCON0_MASK 1 #define LCDCR_LCCON1_MASK 2 #define LCDCR_LCCON2_MASK 4 #define LCDCR_LCCON3_MASK 8 #define LCDCR_LC_MASK 16 #define LCDCR_FC_MASK 32 #define LCDCR_LCDE_MASK 128 #define LCDCR_LCCON_MASK 15 #define LCDCR_LCCON_BITNUM 0 /*** LDAT1 - LCD Data Register; 0x00000052 ***/ typedef union { byte Byte; struct { byte F0B0 :1; /* LCD Segment 0 Data Bit 0 */ byte F0B1 :1; /* LCD Segment 0 Data Bit 1 */ byte F0B2 :1; /* LCD Segment 0 Data Bit 2 */ byte F0B3 :1; /* LCD Segment 0 Data Bit 3 */ byte F1B0 :1; /* LCD Segment 1 Data Bit 0 */ byte F1B1 :1; /* LCD Segment 1 Data Bit 1 */ byte F1B2 :1; /* LCD Segment 1 Data Bit 2 */ byte F1B3 :1; /* LCD Segment 1 Data Bit 3 */ } Bits; struct { byte grpF0B :4; byte grpF1B :4; } MergedBits; } LDAT1STR; extern volatile LDAT1STR _LDAT1 @0x00000052; #define LDAT1 _LDAT1.Byte #define LDAT1_F0B0 _LDAT1.Bits.F0B0 #define LDAT1_F0B1 _LDAT1.Bits.F0B1 #define LDAT1_F0B2 _LDAT1.Bits.F0B2 #define LDAT1_F0B3 _LDAT1.Bits.F0B3 #define LDAT1_F1B0 _LDAT1.Bits.F1B0 #define LDAT1_F1B1 _LDAT1.Bits.F1B1 #define LDAT1_F1B2 _LDAT1.Bits.F1B2 #define LDAT1_F1B3 _LDAT1.Bits.F1B3 #define LDAT1_F0B _LDAT1.MergedBits.grpF0B #define LDAT1_F1B _LDAT1.MergedBits.grpF1B #define LDAT1_F0B0_MASK 1 #define LDAT1_F0B1_MASK 2 #define LDAT1_F0B2_MASK 4 #define LDAT1_F0B3_MASK 8 #define LDAT1_F1B0_MASK 16 #define LDAT1_F1B1_MASK 32 #define LDAT1_F1B2_MASK 64 #define LDAT1_F1B3_MASK 128 #define LDAT1_F0B_MASK 15 #define LDAT1_F0B_BITNUM 0 #define LDAT1_F1B_MASK 240 #define LDAT1_F1B_BITNUM 4 /*** LDAT2 - LCD Data Register; 0x00000053 ***/ typedef union { byte Byte; struct { byte F2B0 :1; /* LCD Segment 2 Data Bit 0 */ byte F2B1 :1; /* LCD Segment 2 Data Bit 1 */ byte F2B2 :1; /* LCD Segment 2 Data Bit 2 */ byte F2B3 :1; /* LCD Segment 2 Data Bit 3 */ byte F3B0 :1; /* LCD Segment 3 Data Bit 0 */ byte F3B1 :1; /* LCD Segment 3 Data Bit 1 */ byte F3B2 :1; /* LCD Segment 3 Data Bit 2 */ byte F3B3 :1; /* LCD Segment 3 Data Bit 3 */ } Bits; struct { byte grpF2B :4; byte grpF3B :4; } MergedBits; } LDAT2STR; extern volatile LDAT2STR _LDAT2 @0x00000053; #define LDAT2 _LDAT2.Byte #define LDAT2_F2B0 _LDAT2.Bits.F2B0 #define LDAT2_F2B1 _LDAT2.Bits.F2B1 #define LDAT2_F2B2 _LDAT2.Bits.F2B2 #define LDAT2_F2B3 _LDAT2.Bits.F2B3 #define LDAT2_F3B0 _LDAT2.Bits.F3B0 #define LDAT2_F3B1 _LDAT2.Bits.F3B1 #define LDAT2_F3B2 _LDAT2.Bits.F3B2 #define LDAT2_F3B3 _LDAT2.Bits.F3B3 #define LDAT2_F2B _LDAT2.MergedBits.grpF2B #define LDAT2_F3B _LDAT2.MergedBits.grpF3B #define LDAT2_F2B0_MASK 1 #define LDAT2_F2B1_MASK 2 #define LDAT2_F2B2_MASK 4 #define LDAT2_F2B3_MASK 8 #define LDAT2_F3B0_MASK 16 #define LDAT2_F3B1_MASK 32 #define LDAT2_F3B2_MASK 64 #define LDAT2_F3B3_MASK 128 #define LDAT2_F2B_MASK 15 #define LDAT2_F2B_BITNUM 0 #define LDAT2_F3B_MASK 240 #define LDAT2_F3B_BITNUM 4 /*** LDAT3 - LCD Data Register; 0x00000054 ***/ typedef union { byte Byte; struct { byte F4B0 :1; /* LCD Segment 4 Data Bit 0 */ byte F4B1 :1; /* LCD Segment 4 Data Bit 1 */ byte F4B2 :1; /* LCD Segment 4 Data Bit 2 */ byte F4B3 :1; /* LCD Segment 4 Data Bit 3 */ byte F5B0 :1; /* LCD Segment 5 Data Bit 0 */ byte F5B1 :1; /* LCD Segment 5 Data Bit 1 */ byte F5B2 :1; /* LCD Segment 5 Data Bit 2 */ byte F5B3 :1; /* LCD Segment 5 Data Bit 3 */ } Bits; struct { byte grpF4B :4; byte grpF5B :4; } MergedBits; } LDAT3STR; extern volatile LDAT3STR _LDAT3 @0x00000054; #define LDAT3 _LDAT3.Byte #define LDAT3_F4B0 _LDAT3.Bits.F4B0 #define LDAT3_F4B1 _LDAT3.Bits.F4B1 #define LDAT3_F4B2 _LDAT3.Bits.F4B2 #define LDAT3_F4B3 _LDAT3.Bits.F4B3 #define LDAT3_F5B0 _LDAT3.Bits.F5B0 #define LDAT3_F5B1 _LDAT3.Bits.F5B1 #define LDAT3_F5B2 _LDAT3.Bits.F5B2 #define LDAT3_F5B3 _LDAT3.Bits.F5B3 #define LDAT3_F4B _LDAT3.MergedBits.grpF4B #define LDAT3_F5B _LDAT3.MergedBits.grpF5B #define LDAT3_F4B0_MASK 1 #define LDAT3_F4B1_MASK 2 #define LDAT3_F4B2_MASK 4 #define LDAT3_F4B3_MASK 8 #define LDAT3_F5B0_MASK 16 #define LDAT3_F5B1_MASK 32 #define LDAT3_F5B2_MASK 64 #define LDAT3_F5B3_MASK 128 #define LDAT3_F4B_MASK 15 #define LDAT3_F4B_BITNUM 0 #define LDAT3_F5B_MASK 240 #define LDAT3_F5B_BITNUM 4 /*** LDAT4 - LCD Data Register; 0x00000055 ***/ typedef union { byte Byte; struct { byte F6B0 :1; /* LCD Segment 6 Data Bit 0 */ byte F6B1 :1; /* LCD Segment 6 Data Bit 1 */ byte F6B2 :1; /* LCD Segment 6 Data Bit 2 */ byte F6B3 :1; /* LCD Segment 6 Data Bit 3 */ byte F7B0 :1; /* LCD Segment 7 Data Bit 0 */ byte F7B1 :1; /* LCD Segment 7 Data Bit 1 */ byte F7B2 :1; /* LCD Segment 7 Data Bit 2 */ byte F7B3 :1; /* LCD Segment 7 Data Bit 3 */ } Bits; struct { byte grpF6B :4; byte grpF7B :4; } MergedBits; } LDAT4STR; extern volatile LDAT4STR _LDAT4 @0x00000055; #define LDAT4 _LDAT4.Byte #define LDAT4_F6B0 _LDAT4.Bits.F6B0 #define LDAT4_F6B1 _LDAT4.Bits.F6B1 #define LDAT4_F6B2 _LDAT4.Bits.F6B2 #define LDAT4_F6B3 _LDAT4.Bits.F6B3 #define LDAT4_F7B0 _LDAT4.Bits.F7B0 #define LDAT4_F7B1 _LDAT4.Bits.F7B1 #define LDAT4_F7B2 _LDAT4.Bits.F7B2 #define LDAT4_F7B3 _LDAT4.Bits.F7B3 #define LDAT4_F6B _LDAT4.MergedBits.grpF6B #define LDAT4_F7B _LDAT4.MergedBits.grpF7B #define LDAT4_F6B0_MASK 1 #define LDAT4_F6B1_MASK 2 #define LDAT4_F6B2_MASK 4 #define LDAT4_F6B3_MASK 8 #define LDAT4_F7B0_MASK 16 #define LDAT4_F7B1_MASK 32 #define LDAT4_F7B2_MASK 64 #define LDAT4_F7B3_MASK 128 #define LDAT4_F6B_MASK 15 #define LDAT4_F6B_BITNUM 0 #define LDAT4_F7B_MASK 240 #define LDAT4_F7B_BITNUM 4 /*** LDAT5 - LCD Data Register; 0x00000056 ***/ typedef union { byte Byte; struct { byte F8B0 :1; /* LCD Segment 8 Data Bit 0 */ byte F8B1 :1; /* LCD Segment 8 Data Bit 1 */ byte F8B2 :1; /* LCD Segment 8 Data Bit 2 */ byte F8B3 :1; /* LCD Segment 8 Data Bit 3 */ byte F9B0 :1; /* LCD Segment 9 Data Bit 0 */ byte F9B1 :1; /* LCD Segment 9 Data Bit 1 */ byte F9B2 :1; /* LCD Segment 9 Data Bit 2 */ byte F9B3 :1; /* LCD Segment 9 Data Bit 3 */ } Bits; struct { byte grpF8B :4; byte grpF9B :4; } MergedBits; } LDAT5STR; extern volatile LDAT5STR _LDAT5 @0x00000056; #define LDAT5 _LDAT5.Byte #define LDAT5_F8B0 _LDAT5.Bits.F8B0 #define LDAT5_F8B1 _LDAT5.Bits.F8B1 #define LDAT5_F8B2 _LDAT5.Bits.F8B2 #define LDAT5_F8B3 _LDAT5.Bits.F8B3 #define LDAT5_F9B0 _LDAT5.Bits.F9B0 #define LDAT5_F9B1 _LDAT5.Bits.F9B1 #define LDAT5_F9B2 _LDAT5.Bits.F9B2 #define LDAT5_F9B3 _LDAT5.Bits.F9B3 #define LDAT5_F8B _LDAT5.MergedBits.grpF8B #define LDAT5_F9B _LDAT5.MergedBits.grpF9B #define LDAT5_F8B0_MASK 1 #define LDAT5_F8B1_MASK 2 #define LDAT5_F8B2_MASK 4 #define LDAT5_F8B3_MASK 8 #define LDAT5_F9B0_MASK 16 #define LDAT5_F9B1_MASK 32 #define LDAT5_F9B2_MASK 64 #define LDAT5_F9B3_MASK 128 #define LDAT5_F8B_MASK 15 #define LDAT5_F8B_BITNUM 0 #define LDAT5_F9B_MASK 240 #define LDAT5_F9B_BITNUM 4 /*** LDAT6 - LCD Data Register; 0x00000057 ***/ typedef union { byte Byte; struct { byte F10B0 :1; /* LCD Segment 10 Data Bit 0 */ byte F10B1 :1; /* LCD Segment 10 Data Bit 1 */ byte F10B2 :1; /* LCD Segment 10 Data Bit 2 */ byte F10B3 :1; /* LCD Segment 10 Data Bit 3 */ byte F11B0 :1; /* LCD Segment 11 Data Bit 0 */ byte F11B1 :1; /* LCD Segment 11 Data Bit 1 */ byte F11B2 :1; /* LCD Segment 11 Data Bit 2 */ byte F11B3 :1; /* LCD Segment 11 Data Bit 3 */ } Bits; struct { byte grpF10B :4; byte grpF11B :4; } MergedBits; } LDAT6STR; extern volatile LDAT6STR _LDAT6 @0x00000057; #define LDAT6 _LDAT6.Byte #define LDAT6_F10B0 _LDAT6.Bits.F10B0 #define LDAT6_F10B1 _LDAT6.Bits.F10B1 #define LDAT6_F10B2 _LDAT6.Bits.F10B2 #define LDAT6_F10B3 _LDAT6.Bits.F10B3 #define LDAT6_F11B0 _LDAT6.Bits.F11B0 #define LDAT6_F11B1 _LDAT6.Bits.F11B1 #define LDAT6_F11B2 _LDAT6.Bits.F11B2 #define LDAT6_F11B3 _LDAT6.Bits.F11B3 #define LDAT6_F10B _LDAT6.MergedBits.grpF10B #define LDAT6_F11B _LDAT6.MergedBits.grpF11B #define LDAT6_F10B0_MASK 1 #define LDAT6_F10B1_MASK 2 #define LDAT6_F10B2_MASK 4 #define LDAT6_F10B3_MASK 8 #define LDAT6_F11B0_MASK 16 #define LDAT6_F11B1_MASK 32 #define LDAT6_F11B2_MASK 64 #define LDAT6_F11B3_MASK 128 #define LDAT6_F10B_MASK 15 #define LDAT6_F10B_BITNUM 0 #define LDAT6_F11B_MASK 240 #define LDAT6_F11B_BITNUM 4 /*** LDAT7 - LCD Data Register; 0x00000058 ***/ typedef union { byte Byte; struct { byte F12B0 :1; /* LCD Segment 12 Data Bit 0 */ byte F12B1 :1; /* LCD Segment 12 Data Bit 1 */ byte F12B2 :1; /* LCD Segment 12 Data Bit 2 */ byte F12B3 :1; /* LCD Segment 12 Data Bit 3 */ byte F13B0 :1; /* LCD Segment 13 Data Bit 0 */ byte F13B1 :1; /* LCD Segment 13 Data Bit 1 */ byte F13B2 :1; /* LCD Segment 13 Data Bit 2 */ byte F13B3 :1; /* LCD Segment 13 Data Bit 3 */ } Bits; struct { byte grpF12B :4; byte grpF13B :4; } MergedBits; } LDAT7STR; extern volatile LDAT7STR _LDAT7 @0x00000058; #define LDAT7 _LDAT7.Byte #define LDAT7_F12B0 _LDAT7.Bits.F12B0 #define LDAT7_F12B1 _LDAT7.Bits.F12B1 #define LDAT7_F12B2 _LDAT7.Bits.F12B2 #define LDAT7_F12B3 _LDAT7.Bits.F12B3 #define LDAT7_F13B0 _LDAT7.Bits.F13B0 #define LDAT7_F13B1 _LDAT7.Bits.F13B1 #define LDAT7_F13B2 _LDAT7.Bits.F13B2 #define LDAT7_F13B3 _LDAT7.Bits.F13B3 #define LDAT7_F12B _LDAT7.MergedBits.grpF12B #define LDAT7_F13B _LDAT7.MergedBits.grpF13B #define LDAT7_F12B0_MASK 1 #define LDAT7_F12B1_MASK 2 #define LDAT7_F12B2_MASK 4 #define LDAT7_F12B3_MASK 8 #define LDAT7_F13B0_MASK 16 #define LDAT7_F13B1_MASK 32 #define LDAT7_F13B2_MASK 64 #define LDAT7_F13B3_MASK 128 #define LDAT7_F12B_MASK 15 #define LDAT7_F12B_BITNUM 0 #define LDAT7_F13B_MASK 240 #define LDAT7_F13B_BITNUM 4 /*** LDAT8 - LCD Data Register; 0x00000059 ***/ typedef union { byte Byte; struct { byte F14B0 :1; /* LCD Segment 14 Data Bit 0 */ byte F14B1 :1; /* LCD Segment 14 Data Bit 1 */ byte F14B2 :1; /* LCD Segment 14 Data Bit 2 */ byte F14B3 :1; /* LCD Segment 14 Data Bit 3 */ byte F15B0 :1; /* LCD Segment 15 Data Bit 0 */ byte F15B1 :1; /* LCD Segment 15 Data Bit 1 */ byte F15B2 :1; /* LCD Segment 15 Data Bit 2 */ byte F15B3 :1; /* LCD Segment 15 Data Bit 3 */ } Bits; struct { byte grpF14B :4; byte grpF15B :4; } MergedBits; } LDAT8STR; extern volatile LDAT8STR _LDAT8 @0x00000059; #define LDAT8 _LDAT8.Byte #define LDAT8_F14B0 _LDAT8.Bits.F14B0 #define LDAT8_F14B1 _LDAT8.Bits.F14B1 #define LDAT8_F14B2 _LDAT8.Bits.F14B2 #define LDAT8_F14B3 _LDAT8.Bits.F14B3 #define LDAT8_F15B0 _LDAT8.Bits.F15B0 #define LDAT8_F15B1 _LDAT8.Bits.F15B1 #define LDAT8_F15B2 _LDAT8.Bits.F15B2 #define LDAT8_F15B3 _LDAT8.Bits.F15B3 #define LDAT8_F14B _LDAT8.MergedBits.grpF14B #define LDAT8_F15B _LDAT8.MergedBits.grpF15B #define LDAT8_F14B0_MASK 1 #define LDAT8_F14B1_MASK 2 #define LDAT8_F14B2_MASK 4 #define LDAT8_F14B3_MASK 8 #define LDAT8_F15B0_MASK 16 #define LDAT8_F15B1_MASK 32 #define LDAT8_F15B2_MASK 64 #define LDAT8_F15B3_MASK 128 #define LDAT8_F14B_MASK 15 #define LDAT8_F14B_BITNUM 0 #define LDAT8_F15B_MASK 240 #define LDAT8_F15B_BITNUM 4 /*** LDAT9 - LCD Data Register; 0x0000005A ***/ typedef union { byte Byte; struct { byte F16B0 :1; /* LCD Segment 16 Data Bit 0 */ byte F16B1 :1; /* LCD Segment 16 Data Bit 1 */ byte F16B2 :1; /* LCD Segment 16 Data Bit 2 */ byte F16B3 :1; /* LCD Segment 16 Data Bit 3 */ byte F17B0 :1; /* LCD Segment 17 Data Bit 0 */ byte F17B1 :1; /* LCD Segment 17 Data Bit 1 */ byte F17B2 :1; /* LCD Segment 17 Data Bit 2 */ byte F17B3 :1; /* LCD Segment 17 Data Bit 3 */ } Bits; struct { byte grpF16B :4; byte grpF17B :4; } MergedBits; } LDAT9STR; extern volatile LDAT9STR _LDAT9 @0x0000005A; #define LDAT9 _LDAT9.Byte #define LDAT9_F16B0 _LDAT9.Bits.F16B0 #define LDAT9_F16B1 _LDAT9.Bits.F16B1 #define LDAT9_F16B2 _LDAT9.Bits.F16B2 #define LDAT9_F16B3 _LDAT9.Bits.F16B3 #define LDAT9_F17B0 _LDAT9.Bits.F17B0 #define LDAT9_F17B1 _LDAT9.Bits.F17B1 #define LDAT9_F17B2 _LDAT9.Bits.F17B2 #define LDAT9_F17B3 _LDAT9.Bits.F17B3 #define LDAT9_F16B _LDAT9.MergedBits.grpF16B #define LDAT9_F17B _LDAT9.MergedBits.grpF17B #define LDAT9_F16B0_MASK 1 #define LDAT9_F16B1_MASK 2 #define LDAT9_F16B2_MASK 4 #define LDAT9_F16B3_MASK 8 #define LDAT9_F17B0_MASK 16 #define LDAT9_F17B1_MASK 32 #define LDAT9_F17B2_MASK 64 #define LDAT9_F17B3_MASK 128 #define LDAT9_F16B_MASK 15 #define LDAT9_F16B_BITNUM 0 #define LDAT9_F17B_MASK 240 #define LDAT9_F17B_BITNUM 4 /*** LDAT10 - LCD Data Register; 0x0000005B ***/ typedef union { byte Byte; struct { byte F18B0 :1; /* LCD Segment 18 Data Bit 0 */ byte F18B1 :1; /* LCD Segment 18 Data Bit 1 */ byte F18B2 :1; /* LCD Segment 18 Data Bit 2 */ byte F18B3 :1; /* LCD Segment 18 Data Bit 3 */ byte F19B0 :1; /* LCD Segment 19 Data Bit 0 */ byte F19B1 :1; /* LCD Segment 19 Data Bit 1 */ byte F19B2 :1; /* LCD Segment 19 Data Bit 2 */ byte F19B3 :1; /* LCD Segment 19 Data Bit 3 */ } Bits; struct { byte grpF18B :4; byte grpF19B :4; } MergedBits; } LDAT10STR; extern volatile LDAT10STR _LDAT10 @0x0000005B; #define LDAT10 _LDAT10.Byte #define LDAT10_F18B0 _LDAT10.Bits.F18B0 #define LDAT10_F18B1 _LDAT10.Bits.F18B1 #define LDAT10_F18B2 _LDAT10.Bits.F18B2 #define LDAT10_F18B3 _LDAT10.Bits.F18B3 #define LDAT10_F19B0 _LDAT10.Bits.F19B0 #define LDAT10_F19B1 _LDAT10.Bits.F19B1 #define LDAT10_F19B2 _LDAT10.Bits.F19B2 #define LDAT10_F19B3 _LDAT10.Bits.F19B3 #define LDAT10_F18B _LDAT10.MergedBits.grpF18B #define LDAT10_F19B _LDAT10.MergedBits.grpF19B #define LDAT10_F18B0_MASK 1 #define LDAT10_F18B1_MASK 2 #define LDAT10_F18B2_MASK 4 #define LDAT10_F18B3_MASK 8 #define LDAT10_F19B0_MASK 16 #define LDAT10_F19B1_MASK 32 #define LDAT10_F19B2_MASK 64 #define LDAT10_F19B3_MASK 128 #define LDAT10_F18B_MASK 15 #define LDAT10_F18B_BITNUM 0 #define LDAT10_F19B_MASK 240 #define LDAT10_F19B_BITNUM 4 /*** LDAT11 - LCD Data Register; 0x0000005C ***/ typedef union { byte Byte; struct { byte F20B0 :1; /* LCD Segment 20 Data Bit 0 */ byte F20B1 :1; /* LCD Segment 20 Data Bit 1 */ byte F20B2 :1; /* LCD Segment 20 Data Bit 2 */ byte F20B3 :1; /* LCD Segment 20 Data Bit 3 */ byte F21B0 :1; /* LCD Segment 21 Data Bit 0 */ byte F21B1 :1; /* LCD Segment 21 Data Bit 1 */ byte F21B2 :1; /* LCD Segment 21 Data Bit 2 */ byte F21B3 :1; /* LCD Segment 21 Data Bit 3 */ } Bits; struct { byte grpF20B :4; byte grpF21B :4; } MergedBits; } LDAT11STR; extern volatile LDAT11STR _LDAT11 @0x0000005C; #define LDAT11 _LDAT11.Byte #define LDAT11_F20B0 _LDAT11.Bits.F20B0 #define LDAT11_F20B1 _LDAT11.Bits.F20B1 #define LDAT11_F20B2 _LDAT11.Bits.F20B2 #define LDAT11_F20B3 _LDAT11.Bits.F20B3 #define LDAT11_F21B0 _LDAT11.Bits.F21B0 #define LDAT11_F21B1 _LDAT11.Bits.F21B1 #define LDAT11_F21B2 _LDAT11.Bits.F21B2 #define LDAT11_F21B3 _LDAT11.Bits.F21B3 #define LDAT11_F20B _LDAT11.MergedBits.grpF20B #define LDAT11_F21B _LDAT11.MergedBits.grpF21B #define LDAT11_F20B0_MASK 1 #define LDAT11_F20B1_MASK 2 #define LDAT11_F20B2_MASK 4 #define LDAT11_F20B3_MASK 8 #define LDAT11_F21B0_MASK 16 #define LDAT11_F21B1_MASK 32 #define LDAT11_F21B2_MASK 64 #define LDAT11_F21B3_MASK 128 #define LDAT11_F20B_MASK 15 #define LDAT11_F20B_BITNUM 0 #define LDAT11_F21B_MASK 240 #define LDAT11_F21B_BITNUM 4 /*** LDAT12 - LCD Data Register; 0x0000005D ***/ typedef union { byte Byte; struct { byte F22B0 :1; /* LCD Segment 22 Data Bit 0 */ byte F22B1 :1; /* LCD Segment 22 Data Bit 1 */ byte F22B2 :1; /* LCD Segment 22 Data Bit 2 */ byte F22B3 :1; /* LCD Segment 22 Data Bit 3 */ byte F23B0 :1; /* LCD Segment 23 Data Bit 0 */ byte F23B1 :1; /* LCD Segment 23 Data Bit 1 */ byte F23B2 :1; /* LCD Segment 23 Data Bit 2 */ byte F23B3 :1; /* LCD Segment 23 Data Bit 3 */ } Bits; struct { byte grpF22B :4; byte grpF23B :4; } MergedBits; } LDAT12STR; extern volatile LDAT12STR _LDAT12 @0x0000005D; #define LDAT12 _LDAT12.Byte #define LDAT12_F22B0 _LDAT12.Bits.F22B0 #define LDAT12_F22B1 _LDAT12.Bits.F22B1 #define LDAT12_F22B2 _LDAT12.Bits.F22B2 #define LDAT12_F22B3 _LDAT12.Bits.F22B3 #define LDAT12_F23B0 _LDAT12.Bits.F23B0 #define LDAT12_F23B1 _LDAT12.Bits.F23B1 #define LDAT12_F23B2 _LDAT12.Bits.F23B2 #define LDAT12_F23B3 _LDAT12.Bits.F23B3 #define LDAT12_F22B _LDAT12.MergedBits.grpF22B #define LDAT12_F23B _LDAT12.MergedBits.grpF23B #define LDAT12_F22B0_MASK 1 #define LDAT12_F22B1_MASK 2 #define LDAT12_F22B2_MASK 4 #define LDAT12_F22B3_MASK 8 #define LDAT12_F23B0_MASK 16 #define LDAT12_F23B1_MASK 32 #define LDAT12_F23B2_MASK 64 #define LDAT12_F23B3_MASK 128 #define LDAT12_F22B_MASK 15 #define LDAT12_F22B_BITNUM 0 #define LDAT12_F23B_MASK 240 #define LDAT12_F23B_BITNUM 4 /*** LDAT13 - LCD Data Register; 0x0000005E ***/ typedef union { byte Byte; struct { byte F24B0 :1; /* LCD Segment 24 Data Bit 0 */ byte F24B1 :1; /* LCD Segment 24 Data Bit 1 */ byte F24B2 :1; /* LCD Segment 24 Data Bit 2 */ byte F24B3 :1; /* LCD Segment 24 Data Bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpF24B :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LDAT13STR; extern volatile LDAT13STR _LDAT13 @0x0000005E; #define LDAT13 _LDAT13.Byte #define LDAT13_F24B0 _LDAT13.Bits.F24B0 #define LDAT13_F24B1 _LDAT13.Bits.F24B1 #define LDAT13_F24B2 _LDAT13.Bits.F24B2 #define LDAT13_F24B3 _LDAT13.Bits.F24B3 #define LDAT13_F24B _LDAT13.MergedBits.grpF24B #define LDAT13_F24B0_MASK 1 #define LDAT13_F24B1_MASK 2 #define LDAT13_F24B2_MASK 4 #define LDAT13_F24B3_MASK 8 #define LDAT13_F24B_MASK 15 #define LDAT13_F24B_BITNUM 0 /*** SBSR - SIM Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte SBSW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SBSRSTR; extern volatile SBSRSTR _SBSR @0x0000FE00; #define SBSR _SBSR.Byte #define SBSR_SBSW _SBSR.Bits.SBSW #define SBSR_SBSW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte :1; byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_LVI _SRSR.Bits.LVI #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_PIN _SRSR.Bits.PIN #define SRSR_POR _SRSR.Bits.POR #define SRSR_LVI_MASK 2 #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_PIN_MASK 64 #define SRSR_POR_MASK 128 /*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } SBFCRSTR; extern volatile SBFCRSTR _SBFCR @0x0000FE03; #define SBFCR _SBFCR.Byte #define SBFCR_BCFE _SBFCR.Bits.BCFE #define SBFCR_BCFE_MASK 128 /*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte IF1 :1; /* Interrupt Flag 1 */ byte IF2 :1; /* Interrupt Flag 2 */ byte IF3 :1; /* Interrupt Flag 3 */ byte IF4 :1; /* Interrupt Flag 4 */ byte IF5 :1; /* Interrupt Flag 5 */ byte IF6 :1; /* Interrupt Flag 6 */ } Bits; struct { byte :1; byte :1; byte grpIF_1 :6; } MergedBits; } INT1STR; extern volatile INT1STR _INT1 @0x0000FE04; #define INT1 _INT1.Byte #define INT1_IF1 _INT1.Bits.IF1 #define INT1_IF2 _INT1.Bits.IF2 #define INT1_IF3 _INT1.Bits.IF3 #define INT1_IF4 _INT1.Bits.IF4 #define INT1_IF5 _INT1.Bits.IF5 #define INT1_IF6 _INT1.Bits.IF6 #define INT1_IF_1 _INT1.MergedBits.grpIF_1 #define INT1_IF INT1_IF_1 #define INT1_IF1_MASK 4 #define INT1_IF2_MASK 8 #define INT1_IF3_MASK 16 #define INT1_IF4_MASK 32 #define INT1_IF5_MASK 64 #define INT1_IF6_MASK 128 #define INT1_IF_1_MASK 252 #define INT1_IF_1_BITNUM 2 /*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/ typedef union { byte Byte; struct { byte IF7 :1; /* Interrupt Flag 7 */ byte IF8 :1; /* Interrupt Flag 8 */ byte IF9 :1; /* Interrupt Flag 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpIF_7 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } INT2STR; extern volatile INT2STR _INT2 @0x0000FE05; #define INT2 _INT2.Byte #define INT2_IF7 _INT2.Bits.IF7 #define INT2_IF8 _INT2.Bits.IF8 #define INT2_IF9 _INT2.Bits.IF9 #define INT2_IF_7 _INT2.MergedBits.grpIF_7 #define INT2_IF INT2_IF_7 #define INT2_IF7_MASK 1 #define INT2_IF8_MASK 2 #define INT2_IF9_MASK 4 #define INT2_IF_7_MASK 7 #define INT2_IF_7_BITNUM 0 /*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/ typedef union { byte Byte; struct { byte :1; byte IF16 :1; /* Interrupt Flag 16 */ byte IF17 :1; /* Interrupt Flag 17 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte :1; byte grpIF_16 :2; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } INT3STR; extern volatile INT3STR _INT3 @0x0000FE06; #define INT3 _INT3.Byte #define INT3_IF16 _INT3.Bits.IF16 #define INT3_IF17 _INT3.Bits.IF17 #define INT3_IF_16 _INT3.MergedBits.grpIF_16 #define INT3_IF INT3_IF_16 #define INT3_IF16_MASK 2 #define INT3_IF17_MASK 4 #define INT3_IF_16_MASK 6 #define INT3_IF_16_BITNUM 1 /*** FLCR - FLASH Control Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000FE08; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_ERASE _FLCR.Bits.ERASE #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_ERASE_MASK 2 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** BRK - Break Address Register; 0x0000FE0C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register; 0x0000FE0C ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Register Bit */ byte BIT9 :1; /* Break Address Register Bit */ byte BIT10 :1; /* Break Address Register Bit */ byte BIT11 :1; /* Break Address Register Bit */ byte BIT12 :1; /* Break Address Register Bit */ byte BIT13 :1; /* Break Address Register Bit */ byte BIT14 :1; /* Break Address Register Bit */ byte BIT15 :1; /* Break Address Register Bit */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register; 0x0000FE0D ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Register Bit */ byte BIT1 :1; /* Break Address Register Bit */ byte BIT2 :1; /* Break Address Register Bit */ byte BIT3 :1; /* Break Address Register Bit */ byte BIT4 :1; /* Break Address Register Bit */ byte BIT5 :1; /* Break Address Register Bit */ byte BIT6 :1; /* Break Address Register Bit */ byte BIT7 :1; /* Break Address Register Bit */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE0C; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0E; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** LVISR - LVI Status Register; 0x0000FE0F ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte LVIIAK :1; /* LVI Interrupt Acknowledge */ byte LVIIF :1; /* LVI Interrupt Flag */ byte LVIIE :1; /* LVI Interrupt Enable Bit */ byte LVIOUT :1; /* LVI Output Bit */ } Bits; } LVISRSTR; extern volatile LVISRSTR _LVISR @0x0000FE0F; #define LVISR _LVISR.Byte #define LVISR_LVIIAK _LVISR.Bits.LVIIAK #define LVISR_LVIIF _LVISR.Bits.LVIIF #define LVISR_LVIIE _LVISR.Bits.LVIIE #define LVISR_LVIOUT _LVISR.Bits.LVIOUT #define LVISR_LVIIAK_MASK 16 #define LVISR_LVIIF_MASK 32 #define LVISR_LVIIE_MASK 64 #define LVISR_LVIOUT_MASK 128 /*** FLBPR - FLASH1 Block Protect Register; 0x0000FF7E ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* Block Protect Register Bit 0 */ byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte BPR4 :1; /* Block Protect Register Bit 4 */ byte BPR5 :1; /* Block Protect Register Bit 5 */ byte BPR6 :1; /* Block Protect Register Bit 6 */ byte BPR7 :1; /* Block Protect Register Bit 7 */ } Bits; } FLBPRSTR; /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FF7E = ; */ #define _FLBPR (*(const FLBPRSTR * __far)0x0000FF7E) #define FLBPR _FLBPR.Byte #define FLBPR_BPR0 _FLBPR.Bits.BPR0 #define FLBPR_BPR1 _FLBPR.Bits.BPR1 #define FLBPR_BPR2 _FLBPR.Bits.BPR2 #define FLBPR_BPR3 _FLBPR.Bits.BPR3 #define FLBPR_BPR4 _FLBPR.Bits.BPR4 #define FLBPR_BPR5 _FLBPR.Bits.BPR5 #define FLBPR_BPR6 _FLBPR.Bits.BPR6 #define FLBPR_BPR7 _FLBPR.Bits.BPR7 #define FLBPR_BPR0_MASK 1 #define FLBPR_BPR1_MASK 2 #define FLBPR_BPR2_MASK 4 #define FLBPR_BPR3_MASK 8 #define FLBPR_BPR4_MASK 16 #define FLBPR_BPR5_MASK 32 #define FLBPR_BPR6_MASK 64 #define FLBPR_BPR7_MASK 128 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 12:42:42 */ #define T1CH_ARR This_symb_has_been_depreciated #define T2CH_ARR This_symb_has_been_depreciated #endif