/* Based on CPU DB MC68HC908KX8, version 2.89.059 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908kx8.h ** Processor : MC68HC908KX8CP ** FileFormat: V2.30 ** DataSheet : MC68HC908KX8 Rev. 2.1 07/2005 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:09 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908KX8_H #define _MC68HC908KX8_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_TBM 17 #define VectorNumber_ADC 16 #define VectorNumber_KBI 15 #define VectorNumber_SCITransmit 14 #define VectorNumber_SCIReceive 13 #define VectorNumber_SCIError 12 #define VectorNumber_Int7 11 #define VectorNumber_Int8 10 #define VectorNumber_Int9 9 #define VectorNumber_Int10 8 #define VectorNumber_Int11 7 #define VectorNumber_TIMOvr 6 #define VectorNumber_TIMCH1 5 #define VectorNumber_TIMCH0 4 #define VectorNumber_ICG 3 #define VectorNumber_IRQ1 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_TBM 0x0000FFDC #define INT_ADC 0x0000FFDE #define INT_KBI 0x0000FFE0 #define INT_SCITransmit 0x0000FFE2 #define INT_SCIReceive 0x0000FFE4 #define INT_SCIError 0x0000FFE6 #define Int7 0x0000FFE8 #define Int8 0x0000FFEA #define Int9 0x0000FFEC #define Int10 0x0000FFEE #define Int11 0x0000FFF0 #define INT_TIMOvr 0x0000FFF2 #define INT_TIMCH1 0x0000FFF4 #define INT_TIMCH0 0x0000FFF6 #define INT_ICG 0x0000FFF8 #define INT_IRQ1 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte :1; byte :1; byte :1; } Bits; struct { byte grpPTA :5; byte :1; byte :1; byte :1; } MergedBits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA _PTA.MergedBits.grpPTA #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA_MASK 31 #define PTA_PTA_BITNUM 0 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRA :5; byte :1; byte :1; byte :1; } MergedBits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA _DDRA.MergedBits.grpDDRA #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA_MASK 31 #define DDRA_DDRA_BITNUM 0 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** PTAPUE - Input Pull-Up Enable Register PTAPUE; 0x0000000D ***/ typedef union { byte Byte; struct { byte PTAPUE0 :1; /* Pull-Up Enable bit 0, Port A */ byte PTAPUE1 :1; /* Pull-Up Enable bit 1, Port A */ byte PTAPUE2 :1; /* Pull-Up Enable bit 2, Port A */ byte PTAPUE3 :1; /* Pull-Up Enable bit 3, Port A */ byte PTAPUE4 :1; /* Pull-Up Enable bit 4, Port A */ byte :1; byte :1; byte :1; } Bits; struct { byte grpPTAPUE :5; byte :1; byte :1; byte :1; } MergedBits; } PTAPUESTR; extern volatile PTAPUESTR _PTAPUE @0x0000000D; #define PTAPUE _PTAPUE.Byte #define PTAPUE_PTAPUE0 _PTAPUE.Bits.PTAPUE0 #define PTAPUE_PTAPUE1 _PTAPUE.Bits.PTAPUE1 #define PTAPUE_PTAPUE2 _PTAPUE.Bits.PTAPUE2 #define PTAPUE_PTAPUE3 _PTAPUE.Bits.PTAPUE3 #define PTAPUE_PTAPUE4 _PTAPUE.Bits.PTAPUE4 #define PTAPUE_PTAPUE _PTAPUE.MergedBits.grpPTAPUE #define PTAPUE_PTAPUE0_MASK 1 #define PTAPUE_PTAPUE1_MASK 2 #define PTAPUE_PTAPUE2_MASK 4 #define PTAPUE_PTAPUE3_MASK 8 #define PTAPUE_PTAPUE4_MASK 16 #define PTAPUE_PTAPUE_MASK 31 #define PTAPUE_PTAPUE_BITNUM 0 /*** SCC1 - SCI Control Register 1; 0x00000013 ***/ typedef union { byte Byte; struct { byte PTY :1; /* Parity Bit */ byte PEN :1; /* Parity Enable Bit */ byte ILTY :1; /* Idle Line Type Bit */ byte WAKE :1; /* Wakeup Condition Bit */ byte M :1; /* Mode (Character Length) Bit */ byte TXINV :1; /* Transmit Inversion Bit */ byte ENSCI :1; /* Enable SCI Bit */ byte LOOPS :1; /* Loop Mode Select Bit */ } Bits; } SCC1STR; extern volatile SCC1STR _SCC1 @0x00000013; #define SCC1 _SCC1.Byte #define SCC1_PTY _SCC1.Bits.PTY #define SCC1_PEN _SCC1.Bits.PEN #define SCC1_ILTY _SCC1.Bits.ILTY #define SCC1_WAKE _SCC1.Bits.WAKE #define SCC1_M _SCC1.Bits.M #define SCC1_TXINV _SCC1.Bits.TXINV #define SCC1_ENSCI _SCC1.Bits.ENSCI #define SCC1_LOOPS _SCC1.Bits.LOOPS #define SCC1_PTY_MASK 1 #define SCC1_PEN_MASK 2 #define SCC1_ILTY_MASK 4 #define SCC1_WAKE_MASK 8 #define SCC1_M_MASK 16 #define SCC1_TXINV_MASK 32 #define SCC1_ENSCI_MASK 64 #define SCC1_LOOPS_MASK 128 /*** SCC2 - SCI Control Register 2; 0x00000014 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break Bit */ byte RWU :1; /* Receiver Wakeup Bit */ byte RE :1; /* Receiver Enable Bit */ byte TE :1; /* Transmitter Enable Bit */ byte ILIE :1; /* Idle Line Interrupt Enable Bit */ byte SCRIE :1; /* SCI Receive Interrupt Enable Bit */ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ byte SCTIE :1; /* SCI Transmit Interrupt Enable Bit */ } Bits; } SCC2STR; extern volatile SCC2STR _SCC2 @0x00000014; #define SCC2 _SCC2.Byte #define SCC2_SBK _SCC2.Bits.SBK #define SCC2_RWU _SCC2.Bits.RWU #define SCC2_RE _SCC2.Bits.RE #define SCC2_TE _SCC2.Bits.TE #define SCC2_ILIE _SCC2.Bits.ILIE #define SCC2_SCRIE _SCC2.Bits.SCRIE #define SCC2_TCIE _SCC2.Bits.TCIE #define SCC2_SCTIE _SCC2.Bits.SCTIE #define SCC2_SBK_MASK 1 #define SCC2_RWU_MASK 2 #define SCC2_RE_MASK 4 #define SCC2_TE_MASK 8 #define SCC2_ILIE_MASK 16 #define SCC2_SCRIE_MASK 32 #define SCC2_TCIE_MASK 64 #define SCC2_SCTIE_MASK 128 /*** SCC3 - SCI Control Register 3; 0x00000015 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Receiver Parity Error Interrupt Enable Bit */ byte FEIE :1; /* Receiver Framing Error Interrupt Enable Bit */ byte NEIE :1; /* Receiver Noise Error Interrupt Enable Bit */ byte ORIE :1; /* Receiver Overrun Interrupt Enable Bit */ byte :1; byte :1; byte T8 :1; /* Transmitted Bit 8 */ byte R8 :1; /* Received Bit 8 */ } Bits; } SCC3STR; extern volatile SCC3STR _SCC3 @0x00000015; #define SCC3 _SCC3.Byte #define SCC3_PEIE _SCC3.Bits.PEIE #define SCC3_FEIE _SCC3.Bits.FEIE #define SCC3_NEIE _SCC3.Bits.NEIE #define SCC3_ORIE _SCC3.Bits.ORIE #define SCC3_T8 _SCC3.Bits.T8 #define SCC3_R8 _SCC3.Bits.R8 #define SCC3_PEIE_MASK 1 #define SCC3_FEIE_MASK 2 #define SCC3_NEIE_MASK 4 #define SCC3_ORIE_MASK 8 #define SCC3_T8_MASK 64 #define SCC3_R8_MASK 128 /*** SCS1 - SCI Status Register 1; 0x00000016 ***/ typedef union { byte Byte; struct { byte PE :1; /* Receiver Parity Error Bit */ byte FE :1; /* Receiver Framing Error Bit */ byte NF :1; /* Receiver Noise Flag Bit */ byte OR :1; /* Receiver Overrun Bit */ byte IDLE :1; /* Receiver Idle Bit */ byte SCRF :1; /* SCI Receiver Full Bit */ byte TC :1; /* Transmission Complete Bit */ byte SCTE :1; /* SCI Transmitter Empty Bit */ } Bits; } SCS1STR; extern volatile SCS1STR _SCS1 @0x00000016; #define SCS1 _SCS1.Byte #define SCS1_PE _SCS1.Bits.PE #define SCS1_FE _SCS1.Bits.FE #define SCS1_NF _SCS1.Bits.NF #define SCS1_OR _SCS1.Bits.OR #define SCS1_IDLE _SCS1.Bits.IDLE #define SCS1_SCRF _SCS1.Bits.SCRF #define SCS1_TC _SCS1.Bits.TC #define SCS1_SCTE _SCS1.Bits.SCTE #define SCS1_PE_MASK 1 #define SCS1_FE_MASK 2 #define SCS1_NF_MASK 4 #define SCS1_OR_MASK 8 #define SCS1_IDLE_MASK 16 #define SCS1_SCRF_MASK 32 #define SCS1_TC_MASK 64 #define SCS1_SCTE_MASK 128 /*** SCS2 - SCI Status Register 2; 0x00000017 ***/ typedef union { byte Byte; struct { byte RPF :1; /* Reception in Progress Flag Bit */ byte BKF :1; /* Break Flag Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SCS2STR; extern volatile SCS2STR _SCS2 @0x00000017; #define SCS2 _SCS2.Byte #define SCS2_RPF _SCS2.Bits.RPF #define SCS2_BKF _SCS2.Bits.BKF #define SCS2_RPF_MASK 1 #define SCS2_BKF_MASK 2 /*** SCDR - SCI Data Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCDRSTR; extern volatile SCDRSTR _SCDR @0x00000018; #define SCDR _SCDR.Byte #define SCDR_R0_T0 _SCDR.Bits.R0_T0 #define SCDR_R1_T1 _SCDR.Bits.R1_T1 #define SCDR_R2_T2 _SCDR.Bits.R2_T2 #define SCDR_R3_T3 _SCDR.Bits.R3_T3 #define SCDR_R4_T4 _SCDR.Bits.R4_T4 #define SCDR_R5_T5 _SCDR.Bits.R5_T5 #define SCDR_R6_T6 _SCDR.Bits.R6_T6 #define SCDR_R7_T7 _SCDR.Bits.R7_T7 #define SCDR_R0_T0_MASK 1 #define SCDR_R1_T1_MASK 2 #define SCDR_R2_T2_MASK 4 #define SCDR_R3_T3_MASK 8 #define SCDR_R4_T4_MASK 16 #define SCDR_R5_T5_MASK 32 #define SCDR_R6_T6_MASK 64 #define SCDR_R7_T7_MASK 128 /*** SCBR - SCI Baud Rate Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte SCR0 :1; /* SCI Baud Rate Select Bit 0 */ byte SCR1 :1; /* SCI Baud Rate Select Bit 1 */ byte SCR2 :1; /* SCI Baud Rate Select Bit 2 */ byte :1; byte SCP0 :1; /* SCI Baud Rate Prescaler Bit 0 */ byte SCP1 :1; /* SCI Baud Rate Prescaler Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpSCR :3; byte :1; byte grpSCP :2; byte :1; byte :1; } MergedBits; } SCBRSTR; extern volatile SCBRSTR _SCBR @0x00000019; #define SCBR _SCBR.Byte #define SCBR_SCR0 _SCBR.Bits.SCR0 #define SCBR_SCR1 _SCBR.Bits.SCR1 #define SCBR_SCR2 _SCBR.Bits.SCR2 #define SCBR_SCP0 _SCBR.Bits.SCP0 #define SCBR_SCP1 _SCBR.Bits.SCP1 #define SCBR_SCR _SCBR.MergedBits.grpSCR #define SCBR_SCP _SCBR.MergedBits.grpSCP #define SCBR_SCR0_MASK 1 #define SCBR_SCR1_MASK 2 #define SCBR_SCR2_MASK 4 #define SCBR_SCP0_MASK 16 #define SCBR_SCP1_MASK 32 #define SCBR_SCR_MASK 7 #define SCBR_SCR_BITNUM 0 #define SCBR_SCP_MASK 48 #define SCBR_SCP_BITNUM 4 /*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */ byte IMASKK :1; /* Keyboard Interrupt Mask Bit */ byte ACKK :1; /* Keyboard Acknowledge Bit */ byte KEYF :1; /* Keyboard Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBSCRSTR; extern volatile KBSCRSTR _KBSCR @0x0000001A; #define KBSCR _KBSCR.Byte #define KBSCR_MODEK _KBSCR.Bits.MODEK #define KBSCR_IMASKK _KBSCR.Bits.IMASKK #define KBSCR_ACKK _KBSCR.Bits.ACKK #define KBSCR_KEYF _KBSCR.Bits.KEYF #define KBSCR_MODEK_MASK 1 #define KBSCR_IMASKK_MASK 2 #define KBSCR_ACKK_MASK 4 #define KBSCR_KEYF_MASK 8 /*** KBIER - Keyboard Interrrupt Enable Register KBIER; 0x0000001B ***/ typedef union { byte Byte; struct { byte KBIE0 :1; /* Keyboard Interrupt Enable Bit 0 */ byte KBIE1 :1; /* Keyboard Interrupt Enable Bit 1 */ byte KBIE2 :1; /* Keyboard Interrupt Enable Bit 2 */ byte KBIE3 :1; /* Keyboard Interrupt Enable Bit 3 */ byte KBIE4 :1; /* Keyboard Interrupt Enable Bit 4 */ byte :1; byte :1; byte :1; } Bits; struct { byte grpKBIE :5; byte :1; byte :1; byte :1; } MergedBits; } KBIERSTR; extern volatile KBIERSTR _KBIER @0x0000001B; #define KBIER _KBIER.Byte #define KBIER_KBIE0 _KBIER.Bits.KBIE0 #define KBIER_KBIE1 _KBIER.Bits.KBIE1 #define KBIER_KBIE2 _KBIER.Bits.KBIE2 #define KBIER_KBIE3 _KBIER.Bits.KBIE3 #define KBIER_KBIE4 _KBIER.Bits.KBIE4 #define KBIER_KBIE _KBIER.MergedBits.grpKBIE #define KBIER_KBIE0_MASK 1 #define KBIER_KBIE1_MASK 2 #define KBIER_KBIE2_MASK 4 #define KBIER_KBIE3_MASK 8 #define KBIER_KBIE4_MASK 16 #define KBIER_KBIE_MASK 31 #define KBIER_KBIE_BITNUM 0 /*** TBCR - Timebase Control Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte :1; byte TBON :1; /* Timebase Enabled Bit */ byte TBIE :1; /* Timebase Interrupt Enable Bit */ byte TACK :1; /* Timebase ACKnowledge Bit */ byte TBR0 :1; /* Timebase Divider Selection Bit 0 */ byte TBR1 :1; /* Timebase Divider Selection Bit 1 */ byte TBR2 :1; /* Timebase Divider Selection Bit 2 */ byte TBIF :1; /* Timebase Interrupt Flag */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpTBR :3; byte :1; } MergedBits; } TBCRSTR; extern volatile TBCRSTR _TBCR @0x0000001C; #define TBCR _TBCR.Byte #define TBCR_TBON _TBCR.Bits.TBON #define TBCR_TBIE _TBCR.Bits.TBIE #define TBCR_TACK _TBCR.Bits.TACK #define TBCR_TBR0 _TBCR.Bits.TBR0 #define TBCR_TBR1 _TBCR.Bits.TBR1 #define TBCR_TBR2 _TBCR.Bits.TBR2 #define TBCR_TBIF _TBCR.Bits.TBIF #define TBCR_TBR _TBCR.MergedBits.grpTBR #define TBCR_TBON_MASK 2 #define TBCR_TBIE_MASK 4 #define TBCR_TACK_MASK 8 #define TBCR_TBR0_MASK 16 #define TBCR_TBR1_MASK 32 #define TBCR_TBR2_MASK 64 #define TBCR_TBIF_MASK 128 #define TBCR_TBR_MASK 112 #define TBCR_TBR_BITNUM 4 /*** ISCR - IRQ Status and Control Register; 0x0000001D ***/ typedef union { byte Byte; struct { byte MODE1 :1; /* IRQ Edge/Level Select Bit */ byte IMASK1 :1; /* IRQ1 Interrupt Mask Bit */ byte ACK1 :1; /* IRQ1 Interrupt Request Acknowledge Bit */ byte IRQF1 :1; /* IRQ1 Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } ISCRSTR; extern volatile ISCRSTR _ISCR @0x0000001D; #define ISCR _ISCR.Byte #define ISCR_MODE1 _ISCR.Bits.MODE1 #define ISCR_IMASK1 _ISCR.Bits.IMASK1 #define ISCR_ACK1 _ISCR.Bits.ACK1 #define ISCR_IRQF1 _ISCR.Bits.IRQF1 #define ISCR_MODE1_MASK 1 #define ISCR_IMASK1_MASK 2 #define ISCR_ACK1_MASK 4 #define ISCR_IRQF1_MASK 8 /*** CONFIG2 - Configuration Register 2; 0x0000001E ***/ typedef union { byte Byte; struct { byte SCIBDSRC :1; /* SCI Baud Rate Clock Source Bit */ byte OSCENINSTOP :1; /* Oscilator Enable In Stop Mode Bit */ byte :1; byte EXTCLKEN :1; /* External Clock Enable Bit */ byte EXTSLOW :1; /* Slow External Crystal Enable Bit */ byte EXTXTALEN :1; /* External Crystal Enable Bit */ byte :1; byte :1; } Bits; } CONFIG2STR; extern volatile CONFIG2STR _CONFIG2 @0x0000001E; #define CONFIG2 _CONFIG2.Byte #define CONFIG2_SCIBDSRC _CONFIG2.Bits.SCIBDSRC #define CONFIG2_OSCENINSTOP _CONFIG2.Bits.OSCENINSTOP #define CONFIG2_EXTCLKEN _CONFIG2.Bits.EXTCLKEN #define CONFIG2_EXTSLOW _CONFIG2.Bits.EXTSLOW #define CONFIG2_EXTXTALEN _CONFIG2.Bits.EXTXTALEN #define CONFIG2_SCIBDSRC_MASK 1 #define CONFIG2_OSCENINSTOP_MASK 2 #define CONFIG2_EXTCLKEN_MASK 8 #define CONFIG2_EXTSLOW_MASK 16 #define CONFIG2_EXTXTALEN_MASK 32 /*** CONFIG1 - Configuration Register 1; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte SSREC :1; /* Short Stop Recovery Bit */ byte LVI5OR3 :1; /* LVI 5-V or 3-V Operating Mode Bit */ byte LVIPWRD :1; /* Low Voltage Inhibit Power Disable Bit */ byte LVIRSTD :1; /* Low Voltage Inhibit Reset Disable Bit */ byte LVISTOP :1; /* LVI Enable in Stop Mode Bit */ byte COPRS :1; /* COP Reset Period Selection Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVI5OR3 _CONFIG1.Bits.LVI5OR3 #define CONFIG1_LVIPWRD _CONFIG1.Bits.LVIPWRD #define CONFIG1_LVIRSTD _CONFIG1.Bits.LVIRSTD #define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP #define CONFIG1_COPRS _CONFIG1.Bits.COPRS #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_SSREC_MASK 4 #define CONFIG1_LVI5OR3_MASK 8 #define CONFIG1_LVIPWRD_MASK 16 #define CONFIG1_LVIRSTD_MASK 32 #define CONFIG1_LVISTOP_MASK 64 #define CONFIG1_COPRS_MASK 128 /*** TSC - TIM Status and Control Register TSC; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM Reset Bit */ byte TSTOP :1; /* TIM Stop Bit */ byte TOIE :1; /* TIM Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TSCSTR; extern volatile TSCSTR _TSC @0x00000020; #define TSC _TSC.Byte #define TSC_PS0 _TSC.Bits.PS0 #define TSC_PS1 _TSC.Bits.PS1 #define TSC_PS2 _TSC.Bits.PS2 #define TSC_TRST _TSC.Bits.TRST #define TSC_TSTOP _TSC.Bits.TSTOP #define TSC_TOIE _TSC.Bits.TOIE #define TSC_TOF _TSC.Bits.TOF #define TSC_PS _TSC.MergedBits.grpPS #define TSC_PS0_MASK 1 #define TSC_PS1_MASK 2 #define TSC_PS2_MASK 4 #define TSC_TRST_MASK 16 #define TSC_TSTOP_MASK 32 #define TSC_TOIE_MASK 64 #define TSC_TOF_MASK 128 #define TSC_PS_MASK 7 #define TSC_PS_BITNUM 0 /*** TCNT - TIM Counter Register; 0x00000021 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCNTH - TIM Counter Register High; 0x00000021 ***/ union { byte Byte; } TCNTHSTR; #define TCNTH _TCNT.Overlap_STR.TCNTHSTR.Byte /*** TCNTL - TIM Counter Register Low; 0x00000022 ***/ union { byte Byte; } TCNTLSTR; #define TCNTL _TCNT.Overlap_STR.TCNTLSTR.Byte } Overlap_STR; } TCNTSTR; extern volatile TCNTSTR _TCNT @0x00000021; #define TCNT _TCNT.Word /*** TMOD - TIM Counter Modulo Register; 0x00000023 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TMODH - TIM Counter Modulo Register High; 0x00000023 ***/ union { byte Byte; } TMODHSTR; #define TMODH _TMOD.Overlap_STR.TMODHSTR.Byte /*** TMODL - TIM Counter Modulo Register Low; 0x00000024 ***/ union { byte Byte; } TMODLSTR; #define TMODL _TMOD.Overlap_STR.TMODLSTR.Byte } Overlap_STR; } TMODSTR; extern volatile TMODSTR _TMOD @0x00000023; #define TMOD _TMOD.Word /*** TSC0 - TIM Channel 0 Status and Control Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TSC0STR; extern volatile TSC0STR _TSC0 @0x00000025; #define TSC0 _TSC0.Byte #define TSC0_CH0MAX _TSC0.Bits.CH0MAX #define TSC0_TOV0 _TSC0.Bits.TOV0 #define TSC0_ELS0A _TSC0.Bits.ELS0A #define TSC0_ELS0B _TSC0.Bits.ELS0B #define TSC0_MS0A _TSC0.Bits.MS0A #define TSC0_MS0B _TSC0.Bits.MS0B #define TSC0_CH0IE _TSC0.Bits.CH0IE #define TSC0_CH0F _TSC0.Bits.CH0F #define TSC0_ELS0x _TSC0.MergedBits.grpELS0x #define TSC0_MS0x _TSC0.MergedBits.grpMS0x #define TSC0_CH0MAX_MASK 1 #define TSC0_TOV0_MASK 2 #define TSC0_ELS0A_MASK 4 #define TSC0_ELS0B_MASK 8 #define TSC0_MS0A_MASK 16 #define TSC0_MS0B_MASK 32 #define TSC0_CH0IE_MASK 64 #define TSC0_CH0F_MASK 128 #define TSC0_ELS0x_MASK 12 #define TSC0_ELS0x_BITNUM 2 #define TSC0_MS0x_MASK 48 #define TSC0_MS0x_BITNUM 4 /*** TCH0 - TIM Channel 0 Register; 0x00000026 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCH0H - TIM Channel 0 Register High; 0x00000026 ***/ union { byte Byte; } TCH0HSTR; #define TCH0H _TCH0.Overlap_STR.TCH0HSTR.Byte /*** TCH0L - TIM Channel 0 Register Low; 0x00000027 ***/ union { byte Byte; } TCH0LSTR; #define TCH0L _TCH0.Overlap_STR.TCH0LSTR.Byte } Overlap_STR; } TCH0STR; extern volatile TCH0STR _TCH0 @0x00000026; #define TCH0 _TCH0.Word /*** TSC1 - TIM Channel 1 Status and Control Register; 0x00000028 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } TSC1STR; extern volatile TSC1STR _TSC1 @0x00000028; #define TSC1 _TSC1.Byte #define TSC1_CH1MAX _TSC1.Bits.CH1MAX #define TSC1_TOV1 _TSC1.Bits.TOV1 #define TSC1_ELS1A _TSC1.Bits.ELS1A #define TSC1_ELS1B _TSC1.Bits.ELS1B #define TSC1_MS1A _TSC1.Bits.MS1A #define TSC1_CH1IE _TSC1.Bits.CH1IE #define TSC1_CH1F _TSC1.Bits.CH1F #define TSC1_ELS1x _TSC1.MergedBits.grpELS1x #define TSC1_CH1MAX_MASK 1 #define TSC1_TOV1_MASK 2 #define TSC1_ELS1A_MASK 4 #define TSC1_ELS1B_MASK 8 #define TSC1_MS1A_MASK 16 #define TSC1_CH1IE_MASK 64 #define TSC1_CH1F_MASK 128 #define TSC1_ELS1x_MASK 12 #define TSC1_ELS1x_BITNUM 2 /*** TCH1 - TIM Channel 1 Register; 0x00000029 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCH1H - TIM Channel 1 Register High; 0x00000029 ***/ union { byte Byte; } TCH1HSTR; #define TCH1H _TCH1.Overlap_STR.TCH1HSTR.Byte /*** TCH1L - TIM Channel 1 Register Low; 0x0000002A ***/ union { byte Byte; } TCH1LSTR; #define TCH1L _TCH1.Overlap_STR.TCH1LSTR.Byte } Overlap_STR; } TCH1STR; extern volatile TCH1STR _TCH1 @0x00000029; #define TCH1 _TCH1.Word /*** ICGCR - ICG Control Register; 0x00000036 ***/ typedef union { byte Byte; struct { byte ECGS :1; /* Extrernal Clock Generator Stable Bit */ byte ECGON :1; /* External Clock Generator On Bit */ byte ICGS :1; /* Internal Clock Generator Stable Bit */ byte ICGON :1; /* Internal Clock Generator On Bit */ byte CS :1; /* Clock Select Bit */ byte CMON :1; /* Clock Monitor On Bit */ byte CMF :1; /* Clock Monitor Interrupt Flag */ byte CMIE :1; /* Clock Monitor Interrupt Enable Bit */ } Bits; } ICGCRSTR; extern volatile ICGCRSTR _ICGCR @0x00000036; #define ICGCR _ICGCR.Byte #define ICGCR_ECGS _ICGCR.Bits.ECGS #define ICGCR_ECGON _ICGCR.Bits.ECGON #define ICGCR_ICGS _ICGCR.Bits.ICGS #define ICGCR_ICGON _ICGCR.Bits.ICGON #define ICGCR_CS _ICGCR.Bits.CS #define ICGCR_CMON _ICGCR.Bits.CMON #define ICGCR_CMF _ICGCR.Bits.CMF #define ICGCR_CMIE _ICGCR.Bits.CMIE #define ICGCR_ECGS_MASK 1 #define ICGCR_ECGON_MASK 2 #define ICGCR_ICGS_MASK 4 #define ICGCR_ICGON_MASK 8 #define ICGCR_CS_MASK 16 #define ICGCR_CMON_MASK 32 #define ICGCR_CMF_MASK 64 #define ICGCR_CMIE_MASK 128 /*** ICGMR - ICG Multiplier Register ; 0x00000037 ***/ typedef union { byte Byte; struct { byte N0 :1; /* ICG Multiplier Factor Bit 0 */ byte N1 :1; /* ICG Multiplier Factor Bit 1 */ byte N2 :1; /* ICG Multiplier Factor Bit 2 */ byte N3 :1; /* ICG Multiplier Factor Bit 3 */ byte N4 :1; /* ICG Multiplier Factor Bit 4 */ byte N5 :1; /* ICG Multiplier Factor Bit 5 */ byte N6 :1; /* ICG Multiplier Factor Bit 6 */ byte :1; } Bits; struct { byte grpN :7; byte :1; } MergedBits; } ICGMRSTR; extern volatile ICGMRSTR _ICGMR @0x00000037; #define ICGMR _ICGMR.Byte #define ICGMR_N0 _ICGMR.Bits.N0 #define ICGMR_N1 _ICGMR.Bits.N1 #define ICGMR_N2 _ICGMR.Bits.N2 #define ICGMR_N3 _ICGMR.Bits.N3 #define ICGMR_N4 _ICGMR.Bits.N4 #define ICGMR_N5 _ICGMR.Bits.N5 #define ICGMR_N6 _ICGMR.Bits.N6 #define ICGMR_N _ICGMR.MergedBits.grpN #define ICGMR_N0_MASK 1 #define ICGMR_N1_MASK 2 #define ICGMR_N2_MASK 4 #define ICGMR_N3_MASK 8 #define ICGMR_N4_MASK 16 #define ICGMR_N5_MASK 32 #define ICGMR_N6_MASK 64 #define ICGMR_N_MASK 127 #define ICGMR_N_BITNUM 0 /*** ICGTR - ICG Trim Register; 0x00000038 ***/ typedef union { byte Byte; struct { byte TRIM0 :1; /* ICG Trim Factor Bit 0 */ byte TRIM1 :1; /* ICG Trim Factor Bit 1 */ byte TRIM2 :1; /* ICG Trim Factor Bit 2 */ byte TRIM3 :1; /* ICG Trim Factor Bit 3 */ byte TRIM4 :1; /* ICG Trim Factor Bit 4 */ byte TRIM5 :1; /* ICG Trim Factor Bit 5 */ byte TRIM6 :1; /* ICG Trim Factor Bit 6 */ byte TRIM7 :1; /* ICG Trim Factor Bit 7 */ } Bits; } ICGTRSTR; extern volatile ICGTRSTR _ICGTR @0x00000038; #define ICGTR _ICGTR.Byte #define ICGTR_TRIM0 _ICGTR.Bits.TRIM0 #define ICGTR_TRIM1 _ICGTR.Bits.TRIM1 #define ICGTR_TRIM2 _ICGTR.Bits.TRIM2 #define ICGTR_TRIM3 _ICGTR.Bits.TRIM3 #define ICGTR_TRIM4 _ICGTR.Bits.TRIM4 #define ICGTR_TRIM5 _ICGTR.Bits.TRIM5 #define ICGTR_TRIM6 _ICGTR.Bits.TRIM6 #define ICGTR_TRIM7 _ICGTR.Bits.TRIM7 #define ICGTR_TRIM0_MASK 1 #define ICGTR_TRIM1_MASK 2 #define ICGTR_TRIM2_MASK 4 #define ICGTR_TRIM3_MASK 8 #define ICGTR_TRIM4_MASK 16 #define ICGTR_TRIM5_MASK 32 #define ICGTR_TRIM6_MASK 64 #define ICGTR_TRIM7_MASK 128 /*** ICGDVR - ICG Divider Control Register; 0x00000039 ***/ typedef union { byte Byte; struct { byte DDIV0 :1; /* ICG DCO Divider Control Bit 0 */ byte DDIV1 :1; /* ICG DCO Divider Control Bit 1 */ byte DDIV2 :1; /* ICG DCO Divider Control Bit 2 */ byte DDIV3 :1; /* ICG DCO Divider Control Bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDIV :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ICGDVRSTR; extern volatile ICGDVRSTR _ICGDVR @0x00000039; #define ICGDVR _ICGDVR.Byte #define ICGDVR_DDIV0 _ICGDVR.Bits.DDIV0 #define ICGDVR_DDIV1 _ICGDVR.Bits.DDIV1 #define ICGDVR_DDIV2 _ICGDVR.Bits.DDIV2 #define ICGDVR_DDIV3 _ICGDVR.Bits.DDIV3 #define ICGDVR_DDIV _ICGDVR.MergedBits.grpDDIV #define ICGDVR_DDIV0_MASK 1 #define ICGDVR_DDIV1_MASK 2 #define ICGDVR_DDIV2_MASK 4 #define ICGDVR_DDIV3_MASK 8 #define ICGDVR_DDIV_MASK 15 #define ICGDVR_DDIV_BITNUM 0 /*** ICGDSR - ICG DCO State Control Register ; 0x0000003A ***/ typedef union { byte Byte; struct { byte DSTG0 :1; /* ICG DCO Stage Control Bit 0 */ byte DSTG1 :1; /* ICG DCO Stage Control Bit 1 */ byte DSTG2 :1; /* ICG DCO Stage Control Bit 2 */ byte DSTG3 :1; /* ICG DCO Stage Control Bit 3 */ byte DSTG4 :1; /* ICG DCO Stage Control Bit 4 */ byte DSTG5 :1; /* ICG DCO Stage Control Bit 5 */ byte DSTG6 :1; /* ICG DCO Stage Control Bit 6 */ byte DSTG7 :1; /* ICG DCO Stage Control Bit 7 */ } Bits; } ICGDSRSTR; extern volatile ICGDSRSTR _ICGDSR @0x0000003A; #define ICGDSR _ICGDSR.Byte #define ICGDSR_DSTG0 _ICGDSR.Bits.DSTG0 #define ICGDSR_DSTG1 _ICGDSR.Bits.DSTG1 #define ICGDSR_DSTG2 _ICGDSR.Bits.DSTG2 #define ICGDSR_DSTG3 _ICGDSR.Bits.DSTG3 #define ICGDSR_DSTG4 _ICGDSR.Bits.DSTG4 #define ICGDSR_DSTG5 _ICGDSR.Bits.DSTG5 #define ICGDSR_DSTG6 _ICGDSR.Bits.DSTG6 #define ICGDSR_DSTG7 _ICGDSR.Bits.DSTG7 #define ICGDSR_DSTG0_MASK 1 #define ICGDSR_DSTG1_MASK 2 #define ICGDSR_DSTG2_MASK 4 #define ICGDSR_DSTG3_MASK 8 #define ICGDSR_DSTG4_MASK 16 #define ICGDSR_DSTG5_MASK 32 #define ICGDSR_DSTG6_MASK 64 #define ICGDSR_DSTG7_MASK 128 /*** ADSCR - ADC Status and Control Register; 0x0000003C ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x0000003C; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADR - ADC Data Register; 0x0000003D ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADRSTR; extern volatile ADRSTR _ADR @0x0000003D; #define ADR _ADR.Byte #define ADR_AD0 _ADR.Bits.AD0 #define ADR_AD1 _ADR.Bits.AD1 #define ADR_AD2 _ADR.Bits.AD2 #define ADR_AD3 _ADR.Bits.AD3 #define ADR_AD4 _ADR.Bits.AD4 #define ADR_AD5 _ADR.Bits.AD5 #define ADR_AD6 _ADR.Bits.AD6 #define ADR_AD7 _ADR.Bits.AD7 #define ADR_AD0_MASK 1 #define ADR_AD1_MASK 2 #define ADR_AD2_MASK 4 #define ADR_AD3_MASK 8 #define ADR_AD4_MASK 16 #define ADR_AD5_MASK 32 #define ADR_AD6_MASK 64 #define ADR_AD7_MASK 128 /*** ADCLK - ADC Input Clock Register; 0x0000003E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte ADICLK :1; /* ADC Input Clock Select Bit */ byte ADIV0 :1; /* ADC Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC Clock Prescaler Bit 1 */ byte ADIV2 :1; /* ADC Clock Prescaler Bit 2 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte grpADIV :3; } MergedBits; } ADCLKSTR; extern volatile ADCLKSTR _ADCLK @0x0000003E; #define ADCLK _ADCLK.Byte #define ADCLK_ADICLK _ADCLK.Bits.ADICLK #define ADCLK_ADIV0 _ADCLK.Bits.ADIV0 #define ADCLK_ADIV1 _ADCLK.Bits.ADIV1 #define ADCLK_ADIV2 _ADCLK.Bits.ADIV2 #define ADCLK_ADIV _ADCLK.MergedBits.grpADIV #define ADCLK_ADICLK_MASK 16 #define ADCLK_ADIV0_MASK 32 #define ADCLK_ADIV1_MASK 64 #define ADCLK_ADIV2_MASK 128 #define ADCLK_ADIV_MASK 224 #define ADCLK_ADIV_BITNUM 5 /*** SBSR - SIM Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte BW :1; /* Break Wait Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SBSRSTR; extern volatile SBSRSTR _SBSR @0x0000FE00; #define SBSR _SBSR.Byte #define SBSR_BW _SBSR.Bits.BW #define SBSR_BW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte MENRST :1; /* Forced Monitor Mode Entry Reset Bit */ byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte :1; byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_LVI _SRSR.Bits.LVI #define SRSR_MENRST _SRSR.Bits.MENRST #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_POR _SRSR.Bits.POR #define SRSR_LVI_MASK 2 #define SRSR_MENRST_MASK 4 #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_POR_MASK 128 /*** BRKAR - Break Auxiliary Register; 0x0000FE02 ***/ typedef union { byte Byte; struct { byte BDCOP :1; /* Break Disable COP Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } BRKARSTR; extern volatile BRKARSTR _BRKAR @0x0000FE02; #define BRKAR _BRKAR.Byte #define BRKAR_BDCOP _BRKAR.Bits.BDCOP #define BRKAR_BDCOP_MASK 1 /*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } SBFCRSTR; extern volatile SBFCRSTR _SBFCR @0x0000FE03; #define SBFCR _SBFCR.Byte #define SBFCR_BCFE _SBFCR.Bits.BCFE #define SBFCR_BCFE_MASK 128 /*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte IF1 :1; /* Interrupt Flag 1 */ byte IF2 :1; /* Interrrupt Flag 2 */ byte IF3 :1; /* Interrupt Flag 3 */ byte IF4 :1; /* Interrupt Flag 4 */ byte IF5 :1; /* Interrupt Flag 5 */ byte :1; } Bits; struct { byte :1; byte :1; byte grpIF_1 :5; byte :1; } MergedBits; } INT1STR; extern volatile INT1STR _INT1 @0x0000FE04; #define INT1 _INT1.Byte #define INT1_IF1 _INT1.Bits.IF1 #define INT1_IF2 _INT1.Bits.IF2 #define INT1_IF3 _INT1.Bits.IF3 #define INT1_IF4 _INT1.Bits.IF4 #define INT1_IF5 _INT1.Bits.IF5 #define INT1_IF_1 _INT1.MergedBits.grpIF_1 #define INT1_IF INT1_IF_1 #define INT1_IF1_MASK 4 #define INT1_IF2_MASK 8 #define INT1_IF3_MASK 16 #define INT1_IF4_MASK 32 #define INT1_IF5_MASK 64 #define INT1_IF_1_MASK 124 #define INT1_IF_1_BITNUM 2 /*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte IF11 :1; /* Interrupt Flag 11 */ byte IF12 :1; /* Interrupt Flag 12 */ byte IF13 :1; /* Interrupt Flag 13 */ byte IF14 :1; /* Interrupt Flag 14 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpIF_11 :4; } MergedBits; } INT2STR; extern volatile INT2STR _INT2 @0x0000FE05; #define INT2 _INT2.Byte #define INT2_IF11 _INT2.Bits.IF11 #define INT2_IF12 _INT2.Bits.IF12 #define INT2_IF13 _INT2.Bits.IF13 #define INT2_IF14 _INT2.Bits.IF14 #define INT2_IF_11 _INT2.MergedBits.grpIF_11 #define INT2_IF INT2_IF_11 #define INT2_IF11_MASK 16 #define INT2_IF12_MASK 32 #define INT2_IF13_MASK 64 #define INT2_IF14_MASK 128 #define INT2_IF_11_MASK 240 #define INT2_IF_11_BITNUM 4 /*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/ typedef union { byte Byte; struct { byte IF15 :1; /* Interrupt Flag 15 */ byte IF16 :1; /* Interrupt Flag 16 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpIF_15 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } INT3STR; extern volatile INT3STR _INT3 @0x0000FE06; #define INT3 _INT3.Byte #define INT3_IF15 _INT3.Bits.IF15 #define INT3_IF16 _INT3.Bits.IF16 #define INT3_IF_15 _INT3.MergedBits.grpIF_15 #define INT3_IF INT3_IF_15 #define INT3_IF15_MASK 1 #define INT3_IF16_MASK 2 #define INT3_IF_15_MASK 3 #define INT3_IF_15_BITNUM 0 /*** FLCR - FLASH Control Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000FE08; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_ERASE _FLCR.Bits.ERASE #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_ERASE_MASK 2 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** BRK - Break Address Register; 0x0000FE09 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register High; 0x0000FE09 ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Register Bit 8 */ byte BIT9 :1; /* Break Address Register Bit 9 */ byte BIT10 :1; /* Break Address Register Bit 10 */ byte BIT11 :1; /* Break Address Register Bit 11 */ byte BIT12 :1; /* Break Address Register Bit 12 */ byte BIT13 :1; /* Break Address Register Bit 13 */ byte BIT14 :1; /* Break Address Register Bit 14 */ byte BIT15 :1; /* Break Address Register Bit 15 */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register Low; 0x0000FE0A ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Register Bit 0 */ byte BIT1 :1; /* Break Address Register Bit 1 */ byte BIT2 :1; /* Break Address Register Bit 2 */ byte BIT3 :1; /* Break Address Register Bit 3 */ byte BIT4 :1; /* Break Address Register Bit 4 */ byte BIT5 :1; /* Break Address Register Bit 5 */ byte BIT6 :1; /* Break Address Register Bit 6 */ byte BIT7 :1; /* Break Address Register Bit 7 */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE09; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0B ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0B; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** LVISR - LVI Status Register; 0x0000FE0C ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LVIOUT :1; /* LVI Output Bit */ } Bits; } LVISRSTR; extern volatile LVISRSTR _LVISR @0x0000FE0C; #define LVISR _LVISR.Byte #define LVISR_LVIOUT _LVISR.Bits.LVIOUT #define LVISR_LVIOUT_MASK 128 /*** FLBPR - FLASH Block Protect Register; 0x0000FF7E ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* Block Protect Register Bit 0 */ byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte BPR4 :1; /* Block Protect Register Bit 4 */ byte BPR5 :1; /* Block Protect Register Bit 5 */ byte BPR6 :1; /* Block Protect Register Bit 6 */ byte BPR7 :1; /* Block Protect Register Bit 7 */ } Bits; } FLBPRSTR; /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FF7E = ; */ #define _FLBPR (*(const FLBPRSTR * __far)0x0000FF7E) #define FLBPR _FLBPR.Byte #define FLBPR_BPR0 _FLBPR.Bits.BPR0 #define FLBPR_BPR1 _FLBPR.Bits.BPR1 #define FLBPR_BPR2 _FLBPR.Bits.BPR2 #define FLBPR_BPR3 _FLBPR.Bits.BPR3 #define FLBPR_BPR4 _FLBPR.Bits.BPR4 #define FLBPR_BPR5 _FLBPR.Bits.BPR5 #define FLBPR_BPR6 _FLBPR.Bits.BPR6 #define FLBPR_BPR7 _FLBPR.Bits.BPR7 #define FLBPR_BPR0_MASK 1 #define FLBPR_BPR1_MASK 2 #define FLBPR_BPR2_MASK 4 #define FLBPR_BPR3_MASK 8 #define FLBPR_BPR4_MASK 16 #define FLBPR_BPR5_MASK 32 #define FLBPR_BPR6_MASK 64 #define FLBPR_BPR7_MASK 128 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------------------------------- Exceptions in bit names of timer status and control registers due to backward compatibility with previous releases */ #define TSC0_CHxMAX _TSC0.Bits.CH0MAX #define TSC0_TOVx _TSC0.Bits.TOV0 #define TSC0_ELSxA _TSC0.Bits.ELS0A #define TSC0_ELSxB _TSC0.Bits.ELS0B #define TSC0_MSxA _TSC0.Bits.MS0A #define TSC0_MSxB _TSC0.Bits.MS0B #define TSC0_CHxIE _TSC0.Bits.CH0IE #define TSC0_CHxF _TSC0.Bits.CH0F #define TSC1_CHxMAX _TSC1.Bits.CH1MAX #define TSC1_TOVx _TSC1.Bits.TOV1 #define TSC1_ELSxA _TSC1.Bits.ELS1A #define TSC1_ELSxB _TSC1.Bits.ELS1B #define TSC1_MSxA _TSC1.Bits.MS1A #define TSC1_CHxIE _TSC1.Bits.CH1IE #define TSC1_CHxF _TSC1.Bits.CH1F /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 12:42:40 */ #define TCH_ARR This_symb_has_been_depreciated #endif