/* Based on CPU DB MC68HC908JL8_32, version 2.89.073 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908jl8.h ** Processor : MC68HC908JL8CFA ** FileFormat: V2.30 ** DataSheet : MC68HC908JL8/D Rev. 2, 12/2002 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:08 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - 23.03.2006, V2.89.056: ** - Renamed bits ADSCR_CHx ==> ADSCR_ADCHx. REASON: Bug-fix (#3140 in Issue Manager) ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908JL8_H #define _MC68HC908JL8_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_ADC 16 #define VectorNumber_KBI 15 #define VectorNumber_SCITransmit 14 #define VectorNumber_SCIReceive 13 #define VectorNumber_SCIError 12 #define VectorNumber_Reserved5 11 #define VectorNumber_Reserved6 10 #define VectorNumber_TIM2Ovr 9 #define VectorNumber_TIM2CH1 8 #define VectorNumber_TIM2CH0 7 #define VectorNumber_TIM1Ovr 6 #define VectorNumber_TIM1CH1 5 #define VectorNumber_TIM1CH0 4 #define VectorNumber_Reserved13 3 #define VectorNumber_IRQ1 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_ADC 0x0000FFDE #define INT_KBI 0x0000FFE0 #define INT_SCITransmit 0x0000FFE2 #define INT_SCIReceive 0x0000FFE4 #define INT_SCIError 0x0000FFE6 #define Reserved5 0x0000FFE8 #define Reserved6 0x0000FFEA #define INT_TIM2Ovr 0x0000FFEC #define INT_TIM2CH1 0x0000FFEE #define INT_TIM2CH0 0x0000FFF0 #define INT_TIM1Ovr 0x0000FFF2 #define INT_TIM1CH1 0x0000FFF4 #define INT_TIM1CH0 0x0000FFF6 #define Reserved13 0x0000FFF8 #define INT_IRQ1 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte PTA6 :1; /* Port A Data Bit 6 */ byte PTA7 :1; /* Port A Data Bit 7 */ } Bits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_PTA6 _PTA.Bits.PTA6 #define PTA_PTA7 _PTA.Bits.PTA7 #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_PTA6_MASK 64 #define PTA_PTA7_MASK 128 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** PTD - Port D Data Register; 0x00000003 ***/ typedef union { byte Byte; struct { byte PTD0 :1; /* Port D Data Bit 0 */ byte PTD1 :1; /* Port D Data Bit 1 */ byte PTD2 :1; /* Port D Data Bit 2 */ byte PTD3 :1; /* Port D Data Bit 3 */ byte PTD4 :1; /* Port D Data Bit 4 */ byte PTD5 :1; /* Port D Data Bit 5 */ byte PTD6 :1; /* Port D Data Bit 6 */ byte PTD7 :1; /* Port D Data Bit 7 */ } Bits; } PTDSTR; extern volatile PTDSTR _PTD @0x00000003; #define PTD _PTD.Byte #define PTD_PTD0 _PTD.Bits.PTD0 #define PTD_PTD1 _PTD.Bits.PTD1 #define PTD_PTD2 _PTD.Bits.PTD2 #define PTD_PTD3 _PTD.Bits.PTD3 #define PTD_PTD4 _PTD.Bits.PTD4 #define PTD_PTD5 _PTD.Bits.PTD5 #define PTD_PTD6 _PTD.Bits.PTD6 #define PTD_PTD7 _PTD.Bits.PTD7 #define PTD_PTD0_MASK 1 #define PTD_PTD1_MASK 2 #define PTD_PTD2_MASK 4 #define PTD_PTD3_MASK 8 #define PTD_PTD4_MASK 16 #define PTD_PTD5_MASK 32 #define PTD_PTD6_MASK 64 #define PTD_PTD7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte DDRA6 :1; /* Data Direction Register A Bit 6 */ byte DDRA7 :1; /* Data Direction Register A Bit 7 */ } Bits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA6 _DDRA.Bits.DDRA6 #define DDRA_DDRA7 _DDRA.Bits.DDRA7 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA6_MASK 64 #define DDRA_DDRA7_MASK 128 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** DDRD - Data Direction Register D; 0x00000007 ***/ typedef union { byte Byte; struct { byte DDRD0 :1; /* Data Direction Register D Bit 0 */ byte DDRD1 :1; /* Data Direction Register D Bit 1 */ byte DDRD2 :1; /* Data Direction Register D Bit 2 */ byte DDRD3 :1; /* Data Direction Register D Bit 3 */ byte DDRD4 :1; /* Data Direction Register D Bit 4 */ byte DDRD5 :1; /* Data Direction Register D Bit 5 */ byte DDRD6 :1; /* Data Direction Register D Bit 6 */ byte DDRD7 :1; /* Data Direction Register D Bit 7 */ } Bits; } DDRDSTR; extern volatile DDRDSTR _DDRD @0x00000007; #define DDRD _DDRD.Byte #define DDRD_DDRD0 _DDRD.Bits.DDRD0 #define DDRD_DDRD1 _DDRD.Bits.DDRD1 #define DDRD_DDRD2 _DDRD.Bits.DDRD2 #define DDRD_DDRD3 _DDRD.Bits.DDRD3 #define DDRD_DDRD4 _DDRD.Bits.DDRD4 #define DDRD_DDRD5 _DDRD.Bits.DDRD5 #define DDRD_DDRD6 _DDRD.Bits.DDRD6 #define DDRD_DDRD7 _DDRD.Bits.DDRD7 #define DDRD_DDRD0_MASK 1 #define DDRD_DDRD1_MASK 2 #define DDRD_DDRD2_MASK 4 #define DDRD_DDRD3_MASK 8 #define DDRD_DDRD4_MASK 16 #define DDRD_DDRD5_MASK 32 #define DDRD_DDRD6_MASK 64 #define DDRD_DDRD7_MASK 128 /*** PTE - Port E Data Register; 0x00000008 ***/ typedef union { byte Byte; struct { byte PTE0 :1; /* Port E Data Bit 0 */ byte PTE1 :1; /* Port E Data Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTE :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTESTR; extern volatile PTESTR _PTE @0x00000008; #define PTE _PTE.Byte #define PTE_PTE0 _PTE.Bits.PTE0 #define PTE_PTE1 _PTE.Bits.PTE1 #define PTE_PTE _PTE.MergedBits.grpPTE #define PTE_PTE0_MASK 1 #define PTE_PTE1_MASK 2 #define PTE_PTE_MASK 3 #define PTE_PTE_BITNUM 0 /*** PDCR - Port D Control Register; 0x0000000A ***/ typedef union { byte Byte; struct { byte PTDPU6 :1; /* Pull-Up Enable bit 6, port D */ byte PTDPU7 :1; /* Pull-Up Enable bit 7, port D */ byte SLOWD6 :1; /* Slow Edge Enable bit 6, port D */ byte SLOWD7 :1; /* Slow Edge Enable bit 7, port D */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTDPU_6 :2; byte grpSLOWD_6 :2; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PDCRSTR; extern volatile PDCRSTR _PDCR @0x0000000A; #define PDCR _PDCR.Byte #define PDCR_PTDPU6 _PDCR.Bits.PTDPU6 #define PDCR_PTDPU7 _PDCR.Bits.PTDPU7 #define PDCR_SLOWD6 _PDCR.Bits.SLOWD6 #define PDCR_SLOWD7 _PDCR.Bits.SLOWD7 #define PDCR_PTDPU_6 _PDCR.MergedBits.grpPTDPU_6 #define PDCR_SLOWD_6 _PDCR.MergedBits.grpSLOWD_6 #define PDCR_PTDPU PDCR_PTDPU_6 #define PDCR_SLOWD PDCR_SLOWD_6 #define PDCR_PTDPU6_MASK 1 #define PDCR_PTDPU7_MASK 2 #define PDCR_SLOWD6_MASK 4 #define PDCR_SLOWD7_MASK 8 #define PDCR_PTDPU_6_MASK 3 #define PDCR_PTDPU_6_BITNUM 0 #define PDCR_SLOWD_6_MASK 12 #define PDCR_SLOWD_6_BITNUM 2 /*** DDRE - Data Direction Register E; 0x0000000C ***/ typedef union { byte Byte; struct { byte DDRE0 :1; /* Data Direction Register E Bit 0 */ byte DDRE1 :1; /* Data Direction Register E Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRE :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DDRESTR; extern volatile DDRESTR _DDRE @0x0000000C; #define DDRE _DDRE.Byte #define DDRE_DDRE0 _DDRE.Bits.DDRE0 #define DDRE_DDRE1 _DDRE.Bits.DDRE1 #define DDRE_DDRE _DDRE.MergedBits.grpDDRE #define DDRE_DDRE0_MASK 1 #define DDRE_DDRE1_MASK 2 #define DDRE_DDRE_MASK 3 #define DDRE_DDRE_BITNUM 0 /*** PTAPUE - Input Pull-Up Enable Register; 0x0000000D ***/ typedef union { byte Byte; struct { byte PTAPUE0 :1; /* Pull-Up Enable bit 0, Port A */ byte PTAPUE1 :1; /* Pull-Up Enable bit 1, Port A */ byte PTAPUE2 :1; /* Pull-Up Enable bit 2, Port A */ byte PTAPUE3 :1; /* Pull-Up Enable bit 3, Port A */ byte PTAPUE4 :1; /* Pull-Up Enable bit 4, Port A */ byte PTAPUE5 :1; /* Pull-Up Enable bit 5, Port A */ byte PTAPUE6 :1; /* Pull-Up Enable bit 6, Port A */ byte PTA6EN :1; /* Enable PTA6 on OSC2, Port A */ } Bits; struct { byte grpPTAPUE :7; byte :1; } MergedBits; } PTAPUESTR; extern volatile PTAPUESTR _PTAPUE @0x0000000D; #define PTAPUE _PTAPUE.Byte #define PTAPUE_PTAPUE0 _PTAPUE.Bits.PTAPUE0 #define PTAPUE_PTAPUE1 _PTAPUE.Bits.PTAPUE1 #define PTAPUE_PTAPUE2 _PTAPUE.Bits.PTAPUE2 #define PTAPUE_PTAPUE3 _PTAPUE.Bits.PTAPUE3 #define PTAPUE_PTAPUE4 _PTAPUE.Bits.PTAPUE4 #define PTAPUE_PTAPUE5 _PTAPUE.Bits.PTAPUE5 #define PTAPUE_PTAPUE6 _PTAPUE.Bits.PTAPUE6 #define PTAPUE_PTA6EN _PTAPUE.Bits.PTA6EN #define PTAPUE_PTAPUE _PTAPUE.MergedBits.grpPTAPUE #define PTAPUE_PTAPUE0_MASK 1 #define PTAPUE_PTAPUE1_MASK 2 #define PTAPUE_PTAPUE2_MASK 4 #define PTAPUE_PTAPUE3_MASK 8 #define PTAPUE_PTAPUE4_MASK 16 #define PTAPUE_PTAPUE5_MASK 32 #define PTAPUE_PTAPUE6_MASK 64 #define PTAPUE_PTA6EN_MASK 128 #define PTAPUE_PTAPUE_MASK 127 #define PTAPUE_PTAPUE_BITNUM 0 /*** PTA7PUE - Input Pull-Up Enable Register; 0x0000000E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte PTAPUE7 :1; /* Pull-Up Enable bit 7, Port A */ } Bits; } PTA7PUESTR; extern volatile PTA7PUESTR _PTA7PUE @0x0000000E; #define PTA7PUE _PTA7PUE.Byte #define PTA7PUE_PTAPUE7 _PTA7PUE.Bits.PTAPUE7 #define PTA7PUE_PTAPUE7_MASK 128 /*** SCC1 - SCI Control Register 1; 0x00000013 ***/ typedef union { byte Byte; struct { byte PTY :1; /* Parity Bit */ byte PEN :1; /* Parity Enable Bit */ byte ILTY :1; /* Idle Line Type Bit */ byte WAKE :1; /* Wakeup Condition Bit */ byte M :1; /* Mode (Character Length) Bit */ byte TXINV :1; /* Transmit Inversion Bit */ byte ENSCI :1; /* Enable SCI Bit */ byte LOOPS :1; /* Loop Mode Select Bit */ } Bits; } SCC1STR; extern volatile SCC1STR _SCC1 @0x00000013; #define SCC1 _SCC1.Byte #define SCC1_PTY _SCC1.Bits.PTY #define SCC1_PEN _SCC1.Bits.PEN #define SCC1_ILTY _SCC1.Bits.ILTY #define SCC1_WAKE _SCC1.Bits.WAKE #define SCC1_M _SCC1.Bits.M #define SCC1_TXINV _SCC1.Bits.TXINV #define SCC1_ENSCI _SCC1.Bits.ENSCI #define SCC1_LOOPS _SCC1.Bits.LOOPS #define SCC1_PTY_MASK 1 #define SCC1_PEN_MASK 2 #define SCC1_ILTY_MASK 4 #define SCC1_WAKE_MASK 8 #define SCC1_M_MASK 16 #define SCC1_TXINV_MASK 32 #define SCC1_ENSCI_MASK 64 #define SCC1_LOOPS_MASK 128 /*** SCC2 - SCI Control Register 2; 0x00000014 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break Bit */ byte RWU :1; /* Receiver Wakeup Bit */ byte RE :1; /* Receiver Enable Bit */ byte TE :1; /* Transmitter Enable Bit */ byte ILIE :1; /* Idle Line Interrupt Enable Bit */ byte SCRIE :1; /* SCI Receive Interrupt Enable Bit */ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ byte SCTIE :1; /* SCI Transmit Interrupt Enable Bit */ } Bits; } SCC2STR; extern volatile SCC2STR _SCC2 @0x00000014; #define SCC2 _SCC2.Byte #define SCC2_SBK _SCC2.Bits.SBK #define SCC2_RWU _SCC2.Bits.RWU #define SCC2_RE _SCC2.Bits.RE #define SCC2_TE _SCC2.Bits.TE #define SCC2_ILIE _SCC2.Bits.ILIE #define SCC2_SCRIE _SCC2.Bits.SCRIE #define SCC2_TCIE _SCC2.Bits.TCIE #define SCC2_SCTIE _SCC2.Bits.SCTIE #define SCC2_SBK_MASK 1 #define SCC2_RWU_MASK 2 #define SCC2_RE_MASK 4 #define SCC2_TE_MASK 8 #define SCC2_ILIE_MASK 16 #define SCC2_SCRIE_MASK 32 #define SCC2_TCIE_MASK 64 #define SCC2_SCTIE_MASK 128 /*** SCC3 - SCI Control Register 3; 0x00000015 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Receiver Parity Error Interrupt Enable Bit */ byte FEIE :1; /* Receiver Framing Error Interrupt Enable Bit */ byte NEIE :1; /* Receiver Noise Error Interrupt Enable Bit */ byte ORIE :1; /* Receiver Overrun Interrupt Enable Bit */ byte :1; byte :1; byte T8 :1; /* Transmitted Bit 8 */ byte R8 :1; /* Received Bit 8 */ } Bits; } SCC3STR; extern volatile SCC3STR _SCC3 @0x00000015; #define SCC3 _SCC3.Byte #define SCC3_PEIE _SCC3.Bits.PEIE #define SCC3_FEIE _SCC3.Bits.FEIE #define SCC3_NEIE _SCC3.Bits.NEIE #define SCC3_ORIE _SCC3.Bits.ORIE #define SCC3_T8 _SCC3.Bits.T8 #define SCC3_R8 _SCC3.Bits.R8 #define SCC3_PEIE_MASK 1 #define SCC3_FEIE_MASK 2 #define SCC3_NEIE_MASK 4 #define SCC3_ORIE_MASK 8 #define SCC3_T8_MASK 64 #define SCC3_R8_MASK 128 /*** SCS1 - SCI Status Register 1; 0x00000016 ***/ typedef union { byte Byte; struct { byte PE :1; /* Receiver Parity Error Bit */ byte FE :1; /* Receiver Framing Error Bit */ byte NF :1; /* Receiver Noise Flag Bit */ byte OR :1; /* Receiver Overrun Bit */ byte IDLE :1; /* Receiver Idle Bit */ byte SCRF :1; /* SCI Receiver Full Bit */ byte TC :1; /* Transmission Complete Bit */ byte SCTE :1; /* SCI Transmitter Empty Bit */ } Bits; } SCS1STR; extern volatile SCS1STR _SCS1 @0x00000016; #define SCS1 _SCS1.Byte #define SCS1_PE _SCS1.Bits.PE #define SCS1_FE _SCS1.Bits.FE #define SCS1_NF _SCS1.Bits.NF #define SCS1_OR _SCS1.Bits.OR #define SCS1_IDLE _SCS1.Bits.IDLE #define SCS1_SCRF _SCS1.Bits.SCRF #define SCS1_TC _SCS1.Bits.TC #define SCS1_SCTE _SCS1.Bits.SCTE #define SCS1_PE_MASK 1 #define SCS1_FE_MASK 2 #define SCS1_NF_MASK 4 #define SCS1_OR_MASK 8 #define SCS1_IDLE_MASK 16 #define SCS1_SCRF_MASK 32 #define SCS1_TC_MASK 64 #define SCS1_SCTE_MASK 128 /*** SCS2 - SCI Status Register 2; 0x00000017 ***/ typedef union { byte Byte; struct { byte RPF :1; /* Reception in Progress Flag Bit */ byte BKF :1; /* Break Flag Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SCS2STR; extern volatile SCS2STR _SCS2 @0x00000017; #define SCS2 _SCS2.Byte #define SCS2_RPF _SCS2.Bits.RPF #define SCS2_BKF _SCS2.Bits.BKF #define SCS2_RPF_MASK 1 #define SCS2_BKF_MASK 2 /*** SCDR - SCI Data Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCDRSTR; extern volatile SCDRSTR _SCDR @0x00000018; #define SCDR _SCDR.Byte #define SCDR_R0_T0 _SCDR.Bits.R0_T0 #define SCDR_R1_T1 _SCDR.Bits.R1_T1 #define SCDR_R2_T2 _SCDR.Bits.R2_T2 #define SCDR_R3_T3 _SCDR.Bits.R3_T3 #define SCDR_R4_T4 _SCDR.Bits.R4_T4 #define SCDR_R5_T5 _SCDR.Bits.R5_T5 #define SCDR_R6_T6 _SCDR.Bits.R6_T6 #define SCDR_R7_T7 _SCDR.Bits.R7_T7 #define SCDR_R0_T0_MASK 1 #define SCDR_R1_T1_MASK 2 #define SCDR_R2_T2_MASK 4 #define SCDR_R3_T3_MASK 8 #define SCDR_R4_T4_MASK 16 #define SCDR_R5_T5_MASK 32 #define SCDR_R6_T6_MASK 64 #define SCDR_R7_T7_MASK 128 /*** SCBR - SCI Baud Rate Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte SCR0 :1; /* SCI Baud Rate Select Bit 0 */ byte SCR1 :1; /* SCI Baud Rate Select Bit 1 */ byte SCR2 :1; /* SCI Baud Rate Select Bit 2 */ byte :1; byte SCP0 :1; /* SCI Baud Rate Prescaler Bit 0 */ byte SCP1 :1; /* SCI Baud Rate Prescaler Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpSCR :3; byte :1; byte grpSCP :2; byte :1; byte :1; } MergedBits; } SCBRSTR; extern volatile SCBRSTR _SCBR @0x00000019; #define SCBR _SCBR.Byte #define SCBR_SCR0 _SCBR.Bits.SCR0 #define SCBR_SCR1 _SCBR.Bits.SCR1 #define SCBR_SCR2 _SCBR.Bits.SCR2 #define SCBR_SCP0 _SCBR.Bits.SCP0 #define SCBR_SCP1 _SCBR.Bits.SCP1 #define SCBR_SCR _SCBR.MergedBits.grpSCR #define SCBR_SCP _SCBR.MergedBits.grpSCP #define SCBR_SCR0_MASK 1 #define SCBR_SCR1_MASK 2 #define SCBR_SCR2_MASK 4 #define SCBR_SCP0_MASK 16 #define SCBR_SCP1_MASK 32 #define SCBR_SCR_MASK 7 #define SCBR_SCR_BITNUM 0 #define SCBR_SCP_MASK 48 #define SCBR_SCP_BITNUM 4 /*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */ byte IMASKK :1; /* Keyboard Interrupt Mask Bit */ byte ACKK :1; /* Keyboard Acknowledge Bit */ byte KEYF :1; /* Keyboard Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBSCRSTR; extern volatile KBSCRSTR _KBSCR @0x0000001A; #define KBSCR _KBSCR.Byte #define KBSCR_MODEK _KBSCR.Bits.MODEK #define KBSCR_IMASKK _KBSCR.Bits.IMASKK #define KBSCR_ACKK _KBSCR.Bits.ACKK #define KBSCR_KEYF _KBSCR.Bits.KEYF #define KBSCR_MODEK_MASK 1 #define KBSCR_IMASKK_MASK 2 #define KBSCR_ACKK_MASK 4 #define KBSCR_KEYF_MASK 8 /*** KBIER - Keyboard Interrrupt Enable Register; 0x0000001B ***/ typedef union { byte Byte; struct { byte KBIE0 :1; /* Keyboard Interrupt Enable Bit 0 */ byte KBIE1 :1; /* Keyboard Interrupt Enable Bit 1 */ byte KBIE2 :1; /* Keyboard Interrupt Enable Bit 2 */ byte KBIE3 :1; /* Keyboard Interrupt Enable Bit 3 */ byte KBIE4 :1; /* Keyboard Interrupt Enable Bit 4 */ byte KBIE5 :1; /* Keyboard Interrupt Enable Bit 5 */ byte KBIE6 :1; /* Keyboard Interrupt Enable Bit 6 */ byte KBIE7 :1; /* Keyboard Interrupt Enable Bit 7 */ } Bits; } KBIERSTR; extern volatile KBIERSTR _KBIER @0x0000001B; #define KBIER _KBIER.Byte #define KBIER_KBIE0 _KBIER.Bits.KBIE0 #define KBIER_KBIE1 _KBIER.Bits.KBIE1 #define KBIER_KBIE2 _KBIER.Bits.KBIE2 #define KBIER_KBIE3 _KBIER.Bits.KBIE3 #define KBIER_KBIE4 _KBIER.Bits.KBIE4 #define KBIER_KBIE5 _KBIER.Bits.KBIE5 #define KBIER_KBIE6 _KBIER.Bits.KBIE6 #define KBIER_KBIE7 _KBIER.Bits.KBIE7 #define KBIER_KBIE0_MASK 1 #define KBIER_KBIE1_MASK 2 #define KBIER_KBIE2_MASK 4 #define KBIER_KBIE3_MASK 8 #define KBIER_KBIE4_MASK 16 #define KBIER_KBIE5_MASK 32 #define KBIER_KBIE6_MASK 64 #define KBIER_KBIE7_MASK 128 /*** INTSCR - IRQ Status and Control Register; 0x0000001D ***/ typedef union { byte Byte; struct { byte MODE :1; /* IRQ Edge/Level Select Bit */ byte IMASK :1; /* IRQ Interrupt Mask Bit */ byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */ byte IRQF :1; /* IRQ Flag */ byte :1; byte :1; byte :1; byte :1; } Bits; } INTSCRSTR; extern volatile INTSCRSTR _INTSCR @0x0000001D; #define INTSCR _INTSCR.Byte #define INTSCR_MODE _INTSCR.Bits.MODE #define INTSCR_IMASK _INTSCR.Bits.IMASK #define INTSCR_ACK _INTSCR.Bits.ACK #define INTSCR_IRQF _INTSCR.Bits.IRQF #define INTSCR_MODE_MASK 1 #define INTSCR_IMASK_MASK 2 #define INTSCR_ACK_MASK 4 #define INTSCR_IRQF_MASK 8 /*** CONFIG2 - Configuration Register 2; 0x0000001E ***/ typedef union { byte Byte; struct { byte STOP_ICLKDIS :1; /* Internal oscillator STOP mode disable bit */ byte :1; byte :1; byte LVIT0 :1; /* Low Voltage Inhibit Trip Voltage Selection Bit 0 */ byte LVIT1 :1; /* Low Voltage Inhibit Trip Voltage Selection Bit 1 */ byte :1; byte :1; byte IRQPUD :1; /* IRQ1 Pin Pull-Up Control Bit */ } Bits; struct { byte :1; byte :1; byte :1; byte grpLVIT :2; byte :1; byte :1; byte :1; } MergedBits; } CONFIG2STR; extern volatile CONFIG2STR _CONFIG2 @0x0000001E; #define CONFIG2 _CONFIG2.Byte #define CONFIG2_STOP_ICLKDIS _CONFIG2.Bits.STOP_ICLKDIS #define CONFIG2_LVIT0 _CONFIG2.Bits.LVIT0 #define CONFIG2_LVIT1 _CONFIG2.Bits.LVIT1 #define CONFIG2_IRQPUD _CONFIG2.Bits.IRQPUD #define CONFIG2_LVIT _CONFIG2.MergedBits.grpLVIT #define CONFIG2_STOP_ICLKDIS_MASK 1 #define CONFIG2_LVIT0_MASK 8 #define CONFIG2_LVIT1_MASK 16 #define CONFIG2_IRQPUD_MASK 128 #define CONFIG2_LVIT_MASK 24 #define CONFIG2_LVIT_BITNUM 3 /*** CONFIG1 - Configuration Register 1; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte SSREC :1; /* Short Stop Recovery Bit */ byte :1; byte LVID :1; /* Low Voltage Inhibit Disable Bit */ byte :1; byte :1; byte COPRS :1; /* COP Reset Period Selection Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVID _CONFIG1.Bits.LVID #define CONFIG1_COPRS _CONFIG1.Bits.COPRS #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_SSREC_MASK 4 #define CONFIG1_LVID_MASK 16 #define CONFIG1_COPRS_MASK 128 /*** T1SC - TIM1 Status and Control Register TSC; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM1 Reset Bit */ byte TSTOP :1; /* TIM1 Stop Bit */ byte TOIE :1; /* TIM1 Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM1 Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } T1SCSTR; extern volatile T1SCSTR _T1SC @0x00000020; #define T1SC _T1SC.Byte #define T1SC_PS0 _T1SC.Bits.PS0 #define T1SC_PS1 _T1SC.Bits.PS1 #define T1SC_PS2 _T1SC.Bits.PS2 #define T1SC_TRST _T1SC.Bits.TRST #define T1SC_TSTOP _T1SC.Bits.TSTOP #define T1SC_TOIE _T1SC.Bits.TOIE #define T1SC_TOF _T1SC.Bits.TOF #define T1SC_PS _T1SC.MergedBits.grpPS #define T1SC_PS0_MASK 1 #define T1SC_PS1_MASK 2 #define T1SC_PS2_MASK 4 #define T1SC_TRST_MASK 16 #define T1SC_TSTOP_MASK 32 #define T1SC_TOIE_MASK 64 #define T1SC_TOF_MASK 128 #define T1SC_PS_MASK 7 #define T1SC_PS_BITNUM 0 /*** T1CNT - TIM1 Counter Register; 0x00000021 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CNTH - TIM1 Counter Register High; 0x00000021 ***/ union { byte Byte; } T1CNTHSTR; #define T1CNTH _T1CNT.Overlap_STR.T1CNTHSTR.Byte /*** T1CNTL - TIM1 Counter Register Low; 0x00000022 ***/ union { byte Byte; } T1CNTLSTR; #define T1CNTL _T1CNT.Overlap_STR.T1CNTLSTR.Byte } Overlap_STR; } T1CNTSTR; extern volatile T1CNTSTR _T1CNT @0x00000021; #define T1CNT _T1CNT.Word /*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1MODH - TIM1 Counter Modulo Register High; 0x00000023 ***/ union { byte Byte; } T1MODHSTR; #define T1MODH _T1MOD.Overlap_STR.T1MODHSTR.Byte /*** T1MODL - TIM1 Counter Modulo Register Low; 0x00000024 ***/ union { byte Byte; } T1MODLSTR; #define T1MODL _T1MOD.Overlap_STR.T1MODLSTR.Byte } Overlap_STR; } T1MODSTR; extern volatile T1MODSTR _T1MOD @0x00000023; #define T1MOD _T1MOD.Word /*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } T1SC0STR; extern volatile T1SC0STR _T1SC0 @0x00000025; #define T1SC0 _T1SC0.Byte #define T1SC0_CH0MAX _T1SC0.Bits.CH0MAX #define T1SC0_TOV0 _T1SC0.Bits.TOV0 #define T1SC0_ELS0A _T1SC0.Bits.ELS0A #define T1SC0_ELS0B _T1SC0.Bits.ELS0B #define T1SC0_MS0A _T1SC0.Bits.MS0A #define T1SC0_MS0B _T1SC0.Bits.MS0B #define T1SC0_CH0IE _T1SC0.Bits.CH0IE #define T1SC0_CH0F _T1SC0.Bits.CH0F #define T1SC0_ELS0x _T1SC0.MergedBits.grpELS0x #define T1SC0_MS0x _T1SC0.MergedBits.grpMS0x #define T1SC0_CH0MAX_MASK 1 #define T1SC0_TOV0_MASK 2 #define T1SC0_ELS0A_MASK 4 #define T1SC0_ELS0B_MASK 8 #define T1SC0_MS0A_MASK 16 #define T1SC0_MS0B_MASK 32 #define T1SC0_CH0IE_MASK 64 #define T1SC0_CH0F_MASK 128 #define T1SC0_ELS0x_MASK 12 #define T1SC0_ELS0x_BITNUM 2 #define T1SC0_MS0x_MASK 48 #define T1SC0_MS0x_BITNUM 4 /*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CH0H - TIM1 Channel 0 Register High; 0x00000026 ***/ union { byte Byte; } T1CH0HSTR; #define T1CH0H _T1CH0.Overlap_STR.T1CH0HSTR.Byte /*** T1CH0L - TIM1 Channel 0 Register Low; 0x00000027 ***/ union { byte Byte; } T1CH0LSTR; #define T1CH0L _T1CH0.Overlap_STR.T1CH0LSTR.Byte } Overlap_STR; } T1CH0STR; extern volatile T1CH0STR _T1CH0 @0x00000026; #define T1CH0 _T1CH0.Word /*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } T1SC1STR; extern volatile T1SC1STR _T1SC1 @0x00000028; #define T1SC1 _T1SC1.Byte #define T1SC1_CH1MAX _T1SC1.Bits.CH1MAX #define T1SC1_TOV1 _T1SC1.Bits.TOV1 #define T1SC1_ELS1A _T1SC1.Bits.ELS1A #define T1SC1_ELS1B _T1SC1.Bits.ELS1B #define T1SC1_MS1A _T1SC1.Bits.MS1A #define T1SC1_CH1IE _T1SC1.Bits.CH1IE #define T1SC1_CH1F _T1SC1.Bits.CH1F #define T1SC1_ELS1x _T1SC1.MergedBits.grpELS1x #define T1SC1_CH1MAX_MASK 1 #define T1SC1_TOV1_MASK 2 #define T1SC1_ELS1A_MASK 4 #define T1SC1_ELS1B_MASK 8 #define T1SC1_MS1A_MASK 16 #define T1SC1_CH1IE_MASK 64 #define T1SC1_CH1F_MASK 128 #define T1SC1_ELS1x_MASK 12 #define T1SC1_ELS1x_BITNUM 2 /*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CH1H - TIM1 Channel 1 Register High; 0x00000029 ***/ union { byte Byte; } T1CH1HSTR; #define T1CH1H _T1CH1.Overlap_STR.T1CH1HSTR.Byte /*** T1CH1L - TIM1 Channel 1 Register Low; 0x0000002A ***/ union { byte Byte; } T1CH1LSTR; #define T1CH1L _T1CH1.Overlap_STR.T1CH1LSTR.Byte } Overlap_STR; } T1CH1STR; extern volatile T1CH1STR _T1CH1 @0x00000029; #define T1CH1 _T1CH1.Word /*** T2SC - TIM2 Status and Control Register; 0x00000030 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM2 Reset Bit */ byte TSTOP :1; /* TIM2 Stop Bit */ byte TOIE :1; /* TIM2 Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM2 Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } T2SCSTR; extern volatile T2SCSTR _T2SC @0x00000030; #define T2SC _T2SC.Byte #define T2SC_PS0 _T2SC.Bits.PS0 #define T2SC_PS1 _T2SC.Bits.PS1 #define T2SC_PS2 _T2SC.Bits.PS2 #define T2SC_TRST _T2SC.Bits.TRST #define T2SC_TSTOP _T2SC.Bits.TSTOP #define T2SC_TOIE _T2SC.Bits.TOIE #define T2SC_TOF _T2SC.Bits.TOF #define T2SC_PS _T2SC.MergedBits.grpPS #define T2SC_PS0_MASK 1 #define T2SC_PS1_MASK 2 #define T2SC_PS2_MASK 4 #define T2SC_TRST_MASK 16 #define T2SC_TSTOP_MASK 32 #define T2SC_TOIE_MASK 64 #define T2SC_TOF_MASK 128 #define T2SC_PS_MASK 7 #define T2SC_PS_BITNUM 0 /*** T2CNT - TIM2 Counter Register; 0x00000031 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CNTH - TIM2 Counter Register High; 0x00000031 ***/ union { byte Byte; } T2CNTHSTR; #define T2CNTH _T2CNT.Overlap_STR.T2CNTHSTR.Byte /*** T2CNTL - TIM2 Counter Register Low; 0x00000032 ***/ union { byte Byte; } T2CNTLSTR; #define T2CNTL _T2CNT.Overlap_STR.T2CNTLSTR.Byte } Overlap_STR; } T2CNTSTR; extern volatile T2CNTSTR _T2CNT @0x00000031; #define T2CNT _T2CNT.Word /*** T2MOD - TIM2 Counter Modulo Register; 0x00000033 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2MODH - TIM2 Counter Modulo Register High; 0x00000033 ***/ union { byte Byte; } T2MODHSTR; #define T2MODH _T2MOD.Overlap_STR.T2MODHSTR.Byte /*** T2MODL - TIM2 Counter Modulo Register Low; 0x00000034 ***/ union { byte Byte; } T2MODLSTR; #define T2MODL _T2MOD.Overlap_STR.T2MODLSTR.Byte } Overlap_STR; } T2MODSTR; extern volatile T2MODSTR _T2MOD @0x00000033; #define T2MOD _T2MOD.Word /*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000035 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } T2SC0STR; extern volatile T2SC0STR _T2SC0 @0x00000035; #define T2SC0 _T2SC0.Byte #define T2SC0_CH0MAX _T2SC0.Bits.CH0MAX #define T2SC0_TOV0 _T2SC0.Bits.TOV0 #define T2SC0_ELS0A _T2SC0.Bits.ELS0A #define T2SC0_ELS0B _T2SC0.Bits.ELS0B #define T2SC0_MS0A _T2SC0.Bits.MS0A #define T2SC0_MS0B _T2SC0.Bits.MS0B #define T2SC0_CH0IE _T2SC0.Bits.CH0IE #define T2SC0_CH0F _T2SC0.Bits.CH0F #define T2SC0_ELS0x _T2SC0.MergedBits.grpELS0x #define T2SC0_MS0x _T2SC0.MergedBits.grpMS0x #define T2SC0_CH0MAX_MASK 1 #define T2SC0_TOV0_MASK 2 #define T2SC0_ELS0A_MASK 4 #define T2SC0_ELS0B_MASK 8 #define T2SC0_MS0A_MASK 16 #define T2SC0_MS0B_MASK 32 #define T2SC0_CH0IE_MASK 64 #define T2SC0_CH0F_MASK 128 #define T2SC0_ELS0x_MASK 12 #define T2SC0_ELS0x_BITNUM 2 #define T2SC0_MS0x_MASK 48 #define T2SC0_MS0x_BITNUM 4 /*** T2CH0 - TIM2 Channel 0 Register; 0x00000036 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CH0H - TIM2 Channel 0 Register High; 0x00000036 ***/ union { byte Byte; } T2CH0HSTR; #define T2CH0H _T2CH0.Overlap_STR.T2CH0HSTR.Byte /*** T2CH0L - TIM2 Channel 0 Register Low; 0x00000037 ***/ union { byte Byte; } T2CH0LSTR; #define T2CH0L _T2CH0.Overlap_STR.T2CH0LSTR.Byte } Overlap_STR; } T2CH0STR; extern volatile T2CH0STR _T2CH0 @0x00000036; #define T2CH0 _T2CH0.Word /*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000038 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } T2SC1STR; extern volatile T2SC1STR _T2SC1 @0x00000038; #define T2SC1 _T2SC1.Byte #define T2SC1_CH1MAX _T2SC1.Bits.CH1MAX #define T2SC1_TOV1 _T2SC1.Bits.TOV1 #define T2SC1_ELS1A _T2SC1.Bits.ELS1A #define T2SC1_ELS1B _T2SC1.Bits.ELS1B #define T2SC1_MS1A _T2SC1.Bits.MS1A #define T2SC1_CH1IE _T2SC1.Bits.CH1IE #define T2SC1_CH1F _T2SC1.Bits.CH1F #define T2SC1_ELS1x _T2SC1.MergedBits.grpELS1x #define T2SC1_CH1MAX_MASK 1 #define T2SC1_TOV1_MASK 2 #define T2SC1_ELS1A_MASK 4 #define T2SC1_ELS1B_MASK 8 #define T2SC1_MS1A_MASK 16 #define T2SC1_CH1IE_MASK 64 #define T2SC1_CH1F_MASK 128 #define T2SC1_ELS1x_MASK 12 #define T2SC1_ELS1x_BITNUM 2 /*** T2CH1 - TIM2 Channel 1 Register; 0x00000039 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CH1H - TIM2 Channel 1 Register High; 0x00000039 ***/ union { byte Byte; } T2CH1HSTR; #define T2CH1H _T2CH1.Overlap_STR.T2CH1HSTR.Byte /*** T2CH1L - TIM2 Channel 1 Register Low; 0x0000003A ***/ union { byte Byte; } T2CH1LSTR; #define T2CH1L _T2CH1.Overlap_STR.T2CH1LSTR.Byte } Overlap_STR; } T2CH1STR; extern volatile T2CH1STR _T2CH1 @0x00000039; #define T2CH1 _T2CH1.Word /*** ADSCR - ADC Status and Control Register; 0x0000003C ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x0000003C; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADR - ADC Data Register; 0x0000003D ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADRSTR; extern volatile ADRSTR _ADR @0x0000003D; #define ADR _ADR.Byte #define ADR_AD0 _ADR.Bits.AD0 #define ADR_AD1 _ADR.Bits.AD1 #define ADR_AD2 _ADR.Bits.AD2 #define ADR_AD3 _ADR.Bits.AD3 #define ADR_AD4 _ADR.Bits.AD4 #define ADR_AD5 _ADR.Bits.AD5 #define ADR_AD6 _ADR.Bits.AD6 #define ADR_AD7 _ADR.Bits.AD7 #define ADR_AD0_MASK 1 #define ADR_AD1_MASK 2 #define ADR_AD2_MASK 4 #define ADR_AD3_MASK 8 #define ADR_AD4_MASK 16 #define ADR_AD5_MASK 32 #define ADR_AD6_MASK 64 #define ADR_AD7_MASK 128 /*** ADICLK - ADC Input Clock Register; 0x0000003E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte ADIV0 :1; /* ADC Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC Clock Prescaler Bit 1 */ byte ADIV2 :1; /* ADC Clock Prescaler Bit 2 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte grpADIV :3; } MergedBits; } ADICLKSTR; extern volatile ADICLKSTR _ADICLK @0x0000003E; #define ADICLK _ADICLK.Byte #define ADICLK_ADIV0 _ADICLK.Bits.ADIV0 #define ADICLK_ADIV1 _ADICLK.Bits.ADIV1 #define ADICLK_ADIV2 _ADICLK.Bits.ADIV2 #define ADICLK_ADIV _ADICLK.MergedBits.grpADIV #define ADICLK_ADIV0_MASK 32 #define ADICLK_ADIV1_MASK 64 #define ADICLK_ADIV2_MASK 128 #define ADICLK_ADIV_MASK 224 #define ADICLK_ADIV_BITNUM 5 /*** BSR - Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte SBSW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } BSRSTR; extern volatile BSRSTR _BSR @0x0000FE00; #define BSR _BSR.Byte #define BSR_SBSW _BSR.Bits.SBSW #define BSR_SBSW_MASK 2 /*** RSR - Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte MODRST :1; /* Monitor Mode Entry Module Reset Bit */ byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } RSRSTR; extern volatile RSRSTR _RSR @0x0000FE01; #define RSR _RSR.Byte #define RSR_LVI _RSR.Bits.LVI #define RSR_MODRST _RSR.Bits.MODRST #define RSR_ILAD _RSR.Bits.ILAD #define RSR_ILOP _RSR.Bits.ILOP #define RSR_COP _RSR.Bits.COP #define RSR_PIN _RSR.Bits.PIN #define RSR_POR _RSR.Bits.POR #define RSR_LVI_MASK 2 #define RSR_MODRST_MASK 4 #define RSR_ILAD_MASK 8 #define RSR_ILOP_MASK 16 #define RSR_COP_MASK 32 #define RSR_PIN_MASK 64 #define RSR_POR_MASK 128 /*** BFCR - Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } BFCRSTR; extern volatile BFCRSTR _BFCR @0x0000FE03; #define BFCR _BFCR.Byte #define BFCR_BCFE _BFCR.Bits.BCFE #define BFCR_BCFE_MASK 128 /*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte IF1 :1; /* Interrupt Flag 1 */ byte :1; byte IF3 :1; /* Interrupt Flag 3 */ byte IF4 :1; /* Interrupt Flag 4 */ byte IF5 :1; /* Interrupt Flag 5 */ byte IF6 :1; /* Interrupt Flag 6 */ } Bits; struct { byte :1; byte :1; byte grpIF_1 :1; byte :1; byte grpIF_3 :4; } MergedBits; } INT1STR; extern volatile INT1STR _INT1 @0x0000FE04; #define INT1 _INT1.Byte #define INT1_IF1 _INT1.Bits.IF1 #define INT1_IF3 _INT1.Bits.IF3 #define INT1_IF4 _INT1.Bits.IF4 #define INT1_IF5 _INT1.Bits.IF5 #define INT1_IF6 _INT1.Bits.IF6 #define INT1_IF_3 _INT1.MergedBits.grpIF_3 #define INT1_IF INT1_IF_3 #define INT1_IF1_MASK 4 #define INT1_IF3_MASK 16 #define INT1_IF4_MASK 32 #define INT1_IF5_MASK 64 #define INT1_IF6_MASK 128 #define INT1_IF_3_MASK 240 #define INT1_IF_3_BITNUM 4 /*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/ typedef union { byte Byte; struct { byte IF7 :1; /* Interrupt Flag 7 */ byte IF8 :1; /* Interrupt Flag 8 */ byte :1; byte :1; byte IF11 :1; /* Interrupt Flag 11 */ byte IF12 :1; /* Interrupt Flag 12 */ byte IF13 :1; /* Interrupt Flag 13 */ byte IF14 :1; /* Interrupt Flag 14 */ } Bits; struct { byte grpIF_7 :2; byte :1; byte :1; byte grpIF_11 :4; } MergedBits; } INT2STR; extern volatile INT2STR _INT2 @0x0000FE05; #define INT2 _INT2.Byte #define INT2_IF7 _INT2.Bits.IF7 #define INT2_IF8 _INT2.Bits.IF8 #define INT2_IF11 _INT2.Bits.IF11 #define INT2_IF12 _INT2.Bits.IF12 #define INT2_IF13 _INT2.Bits.IF13 #define INT2_IF14 _INT2.Bits.IF14 #define INT2_IF_7 _INT2.MergedBits.grpIF_7 #define INT2_IF_11 _INT2.MergedBits.grpIF_11 #define INT2_IF INT2_IF_7 #define INT2_IF7_MASK 1 #define INT2_IF8_MASK 2 #define INT2_IF11_MASK 16 #define INT2_IF12_MASK 32 #define INT2_IF13_MASK 64 #define INT2_IF14_MASK 128 #define INT2_IF_7_MASK 3 #define INT2_IF_7_BITNUM 0 #define INT2_IF_11_MASK 240 #define INT2_IF_11_BITNUM 4 /*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/ typedef union { byte Byte; struct { byte IF15 :1; /* Interrupt Flag 15 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } INT3STR; extern volatile INT3STR _INT3 @0x0000FE06; #define INT3 _INT3.Byte #define INT3_IF15 _INT3.Bits.IF15 #define INT3_IF15_MASK 1 /*** FLCR - FLASH Control Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000FE08; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_ERASE _FLCR.Bits.ERASE #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_ERASE_MASK 2 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** BRK - Break Address Register; 0x0000FE0C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register High; 0x0000FE0C ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Register Bit 8 */ byte BIT9 :1; /* Break Address Register Bit 9 */ byte BIT10 :1; /* Break Address Register Bit 10 */ byte BIT11 :1; /* Break Address Register Bit 11 */ byte BIT12 :1; /* Break Address Register Bit 12 */ byte BIT13 :1; /* Break Address Register Bit 13 */ byte BIT14 :1; /* Break Address Register Bit 14 */ byte BIT15 :1; /* Break Address Register Bit 15 */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register Low; 0x0000FE0D ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Register Bit 0 */ byte BIT1 :1; /* Break Address Register Bit 1 */ byte BIT2 :1; /* Break Address Register Bit 2 */ byte BIT3 :1; /* Break Address Register Bit 3 */ byte BIT4 :1; /* Break Address Register Bit 4 */ byte BIT5 :1; /* Break Address Register Bit 5 */ byte BIT6 :1; /* Break Address Register Bit 6 */ byte BIT7 :1; /* Break Address Register Bit 7 */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE0C; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0E; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** FLBPR - FLASH Block Protect Register; 0x0000FFCF ***/ typedef union { byte Byte; struct { byte :1; byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte BPR4 :1; /* Block Protect Register Bit 4 */ byte BPR5 :1; /* Block Protect Register Bit 5 */ byte BPR6 :1; /* Block Protect Register Bit 6 */ byte BPR7 :1; /* Block Protect Register Bit 7 */ } Bits; struct { byte :1; byte grpBPR_1 :7; } MergedBits; } FLBPRSTR; /* Tip for register initialization in the user code: const byte FLBPR_INIT @0x0000FFCF = ; */ #define _FLBPR (*(const FLBPRSTR * __far)0x0000FFCF) #define FLBPR _FLBPR.Byte #define FLBPR_BPR1 _FLBPR.Bits.BPR1 #define FLBPR_BPR2 _FLBPR.Bits.BPR2 #define FLBPR_BPR3 _FLBPR.Bits.BPR3 #define FLBPR_BPR4 _FLBPR.Bits.BPR4 #define FLBPR_BPR5 _FLBPR.Bits.BPR5 #define FLBPR_BPR6 _FLBPR.Bits.BPR6 #define FLBPR_BPR7 _FLBPR.Bits.BPR7 #define FLBPR_BPR_1 _FLBPR.MergedBits.grpBPR_1 #define FLBPR_BPR FLBPR_BPR_1 #define FLBPR_BPR1_MASK 2 #define FLBPR_BPR2_MASK 4 #define FLBPR_BPR3_MASK 8 #define FLBPR_BPR4_MASK 16 #define FLBPR_BPR5_MASK 32 #define FLBPR_BPR6_MASK 64 #define FLBPR_BPR7_MASK 128 #define FLBPR_BPR_1_MASK 254 #define FLBPR_BPR_1_BITNUM 1 /*** MOR - Mask Option Register; 0x0000FFD0 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte OSCSEL :1; /* Oscillator Select Bit */ } Bits; } MORSTR; /* Tip for register initialization in the user code: const byte MOR_INIT @0x0000FFD0 = ; */ #define _MOR (*(const MORSTR * __far)0x0000FFD0) #define MOR _MOR.Byte #define MOR_OSCSEL _MOR.Bits.OSCSEL #define MOR_OSCSEL_MASK 128 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------------------------------- Exceptions in bit names of timer status and control registers due to backward compatibility with previous releases */ #define T1SC0_CHxMAX _T1SC0.Bits.CH0MAX #define T1SC0_TOVx _T1SC0.Bits.TOV0 #define T1SC0_ELSxA _T1SC0.Bits.ELS0A #define T1SC0_ELSxB _T1SC0.Bits.ELS0B #define T1SC0_MSxA _T1SC0.Bits.MS0A #define T1SC0_MSxB _T1SC0.Bits.MS0B #define T1SC0_CHxIE _T1SC0.Bits.CH0IE #define T1SC0_CHxF _T1SC0.Bits.CH0F #define T1SC1_CHxMAX _T1SC1.Bits.CH1MAX #define T1SC1_TOVx _T1SC1.Bits.TOV1 #define T1SC1_ELSxA _T1SC1.Bits.ELS1A #define T1SC1_ELSxB _T1SC1.Bits.ELS1B #define T1SC1_MSxA _T1SC1.Bits.MS1A #define T1SC1_CHxIE _T1SC1.Bits.CH1IE #define T1SC1_CHxF _T1SC1.Bits.CH1F #define T2SC0_CHxMAX _T2SC0.Bits.CH0MAX #define T2SC0_TOVx _T2SC0.Bits.TOV0 #define T2SC0_ELSxA _T2SC0.Bits.ELS0A #define T2SC0_ELSxB _T2SC0.Bits.ELS0B #define T2SC0_MSxA _T2SC0.Bits.MS0A #define T2SC0_MSxB _T2SC0.Bits.MS0B #define T2SC0_CHxIE _T2SC0.Bits.CH0IE #define T2SC0_CHxF _T2SC0.Bits.CH0F #define T2SC1_CHxMAX _T2SC1.Bits.CH1MAX #define T2SC1_TOVx _T2SC1.Bits.TOV1 #define T2SC1_ELSxA _T2SC1.Bits.ELS1A #define T2SC1_ELSxB _T2SC1.Bits.ELS1B #define T2SC1_MSxA _T2SC1.Bits.MS1A #define T2SC1_CHxIE _T2SC1.Bits.CH1IE #define T2SC1_CHxF _T2SC1.Bits.CH1F /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* * Follows changes from the database 2.89.055 version */ #define ADSCR_CH0 ADSCR_ADCH0 #define ADSCR_CH0_MASK ADSCR_ADCH0_MASK #define ADSCR_CH1 ADSCR_ADCH1 #define ADSCR_CH1_MASK ADSCR_ADCH1_MASK #define ADSCR_CH2 ADSCR_ADCH2 #define ADSCR_CH2_MASK ADSCR_ADCH2_MASK #define ADSCR_CH3 ADSCR_ADCH3 #define ADSCR_CH3_MASK ADSCR_ADCH3_MASK #define ADSCR_CH4 ADSCR_ADCH4 #define ADSCR_CH4_MASK ADSCR_ADCH4_MASK #define ADSCR_CH ADSCR_ADCH #define ADSCR_CH_MASK ADSCR_ADCH_MASK #define ADSCR_CH_BITNUM ADSCR_ADCH_BITNUM /* **** 11.9.2009 12:42:40 */ #define T1CH_ARR This_symb_has_been_depreciated #define T2CH_ARR This_symb_has_been_depreciated #endif