/* Based on CPU DB MC68HC908BD48_44, version 2.87.126 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908bd48.h ** Processor : MC68HC908BD48IFB ** FileFormat: V2.30 ** DataSheet : MC68HC908BD48/D Rev. 2.1 August 1, 2005 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:07 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908BD48_H #define _MC68HC908BD48_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_ADC 11 #define VectorNumber_MMIIC 10 #define VectorNumber_Sync 9 #define VectorNumber_TIMOvr 8 #define VectorNumber_TIMCH1 7 #define VectorNumber_TIMCH0 6 #define VectorNumber_Int7 5 #define VectorNumber_DDC12AB 4 #define VectorNumber_USB 3 #define VectorNumber_IRQ 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_ADC 0x0000FFE8 #define INT_MMIIC 0x0000FFEA #define INT_Sync 0x0000FFEC #define INT_TIMOvr 0x0000FFEE #define INT_TIMCH1 0x0000FFF0 #define INT_TIMCH0 0x0000FFF2 #define Int7 0x0000FFF4 #define INT_DDC12AB 0x0000FFF6 #define INT_USB 0x0000FFF8 #define INT_IRQ 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte PTA6 :1; /* Port A Data Bit 6 */ byte PTA7 :1; /* Port A Data Bit 7 */ } Bits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_PTA6 _PTA.Bits.PTA6 #define PTA_PTA7 _PTA.Bits.PTA7 #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_PTA6_MASK 64 #define PTA_PTA7_MASK 128 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** PTC - Port C Data Register; 0x00000002 ***/ typedef union { byte Byte; struct { byte PTC0 :1; /* Port C Data Bit 0 */ byte PTC1 :1; /* Port C Data Bit 1 */ byte PTC2 :1; /* Port C Data Bit 2 */ byte PTC3 :1; /* Port C Data Bit 3 */ byte PTC4 :1; /* Port C Data Bit 4 */ byte PTC5 :1; /* Port C Data Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpPTC :6; byte :1; byte :1; } MergedBits; } PTCSTR; extern volatile PTCSTR _PTC @0x00000002; #define PTC _PTC.Byte #define PTC_PTC0 _PTC.Bits.PTC0 #define PTC_PTC1 _PTC.Bits.PTC1 #define PTC_PTC2 _PTC.Bits.PTC2 #define PTC_PTC3 _PTC.Bits.PTC3 #define PTC_PTC4 _PTC.Bits.PTC4 #define PTC_PTC5 _PTC.Bits.PTC5 #define PTC_PTC _PTC.MergedBits.grpPTC #define PTC_PTC0_MASK 1 #define PTC_PTC1_MASK 2 #define PTC_PTC2_MASK 4 #define PTC_PTC3_MASK 8 #define PTC_PTC4_MASK 16 #define PTC_PTC5_MASK 32 #define PTC_PTC_MASK 63 #define PTC_PTC_BITNUM 0 /*** PTD - Port D Data Register; 0x00000003 ***/ typedef union { byte Byte; struct { byte PTD0 :1; /* Port D Data Bit 0 */ byte PTD1 :1; /* Port D Data Bit 1 */ byte PTD2 :1; /* Port D Data Bit 2 */ byte PTD3 :1; /* Port D Data Bit 3 */ byte PTD4 :1; /* Port D Data Bit 4 */ byte PTD5 :1; /* Port D Data Bit 5 */ byte PTD6 :1; /* Port D Data Bit 6 */ byte :1; } Bits; struct { byte grpPTD :7; byte :1; } MergedBits; } PTDSTR; extern volatile PTDSTR _PTD @0x00000003; #define PTD _PTD.Byte #define PTD_PTD0 _PTD.Bits.PTD0 #define PTD_PTD1 _PTD.Bits.PTD1 #define PTD_PTD2 _PTD.Bits.PTD2 #define PTD_PTD3 _PTD.Bits.PTD3 #define PTD_PTD4 _PTD.Bits.PTD4 #define PTD_PTD5 _PTD.Bits.PTD5 #define PTD_PTD6 _PTD.Bits.PTD6 #define PTD_PTD _PTD.MergedBits.grpPTD #define PTD_PTD0_MASK 1 #define PTD_PTD1_MASK 2 #define PTD_PTD2_MASK 4 #define PTD_PTD3_MASK 8 #define PTD_PTD4_MASK 16 #define PTD_PTD5_MASK 32 #define PTD_PTD6_MASK 64 #define PTD_PTD_MASK 127 #define PTD_PTD_BITNUM 0 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte DDRA6 :1; /* Data Direction Register A Bit 6 */ byte DDRA7 :1; /* Data Direction Register A Bit 7 */ } Bits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA6 _DDRA.Bits.DDRA6 #define DDRA_DDRA7 _DDRA.Bits.DDRA7 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA6_MASK 64 #define DDRA_DDRA7_MASK 128 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** DDRC - Data Direction Register C; 0x00000006 ***/ typedef union { byte Byte; struct { byte DDRC0 :1; /* Data Direction Register C Bit 0 */ byte DDRC1 :1; /* Data Direction Register C Bit 1 */ byte DDRC2 :1; /* Data Direction Register C Bit 2 */ byte DDRC3 :1; /* Data Direction Register C Bit 3 */ byte DDRC4 :1; /* Data Direction Register C Bit 4 */ byte DDRC5 :1; /* Data Direction Register C Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpDDRC :6; byte :1; byte :1; } MergedBits; } DDRCSTR; extern volatile DDRCSTR _DDRC @0x00000006; #define DDRC _DDRC.Byte #define DDRC_DDRC0 _DDRC.Bits.DDRC0 #define DDRC_DDRC1 _DDRC.Bits.DDRC1 #define DDRC_DDRC2 _DDRC.Bits.DDRC2 #define DDRC_DDRC3 _DDRC.Bits.DDRC3 #define DDRC_DDRC4 _DDRC.Bits.DDRC4 #define DDRC_DDRC5 _DDRC.Bits.DDRC5 #define DDRC_DDRC _DDRC.MergedBits.grpDDRC #define DDRC_DDRC0_MASK 1 #define DDRC_DDRC1_MASK 2 #define DDRC_DDRC2_MASK 4 #define DDRC_DDRC3_MASK 8 #define DDRC_DDRC4_MASK 16 #define DDRC_DDRC5_MASK 32 #define DDRC_DDRC_MASK 63 #define DDRC_DDRC_BITNUM 0 /*** DDRD - Data Direction Register D; 0x00000007 ***/ typedef union { byte Byte; struct { byte DDRD0 :1; /* Data Direction Register D Bit 0 */ byte DDRD1 :1; /* Data Direction Register D Bit 1 */ byte DDRD2 :1; /* Data Direction Register D Bit 2 */ byte DDRD3 :1; /* Data Direction Register D Bit 3 */ byte DDRD4 :1; /* Data Direction Register D Bit 4 */ byte DDRD5 :1; /* Data Direction Register D Bit 5 */ byte DDRD6 :1; /* Data Direction Register D Bit 6 */ byte :1; } Bits; struct { byte grpDDRD :7; byte :1; } MergedBits; } DDRDSTR; extern volatile DDRDSTR _DDRD @0x00000007; #define DDRD _DDRD.Byte #define DDRD_DDRD0 _DDRD.Bits.DDRD0 #define DDRD_DDRD1 _DDRD.Bits.DDRD1 #define DDRD_DDRD2 _DDRD.Bits.DDRD2 #define DDRD_DDRD3 _DDRD.Bits.DDRD3 #define DDRD_DDRD4 _DDRD.Bits.DDRD4 #define DDRD_DDRD5 _DDRD.Bits.DDRD5 #define DDRD_DDRD6 _DDRD.Bits.DDRD6 #define DDRD_DDRD _DDRD.MergedBits.grpDDRD #define DDRD_DDRD0_MASK 1 #define DDRD_DDRD1_MASK 2 #define DDRD_DDRD2_MASK 4 #define DDRD_DDRD3_MASK 8 #define DDRD_DDRD4_MASK 16 #define DDRD_DDRD5_MASK 32 #define DDRD_DDRD6_MASK 64 #define DDRD_DDRD_MASK 127 #define DDRD_DDRD_BITNUM 0 /*** PTE - Port E Data Register; 0x00000008 ***/ typedef union { byte Byte; struct { byte PTE0 :1; /* Port E Data Bit 0 */ byte PTE1 :1; /* Port E Data Bit 1 */ byte PTE2 :1; /* Port E Data Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTE :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTESTR; extern volatile PTESTR _PTE @0x00000008; #define PTE _PTE.Byte #define PTE_PTE0 _PTE.Bits.PTE0 #define PTE_PTE1 _PTE.Bits.PTE1 #define PTE_PTE2 _PTE.Bits.PTE2 #define PTE_PTE _PTE.MergedBits.grpPTE #define PTE_PTE0_MASK 1 #define PTE_PTE1_MASK 2 #define PTE_PTE2_MASK 4 #define PTE_PTE_MASK 7 #define PTE_PTE_BITNUM 0 /*** DDRE - Data Direction Register E; 0x00000009 ***/ typedef union { byte Byte; struct { byte DDRE0 :1; /* Data Direction Register E Bit 0 */ byte DDRE1 :1; /* Data Direction Register E Bit 1 */ byte DDRE2 :1; /* Data Direction Register E Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRE :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DDRESTR; extern volatile DDRESTR _DDRE @0x00000009; #define DDRE _DDRE.Byte #define DDRE_DDRE0 _DDRE.Bits.DDRE0 #define DDRE_DDRE1 _DDRE.Bits.DDRE1 #define DDRE_DDRE2 _DDRE.Bits.DDRE2 #define DDRE_DDRE _DDRE.MergedBits.grpDDRE #define DDRE_DDRE0_MASK 1 #define DDRE_DDRE1_MASK 2 #define DDRE_DDRE2_MASK 4 #define DDRE_DDRE_MASK 7 #define DDRE_DDRE_BITNUM 0 /*** TSC - Timer Status & Control; 0x0000000A ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM Reset Bit */ byte TSTOP :1; /* TIM Stop Bit */ byte TOIE :1; /* TIM Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TSCSTR; extern volatile TSCSTR _TSC @0x0000000A; #define TSC _TSC.Byte #define TSC_PS0 _TSC.Bits.PS0 #define TSC_PS1 _TSC.Bits.PS1 #define TSC_PS2 _TSC.Bits.PS2 #define TSC_TRST _TSC.Bits.TRST #define TSC_TSTOP _TSC.Bits.TSTOP #define TSC_TOIE _TSC.Bits.TOIE #define TSC_TOF _TSC.Bits.TOF #define TSC_PS _TSC.MergedBits.grpPS #define TSC_PS0_MASK 1 #define TSC_PS1_MASK 2 #define TSC_PS2_MASK 4 #define TSC_TRST_MASK 16 #define TSC_TSTOP_MASK 32 #define TSC_TOIE_MASK 64 #define TSC_TOF_MASK 128 #define TSC_PS_MASK 7 #define TSC_PS_BITNUM 0 /*** TCNT - TIM Counter Register; 0x0000000C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCNTH - TIM Counter Register High; 0x0000000C ***/ union { byte Byte; } TCNTHSTR; #define TCNTH _TCNT.Overlap_STR.TCNTHSTR.Byte /*** TCNTL - TIM Counter Register; 0x0000000D ***/ union { byte Byte; } TCNTLSTR; #define TCNTL _TCNT.Overlap_STR.TCNTLSTR.Byte } Overlap_STR; } TCNTSTR; extern volatile TCNTSTR _TCNT @0x0000000C; #define TCNT _TCNT.Word /*** TMOD - TIM Counter Modulo Register; 0x0000000E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TMODH - TIM Counter Modulo Register; 0x0000000E ***/ union { byte Byte; } TMODHSTR; #define TMODH _TMOD.Overlap_STR.TMODHSTR.Byte /*** TMODL - TIM Counter Modulo Register; 0x0000000F ***/ union { byte Byte; } TMODLSTR; #define TMODL _TMOD.Overlap_STR.TMODLSTR.Byte } Overlap_STR; } TMODSTR; extern volatile TMODSTR _TMOD @0x0000000E; #define TMOD _TMOD.Word /*** TSC0 - TIM Channel 0 Status and Control Register; 0x00000010 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TSC0STR; extern volatile TSC0STR _TSC0 @0x00000010; #define TSC0 _TSC0.Byte #define TSC0_CH0MAX _TSC0.Bits.CH0MAX #define TSC0_TOV0 _TSC0.Bits.TOV0 #define TSC0_ELS0A _TSC0.Bits.ELS0A #define TSC0_ELS0B _TSC0.Bits.ELS0B #define TSC0_MS0A _TSC0.Bits.MS0A #define TSC0_MS0B _TSC0.Bits.MS0B #define TSC0_CH0IE _TSC0.Bits.CH0IE #define TSC0_CH0F _TSC0.Bits.CH0F #define TSC0_ELS0x _TSC0.MergedBits.grpELS0x #define TSC0_MS0x _TSC0.MergedBits.grpMS0x #define TSC0_CH0MAX_MASK 1 #define TSC0_TOV0_MASK 2 #define TSC0_ELS0A_MASK 4 #define TSC0_ELS0B_MASK 8 #define TSC0_MS0A_MASK 16 #define TSC0_MS0B_MASK 32 #define TSC0_CH0IE_MASK 64 #define TSC0_CH0F_MASK 128 #define TSC0_ELS0x_MASK 12 #define TSC0_ELS0x_BITNUM 2 #define TSC0_MS0x_MASK 48 #define TSC0_MS0x_BITNUM 4 /*** TCH0 - TIM Channel 0 Register; 0x00000011 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCH0H - TIM Channel 0 Register High; 0x00000011 ***/ union { byte Byte; } TCH0HSTR; #define TCH0H _TCH0.Overlap_STR.TCH0HSTR.Byte /*** TCH0L - TIM Channel 0 Register Low; 0x00000012 ***/ union { byte Byte; } TCH0LSTR; #define TCH0L _TCH0.Overlap_STR.TCH0LSTR.Byte } Overlap_STR; } TCH0STR; extern volatile TCH0STR _TCH0 @0x00000011; #define TCH0 _TCH0.Word /*** TSC1 - TIM Channel 1 Status and Control Register; 0x00000013 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } TSC1STR; extern volatile TSC1STR _TSC1 @0x00000013; #define TSC1 _TSC1.Byte #define TSC1_CH1MAX _TSC1.Bits.CH1MAX #define TSC1_TOV1 _TSC1.Bits.TOV1 #define TSC1_ELS1A _TSC1.Bits.ELS1A #define TSC1_ELS1B _TSC1.Bits.ELS1B #define TSC1_MS1A _TSC1.Bits.MS1A #define TSC1_CH1IE _TSC1.Bits.CH1IE #define TSC1_CH1F _TSC1.Bits.CH1F #define TSC1_ELS1x _TSC1.MergedBits.grpELS1x #define TSC1_CH1MAX_MASK 1 #define TSC1_TOV1_MASK 2 #define TSC1_ELS1A_MASK 4 #define TSC1_ELS1B_MASK 8 #define TSC1_MS1A_MASK 16 #define TSC1_CH1IE_MASK 64 #define TSC1_CH1F_MASK 128 #define TSC1_ELS1x_MASK 12 #define TSC1_ELS1x_BITNUM 2 /*** TCH1 - TIM Channel 1 Register; 0x00000014 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCH1H - TIM Channel 1 Register High; 0x00000014 ***/ union { byte Byte; } TCH1HSTR; #define TCH1H _TCH1.Overlap_STR.TCH1HSTR.Byte /*** TCH1L - TIM Channel 1 Register Low; 0x00000015 ***/ union { byte Byte; } TCH1LSTR; #define TCH1L _TCH1.Overlap_STR.TCH1LSTR.Byte } Overlap_STR; } TCH1STR; extern volatile TCH1STR _TCH1 @0x00000014; #define TCH1 _TCH1.Word /*** DMCR - DDC Master Control Register; 0x00000016 ***/ typedef union { byte Byte; struct { byte BR0 :1; /* Baud Rate Select Bit 0 */ byte BR1 :1; /* Baud Rate Select Bit 1 */ byte BR2 :1; /* Baud Rate Select Bit 2 */ byte MRW :1; /* Master Read/Write */ byte MAST :1; /* Master Control Bit */ byte BB :1; /* Bus Busy Flag */ byte NAKIF :1; /* No Acknowledge Interrupt Flag */ byte ALIF :1; /* DDC Arbitration Lost Interrupt Flag */ } Bits; struct { byte grpBR :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DMCRSTR; extern volatile DMCRSTR _DMCR @0x00000016; #define DMCR _DMCR.Byte #define DMCR_BR0 _DMCR.Bits.BR0 #define DMCR_BR1 _DMCR.Bits.BR1 #define DMCR_BR2 _DMCR.Bits.BR2 #define DMCR_MRW _DMCR.Bits.MRW #define DMCR_MAST _DMCR.Bits.MAST #define DMCR_BB _DMCR.Bits.BB #define DMCR_NAKIF _DMCR.Bits.NAKIF #define DMCR_ALIF _DMCR.Bits.ALIF #define DMCR_BR _DMCR.MergedBits.grpBR #define DMCR_BR0_MASK 1 #define DMCR_BR1_MASK 2 #define DMCR_BR2_MASK 4 #define DMCR_MRW_MASK 8 #define DMCR_MAST_MASK 16 #define DMCR_BB_MASK 32 #define DMCR_NAKIF_MASK 64 #define DMCR_ALIF_MASK 128 #define DMCR_BR_MASK 7 #define DMCR_BR_BITNUM 0 /*** DADR - DDC Address Register; 0x00000017 ***/ typedef union { byte Byte; struct { byte EXTAD :1; /* DDC Expanded Address */ byte DDAD1 :1; /* DDC Address Bit 1 */ byte DDAD2 :1; /* DDC Address Bit 2 */ byte DDAD3 :1; /* DDC Address Bit 3 */ byte DDAD4 :1; /* DDC Address Bit 4 */ byte DDAD5 :1; /* DDC Address Bit 5 */ byte DDAD6 :1; /* DDC Address Bit 6 */ byte DDAD7 :1; /* DDC Address Bit 7 */ } Bits; struct { byte :1; byte grpDDAD_1 :7; } MergedBits; } DADRSTR; extern volatile DADRSTR _DADR @0x00000017; #define DADR _DADR.Byte #define DADR_EXTAD _DADR.Bits.EXTAD #define DADR_DDAD1 _DADR.Bits.DDAD1 #define DADR_DDAD2 _DADR.Bits.DDAD2 #define DADR_DDAD3 _DADR.Bits.DDAD3 #define DADR_DDAD4 _DADR.Bits.DDAD4 #define DADR_DDAD5 _DADR.Bits.DDAD5 #define DADR_DDAD6 _DADR.Bits.DDAD6 #define DADR_DDAD7 _DADR.Bits.DDAD7 #define DADR_DDAD_1 _DADR.MergedBits.grpDDAD_1 #define DADR_DDAD DADR_DDAD_1 #define DADR_EXTAD_MASK 1 #define DADR_DDAD1_MASK 2 #define DADR_DDAD2_MASK 4 #define DADR_DDAD3_MASK 8 #define DADR_DDAD4_MASK 16 #define DADR_DDAD5_MASK 32 #define DADR_DDAD6_MASK 64 #define DADR_DDAD7_MASK 128 #define DADR_DDAD_1_MASK 254 #define DADR_DDAD_1_BITNUM 1 /*** DCR - DDC Control Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte :1; byte DDC1EN :1; /* DDC1 Protocol Enable */ byte SCLIEN :1; /* SCL Interrupt Enable */ byte TXAK :1; /* Transmit Acknowledge Enable */ byte :1; byte :1; byte DIEN :1; /* DDC Interrupt Enable */ byte DEN :1; /* DDC Enable */ } Bits; } DCRSTR; extern volatile DCRSTR _DCR @0x00000018; #define DCR _DCR.Byte #define DCR_DDC1EN _DCR.Bits.DDC1EN #define DCR_SCLIEN _DCR.Bits.SCLIEN #define DCR_TXAK _DCR.Bits.TXAK #define DCR_DIEN _DCR.Bits.DIEN #define DCR_DEN _DCR.Bits.DEN #define DCR_DDC1EN_MASK 2 #define DCR_SCLIEN_MASK 4 #define DCR_TXAK_MASK 8 #define DCR_DIEN_MASK 64 #define DCR_DEN_MASK 128 /*** DSR - DDC Status Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte RXBF :1; /* DDC Receive Buffer Full */ byte TXBE :1; /* DDC Transmit Buffer Empty */ byte SCLIF :1; /* SCL Interrupt Flag */ byte RXAK :1; /* DDC Receive Acknowledge */ byte SRW :1; /* DDC Slave Read/Write */ byte MATCH :1; /* DDC Address Match */ byte TXIF :1; /* DDC Transmit Interrupt Flag */ byte RXIF :1; /* DDC Receive Interrupt Flag */ } Bits; } DSRSTR; extern volatile DSRSTR _DSR @0x00000019; #define DSR _DSR.Byte #define DSR_RXBF _DSR.Bits.RXBF #define DSR_TXBE _DSR.Bits.TXBE #define DSR_SCLIF _DSR.Bits.SCLIF #define DSR_RXAK _DSR.Bits.RXAK #define DSR_SRW _DSR.Bits.SRW #define DSR_MATCH _DSR.Bits.MATCH #define DSR_TXIF _DSR.Bits.TXIF #define DSR_RXIF _DSR.Bits.RXIF #define DSR_RXBF_MASK 1 #define DSR_TXBE_MASK 2 #define DSR_SCLIF_MASK 4 #define DSR_RXAK_MASK 8 #define DSR_SRW_MASK 16 #define DSR_MATCH_MASK 32 #define DSR_TXIF_MASK 64 #define DSR_RXIF_MASK 128 /*** DDTR - DDC Data Transmit Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte DTD0 :1; /* DDC Data Transmit Bit 0 */ byte DTD1 :1; /* DDC Data Transmit Bit 1 */ byte DTD2 :1; /* DDC Data Transmit Bit 2 */ byte DTD3 :1; /* DDC Data Transmit Bit 3 */ byte DTD4 :1; /* DDC Data Transmit Bit 4 */ byte DTD5 :1; /* DDC Data Transmit Bit 5 */ byte DTD6 :1; /* DDC Data Transmit Bit 6 */ byte DTD7 :1; /* DDC Data Transmit Bit 7 */ } Bits; } DDTRSTR; extern volatile DDTRSTR _DDTR @0x0000001A; #define DDTR _DDTR.Byte #define DDTR_DTD0 _DDTR.Bits.DTD0 #define DDTR_DTD1 _DDTR.Bits.DTD1 #define DDTR_DTD2 _DDTR.Bits.DTD2 #define DDTR_DTD3 _DDTR.Bits.DTD3 #define DDTR_DTD4 _DDTR.Bits.DTD4 #define DDTR_DTD5 _DDTR.Bits.DTD5 #define DDTR_DTD6 _DDTR.Bits.DTD6 #define DDTR_DTD7 _DDTR.Bits.DTD7 #define DDTR_DTD0_MASK 1 #define DDTR_DTD1_MASK 2 #define DDTR_DTD2_MASK 4 #define DDTR_DTD3_MASK 8 #define DDTR_DTD4_MASK 16 #define DDTR_DTD5_MASK 32 #define DDTR_DTD6_MASK 64 #define DDTR_DTD7_MASK 128 /*** DDRR - DDC Data Receive Register; 0x0000001B ***/ typedef union { byte Byte; struct { byte DRD0 :1; /* DDC Data Receive Bit 0 */ byte DRD1 :1; /* DDC Data Receive Bit 1 */ byte DRD2 :1; /* DDC Data Receive Bit 2 */ byte DRD3 :1; /* DDC Data Receive Bit 3 */ byte DRD4 :1; /* DDC Data Receive Bit 4 */ byte DRD5 :1; /* DDC Data Receive Bit 5 */ byte DRD6 :1; /* DDC Data Receive Bit 6 */ byte DRD7 :1; /* DDC Data Receive Bit 7 */ } Bits; } DDRRSTR; extern volatile DDRRSTR _DDRR @0x0000001B; #define DDRR _DDRR.Byte #define DDRR_DRD0 _DDRR.Bits.DRD0 #define DDRR_DRD1 _DDRR.Bits.DRD1 #define DDRR_DRD2 _DDRR.Bits.DRD2 #define DDRR_DRD3 _DDRR.Bits.DRD3 #define DDRR_DRD4 _DDRR.Bits.DRD4 #define DDRR_DRD5 _DDRR.Bits.DRD5 #define DDRR_DRD6 _DDRR.Bits.DRD6 #define DDRR_DRD7 _DDRR.Bits.DRD7 #define DDRR_DRD0_MASK 1 #define DDRR_DRD1_MASK 2 #define DDRR_DRD2_MASK 4 #define DDRR_DRD3_MASK 8 #define DDRR_DRD4_MASK 16 #define DDRR_DRD5_MASK 32 #define DDRR_DRD6_MASK 64 #define DDRR_DRD7_MASK 128 /*** D2ADR - DDC2 Address Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte :1; byte D2AD1 :1; /* DDC2 Address Bit 1 */ byte D2AD2 :1; /* DDC2 Address Bit 2 */ byte D2AD3 :1; /* DDC2 Address Bit 3 */ byte D2AD4 :1; /* DDC2 Address Bit 4 */ byte D2AD5 :1; /* DDC2 Address Bit 5 */ byte D2AD6 :1; /* DDC2 Address Bit 6 */ byte D2AD7 :1; /* DDC2 Address Bit 7 */ } Bits; struct { byte :1; byte grpD2AD_1 :7; } MergedBits; } D2ADRSTR; extern volatile D2ADRSTR _D2ADR @0x0000001C; #define D2ADR _D2ADR.Byte #define D2ADR_D2AD1 _D2ADR.Bits.D2AD1 #define D2ADR_D2AD2 _D2ADR.Bits.D2AD2 #define D2ADR_D2AD3 _D2ADR.Bits.D2AD3 #define D2ADR_D2AD4 _D2ADR.Bits.D2AD4 #define D2ADR_D2AD5 _D2ADR.Bits.D2AD5 #define D2ADR_D2AD6 _D2ADR.Bits.D2AD6 #define D2ADR_D2AD7 _D2ADR.Bits.D2AD7 #define D2ADR_D2AD_1 _D2ADR.MergedBits.grpD2AD_1 #define D2ADR_D2AD D2ADR_D2AD_1 #define D2ADR_D2AD1_MASK 2 #define D2ADR_D2AD2_MASK 4 #define D2ADR_D2AD3_MASK 8 #define D2ADR_D2AD4_MASK 16 #define D2ADR_D2AD5_MASK 32 #define D2ADR_D2AD6_MASK 64 #define D2ADR_D2AD7_MASK 128 #define D2ADR_D2AD_1_MASK 254 #define D2ADR_D2AD_1_BITNUM 1 /*** CONFIG0 - Configuration Register 0; 0x0000001D ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte SOGE :1; /* SOG Enable */ byte VSYNCOE :1; /* VSYNCO Enable */ byte HSYNCOE :1; /* HSYNCO Enable */ } Bits; } CONFIG0STR; extern volatile CONFIG0STR _CONFIG0 @0x0000001D; #define CONFIG0 _CONFIG0.Byte #define CONFIG0_SOGE _CONFIG0.Bits.SOGE #define CONFIG0_VSYNCOE _CONFIG0.Bits.VSYNCOE #define CONFIG0_HSYNCOE _CONFIG0.Bits.HSYNCOE #define CONFIG0_SOGE_MASK 32 #define CONFIG0_VSYNCOE_MASK 64 #define CONFIG0_HSYNCOE_MASK 128 /*** INTSCR - IRQ Status and Control Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte MODE :1; /* IRQ Edge/Level Select Bit */ byte IMASK :1; /* IRQ Interrupt Mask Bit */ byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */ byte IRQF :1; /* IRQ Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } INTSCRSTR; extern volatile INTSCRSTR _INTSCR @0x0000001E; #define INTSCR _INTSCR.Byte #define INTSCR_MODE _INTSCR.Bits.MODE #define INTSCR_IMASK _INTSCR.Bits.IMASK #define INTSCR_ACK _INTSCR.Bits.ACK #define INTSCR_IRQF _INTSCR.Bits.IRQF #define INTSCR_MODE_MASK 1 #define INTSCR_IMASK_MASK 2 #define INTSCR_ACK_MASK 4 #define INTSCR_IRQF_MASK 8 /*** CONFIG1 - Configuration Register 1; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* Stop Instruction Enable Bit */ byte COPRS :1; /* COP Rate Select Bit */ byte SSREC :1; /* Short Stop Recovery Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_COPRS _CONFIG1.Bits.COPRS #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_COPRS_MASK 4 #define CONFIG1_SSREC_MASK 8 /*** PWM0 - PWM0 Data Register; 0x00000020 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM0STR; extern volatile PWM0STR _PWM0 @0x00000020; #define PWM0 _PWM0.Byte #define PWM0_BRM0 _PWM0.Bits.BRM0 #define PWM0_BRM1 _PWM0.Bits.BRM1 #define PWM0_BRM2 _PWM0.Bits.BRM2 #define PWM0_PWM_0 _PWM0.Bits.PWM_0 #define PWM0_PWM_1 _PWM0.Bits.PWM_1 #define PWM0_PWM_2 _PWM0.Bits.PWM_2 #define PWM0_PWM_3 _PWM0.Bits.PWM_3 #define PWM0_PWM_4 _PWM0.Bits.PWM_4 /* PWM_ARR: Access 8 PWMx registers in an array */ #define PWM_ARR ((volatile byte * __far) &PWM0) #define PWM0_BRM _PWM0.MergedBits.grpBRM #define PWM0_PWM _PWM0.MergedBits.grpPWM #define PWM0_BRM0_MASK 1 #define PWM0_BRM1_MASK 2 #define PWM0_BRM2_MASK 4 #define PWM0_PWM_0_MASK 8 #define PWM0_PWM_1_MASK 16 #define PWM0_PWM_2_MASK 32 #define PWM0_PWM_3_MASK 64 #define PWM0_PWM_4_MASK 128 #define PWM0_BRM_MASK 7 #define PWM0_BRM_BITNUM 0 #define PWM0_PWM_MASK 248 #define PWM0_PWM_BITNUM 3 /*** PWM1 - PWM1 Data Register; 0x00000021 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM1STR; extern volatile PWM1STR _PWM1 @0x00000021; #define PWM1 _PWM1.Byte #define PWM1_BRM0 _PWM1.Bits.BRM0 #define PWM1_BRM1 _PWM1.Bits.BRM1 #define PWM1_BRM2 _PWM1.Bits.BRM2 #define PWM1_PWM_0 _PWM1.Bits.PWM_0 #define PWM1_PWM_1 _PWM1.Bits.PWM_1 #define PWM1_PWM_2 _PWM1.Bits.PWM_2 #define PWM1_PWM_3 _PWM1.Bits.PWM_3 #define PWM1_PWM_4 _PWM1.Bits.PWM_4 #define PWM1_BRM _PWM1.MergedBits.grpBRM #define PWM1_PWM _PWM1.MergedBits.grpPWM #define PWM1_BRM0_MASK 1 #define PWM1_BRM1_MASK 2 #define PWM1_BRM2_MASK 4 #define PWM1_PWM_0_MASK 8 #define PWM1_PWM_1_MASK 16 #define PWM1_PWM_2_MASK 32 #define PWM1_PWM_3_MASK 64 #define PWM1_PWM_4_MASK 128 #define PWM1_BRM_MASK 7 #define PWM1_BRM_BITNUM 0 #define PWM1_PWM_MASK 248 #define PWM1_PWM_BITNUM 3 /*** PWM2 - PWM2 Data Register; 0x00000022 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM2STR; extern volatile PWM2STR _PWM2 @0x00000022; #define PWM2 _PWM2.Byte #define PWM2_BRM0 _PWM2.Bits.BRM0 #define PWM2_BRM1 _PWM2.Bits.BRM1 #define PWM2_BRM2 _PWM2.Bits.BRM2 #define PWM2_PWM_0 _PWM2.Bits.PWM_0 #define PWM2_PWM_1 _PWM2.Bits.PWM_1 #define PWM2_PWM_2 _PWM2.Bits.PWM_2 #define PWM2_PWM_3 _PWM2.Bits.PWM_3 #define PWM2_PWM_4 _PWM2.Bits.PWM_4 #define PWM2_BRM _PWM2.MergedBits.grpBRM #define PWM2_PWM _PWM2.MergedBits.grpPWM #define PWM2_BRM0_MASK 1 #define PWM2_BRM1_MASK 2 #define PWM2_BRM2_MASK 4 #define PWM2_PWM_0_MASK 8 #define PWM2_PWM_1_MASK 16 #define PWM2_PWM_2_MASK 32 #define PWM2_PWM_3_MASK 64 #define PWM2_PWM_4_MASK 128 #define PWM2_BRM_MASK 7 #define PWM2_BRM_BITNUM 0 #define PWM2_PWM_MASK 248 #define PWM2_PWM_BITNUM 3 /*** PWM3 - PWM3 Data Register; 0x00000023 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM3STR; extern volatile PWM3STR _PWM3 @0x00000023; #define PWM3 _PWM3.Byte #define PWM3_BRM0 _PWM3.Bits.BRM0 #define PWM3_BRM1 _PWM3.Bits.BRM1 #define PWM3_BRM2 _PWM3.Bits.BRM2 #define PWM3_PWM_0 _PWM3.Bits.PWM_0 #define PWM3_PWM_1 _PWM3.Bits.PWM_1 #define PWM3_PWM_2 _PWM3.Bits.PWM_2 #define PWM3_PWM_3 _PWM3.Bits.PWM_3 #define PWM3_PWM_4 _PWM3.Bits.PWM_4 #define PWM3_BRM _PWM3.MergedBits.grpBRM #define PWM3_PWM _PWM3.MergedBits.grpPWM #define PWM3_BRM0_MASK 1 #define PWM3_BRM1_MASK 2 #define PWM3_BRM2_MASK 4 #define PWM3_PWM_0_MASK 8 #define PWM3_PWM_1_MASK 16 #define PWM3_PWM_2_MASK 32 #define PWM3_PWM_3_MASK 64 #define PWM3_PWM_4_MASK 128 #define PWM3_BRM_MASK 7 #define PWM3_BRM_BITNUM 0 #define PWM3_PWM_MASK 248 #define PWM3_PWM_BITNUM 3 /*** PWM4 - PWM4 Data Register; 0x00000024 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM4STR; extern volatile PWM4STR _PWM4 @0x00000024; #define PWM4 _PWM4.Byte #define PWM4_BRM0 _PWM4.Bits.BRM0 #define PWM4_BRM1 _PWM4.Bits.BRM1 #define PWM4_BRM2 _PWM4.Bits.BRM2 #define PWM4_PWM_0 _PWM4.Bits.PWM_0 #define PWM4_PWM_1 _PWM4.Bits.PWM_1 #define PWM4_PWM_2 _PWM4.Bits.PWM_2 #define PWM4_PWM_3 _PWM4.Bits.PWM_3 #define PWM4_PWM_4 _PWM4.Bits.PWM_4 #define PWM4_BRM _PWM4.MergedBits.grpBRM #define PWM4_PWM _PWM4.MergedBits.grpPWM #define PWM4_BRM0_MASK 1 #define PWM4_BRM1_MASK 2 #define PWM4_BRM2_MASK 4 #define PWM4_PWM_0_MASK 8 #define PWM4_PWM_1_MASK 16 #define PWM4_PWM_2_MASK 32 #define PWM4_PWM_3_MASK 64 #define PWM4_PWM_4_MASK 128 #define PWM4_BRM_MASK 7 #define PWM4_BRM_BITNUM 0 #define PWM4_PWM_MASK 248 #define PWM4_PWM_BITNUM 3 /*** PWM5 - PWM5 Data Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM5STR; extern volatile PWM5STR _PWM5 @0x00000025; #define PWM5 _PWM5.Byte #define PWM5_BRM0 _PWM5.Bits.BRM0 #define PWM5_BRM1 _PWM5.Bits.BRM1 #define PWM5_BRM2 _PWM5.Bits.BRM2 #define PWM5_PWM_0 _PWM5.Bits.PWM_0 #define PWM5_PWM_1 _PWM5.Bits.PWM_1 #define PWM5_PWM_2 _PWM5.Bits.PWM_2 #define PWM5_PWM_3 _PWM5.Bits.PWM_3 #define PWM5_PWM_4 _PWM5.Bits.PWM_4 #define PWM5_BRM _PWM5.MergedBits.grpBRM #define PWM5_PWM _PWM5.MergedBits.grpPWM #define PWM5_BRM0_MASK 1 #define PWM5_BRM1_MASK 2 #define PWM5_BRM2_MASK 4 #define PWM5_PWM_0_MASK 8 #define PWM5_PWM_1_MASK 16 #define PWM5_PWM_2_MASK 32 #define PWM5_PWM_3_MASK 64 #define PWM5_PWM_4_MASK 128 #define PWM5_BRM_MASK 7 #define PWM5_BRM_BITNUM 0 #define PWM5_PWM_MASK 248 #define PWM5_PWM_BITNUM 3 /*** PWM6 - PWM6 Data Register; 0x00000026 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM6STR; extern volatile PWM6STR _PWM6 @0x00000026; #define PWM6 _PWM6.Byte #define PWM6_BRM0 _PWM6.Bits.BRM0 #define PWM6_BRM1 _PWM6.Bits.BRM1 #define PWM6_BRM2 _PWM6.Bits.BRM2 #define PWM6_PWM_0 _PWM6.Bits.PWM_0 #define PWM6_PWM_1 _PWM6.Bits.PWM_1 #define PWM6_PWM_2 _PWM6.Bits.PWM_2 #define PWM6_PWM_3 _PWM6.Bits.PWM_3 #define PWM6_PWM_4 _PWM6.Bits.PWM_4 #define PWM6_BRM _PWM6.MergedBits.grpBRM #define PWM6_PWM _PWM6.MergedBits.grpPWM #define PWM6_BRM0_MASK 1 #define PWM6_BRM1_MASK 2 #define PWM6_BRM2_MASK 4 #define PWM6_PWM_0_MASK 8 #define PWM6_PWM_1_MASK 16 #define PWM6_PWM_2_MASK 32 #define PWM6_PWM_3_MASK 64 #define PWM6_PWM_4_MASK 128 #define PWM6_BRM_MASK 7 #define PWM6_BRM_BITNUM 0 #define PWM6_PWM_MASK 248 #define PWM6_PWM_BITNUM 3 /*** PWM7 - PWM7 Data Register; 0x00000027 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM7STR; extern volatile PWM7STR _PWM7 @0x00000027; #define PWM7 _PWM7.Byte #define PWM7_BRM0 _PWM7.Bits.BRM0 #define PWM7_BRM1 _PWM7.Bits.BRM1 #define PWM7_BRM2 _PWM7.Bits.BRM2 #define PWM7_PWM_0 _PWM7.Bits.PWM_0 #define PWM7_PWM_1 _PWM7.Bits.PWM_1 #define PWM7_PWM_2 _PWM7.Bits.PWM_2 #define PWM7_PWM_3 _PWM7.Bits.PWM_3 #define PWM7_PWM_4 _PWM7.Bits.PWM_4 #define PWM7_BRM _PWM7.MergedBits.grpBRM #define PWM7_PWM _PWM7.MergedBits.grpPWM #define PWM7_BRM0_MASK 1 #define PWM7_BRM1_MASK 2 #define PWM7_BRM2_MASK 4 #define PWM7_PWM_0_MASK 8 #define PWM7_PWM_1_MASK 16 #define PWM7_PWM_2_MASK 32 #define PWM7_PWM_3_MASK 64 #define PWM7_PWM_4_MASK 128 #define PWM7_BRM_MASK 7 #define PWM7_BRM_BITNUM 0 #define PWM7_PWM_MASK 248 #define PWM7_PWM_BITNUM 3 /*** PWMCR1 - PWM Control Register 1; 0x00000028 ***/ typedef union { byte Byte; struct { byte PWM0E :1; /* PWM Output 0 Enable */ byte PWM1E :1; /* PWM Output 1 Enable */ byte PWM2E :1; /* PWM Output 2 Enable */ byte PWM3E :1; /* PWM Output 3 Enable */ byte PWM4E :1; /* PWM Output 4 Enable */ byte PWM5E :1; /* PWM Output 5 Enable */ byte PWM6E :1; /* PWM Output 6 Enable */ byte PWM7E :1; /* PWM Output 7 Enable */ } Bits; } PWMCR1STR; extern volatile PWMCR1STR _PWMCR1 @0x00000028; #define PWMCR1 _PWMCR1.Byte #define PWMCR1_PWM0E _PWMCR1.Bits.PWM0E #define PWMCR1_PWM1E _PWMCR1.Bits.PWM1E #define PWMCR1_PWM2E _PWMCR1.Bits.PWM2E #define PWMCR1_PWM3E _PWMCR1.Bits.PWM3E #define PWMCR1_PWM4E _PWMCR1.Bits.PWM4E #define PWMCR1_PWM5E _PWMCR1.Bits.PWM5E #define PWMCR1_PWM6E _PWMCR1.Bits.PWM6E #define PWMCR1_PWM7E _PWMCR1.Bits.PWM7E #define PWMCR1_PWM0E_MASK 1 #define PWMCR1_PWM1E_MASK 2 #define PWMCR1_PWM2E_MASK 4 #define PWMCR1_PWM3E_MASK 8 #define PWMCR1_PWM4E_MASK 16 #define PWMCR1_PWM5E_MASK 32 #define PWMCR1_PWM6E_MASK 64 #define PWMCR1_PWM7E_MASK 128 /*** UADR - USB Address Register; 0x00000029 ***/ typedef union { byte Byte; struct { byte UADD0 :1; /* USB Address Bit 0 */ byte UADD1 :1; /* USB Address Bit 1 */ byte UADD2 :1; /* USB Address Bit 2 */ byte UADD3 :1; /* USB Address Bit 3 */ byte UADD4 :1; /* USB Address Bit 4 */ byte UADD5 :1; /* USB Address Bit 5 */ byte UADD6 :1; /* USB Address Bit 6 */ byte USBEN :1; /* USB Enable */ } Bits; struct { byte grpUADD :7; byte :1; } MergedBits; } UADRSTR; extern volatile UADRSTR _UADR @0x00000029; #define UADR _UADR.Byte #define UADR_UADD0 _UADR.Bits.UADD0 #define UADR_UADD1 _UADR.Bits.UADD1 #define UADR_UADD2 _UADR.Bits.UADD2 #define UADR_UADD3 _UADR.Bits.UADD3 #define UADR_UADD4 _UADR.Bits.UADD4 #define UADR_UADD5 _UADR.Bits.UADD5 #define UADR_UADD6 _UADR.Bits.UADD6 #define UADR_USBEN _UADR.Bits.USBEN #define UADR_UADD _UADR.MergedBits.grpUADD #define UADR_UADD0_MASK 1 #define UADR_UADD1_MASK 2 #define UADR_UADD2_MASK 4 #define UADR_UADD3_MASK 8 #define UADR_UADD4_MASK 16 #define UADR_UADD5_MASK 32 #define UADR_UADD6_MASK 64 #define UADR_USBEN_MASK 128 #define UADR_UADD_MASK 127 #define UADR_UADD_BITNUM 0 /*** UINTR - USB Interrupt Register; 0x0000002A ***/ typedef union { byte Byte; struct { byte RSTIE :1; /* Reset Interrupt Enable */ byte EOPIE :1; /* End Of Packet Interrupt Enable */ byte RBIE :1; /* Receive Buffer Interrupt Enable */ byte TBIE :1; /* Transmit Buffer Interrupt Enable */ byte RSTIF :1; /* Reset Interrupt Flag */ byte EOPIF :1; /* End Of Packet Interrupt Flag */ byte RBIFF :1; /* Receive Buffer Full Flag */ byte TBEF :1; /* Transmit Buffer Empty Flag */ } Bits; } UINTRSTR; extern volatile UINTRSTR _UINTR @0x0000002A; #define UINTR _UINTR.Byte #define UINTR_RSTIE _UINTR.Bits.RSTIE #define UINTR_EOPIE _UINTR.Bits.EOPIE #define UINTR_RBIE _UINTR.Bits.RBIE #define UINTR_TBIE _UINTR.Bits.TBIE #define UINTR_RSTIF _UINTR.Bits.RSTIF #define UINTR_EOPIF _UINTR.Bits.EOPIF #define UINTR_RBIFF _UINTR.Bits.RBIFF #define UINTR_TBEF _UINTR.Bits.TBEF #define UINTR_RSTIE_MASK 1 #define UINTR_EOPIE_MASK 2 #define UINTR_RBIE_MASK 4 #define UINTR_TBIE_MASK 8 #define UINTR_RSTIF_MASK 16 #define UINTR_EOPIF_MASK 32 #define UINTR_RBIFF_MASK 64 #define UINTR_TBEF_MASK 128 /*** UCR0 - USB Control Register 0; 0x0000002B ***/ typedef union { byte Byte; struct { byte TP0SIZ0 :1; /* Endpoint 0 Transmit Data Size Bit 0 */ byte TP0SIZ1 :1; /* Endpoint 0 Transmit Data Size Bit 1 */ byte TP0SIZ2 :1; /* Endpoint 0 Transmit Data Size Bit 2 */ byte TP0SIZ3 :1; /* Endpoint 0 Transmit Data Size Bit 3 */ byte RX0E :1; /* Endpoint 0 Receive Enable */ byte TX0E :1; /* Endpoint 0 Transmit Enable */ byte STALL0 :1; /* Endpoint 0 STALL Handshake */ byte T0SEQ :1; /* Endpoint 0 Data Packet PID Select */ } Bits; struct { byte grpTP0SIZ :4; byte :1; byte :1; byte grpSTALL :1; byte :1; } MergedBits; } UCR0STR; extern volatile UCR0STR _UCR0 @0x0000002B; #define UCR0 _UCR0.Byte #define UCR0_TP0SIZ0 _UCR0.Bits.TP0SIZ0 #define UCR0_TP0SIZ1 _UCR0.Bits.TP0SIZ1 #define UCR0_TP0SIZ2 _UCR0.Bits.TP0SIZ2 #define UCR0_TP0SIZ3 _UCR0.Bits.TP0SIZ3 #define UCR0_RX0E _UCR0.Bits.RX0E #define UCR0_TX0E _UCR0.Bits.TX0E #define UCR0_STALL0 _UCR0.Bits.STALL0 #define UCR0_T0SEQ _UCR0.Bits.T0SEQ #define UCR0_TP0SIZ _UCR0.MergedBits.grpTP0SIZ #define UCR0_TP0SIZ0_MASK 1 #define UCR0_TP0SIZ1_MASK 2 #define UCR0_TP0SIZ2_MASK 4 #define UCR0_TP0SIZ3_MASK 8 #define UCR0_RX0E_MASK 16 #define UCR0_TX0E_MASK 32 #define UCR0_STALL0_MASK 64 #define UCR0_T0SEQ_MASK 128 #define UCR0_TP0SIZ_MASK 15 #define UCR0_TP0SIZ_BITNUM 0 /*** USR - USB Status Register; 0x0000002C ***/ typedef union { byte Byte; struct { byte RPSIZ0 :1; /* Received Data Size Bit 0 */ byte RPSIZ1 :1; /* Received Data Size Bit 1 */ byte RPSIZ2 :1; /* Received Data Size Bit 2 */ byte RPSIZ3 :1; /* Received Data Size Bit 3 */ byte :1; byte TX1ST :1; /* Transmit First Flag */ byte SETUP :1; /* SETUP Token */ byte RSEQ :1; /* Received Data Sequence */ } Bits; struct { byte grpRPSIZ :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } USRSTR; extern volatile USRSTR _USR @0x0000002C; #define USR _USR.Byte #define USR_RPSIZ0 _USR.Bits.RPSIZ0 #define USR_RPSIZ1 _USR.Bits.RPSIZ1 #define USR_RPSIZ2 _USR.Bits.RPSIZ2 #define USR_RPSIZ3 _USR.Bits.RPSIZ3 #define USR_TX1ST _USR.Bits.TX1ST #define USR_SETUP _USR.Bits.SETUP #define USR_RSEQ _USR.Bits.RSEQ #define USR_RPSIZ _USR.MergedBits.grpRPSIZ #define USR_RPSIZ0_MASK 1 #define USR_RPSIZ1_MASK 2 #define USR_RPSIZ2_MASK 4 #define USR_RPSIZ3_MASK 8 #define USR_TX1ST_MASK 32 #define USR_SETUP_MASK 64 #define USR_RSEQ_MASK 128 #define USR_RPSIZ_MASK 15 #define USR_RPSIZ_BITNUM 0 /*** UCR2 - USB Control Register 2; 0x0000002D ***/ typedef union { byte Byte; struct { byte STALL1 :1; /* Endpoint 1 STALL Handshake */ byte STALL2 :1; /* Endpoint 2 STALL Handshake */ byte ENABLE1 :1; /* Endpoint 1 Enable */ byte ENABLE2 :1; /* Endpoint 2 Enable */ byte SUSPND :1; /* USB Suspend */ byte PULLEN :1; /* Pullup Enable on D- */ byte TX1STR :1; /* TX1ST Clear */ byte RSTIFR :1; /* Reset Interrupt Flag Clear */ } Bits; struct { byte grpSTALL_1 :2; byte grpENABLE_1 :2; byte :1; byte :1; byte :1; byte :1; } MergedBits; } UCR2STR; extern volatile UCR2STR _UCR2 @0x0000002D; #define UCR2 _UCR2.Byte #define UCR2_STALL1 _UCR2.Bits.STALL1 #define UCR2_STALL2 _UCR2.Bits.STALL2 #define UCR2_ENABLE1 _UCR2.Bits.ENABLE1 #define UCR2_ENABLE2 _UCR2.Bits.ENABLE2 #define UCR2_SUSPND _UCR2.Bits.SUSPND #define UCR2_PULLEN _UCR2.Bits.PULLEN #define UCR2_TX1STR _UCR2.Bits.TX1STR #define UCR2_RSTIFR _UCR2.Bits.RSTIFR #define UCR2_STALL_1 _UCR2.MergedBits.grpSTALL_1 #define UCR2_ENABLE_1 _UCR2.MergedBits.grpENABLE_1 #define UCR2_STALL UCR2_STALL_1 #define UCR2_ENABLE UCR2_ENABLE_1 #define UCR2_STALL1_MASK 1 #define UCR2_STALL2_MASK 2 #define UCR2_ENABLE1_MASK 4 #define UCR2_ENABLE2_MASK 8 #define UCR2_SUSPND_MASK 16 #define UCR2_PULLEN_MASK 32 #define UCR2_TX1STR_MASK 64 #define UCR2_RSTIFR_MASK 128 #define UCR2_STALL_1_MASK 3 #define UCR2_STALL_1_BITNUM 0 #define UCR2_ENABLE_1_MASK 12 #define UCR2_ENABLE_1_BITNUM 2 /*** UIR1 - USB Interrupt Register 1; 0x0000002E ***/ typedef union { byte Byte; struct { byte EOPFR :1; /* End Of Packet Interrupt Flag Clear */ byte TXD1FR :1; /* Endpoint 1 and 2 Data Buffer Transmit Flag Clear */ byte RBFFR :1; /* Receive Buffer Full Flag Clear */ byte TBEFR :1; /* Transmit Buffer Empty Flag Clear */ byte RESUMFR :1; /* Resume Flag Clear */ byte RESUMF :1; /* Resume Flag */ byte TXD1IE :1; /* Transmit Buffer Interrupt Enable */ byte TXD1F :1; /* Endpoint 1/2 Data Buffer Transmit Flag */ } Bits; } UIR1STR; extern volatile UIR1STR _UIR1 @0x0000002E; #define UIR1 _UIR1.Byte #define UIR1_EOPFR _UIR1.Bits.EOPFR #define UIR1_TXD1FR _UIR1.Bits.TXD1FR #define UIR1_RBFFR _UIR1.Bits.RBFFR #define UIR1_TBEFR _UIR1.Bits.TBEFR #define UIR1_RESUMFR _UIR1.Bits.RESUMFR #define UIR1_RESUMF _UIR1.Bits.RESUMF #define UIR1_TXD1IE _UIR1.Bits.TXD1IE #define UIR1_TXD1F _UIR1.Bits.TXD1F #define UIR1_EOPFR_MASK 1 #define UIR1_TXD1FR_MASK 2 #define UIR1_RBFFR_MASK 4 #define UIR1_TBEFR_MASK 8 #define UIR1_RESUMFR_MASK 16 #define UIR1_RESUMF_MASK 32 #define UIR1_TXD1IE_MASK 64 #define UIR1_TXD1F_MASK 128 /*** UCR1 - USB Control Register 1; 0x0000002F ***/ typedef union { byte Byte; struct { byte TP1SIZ0 :1; /* Endpoint 1/2 Transmit Data Size Bit 0 */ byte TP1SIZ1 :1; /* Endpoint 1/2 Transmit Data Size Bit 1 */ byte TP1SIZ2 :1; /* Endpoint 1/2 Transmit Data Size Bit 2 */ byte TP1SIZ3 :1; /* Endpoint 1/2 Transmit Data Size Bit 3 */ byte FRESUM :1; /* Force Resume */ byte TX1E :1; /* Endpoint 1/2 Transmit Enable */ byte ENDADD :1; /* Endpoint Address Select */ byte T1SEQ :1; /* Endpoint 1/2 Data Packet PID Select */ } Bits; struct { byte grpTP1SIZ :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } UCR1STR; extern volatile UCR1STR _UCR1 @0x0000002F; #define UCR1 _UCR1.Byte #define UCR1_TP1SIZ0 _UCR1.Bits.TP1SIZ0 #define UCR1_TP1SIZ1 _UCR1.Bits.TP1SIZ1 #define UCR1_TP1SIZ2 _UCR1.Bits.TP1SIZ2 #define UCR1_TP1SIZ3 _UCR1.Bits.TP1SIZ3 #define UCR1_FRESUM _UCR1.Bits.FRESUM #define UCR1_TX1E _UCR1.Bits.TX1E #define UCR1_ENDADD _UCR1.Bits.ENDADD #define UCR1_T1SEQ _UCR1.Bits.T1SEQ #define UCR1_TP1SIZ _UCR1.MergedBits.grpTP1SIZ #define UCR1_TP1SIZ0_MASK 1 #define UCR1_TP1SIZ1_MASK 2 #define UCR1_TP1SIZ2_MASK 4 #define UCR1_TP1SIZ3_MASK 8 #define UCR1_FRESUM_MASK 16 #define UCR1_TX1E_MASK 32 #define UCR1_ENDADD_MASK 64 #define UCR1_T1SEQ_MASK 128 #define UCR1_TP1SIZ_MASK 15 #define UCR1_TP1SIZ_BITNUM 0 /*** UD0R0 - USB Endpoint 0 Data Register 0; 0x00000030 ***/ typedef union { byte Byte; struct { byte UE0RD00_UE0TD00 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 0, Endpoint 0 Transmit Data Buffer 0 Bit 0 */ byte UE0RD01_UE0TD01 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 1, Endpoint 0 Transmit Data Buffer 0 Bit 1 */ byte UE0RD02_UE0TD02 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 2, Endpoint 0 Transmit Data Buffer 0 Bit 2 */ byte UE0RD03_UE0TD03 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 3, Endpoint 0 Transmit Data Buffer 0 Bit 3 */ byte UE0RD04_UE0TD04 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 4, Endpoint 0 Transmit Data Buffer 0 Bit 4 */ byte UE0RD05_UE0TD05 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 5, Endpoint 0 Transmit Data Buffer 0 Bit 5 */ byte UE0RD06_UE0TD06 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 6, Endpoint 0 Transmit Data Buffer 0 Bit 6 */ byte UE0RD07_UE0TD07 :1; /* Endpoint 0 Receive Data Buffer 0 Bit 7, Endpoint 0 Transmit Data Buffer 0 Bit 7 */ } Bits; } UD0R0STR; extern volatile UD0R0STR _UD0R0 @0x00000030; #define UD0R0 _UD0R0.Byte #define UD0R0_UE0RD00_UE0TD00 _UD0R0.Bits.UE0RD00_UE0TD00 #define UD0R0_UE0RD01_UE0TD01 _UD0R0.Bits.UE0RD01_UE0TD01 #define UD0R0_UE0RD02_UE0TD02 _UD0R0.Bits.UE0RD02_UE0TD02 #define UD0R0_UE0RD03_UE0TD03 _UD0R0.Bits.UE0RD03_UE0TD03 #define UD0R0_UE0RD04_UE0TD04 _UD0R0.Bits.UE0RD04_UE0TD04 #define UD0R0_UE0RD05_UE0TD05 _UD0R0.Bits.UE0RD05_UE0TD05 #define UD0R0_UE0RD06_UE0TD06 _UD0R0.Bits.UE0RD06_UE0TD06 #define UD0R0_UE0RD07_UE0TD07 _UD0R0.Bits.UE0RD07_UE0TD07 /* UD0R_ARR: Access 8 UD0Rx registers in an array */ #define UD0R_ARR ((volatile byte * __far) &UD0R0) #define UD0R0_UE0RD00_UE0TD00_MASK 1 #define UD0R0_UE0RD01_UE0TD01_MASK 2 #define UD0R0_UE0RD02_UE0TD02_MASK 4 #define UD0R0_UE0RD03_UE0TD03_MASK 8 #define UD0R0_UE0RD04_UE0TD04_MASK 16 #define UD0R0_UE0RD05_UE0TD05_MASK 32 #define UD0R0_UE0RD06_UE0TD06_MASK 64 #define UD0R0_UE0RD07_UE0TD07_MASK 128 /*** UD0R1 - USB Endpoint 0 Data Register 1; 0x00000031 ***/ typedef union { byte Byte; struct { byte UE0RD10_UE0TD10 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 0, Endpoint 0 Transmit Data Buffer 1 Bit 0 */ byte UE0RD11_UE0TD11 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 1, Endpoint 0 Transmit Data Buffer 1 Bit 1 */ byte UE0RD12_UE0TD12 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 2, Endpoint 0 Transmit Data Buffer 1 Bit 2 */ byte UE0RD13_UE0TD13 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 3, Endpoint 0 Transmit Data Buffer 1 Bit 3 */ byte UE0RD14_UE0TD14 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 4, Endpoint 0 Transmit Data Buffer 1 Bit 4 */ byte UE0RD15_UE0TD15 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 5, Endpoint 0 Transmit Data Buffer 1 Bit 5 */ byte UE0RD16_UE0TD16 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 6, Endpoint 0 Transmit Data Buffer 1 Bit 6 */ byte UE0RD17_UE0TD17 :1; /* Endpoint 0 Receive Data Buffer 1 Bit 7, Endpoint 0 Transmit Data Buffer 1 Bit 7 */ } Bits; } UD0R1STR; extern volatile UD0R1STR _UD0R1 @0x00000031; #define UD0R1 _UD0R1.Byte #define UD0R1_UE0RD10_UE0TD10 _UD0R1.Bits.UE0RD10_UE0TD10 #define UD0R1_UE0RD11_UE0TD11 _UD0R1.Bits.UE0RD11_UE0TD11 #define UD0R1_UE0RD12_UE0TD12 _UD0R1.Bits.UE0RD12_UE0TD12 #define UD0R1_UE0RD13_UE0TD13 _UD0R1.Bits.UE0RD13_UE0TD13 #define UD0R1_UE0RD14_UE0TD14 _UD0R1.Bits.UE0RD14_UE0TD14 #define UD0R1_UE0RD15_UE0TD15 _UD0R1.Bits.UE0RD15_UE0TD15 #define UD0R1_UE0RD16_UE0TD16 _UD0R1.Bits.UE0RD16_UE0TD16 #define UD0R1_UE0RD17_UE0TD17 _UD0R1.Bits.UE0RD17_UE0TD17 #define UD0R1_UE0RD10_UE0TD10_MASK 1 #define UD0R1_UE0RD11_UE0TD11_MASK 2 #define UD0R1_UE0RD12_UE0TD12_MASK 4 #define UD0R1_UE0RD13_UE0TD13_MASK 8 #define UD0R1_UE0RD14_UE0TD14_MASK 16 #define UD0R1_UE0RD15_UE0TD15_MASK 32 #define UD0R1_UE0RD16_UE0TD16_MASK 64 #define UD0R1_UE0RD17_UE0TD17_MASK 128 /*** UD0R2 - USB Endpoint 0 Data Register 2; 0x00000032 ***/ typedef union { byte Byte; struct { byte UE0RD20_UE0TD20 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 0, Endpoint 0 Transmit Data Buffer 2 Bit 0 */ byte UE0RD21_UE0TD21 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 1, Endpoint 0 Transmit Data Buffer 2 Bit 1 */ byte UE0RD22_UE0TD22 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 2, Endpoint 0 Transmit Data Buffer 2 Bit 2 */ byte UE0RD23_UE0TD23 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 3, Endpoint 0 Transmit Data Buffer 2 Bit 3 */ byte UE0RD24_UE0TD24 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 4, Endpoint 0 Transmit Data Buffer 2 Bit 4 */ byte UE0RD25_UE0TD25 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 5, Endpoint 0 Transmit Data Buffer 2 Bit 5 */ byte UE0RD26_UE0TD26 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 6, Endpoint 0 Transmit Data Buffer 2 Bit 6 */ byte UE0RD27_UE0TD27 :1; /* Endpoint 0 Receive Data Buffer 2 Bit 7, Endpoint 0 Transmit Data Buffer 2 Bit 7 */ } Bits; } UD0R2STR; extern volatile UD0R2STR _UD0R2 @0x00000032; #define UD0R2 _UD0R2.Byte #define UD0R2_UE0RD20_UE0TD20 _UD0R2.Bits.UE0RD20_UE0TD20 #define UD0R2_UE0RD21_UE0TD21 _UD0R2.Bits.UE0RD21_UE0TD21 #define UD0R2_UE0RD22_UE0TD22 _UD0R2.Bits.UE0RD22_UE0TD22 #define UD0R2_UE0RD23_UE0TD23 _UD0R2.Bits.UE0RD23_UE0TD23 #define UD0R2_UE0RD24_UE0TD24 _UD0R2.Bits.UE0RD24_UE0TD24 #define UD0R2_UE0RD25_UE0TD25 _UD0R2.Bits.UE0RD25_UE0TD25 #define UD0R2_UE0RD26_UE0TD26 _UD0R2.Bits.UE0RD26_UE0TD26 #define UD0R2_UE0RD27_UE0TD27 _UD0R2.Bits.UE0RD27_UE0TD27 #define UD0R2_UE0RD20_UE0TD20_MASK 1 #define UD0R2_UE0RD21_UE0TD21_MASK 2 #define UD0R2_UE0RD22_UE0TD22_MASK 4 #define UD0R2_UE0RD23_UE0TD23_MASK 8 #define UD0R2_UE0RD24_UE0TD24_MASK 16 #define UD0R2_UE0RD25_UE0TD25_MASK 32 #define UD0R2_UE0RD26_UE0TD26_MASK 64 #define UD0R2_UE0RD27_UE0TD27_MASK 128 /*** UD0R3 - USB Endpoint 0 Data Register 3; 0x00000033 ***/ typedef union { byte Byte; struct { byte UE0RD30_UE0TD30 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 0, Endpoint 0 Transmit Data Buffer 3 Bit 0 */ byte UE0RD31_UE0TD31 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 1, Endpoint 0 Transmit Data Buffer 3 Bit 1 */ byte UE0RD32_UE0TD32 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 2, Endpoint 0 Transmit Data Buffer 3 Bit 2 */ byte UE0RD33_UE0TD33 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 3, Endpoint 0 Transmit Data Buffer 3 Bit 3 */ byte UE0RD34_UE0TD34 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 4, Endpoint 0 Transmit Data Buffer 3 Bit 4 */ byte UE0RD35_UE0TD35 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 5, Endpoint 0 Transmit Data Buffer 3 Bit 5 */ byte UE0RD36_UE0TD36 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 6, Endpoint 0 Transmit Data Buffer 3 Bit 6 */ byte UE0RD37_UE0TD37 :1; /* Endpoint 0 Receive Data Buffer 3 Bit 7, Endpoint 0 Transmit Data Buffer 3 Bit 7 */ } Bits; } UD0R3STR; extern volatile UD0R3STR _UD0R3 @0x00000033; #define UD0R3 _UD0R3.Byte #define UD0R3_UE0RD30_UE0TD30 _UD0R3.Bits.UE0RD30_UE0TD30 #define UD0R3_UE0RD31_UE0TD31 _UD0R3.Bits.UE0RD31_UE0TD31 #define UD0R3_UE0RD32_UE0TD32 _UD0R3.Bits.UE0RD32_UE0TD32 #define UD0R3_UE0RD33_UE0TD33 _UD0R3.Bits.UE0RD33_UE0TD33 #define UD0R3_UE0RD34_UE0TD34 _UD0R3.Bits.UE0RD34_UE0TD34 #define UD0R3_UE0RD35_UE0TD35 _UD0R3.Bits.UE0RD35_UE0TD35 #define UD0R3_UE0RD36_UE0TD36 _UD0R3.Bits.UE0RD36_UE0TD36 #define UD0R3_UE0RD37_UE0TD37 _UD0R3.Bits.UE0RD37_UE0TD37 #define UD0R3_UE0RD30_UE0TD30_MASK 1 #define UD0R3_UE0RD31_UE0TD31_MASK 2 #define UD0R3_UE0RD32_UE0TD32_MASK 4 #define UD0R3_UE0RD33_UE0TD33_MASK 8 #define UD0R3_UE0RD34_UE0TD34_MASK 16 #define UD0R3_UE0RD35_UE0TD35_MASK 32 #define UD0R3_UE0RD36_UE0TD36_MASK 64 #define UD0R3_UE0RD37_UE0TD37_MASK 128 /*** UD0R4 - USB Endpoint 0 Data Register 4; 0x00000034 ***/ typedef union { byte Byte; struct { byte UE0RD40_UE0TD40 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 0, Endpoint 0 Transmit Data Buffer 4 Bit 0 */ byte UE0RD41_UE0TD41 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 1, Endpoint 0 Transmit Data Buffer 4 Bit 1 */ byte UE0RD42_UE0TD42 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 2, Endpoint 0 Transmit Data Buffer 4 Bit 2 */ byte UE0RD43_UE0TD43 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 3, Endpoint 0 Transmit Data Buffer 4 Bit 3 */ byte UE0RD44_UE0TD44 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 4, Endpoint 0 Transmit Data Buffer 4 Bit 4 */ byte UE0RD45_UE0TD45 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 5, Endpoint 0 Transmit Data Buffer 4 Bit 5 */ byte UE0RD46_UE0TD46 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 6, Endpoint 0 Transmit Data Buffer 4 Bit 6 */ byte UE0RD47_UE0TD47 :1; /* Endpoint 0 Receive Data Buffer 4 Bit 7, Endpoint 0 Transmit Data Buffer 4 Bit 7 */ } Bits; } UD0R4STR; extern volatile UD0R4STR _UD0R4 @0x00000034; #define UD0R4 _UD0R4.Byte #define UD0R4_UE0RD40_UE0TD40 _UD0R4.Bits.UE0RD40_UE0TD40 #define UD0R4_UE0RD41_UE0TD41 _UD0R4.Bits.UE0RD41_UE0TD41 #define UD0R4_UE0RD42_UE0TD42 _UD0R4.Bits.UE0RD42_UE0TD42 #define UD0R4_UE0RD43_UE0TD43 _UD0R4.Bits.UE0RD43_UE0TD43 #define UD0R4_UE0RD44_UE0TD44 _UD0R4.Bits.UE0RD44_UE0TD44 #define UD0R4_UE0RD45_UE0TD45 _UD0R4.Bits.UE0RD45_UE0TD45 #define UD0R4_UE0RD46_UE0TD46 _UD0R4.Bits.UE0RD46_UE0TD46 #define UD0R4_UE0RD47_UE0TD47 _UD0R4.Bits.UE0RD47_UE0TD47 #define UD0R4_UE0RD40_UE0TD40_MASK 1 #define UD0R4_UE0RD41_UE0TD41_MASK 2 #define UD0R4_UE0RD42_UE0TD42_MASK 4 #define UD0R4_UE0RD43_UE0TD43_MASK 8 #define UD0R4_UE0RD44_UE0TD44_MASK 16 #define UD0R4_UE0RD45_UE0TD45_MASK 32 #define UD0R4_UE0RD46_UE0TD46_MASK 64 #define UD0R4_UE0RD47_UE0TD47_MASK 128 /*** UD0R5 - USB Endpoint 0 Data Register 5; 0x00000035 ***/ typedef union { byte Byte; struct { byte UE0RD50_UE0TD50 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 0, Endpoint 0 Transmit Data Buffer 5 Bit 0 */ byte UE0RD51_UE0TD51 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 1, Endpoint 0 Transmit Data Buffer 5 Bit 1 */ byte UE0RD52_UE0TD52 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 2, Endpoint 0 Transmit Data Buffer 5 Bit 2 */ byte UE0RD53_UE0TD53 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 3, Endpoint 0 Transmit Data Buffer 5 Bit 3 */ byte UE0RD54_UE0TD54 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 4, Endpoint 0 Transmit Data Buffer 5 Bit 4 */ byte UE0RD55_UE0TD55 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 5, Endpoint 0 Transmit Data Buffer 5 Bit 5 */ byte UE0RD56_UE0TD56 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 6, Endpoint 0 Transmit Data Buffer 5 Bit 6 */ byte UE0RD57_UE0TD57 :1; /* Endpoint 0 Receive Data Buffer 5 Bit 7, Endpoint 0 Transmit Data Buffer 5 Bit 7 */ } Bits; } UD0R5STR; extern volatile UD0R5STR _UD0R5 @0x00000035; #define UD0R5 _UD0R5.Byte #define UD0R5_UE0RD50_UE0TD50 _UD0R5.Bits.UE0RD50_UE0TD50 #define UD0R5_UE0RD51_UE0TD51 _UD0R5.Bits.UE0RD51_UE0TD51 #define UD0R5_UE0RD52_UE0TD52 _UD0R5.Bits.UE0RD52_UE0TD52 #define UD0R5_UE0RD53_UE0TD53 _UD0R5.Bits.UE0RD53_UE0TD53 #define UD0R5_UE0RD54_UE0TD54 _UD0R5.Bits.UE0RD54_UE0TD54 #define UD0R5_UE0RD55_UE0TD55 _UD0R5.Bits.UE0RD55_UE0TD55 #define UD0R5_UE0RD56_UE0TD56 _UD0R5.Bits.UE0RD56_UE0TD56 #define UD0R5_UE0RD57_UE0TD57 _UD0R5.Bits.UE0RD57_UE0TD57 #define UD0R5_UE0RD50_UE0TD50_MASK 1 #define UD0R5_UE0RD51_UE0TD51_MASK 2 #define UD0R5_UE0RD52_UE0TD52_MASK 4 #define UD0R5_UE0RD53_UE0TD53_MASK 8 #define UD0R5_UE0RD54_UE0TD54_MASK 16 #define UD0R5_UE0RD55_UE0TD55_MASK 32 #define UD0R5_UE0RD56_UE0TD56_MASK 64 #define UD0R5_UE0RD57_UE0TD57_MASK 128 /*** UD0R6 - USB Endpoint 0 Data Register 6; 0x00000036 ***/ typedef union { byte Byte; struct { byte UE0RD60_UE0TD60 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 0, Endpoint 0 Transmit Data Buffer 6 Bit 0 */ byte UE0RD61_UE0TD61 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 1, Endpoint 0 Transmit Data Buffer 6 Bit 1 */ byte UE0RD62_UE0TD62 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 2, Endpoint 0 Transmit Data Buffer 6 Bit 2 */ byte UE0RD63_UE0TD63 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 3, Endpoint 0 Transmit Data Buffer 6 Bit 3 */ byte UE0RD64_UE0TD64 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 4, Endpoint 0 Transmit Data Buffer 6 Bit 4 */ byte UE0RD65_UE0TD65 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 5, Endpoint 0 Transmit Data Buffer 6 Bit 5 */ byte UE0RD66_UE0TD66 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 6, Endpoint 0 Transmit Data Buffer 6 Bit 6 */ byte UE0RD67_UE0TD67 :1; /* Endpoint 0 Receive Data Buffer 6 Bit 7, Endpoint 0 Transmit Data Buffer 6 Bit 7 */ } Bits; } UD0R6STR; extern volatile UD0R6STR _UD0R6 @0x00000036; #define UD0R6 _UD0R6.Byte #define UD0R6_UE0RD60_UE0TD60 _UD0R6.Bits.UE0RD60_UE0TD60 #define UD0R6_UE0RD61_UE0TD61 _UD0R6.Bits.UE0RD61_UE0TD61 #define UD0R6_UE0RD62_UE0TD62 _UD0R6.Bits.UE0RD62_UE0TD62 #define UD0R6_UE0RD63_UE0TD63 _UD0R6.Bits.UE0RD63_UE0TD63 #define UD0R6_UE0RD64_UE0TD64 _UD0R6.Bits.UE0RD64_UE0TD64 #define UD0R6_UE0RD65_UE0TD65 _UD0R6.Bits.UE0RD65_UE0TD65 #define UD0R6_UE0RD66_UE0TD66 _UD0R6.Bits.UE0RD66_UE0TD66 #define UD0R6_UE0RD67_UE0TD67 _UD0R6.Bits.UE0RD67_UE0TD67 #define UD0R6_UE0RD60_UE0TD60_MASK 1 #define UD0R6_UE0RD61_UE0TD61_MASK 2 #define UD0R6_UE0RD62_UE0TD62_MASK 4 #define UD0R6_UE0RD63_UE0TD63_MASK 8 #define UD0R6_UE0RD64_UE0TD64_MASK 16 #define UD0R6_UE0RD65_UE0TD65_MASK 32 #define UD0R6_UE0RD66_UE0TD66_MASK 64 #define UD0R6_UE0RD67_UE0TD67_MASK 128 /*** UD0R7 - USB Endpoint 0 Data Register 7; 0x00000037 ***/ typedef union { byte Byte; struct { byte UE0RD70_UE0TD70 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 0, Endpoint 0 Transmit Data Buffer 7 Bit 0 */ byte UE0RD71_UE0TD71 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 1, Endpoint 0 Transmit Data Buffer 7 Bit 1 */ byte UE0RD72_UE0TD72 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 2, Endpoint 0 Transmit Data Buffer 7 Bit 2 */ byte UE0RD73_UE0TD73 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 3, Endpoint 0 Transmit Data Buffer 7 Bit 3 */ byte UE0RD74_UE0TD74 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 4, Endpoint 0 Transmit Data Buffer 7 Bit 4 */ byte UE0RD75_UE0TD75 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 5, Endpoint 0 Transmit Data Buffer 7 Bit 5 */ byte UE0RD76_UE0TD76 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 6, Endpoint 0 Transmit Data Buffer 7 Bit 6 */ byte UE0RD77_UE0TD77 :1; /* Endpoint 0 Receive Data Buffer 7 Bit 7, Endpoint 0 Transmit Data Buffer 7 Bit 7 */ } Bits; } UD0R7STR; extern volatile UD0R7STR _UD0R7 @0x00000037; #define UD0R7 _UD0R7.Byte #define UD0R7_UE0RD70_UE0TD70 _UD0R7.Bits.UE0RD70_UE0TD70 #define UD0R7_UE0RD71_UE0TD71 _UD0R7.Bits.UE0RD71_UE0TD71 #define UD0R7_UE0RD72_UE0TD72 _UD0R7.Bits.UE0RD72_UE0TD72 #define UD0R7_UE0RD73_UE0TD73 _UD0R7.Bits.UE0RD73_UE0TD73 #define UD0R7_UE0RD74_UE0TD74 _UD0R7.Bits.UE0RD74_UE0TD74 #define UD0R7_UE0RD75_UE0TD75 _UD0R7.Bits.UE0RD75_UE0TD75 #define UD0R7_UE0RD76_UE0TD76 _UD0R7.Bits.UE0RD76_UE0TD76 #define UD0R7_UE0RD77_UE0TD77 _UD0R7.Bits.UE0RD77_UE0TD77 #define UD0R7_UE0RD70_UE0TD70_MASK 1 #define UD0R7_UE0RD71_UE0TD71_MASK 2 #define UD0R7_UE0RD72_UE0TD72_MASK 4 #define UD0R7_UE0RD73_UE0TD73_MASK 8 #define UD0R7_UE0RD74_UE0TD74_MASK 16 #define UD0R7_UE0RD75_UE0TD75_MASK 32 #define UD0R7_UE0RD76_UE0TD76_MASK 64 #define UD0R7_UE0RD77_UE0TD77_MASK 128 /*** UD1R0 - USB Endpoint 1/2 Data Register 0; 0x00000038 ***/ typedef union { byte Byte; struct { byte UE1TD00 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 0 */ byte UE1TD01 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 1 */ byte UE1TD02 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 2 */ byte UE1TD03 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 3 */ byte UE1TD04 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 4 */ byte UE1TD05 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 5 */ byte UE1TD06 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 6 */ byte UE1TD07 :1; /* Endpoint 1/2 Transmit Data Buffer 0 Bit 7 */ } Bits; } UD1R0STR; extern volatile UD1R0STR _UD1R0 @0x00000038; #define UD1R0 _UD1R0.Byte #define UD1R0_UE1TD00 _UD1R0.Bits.UE1TD00 #define UD1R0_UE1TD01 _UD1R0.Bits.UE1TD01 #define UD1R0_UE1TD02 _UD1R0.Bits.UE1TD02 #define UD1R0_UE1TD03 _UD1R0.Bits.UE1TD03 #define UD1R0_UE1TD04 _UD1R0.Bits.UE1TD04 #define UD1R0_UE1TD05 _UD1R0.Bits.UE1TD05 #define UD1R0_UE1TD06 _UD1R0.Bits.UE1TD06 #define UD1R0_UE1TD07 _UD1R0.Bits.UE1TD07 /* UD1R_ARR: Access 8 UD1Rx registers in an array */ #define UD1R_ARR ((volatile byte * __far) &UD1R0) #define UD1R0_UE1TD00_MASK 1 #define UD1R0_UE1TD01_MASK 2 #define UD1R0_UE1TD02_MASK 4 #define UD1R0_UE1TD03_MASK 8 #define UD1R0_UE1TD04_MASK 16 #define UD1R0_UE1TD05_MASK 32 #define UD1R0_UE1TD06_MASK 64 #define UD1R0_UE1TD07_MASK 128 /*** UD1R1 - USB Endpoint 1/2 Data Register 1; 0x00000039 ***/ typedef union { byte Byte; struct { byte UE1TD10 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 0 */ byte UE1TD11 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 1 */ byte UE1TD12 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 2 */ byte UE1TD13 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 3 */ byte UE1TD14 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 4 */ byte UE1TD15 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 5 */ byte UE1TD16 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 6 */ byte UE1TD17 :1; /* Endpoint 1/2 Transmit Data Buffer 1 Bit 7 */ } Bits; } UD1R1STR; extern volatile UD1R1STR _UD1R1 @0x00000039; #define UD1R1 _UD1R1.Byte #define UD1R1_UE1TD10 _UD1R1.Bits.UE1TD10 #define UD1R1_UE1TD11 _UD1R1.Bits.UE1TD11 #define UD1R1_UE1TD12 _UD1R1.Bits.UE1TD12 #define UD1R1_UE1TD13 _UD1R1.Bits.UE1TD13 #define UD1R1_UE1TD14 _UD1R1.Bits.UE1TD14 #define UD1R1_UE1TD15 _UD1R1.Bits.UE1TD15 #define UD1R1_UE1TD16 _UD1R1.Bits.UE1TD16 #define UD1R1_UE1TD17 _UD1R1.Bits.UE1TD17 #define UD1R1_UE1TD10_MASK 1 #define UD1R1_UE1TD11_MASK 2 #define UD1R1_UE1TD12_MASK 4 #define UD1R1_UE1TD13_MASK 8 #define UD1R1_UE1TD14_MASK 16 #define UD1R1_UE1TD15_MASK 32 #define UD1R1_UE1TD16_MASK 64 #define UD1R1_UE1TD17_MASK 128 /*** UD1R2 - USB Endpoint 1/2 Data Register 2; 0x0000003A ***/ typedef union { byte Byte; struct { byte UE1TD20 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 0 */ byte UE1TD21 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 1 */ byte UE1TD22 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 2 */ byte UE1TD23 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 3 */ byte UE1TD24 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 4 */ byte UE1TD25 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 5 */ byte UE1TD26 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 6 */ byte UE1TD27 :1; /* Endpoint 1/2 Transmit Data Buffer 2 Bit 7 */ } Bits; } UD1R2STR; extern volatile UD1R2STR _UD1R2 @0x0000003A; #define UD1R2 _UD1R2.Byte #define UD1R2_UE1TD20 _UD1R2.Bits.UE1TD20 #define UD1R2_UE1TD21 _UD1R2.Bits.UE1TD21 #define UD1R2_UE1TD22 _UD1R2.Bits.UE1TD22 #define UD1R2_UE1TD23 _UD1R2.Bits.UE1TD23 #define UD1R2_UE1TD24 _UD1R2.Bits.UE1TD24 #define UD1R2_UE1TD25 _UD1R2.Bits.UE1TD25 #define UD1R2_UE1TD26 _UD1R2.Bits.UE1TD26 #define UD1R2_UE1TD27 _UD1R2.Bits.UE1TD27 #define UD1R2_UE1TD20_MASK 1 #define UD1R2_UE1TD21_MASK 2 #define UD1R2_UE1TD22_MASK 4 #define UD1R2_UE1TD23_MASK 8 #define UD1R2_UE1TD24_MASK 16 #define UD1R2_UE1TD25_MASK 32 #define UD1R2_UE1TD26_MASK 64 #define UD1R2_UE1TD27_MASK 128 /*** UD1R3 - USB Endpoint 1/2 Data Register 3; 0x0000003B ***/ typedef union { byte Byte; struct { byte UE1TD30 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 0 */ byte UE1TD31 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 1 */ byte UE1TD32 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 2 */ byte UE1TD33 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 3 */ byte UE1TD34 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 4 */ byte UE1TD35 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 5 */ byte UE1TD36 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 6 */ byte UE1TD37 :1; /* Endpoint 1/2 Transmit Data Buffer 3 Bit 7 */ } Bits; } UD1R3STR; extern volatile UD1R3STR _UD1R3 @0x0000003B; #define UD1R3 _UD1R3.Byte #define UD1R3_UE1TD30 _UD1R3.Bits.UE1TD30 #define UD1R3_UE1TD31 _UD1R3.Bits.UE1TD31 #define UD1R3_UE1TD32 _UD1R3.Bits.UE1TD32 #define UD1R3_UE1TD33 _UD1R3.Bits.UE1TD33 #define UD1R3_UE1TD34 _UD1R3.Bits.UE1TD34 #define UD1R3_UE1TD35 _UD1R3.Bits.UE1TD35 #define UD1R3_UE1TD36 _UD1R3.Bits.UE1TD36 #define UD1R3_UE1TD37 _UD1R3.Bits.UE1TD37 #define UD1R3_UE1TD30_MASK 1 #define UD1R3_UE1TD31_MASK 2 #define UD1R3_UE1TD32_MASK 4 #define UD1R3_UE1TD33_MASK 8 #define UD1R3_UE1TD34_MASK 16 #define UD1R3_UE1TD35_MASK 32 #define UD1R3_UE1TD36_MASK 64 #define UD1R3_UE1TD37_MASK 128 /*** UD1R4 - USB Endpoint 1/2 Data Register 4; 0x0000003C ***/ typedef union { byte Byte; struct { byte UE1TD40 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 0 */ byte UE1TD41 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 1 */ byte UE1TD42 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 2 */ byte UE1TD43 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 3 */ byte UE1TD44 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 4 */ byte UE1TD45 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 5 */ byte UE1TD46 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 6 */ byte UE1TD47 :1; /* Endpoint 1/2 Transmit Data Buffer 4 Bit 7 */ } Bits; } UD1R4STR; extern volatile UD1R4STR _UD1R4 @0x0000003C; #define UD1R4 _UD1R4.Byte #define UD1R4_UE1TD40 _UD1R4.Bits.UE1TD40 #define UD1R4_UE1TD41 _UD1R4.Bits.UE1TD41 #define UD1R4_UE1TD42 _UD1R4.Bits.UE1TD42 #define UD1R4_UE1TD43 _UD1R4.Bits.UE1TD43 #define UD1R4_UE1TD44 _UD1R4.Bits.UE1TD44 #define UD1R4_UE1TD45 _UD1R4.Bits.UE1TD45 #define UD1R4_UE1TD46 _UD1R4.Bits.UE1TD46 #define UD1R4_UE1TD47 _UD1R4.Bits.UE1TD47 #define UD1R4_UE1TD40_MASK 1 #define UD1R4_UE1TD41_MASK 2 #define UD1R4_UE1TD42_MASK 4 #define UD1R4_UE1TD43_MASK 8 #define UD1R4_UE1TD44_MASK 16 #define UD1R4_UE1TD45_MASK 32 #define UD1R4_UE1TD46_MASK 64 #define UD1R4_UE1TD47_MASK 128 /*** UD1R5 - USB Endpoint 1/2 Data Register 5; 0x0000003D ***/ typedef union { byte Byte; struct { byte UE1TD50 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 0 */ byte UE1TD51 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 1 */ byte UE1TD52 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 2 */ byte UE1TD53 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 3 */ byte UE1TD54 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 4 */ byte UE1TD55 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 5 */ byte UE1TD56 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 6 */ byte UE1TD57 :1; /* Endpoint 1/2 Transmit Data Buffer 5 Bit 7 */ } Bits; } UD1R5STR; extern volatile UD1R5STR _UD1R5 @0x0000003D; #define UD1R5 _UD1R5.Byte #define UD1R5_UE1TD50 _UD1R5.Bits.UE1TD50 #define UD1R5_UE1TD51 _UD1R5.Bits.UE1TD51 #define UD1R5_UE1TD52 _UD1R5.Bits.UE1TD52 #define UD1R5_UE1TD53 _UD1R5.Bits.UE1TD53 #define UD1R5_UE1TD54 _UD1R5.Bits.UE1TD54 #define UD1R5_UE1TD55 _UD1R5.Bits.UE1TD55 #define UD1R5_UE1TD56 _UD1R5.Bits.UE1TD56 #define UD1R5_UE1TD57 _UD1R5.Bits.UE1TD57 #define UD1R5_UE1TD50_MASK 1 #define UD1R5_UE1TD51_MASK 2 #define UD1R5_UE1TD52_MASK 4 #define UD1R5_UE1TD53_MASK 8 #define UD1R5_UE1TD54_MASK 16 #define UD1R5_UE1TD55_MASK 32 #define UD1R5_UE1TD56_MASK 64 #define UD1R5_UE1TD57_MASK 128 /*** UD1R6 - USB Endpoint 1/2 Data Register 6; 0x0000003E ***/ typedef union { byte Byte; struct { byte UE1TD60 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 0 */ byte UE1TD61 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 1 */ byte UE1TD62 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 2 */ byte UE1TD63 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 3 */ byte UE1TD64 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 4 */ byte UE1TD65 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 5 */ byte UE1TD66 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 6 */ byte UE1TD67 :1; /* Endpoint 1/2 Transmit Data Buffer 6 Bit 7 */ } Bits; } UD1R6STR; extern volatile UD1R6STR _UD1R6 @0x0000003E; #define UD1R6 _UD1R6.Byte #define UD1R6_UE1TD60 _UD1R6.Bits.UE1TD60 #define UD1R6_UE1TD61 _UD1R6.Bits.UE1TD61 #define UD1R6_UE1TD62 _UD1R6.Bits.UE1TD62 #define UD1R6_UE1TD63 _UD1R6.Bits.UE1TD63 #define UD1R6_UE1TD64 _UD1R6.Bits.UE1TD64 #define UD1R6_UE1TD65 _UD1R6.Bits.UE1TD65 #define UD1R6_UE1TD66 _UD1R6.Bits.UE1TD66 #define UD1R6_UE1TD67 _UD1R6.Bits.UE1TD67 #define UD1R6_UE1TD60_MASK 1 #define UD1R6_UE1TD61_MASK 2 #define UD1R6_UE1TD62_MASK 4 #define UD1R6_UE1TD63_MASK 8 #define UD1R6_UE1TD64_MASK 16 #define UD1R6_UE1TD65_MASK 32 #define UD1R6_UE1TD66_MASK 64 #define UD1R6_UE1TD67_MASK 128 /*** UD1R7 - USB Endpoint 1/2 Data Register 7; 0x0000003F ***/ typedef union { byte Byte; struct { byte UE1TD70 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 0 */ byte UE1TD71 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 1 */ byte UE1TD72 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 2 */ byte UE1TD73 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 3 */ byte UE1TD74 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 4 */ byte UE1TD75 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 5 */ byte UE1TD76 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 6 */ byte UE1TD77 :1; /* Endpoint 1/2 Transmit Data Buffer 7 Bit 7 */ } Bits; } UD1R7STR; extern volatile UD1R7STR _UD1R7 @0x0000003F; #define UD1R7 _UD1R7.Byte #define UD1R7_UE1TD70 _UD1R7.Bits.UE1TD70 #define UD1R7_UE1TD71 _UD1R7.Bits.UE1TD71 #define UD1R7_UE1TD72 _UD1R7.Bits.UE1TD72 #define UD1R7_UE1TD73 _UD1R7.Bits.UE1TD73 #define UD1R7_UE1TD74 _UD1R7.Bits.UE1TD74 #define UD1R7_UE1TD75 _UD1R7.Bits.UE1TD75 #define UD1R7_UE1TD76 _UD1R7.Bits.UE1TD76 #define UD1R7_UE1TD77 _UD1R7.Bits.UE1TD77 #define UD1R7_UE1TD70_MASK 1 #define UD1R7_UE1TD71_MASK 2 #define UD1R7_UE1TD72_MASK 4 #define UD1R7_UE1TD73_MASK 8 #define UD1R7_UE1TD74_MASK 16 #define UD1R7_UE1TD75_MASK 32 #define UD1R7_UE1TD76_MASK 64 #define UD1R7_UE1TD77_MASK 128 /*** SPCSR - Sync Processor Control and Status Register; 0x00000040 ***/ typedef union { byte Byte; struct { byte HPOL :1; /* HSync Input Polarity */ byte VPOL :1; /* VSync Input Polarity */ byte HINVO :1; /* HSYNCO Signal Polarity */ byte VINVO :1; /* VSYNCO Signal Polarity */ byte COMP :1; /* Composite Sync Input Enable */ byte VSIF :1; /* VSync Interrupt Flag */ byte VEDGE :1; /* VSync Interrupt Edge Select */ byte VSIE :1; /* VSync Interrupt Enable */ } Bits; } SPCSRSTR; extern volatile SPCSRSTR _SPCSR @0x00000040; #define SPCSR _SPCSR.Byte #define SPCSR_HPOL _SPCSR.Bits.HPOL #define SPCSR_VPOL _SPCSR.Bits.VPOL #define SPCSR_HINVO _SPCSR.Bits.HINVO #define SPCSR_VINVO _SPCSR.Bits.VINVO #define SPCSR_COMP _SPCSR.Bits.COMP #define SPCSR_VSIF _SPCSR.Bits.VSIF #define SPCSR_VEDGE _SPCSR.Bits.VEDGE #define SPCSR_VSIE _SPCSR.Bits.VSIE #define SPCSR_HPOL_MASK 1 #define SPCSR_VPOL_MASK 2 #define SPCSR_HINVO_MASK 4 #define SPCSR_VINVO_MASK 8 #define SPCSR_COMP_MASK 16 #define SPCSR_VSIF_MASK 32 #define SPCSR_VEDGE_MASK 64 #define SPCSR_VSIE_MASK 128 /*** VFHR - Vertical Frequency High Register; 0x00000041 ***/ typedef union { byte Byte; struct { byte VF8 :1; /* Vertical Frame Frequency Bit 8 */ byte VF9 :1; /* Vertical Frame Frequency Bit 9 */ byte VF10 :1; /* Vertical Frame Frequency Bit 10 */ byte VF11 :1; /* Vertical Frame Frequency Bit 11 */ byte VF12 :1; /* Vertical Frame Frequency Bit 12 */ byte CPW0 :1; /* Clamp Pulse Width Bit 0 */ byte CPW1 :1; /* Clamp Pulse Width Bit 1 */ byte VOF :1; /* Vertical Frequency Counter Overflow */ } Bits; struct { byte grpVF_8 :5; byte grpCPW :2; byte :1; } MergedBits; } VFHRSTR; extern volatile VFHRSTR _VFHR @0x00000041; #define VFHR _VFHR.Byte #define VFHR_VF8 _VFHR.Bits.VF8 #define VFHR_VF9 _VFHR.Bits.VF9 #define VFHR_VF10 _VFHR.Bits.VF10 #define VFHR_VF11 _VFHR.Bits.VF11 #define VFHR_VF12 _VFHR.Bits.VF12 #define VFHR_CPW0 _VFHR.Bits.CPW0 #define VFHR_CPW1 _VFHR.Bits.CPW1 #define VFHR_VOF _VFHR.Bits.VOF #define VFHR_VF_8 _VFHR.MergedBits.grpVF_8 #define VFHR_CPW _VFHR.MergedBits.grpCPW #define VFHR_VF VFHR_VF_8 #define VFHR_VF8_MASK 1 #define VFHR_VF9_MASK 2 #define VFHR_VF10_MASK 4 #define VFHR_VF11_MASK 8 #define VFHR_VF12_MASK 16 #define VFHR_CPW0_MASK 32 #define VFHR_CPW1_MASK 64 #define VFHR_VOF_MASK 128 #define VFHR_VF_8_MASK 31 #define VFHR_VF_8_BITNUM 0 #define VFHR_CPW_MASK 96 #define VFHR_CPW_BITNUM 5 /*** VFLR - Vertical Frequency Low Register; 0x00000042 ***/ typedef union { byte Byte; struct { byte VF0 :1; /* Vertical Frame Frequency Bit 0 */ byte VF1 :1; /* Vertical Frame Frequency Bit 1 */ byte VF2 :1; /* Vertical Frame Frequency Bit 2 */ byte VF3 :1; /* Vertical Frame Frequency Bit 3 */ byte VF4 :1; /* Vertical Frame Frequency Bit 4 */ byte VF5 :1; /* Vertical Frame Frequency Bit 5 */ byte VF6 :1; /* Vertical Frame Frequency Bit 6 */ byte VF7 :1; /* Vertical Frame Frequency Bit 7 */ } Bits; } VFLRSTR; extern volatile VFLRSTR _VFLR @0x00000042; #define VFLR _VFLR.Byte #define VFLR_VF0 _VFLR.Bits.VF0 #define VFLR_VF1 _VFLR.Bits.VF1 #define VFLR_VF2 _VFLR.Bits.VF2 #define VFLR_VF3 _VFLR.Bits.VF3 #define VFLR_VF4 _VFLR.Bits.VF4 #define VFLR_VF5 _VFLR.Bits.VF5 #define VFLR_VF6 _VFLR.Bits.VF6 #define VFLR_VF7 _VFLR.Bits.VF7 #define VFLR_VF0_MASK 1 #define VFLR_VF1_MASK 2 #define VFLR_VF2_MASK 4 #define VFLR_VF3_MASK 8 #define VFLR_VF4_MASK 16 #define VFLR_VF5_MASK 32 #define VFLR_VF6_MASK 64 #define VFLR_VF7_MASK 128 /*** HFHR - Hsync Frequency High Register; 0x00000043 ***/ typedef union { byte Byte; struct { byte HFH0 :1; /* Horizontal Line Frequency Bit 5 */ byte HFH1 :1; /* Horizontal Line Frequency Bit 6 */ byte HFH2 :1; /* Horizontal Line Frequency Bit 7 */ byte HFH3 :1; /* Horizontal Line Frequency Bit 8 */ byte HFH4 :1; /* Horizontal Line Frequency Bit 9 */ byte HFH5 :1; /* Horizontal Line Frequency Bit 10 */ byte HFH6 :1; /* Horizontal Line Frequency Bit 11 */ byte HFH7 :1; /* Horizontal Line Frequency Bit 12 */ } Bits; } HFHRSTR; extern volatile HFHRSTR _HFHR @0x00000043; #define HFHR _HFHR.Byte #define HFHR_HFH0 _HFHR.Bits.HFH0 #define HFHR_HFH1 _HFHR.Bits.HFH1 #define HFHR_HFH2 _HFHR.Bits.HFH2 #define HFHR_HFH3 _HFHR.Bits.HFH3 #define HFHR_HFH4 _HFHR.Bits.HFH4 #define HFHR_HFH5 _HFHR.Bits.HFH5 #define HFHR_HFH6 _HFHR.Bits.HFH6 #define HFHR_HFH7 _HFHR.Bits.HFH7 #define HFHR_HFH0_MASK 1 #define HFHR_HFH1_MASK 2 #define HFHR_HFH2_MASK 4 #define HFHR_HFH3_MASK 8 #define HFHR_HFH4_MASK 16 #define HFHR_HFH5_MASK 32 #define HFHR_HFH6_MASK 64 #define HFHR_HFH7_MASK 128 /*** HFLR - Hsync Frequency Low Register; 0x00000044 ***/ typedef union { byte Byte; struct { byte HFL0 :1; /* Horizontal Line Frequency Bit 0 */ byte HFL1 :1; /* Horizontal Line Frequency Bit 1 */ byte HFL2 :1; /* Horizontal Line Frequency Bit 2 */ byte HFL3 :1; /* Horizontal Line Frequency Bit 3 */ byte HFL4 :1; /* Horizontal Line Frequency Bit 4 */ byte :1; byte :1; byte HOVER :1; /* HSync Frequency Counter Overflow */ } Bits; struct { byte grpHFL :5; byte :1; byte :1; byte :1; } MergedBits; } HFLRSTR; extern volatile HFLRSTR _HFLR @0x00000044; #define HFLR _HFLR.Byte #define HFLR_HFL0 _HFLR.Bits.HFL0 #define HFLR_HFL1 _HFLR.Bits.HFL1 #define HFLR_HFL2 _HFLR.Bits.HFL2 #define HFLR_HFL3 _HFLR.Bits.HFL3 #define HFLR_HFL4 _HFLR.Bits.HFL4 #define HFLR_HOVER _HFLR.Bits.HOVER #define HFLR_HFL _HFLR.MergedBits.grpHFL #define HFLR_HFL0_MASK 1 #define HFLR_HFL1_MASK 2 #define HFLR_HFL2_MASK 4 #define HFLR_HFL3_MASK 8 #define HFLR_HFL4_MASK 16 #define HFLR_HOVER_MASK 128 #define HFLR_HFL_MASK 31 #define HFLR_HFL_BITNUM 0 /*** SPIOCR - Sync Processor I/O Control Register; 0x00000045 ***/ typedef union { byte Byte; struct { byte SOUT :1; /* Sync Output Enable */ byte BPOR :1; /* Back Porch */ byte CLAMPOE :1; /* Clamp Output Enable */ byte SOGSEL :1; /* SOG Select */ byte :1; byte COINV :1; /* Clamp Output Invert */ byte HSYNCS :1; /* HSYNC Input State */ byte VSYNCS :1; /* VSYNC Input State */ } Bits; } SPIOCRSTR; extern volatile SPIOCRSTR _SPIOCR @0x00000045; #define SPIOCR _SPIOCR.Byte #define SPIOCR_SOUT _SPIOCR.Bits.SOUT #define SPIOCR_BPOR _SPIOCR.Bits.BPOR #define SPIOCR_CLAMPOE _SPIOCR.Bits.CLAMPOE #define SPIOCR_SOGSEL _SPIOCR.Bits.SOGSEL #define SPIOCR_COINV _SPIOCR.Bits.COINV #define SPIOCR_HSYNCS _SPIOCR.Bits.HSYNCS #define SPIOCR_VSYNCS _SPIOCR.Bits.VSYNCS #define SPIOCR_SOUT_MASK 1 #define SPIOCR_BPOR_MASK 2 #define SPIOCR_CLAMPOE_MASK 4 #define SPIOCR_SOGSEL_MASK 8 #define SPIOCR_COINV_MASK 32 #define SPIOCR_HSYNCS_MASK 64 #define SPIOCR_VSYNCS_MASK 128 /*** SPCR1 - Sync Processor Control Register 1; 0x00000046 ***/ typedef union { byte Byte; struct { byte FSHF :1; /* Fast Horizontal Frequency Count */ byte ATPOL :1; /* Auto Polarity */ byte :1; byte :1; byte HPS0 :1; /* HSYNC Input Detection Pulse Width Bit 0 */ byte HPS1 :1; /* HSYNC Input Detection Pulse Width Bit 1 */ byte LVSIF :1; /* Low VSync Interrupt Flag */ byte LVSIE :1; /* Low VSync Interrupt Enable */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpHPS :2; byte :1; byte :1; } MergedBits; } SPCR1STR; extern volatile SPCR1STR _SPCR1 @0x00000046; #define SPCR1 _SPCR1.Byte #define SPCR1_FSHF _SPCR1.Bits.FSHF #define SPCR1_ATPOL _SPCR1.Bits.ATPOL #define SPCR1_HPS0 _SPCR1.Bits.HPS0 #define SPCR1_HPS1 _SPCR1.Bits.HPS1 #define SPCR1_LVSIF _SPCR1.Bits.LVSIF #define SPCR1_LVSIE _SPCR1.Bits.LVSIE #define SPCR1_HPS _SPCR1.MergedBits.grpHPS #define SPCR1_FSHF_MASK 1 #define SPCR1_ATPOL_MASK 2 #define SPCR1_HPS0_MASK 16 #define SPCR1_HPS1_MASK 32 #define SPCR1_LVSIF_MASK 64 #define SPCR1_LVSIE_MASK 128 #define SPCR1_HPS_MASK 48 #define SPCR1_HPS_BITNUM 4 /*** HVOCR - H&V Sync Output Control Register; 0x00000047 ***/ typedef union { byte Byte; struct { byte HVOCR0 :1; /* H&V Output Select Bit 0 */ byte HVOCR1 :1; /* H&V Output Select Bit 1 */ byte HVOCR2 :1; /* H&V Output Select Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpHVOCR :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } HVOCRSTR; extern volatile HVOCRSTR _HVOCR @0x00000047; #define HVOCR _HVOCR.Byte #define HVOCR_HVOCR0 _HVOCR.Bits.HVOCR0 #define HVOCR_HVOCR1 _HVOCR.Bits.HVOCR1 #define HVOCR_HVOCR2 _HVOCR.Bits.HVOCR2 #define HVOCR_HVOCR _HVOCR.MergedBits.grpHVOCR #define HVOCR_HVOCR0_MASK 1 #define HVOCR_HVOCR1_MASK 2 #define HVOCR_HVOCR2_MASK 4 #define HVOCR_HVOCR_MASK 7 #define HVOCR_HVOCR_BITNUM 0 /*** PDCR - Port D Configuration Register; 0x00000049 ***/ typedef union { byte Byte; struct { byte USBDPLUSE :1; /* USB D+ Pin Enable */ byte USBDMINUSE :1; /* USB D- Pin Enable */ byte DDCDATE :1; /* DDC Data Pin Enable */ byte DDCSCLE :1; /* DDC Clock Pin Enable */ byte CLAMPE :1; /* CLAMP Pin Enable */ byte IICSCLE :1; /* MMIIC Clock Pin Enable */ byte IICDATE :1; /* MMIIC Data Pin Enable */ byte :1; } Bits; } PDCRSTR; extern volatile PDCRSTR _PDCR @0x00000049; #define PDCR _PDCR.Byte #define PDCR_USBDPLUSE _PDCR.Bits.USBDPLUSE #define PDCR_USBDMINUSE _PDCR.Bits.USBDMINUSE #define PDCR_DDCDATE _PDCR.Bits.DDCDATE #define PDCR_DDCSCLE _PDCR.Bits.DDCSCLE #define PDCR_CLAMPE _PDCR.Bits.CLAMPE #define PDCR_IICSCLE _PDCR.Bits.IICSCLE #define PDCR_IICDATE _PDCR.Bits.IICDATE #define PDCR_USBDPLUSE_MASK 1 #define PDCR_USBDMINUSE_MASK 2 #define PDCR_DDCDATE_MASK 4 #define PDCR_DDCSCLE_MASK 8 #define PDCR_CLAMPE_MASK 16 #define PDCR_IICSCLE_MASK 32 #define PDCR_IICDATE_MASK 64 /*** MIMCR - Multi-Master IIC Master Control Register; 0x0000004A ***/ typedef union { byte Byte; struct { byte MMBR0 :1; /* Baud Rate Select Bit 0 */ byte MMBR1 :1; /* Baud Rate Select Bit 1 */ byte MMBR2 :1; /* Baud Rate Select Bit 2 */ byte MMRW :1; /* Master Read/Write */ byte MMAST :1; /* Master Control Bit */ byte MMBB :1; /* Bus Busy Flag */ byte MMNAKIF :1; /* No Acknowledge Interrupt Flag */ byte MMALIF :1; /* Multi-Master Arbitration Lost Interrupt Flag */ } Bits; struct { byte grpMMBR :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } MIMCRSTR; extern volatile MIMCRSTR _MIMCR @0x0000004A; #define MIMCR _MIMCR.Byte #define MIMCR_MMBR0 _MIMCR.Bits.MMBR0 #define MIMCR_MMBR1 _MIMCR.Bits.MMBR1 #define MIMCR_MMBR2 _MIMCR.Bits.MMBR2 #define MIMCR_MMRW _MIMCR.Bits.MMRW #define MIMCR_MMAST _MIMCR.Bits.MMAST #define MIMCR_MMBB _MIMCR.Bits.MMBB #define MIMCR_MMNAKIF _MIMCR.Bits.MMNAKIF #define MIMCR_MMALIF _MIMCR.Bits.MMALIF #define MIMCR_MMBR _MIMCR.MergedBits.grpMMBR #define MIMCR_MMBR0_MASK 1 #define MIMCR_MMBR1_MASK 2 #define MIMCR_MMBR2_MASK 4 #define MIMCR_MMRW_MASK 8 #define MIMCR_MMAST_MASK 16 #define MIMCR_MMBB_MASK 32 #define MIMCR_MMNAKIF_MASK 64 #define MIMCR_MMALIF_MASK 128 #define MIMCR_MMBR_MASK 7 #define MIMCR_MMBR_BITNUM 0 /*** MMADR - Multi-Master IIC Address Register; 0x0000004B ***/ typedef union { byte Byte; struct { byte MMEXTAD :1; /* Multi-Master Expanded Address */ byte MMAD1 :1; /* Multi-Master Address Bit 1 */ byte MMAD2 :1; /* Multi-Master Address Bit 2 */ byte MMAD3 :1; /* Multi-Master Address Bit 3 */ byte MMAD4 :1; /* Multi-Master Address Bit 4 */ byte MMAD5 :1; /* Multi-Master Address Bit 5 */ byte MMAD6 :1; /* Multi-Master Address Bit 6 */ byte MMAD7 :1; /* Multi-Master Address Bit 7 */ } Bits; struct { byte :1; byte grpMMAD_1 :7; } MergedBits; } MMADRSTR; extern volatile MMADRSTR _MMADR @0x0000004B; #define MMADR _MMADR.Byte #define MMADR_MMEXTAD _MMADR.Bits.MMEXTAD #define MMADR_MMAD1 _MMADR.Bits.MMAD1 #define MMADR_MMAD2 _MMADR.Bits.MMAD2 #define MMADR_MMAD3 _MMADR.Bits.MMAD3 #define MMADR_MMAD4 _MMADR.Bits.MMAD4 #define MMADR_MMAD5 _MMADR.Bits.MMAD5 #define MMADR_MMAD6 _MMADR.Bits.MMAD6 #define MMADR_MMAD7 _MMADR.Bits.MMAD7 #define MMADR_MMAD_1 _MMADR.MergedBits.grpMMAD_1 #define MMADR_MMAD MMADR_MMAD_1 #define MMADR_MMEXTAD_MASK 1 #define MMADR_MMAD1_MASK 2 #define MMADR_MMAD2_MASK 4 #define MMADR_MMAD3_MASK 8 #define MMADR_MMAD4_MASK 16 #define MMADR_MMAD5_MASK 32 #define MMADR_MMAD6_MASK 64 #define MMADR_MMAD7_MASK 128 #define MMADR_MMAD_1_MASK 254 #define MMADR_MMAD_1_BITNUM 1 /*** MMCR - Multi-Master IIC Control Register; 0x0000004C ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte MMTXAK :1; /* Transmit Acknowledge Enable */ byte :1; byte :1; byte MMIEN :1; /* Multi-Master IIC Interrupt Enable */ byte MMEN :1; /* Multi-Master IIC Enable */ } Bits; } MMCRSTR; extern volatile MMCRSTR _MMCR @0x0000004C; #define MMCR _MMCR.Byte #define MMCR_MMTXAK _MMCR.Bits.MMTXAK #define MMCR_MMIEN _MMCR.Bits.MMIEN #define MMCR_MMEN _MMCR.Bits.MMEN #define MMCR_MMTXAK_MASK 8 #define MMCR_MMIEN_MASK 64 #define MMCR_MMEN_MASK 128 /*** MMSR - Multi-Master IIC Status Register; 0x0000004D ***/ typedef union { byte Byte; struct { byte MMRXBF :1; /* Multi-Master Receive Buffer Full */ byte MMTXBE :1; /* Multi-Master Transmit Buffer Empty */ byte :1; byte MMRXAK :1; /* Multi-Master Receive Acknowledge */ byte MMSRW :1; /* Multi-Master Slave Read/Write */ byte MMATCH :1; /* Multi-Master Address Match */ byte MMTXIF :1; /* Multi-Master Transmit Interrupt Flag */ byte MMRXIF :1; /* Multi-Master IIC Receive Interrupt Flag */ } Bits; } MMSRSTR; extern volatile MMSRSTR _MMSR @0x0000004D; #define MMSR _MMSR.Byte #define MMSR_MMRXBF _MMSR.Bits.MMRXBF #define MMSR_MMTXBE _MMSR.Bits.MMTXBE #define MMSR_MMRXAK _MMSR.Bits.MMRXAK #define MMSR_MMSRW _MMSR.Bits.MMSRW #define MMSR_MMATCH _MMSR.Bits.MMATCH #define MMSR_MMTXIF _MMSR.Bits.MMTXIF #define MMSR_MMRXIF _MMSR.Bits.MMRXIF #define MMSR_MMRXBF_MASK 1 #define MMSR_MMTXBE_MASK 2 #define MMSR_MMRXAK_MASK 8 #define MMSR_MMSRW_MASK 16 #define MMSR_MMATCH_MASK 32 #define MMSR_MMTXIF_MASK 64 #define MMSR_MMRXIF_MASK 128 /*** MMDTR - Multi-Master IIC Data Transmit Register; 0x0000004E ***/ typedef union { byte Byte; struct { byte MMTD0 :1; /* Multi-Master IIC Transmit Data Bit 0 */ byte MMTD1 :1; /* Multi-Master IIC Transmit Data Bit 1 */ byte MMTD2 :1; /* Multi-Master IIC Transmit Data Bit 2 */ byte MMTD3 :1; /* Multi-Master IIC Transmit Data Bit 3 */ byte MMTD4 :1; /* Multi-Master IIC Transmit Data Bit 4 */ byte MMTD5 :1; /* Multi-Master IIC Transmit Data Bit 5 */ byte MMTD6 :1; /* Multi-Master IIC Transmit Data Bit 6 */ byte MMTD7 :1; /* Multi-Master IIC Transmit Data Bit 7 */ } Bits; } MMDTRSTR; extern volatile MMDTRSTR _MMDTR @0x0000004E; #define MMDTR _MMDTR.Byte #define MMDTR_MMTD0 _MMDTR.Bits.MMTD0 #define MMDTR_MMTD1 _MMDTR.Bits.MMTD1 #define MMDTR_MMTD2 _MMDTR.Bits.MMTD2 #define MMDTR_MMTD3 _MMDTR.Bits.MMTD3 #define MMDTR_MMTD4 _MMDTR.Bits.MMTD4 #define MMDTR_MMTD5 _MMDTR.Bits.MMTD5 #define MMDTR_MMTD6 _MMDTR.Bits.MMTD6 #define MMDTR_MMTD7 _MMDTR.Bits.MMTD7 #define MMDTR_MMTD0_MASK 1 #define MMDTR_MMTD1_MASK 2 #define MMDTR_MMTD2_MASK 4 #define MMDTR_MMTD3_MASK 8 #define MMDTR_MMTD4_MASK 16 #define MMDTR_MMTD5_MASK 32 #define MMDTR_MMTD6_MASK 64 #define MMDTR_MMTD7_MASK 128 /*** MMDRR - Multi-Master IIC Data Receive Register; 0x0000004F ***/ typedef union { byte Byte; struct { byte MMRD0 :1; /* Multi-Master IIC Receive Data Bit 0 */ byte MMRD1 :1; /* Multi-Master IIC Receive Data Bit 1 */ byte MMRD2 :1; /* Multi-Master IIC Receive Data Bit 2 */ byte MMRD3 :1; /* Multi-Master IIC Receive Data Bit 3 */ byte MMRD4 :1; /* Multi-Master IIC Receive Data Bit 4 */ byte MMRD5 :1; /* Multi-Master IIC Receive Data Bit 5 */ byte MMRD6 :1; /* Multi-Master IIC Receive Data Bit 6 */ byte MMRD7 :1; /* Multi-Master IIC Receive Data Bit 7 */ } Bits; } MMDRRSTR; extern volatile MMDRRSTR _MMDRR @0x0000004F; #define MMDRR _MMDRR.Byte #define MMDRR_MMRD0 _MMDRR.Bits.MMRD0 #define MMDRR_MMRD1 _MMDRR.Bits.MMRD1 #define MMDRR_MMRD2 _MMDRR.Bits.MMRD2 #define MMDRR_MMRD3 _MMDRR.Bits.MMRD3 #define MMDRR_MMRD4 _MMDRR.Bits.MMRD4 #define MMDRR_MMRD5 _MMDRR.Bits.MMRD5 #define MMDRR_MMRD6 _MMDRR.Bits.MMRD6 #define MMDRR_MMRD7 _MMDRR.Bits.MMRD7 #define MMDRR_MMRD0_MASK 1 #define MMDRR_MMRD1_MASK 2 #define MMDRR_MMRD2_MASK 4 #define MMDRR_MMRD3_MASK 8 #define MMDRR_MMRD4_MASK 16 #define MMDRR_MMRD5_MASK 32 #define MMDRR_MMRD6_MASK 64 #define MMDRR_MMRD7_MASK 128 /*** PWM8 - PWM8 Data Register; 0x00000051 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM8STR; extern volatile PWM8STR _PWM8 @0x00000051; #define PWM8 _PWM8.Byte #define PWM8_BRM0 _PWM8.Bits.BRM0 #define PWM8_BRM1 _PWM8.Bits.BRM1 #define PWM8_BRM2 _PWM8.Bits.BRM2 #define PWM8_PWM_0 _PWM8.Bits.PWM_0 #define PWM8_PWM_1 _PWM8.Bits.PWM_1 #define PWM8_PWM_2 _PWM8.Bits.PWM_2 #define PWM8_PWM_3 _PWM8.Bits.PWM_3 #define PWM8_PWM_4 _PWM8.Bits.PWM_4 #define PWM8_BRM _PWM8.MergedBits.grpBRM #define PWM8_PWM _PWM8.MergedBits.grpPWM #define PWM8_BRM0_MASK 1 #define PWM8_BRM1_MASK 2 #define PWM8_BRM2_MASK 4 #define PWM8_PWM_0_MASK 8 #define PWM8_PWM_1_MASK 16 #define PWM8_PWM_2_MASK 32 #define PWM8_PWM_3_MASK 64 #define PWM8_PWM_4_MASK 128 #define PWM8_BRM_MASK 7 #define PWM8_BRM_BITNUM 0 #define PWM8_PWM_MASK 248 #define PWM8_PWM_BITNUM 3 /*** PWM9 - PWM9 Data Register; 0x00000052 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM9STR; extern volatile PWM9STR _PWM9 @0x00000052; #define PWM9 _PWM9.Byte #define PWM9_BRM0 _PWM9.Bits.BRM0 #define PWM9_BRM1 _PWM9.Bits.BRM1 #define PWM9_BRM2 _PWM9.Bits.BRM2 #define PWM9_PWM_0 _PWM9.Bits.PWM_0 #define PWM9_PWM_1 _PWM9.Bits.PWM_1 #define PWM9_PWM_2 _PWM9.Bits.PWM_2 #define PWM9_PWM_3 _PWM9.Bits.PWM_3 #define PWM9_PWM_4 _PWM9.Bits.PWM_4 #define PWM9_BRM _PWM9.MergedBits.grpBRM #define PWM9_PWM _PWM9.MergedBits.grpPWM #define PWM9_BRM0_MASK 1 #define PWM9_BRM1_MASK 2 #define PWM9_BRM2_MASK 4 #define PWM9_PWM_0_MASK 8 #define PWM9_PWM_1_MASK 16 #define PWM9_PWM_2_MASK 32 #define PWM9_PWM_3_MASK 64 #define PWM9_PWM_4_MASK 128 #define PWM9_BRM_MASK 7 #define PWM9_BRM_BITNUM 0 #define PWM9_PWM_MASK 248 #define PWM9_PWM_BITNUM 3 /*** PWM10 - PWM10 Data Register; 0x00000053 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM10STR; extern volatile PWM10STR _PWM10 @0x00000053; #define PWM10 _PWM10.Byte #define PWM10_BRM0 _PWM10.Bits.BRM0 #define PWM10_BRM1 _PWM10.Bits.BRM1 #define PWM10_BRM2 _PWM10.Bits.BRM2 #define PWM10_PWM_0 _PWM10.Bits.PWM_0 #define PWM10_PWM_1 _PWM10.Bits.PWM_1 #define PWM10_PWM_2 _PWM10.Bits.PWM_2 #define PWM10_PWM_3 _PWM10.Bits.PWM_3 #define PWM10_PWM_4 _PWM10.Bits.PWM_4 #define PWM10_BRM _PWM10.MergedBits.grpBRM #define PWM10_PWM _PWM10.MergedBits.grpPWM #define PWM10_BRM0_MASK 1 #define PWM10_BRM1_MASK 2 #define PWM10_BRM2_MASK 4 #define PWM10_PWM_0_MASK 8 #define PWM10_PWM_1_MASK 16 #define PWM10_PWM_2_MASK 32 #define PWM10_PWM_3_MASK 64 #define PWM10_PWM_4_MASK 128 #define PWM10_BRM_MASK 7 #define PWM10_BRM_BITNUM 0 #define PWM10_PWM_MASK 248 #define PWM10_PWM_BITNUM 3 /*** PWM11 - PWM11 Data Register; 0x00000054 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM11STR; extern volatile PWM11STR _PWM11 @0x00000054; #define PWM11 _PWM11.Byte #define PWM11_BRM0 _PWM11.Bits.BRM0 #define PWM11_BRM1 _PWM11.Bits.BRM1 #define PWM11_BRM2 _PWM11.Bits.BRM2 #define PWM11_PWM_0 _PWM11.Bits.PWM_0 #define PWM11_PWM_1 _PWM11.Bits.PWM_1 #define PWM11_PWM_2 _PWM11.Bits.PWM_2 #define PWM11_PWM_3 _PWM11.Bits.PWM_3 #define PWM11_PWM_4 _PWM11.Bits.PWM_4 #define PWM11_BRM _PWM11.MergedBits.grpBRM #define PWM11_PWM _PWM11.MergedBits.grpPWM #define PWM11_BRM0_MASK 1 #define PWM11_BRM1_MASK 2 #define PWM11_BRM2_MASK 4 #define PWM11_PWM_0_MASK 8 #define PWM11_PWM_1_MASK 16 #define PWM11_PWM_2_MASK 32 #define PWM11_PWM_3_MASK 64 #define PWM11_PWM_4_MASK 128 #define PWM11_BRM_MASK 7 #define PWM11_BRM_BITNUM 0 #define PWM11_PWM_MASK 248 #define PWM11_PWM_BITNUM 3 /*** PWM12 - PWM12 Data Register; 0x00000055 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM12STR; extern volatile PWM12STR _PWM12 @0x00000055; #define PWM12 _PWM12.Byte #define PWM12_BRM0 _PWM12.Bits.BRM0 #define PWM12_BRM1 _PWM12.Bits.BRM1 #define PWM12_BRM2 _PWM12.Bits.BRM2 #define PWM12_PWM_0 _PWM12.Bits.PWM_0 #define PWM12_PWM_1 _PWM12.Bits.PWM_1 #define PWM12_PWM_2 _PWM12.Bits.PWM_2 #define PWM12_PWM_3 _PWM12.Bits.PWM_3 #define PWM12_PWM_4 _PWM12.Bits.PWM_4 #define PWM12_BRM _PWM12.MergedBits.grpBRM #define PWM12_PWM _PWM12.MergedBits.grpPWM #define PWM12_BRM0_MASK 1 #define PWM12_BRM1_MASK 2 #define PWM12_BRM2_MASK 4 #define PWM12_PWM_0_MASK 8 #define PWM12_PWM_1_MASK 16 #define PWM12_PWM_2_MASK 32 #define PWM12_PWM_3_MASK 64 #define PWM12_PWM_4_MASK 128 #define PWM12_BRM_MASK 7 #define PWM12_BRM_BITNUM 0 #define PWM12_PWM_MASK 248 #define PWM12_PWM_BITNUM 3 /*** PWM13 - PWM13 Data Register; 0x00000056 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM13STR; extern volatile PWM13STR _PWM13 @0x00000056; #define PWM13 _PWM13.Byte #define PWM13_BRM0 _PWM13.Bits.BRM0 #define PWM13_BRM1 _PWM13.Bits.BRM1 #define PWM13_BRM2 _PWM13.Bits.BRM2 #define PWM13_PWM_0 _PWM13.Bits.PWM_0 #define PWM13_PWM_1 _PWM13.Bits.PWM_1 #define PWM13_PWM_2 _PWM13.Bits.PWM_2 #define PWM13_PWM_3 _PWM13.Bits.PWM_3 #define PWM13_PWM_4 _PWM13.Bits.PWM_4 #define PWM13_BRM _PWM13.MergedBits.grpBRM #define PWM13_PWM _PWM13.MergedBits.grpPWM #define PWM13_BRM0_MASK 1 #define PWM13_BRM1_MASK 2 #define PWM13_BRM2_MASK 4 #define PWM13_PWM_0_MASK 8 #define PWM13_PWM_1_MASK 16 #define PWM13_PWM_2_MASK 32 #define PWM13_PWM_3_MASK 64 #define PWM13_PWM_4_MASK 128 #define PWM13_BRM_MASK 7 #define PWM13_BRM_BITNUM 0 #define PWM13_PWM_MASK 248 #define PWM13_PWM_BITNUM 3 /*** PWM14 - PWM14 Data Register; 0x00000057 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM14STR; extern volatile PWM14STR _PWM14 @0x00000057; #define PWM14 _PWM14.Byte #define PWM14_BRM0 _PWM14.Bits.BRM0 #define PWM14_BRM1 _PWM14.Bits.BRM1 #define PWM14_BRM2 _PWM14.Bits.BRM2 #define PWM14_PWM_0 _PWM14.Bits.PWM_0 #define PWM14_PWM_1 _PWM14.Bits.PWM_1 #define PWM14_PWM_2 _PWM14.Bits.PWM_2 #define PWM14_PWM_3 _PWM14.Bits.PWM_3 #define PWM14_PWM_4 _PWM14.Bits.PWM_4 #define PWM14_BRM _PWM14.MergedBits.grpBRM #define PWM14_PWM _PWM14.MergedBits.grpPWM #define PWM14_BRM0_MASK 1 #define PWM14_BRM1_MASK 2 #define PWM14_BRM2_MASK 4 #define PWM14_PWM_0_MASK 8 #define PWM14_PWM_1_MASK 16 #define PWM14_PWM_2_MASK 32 #define PWM14_PWM_3_MASK 64 #define PWM14_PWM_4_MASK 128 #define PWM14_BRM_MASK 7 #define PWM14_BRM_BITNUM 0 #define PWM14_PWM_MASK 248 #define PWM14_PWM_BITNUM 3 /*** PWM15 - PWM15 Data Register; 0x00000058 ***/ typedef union { byte Byte; struct { byte BRM0 :1; /* Binary Rate Multiplier Bit 0 */ byte BRM1 :1; /* Binary Rate Multiplier Bit 1 */ byte BRM2 :1; /* Binary Rate Multiplier Bit 2 */ byte PWM_0 :1; /* PWM Bit 0 */ byte PWM_1 :1; /* PWM Bit 1 */ byte PWM_2 :1; /* PWM Bit 2 */ byte PWM_3 :1; /* PWM Bit 3 */ byte PWM_4 :1; /* PWM Bit 4 */ } Bits; struct { byte grpBRM :3; byte grpPWM :5; } MergedBits; } PWM15STR; extern volatile PWM15STR _PWM15 @0x00000058; #define PWM15 _PWM15.Byte #define PWM15_BRM0 _PWM15.Bits.BRM0 #define PWM15_BRM1 _PWM15.Bits.BRM1 #define PWM15_BRM2 _PWM15.Bits.BRM2 #define PWM15_PWM_0 _PWM15.Bits.PWM_0 #define PWM15_PWM_1 _PWM15.Bits.PWM_1 #define PWM15_PWM_2 _PWM15.Bits.PWM_2 #define PWM15_PWM_3 _PWM15.Bits.PWM_3 #define PWM15_PWM_4 _PWM15.Bits.PWM_4 #define PWM15_BRM _PWM15.MergedBits.grpBRM #define PWM15_PWM _PWM15.MergedBits.grpPWM #define PWM15_BRM0_MASK 1 #define PWM15_BRM1_MASK 2 #define PWM15_BRM2_MASK 4 #define PWM15_PWM_0_MASK 8 #define PWM15_PWM_1_MASK 16 #define PWM15_PWM_2_MASK 32 #define PWM15_PWM_3_MASK 64 #define PWM15_PWM_4_MASK 128 #define PWM15_BRM_MASK 7 #define PWM15_BRM_BITNUM 0 #define PWM15_PWM_MASK 248 #define PWM15_PWM_BITNUM 3 /*** PWMCR2 - PWM Control Register 2; 0x00000059 ***/ typedef union { byte Byte; struct { byte PWM8E :1; /* PWM Output 8 Enable */ byte PWM9E :1; /* PWM Output 9 Enable */ byte PWM10E :1; /* PWM Output 10 Enable */ byte PWM11E :1; /* PWM Output 11 Enable */ byte PWM12E :1; /* PWM Output 12 Enable */ byte PWM13E :1; /* PWM Output 13 Enable */ byte PWM14E :1; /* PWM Output 14 Enable */ byte PWM15E :1; /* PWM Output 15 Enable */ } Bits; } PWMCR2STR; extern volatile PWMCR2STR _PWMCR2 @0x00000059; #define PWMCR2 _PWMCR2.Byte #define PWMCR2_PWM8E _PWMCR2.Bits.PWM8E #define PWMCR2_PWM9E _PWMCR2.Bits.PWM9E #define PWMCR2_PWM10E _PWMCR2.Bits.PWM10E #define PWMCR2_PWM11E _PWMCR2.Bits.PWM11E #define PWMCR2_PWM12E _PWMCR2.Bits.PWM12E #define PWMCR2_PWM13E _PWMCR2.Bits.PWM13E #define PWMCR2_PWM14E _PWMCR2.Bits.PWM14E #define PWMCR2_PWM15E _PWMCR2.Bits.PWM15E #define PWMCR2_PWM8E_MASK 1 #define PWMCR2_PWM9E_MASK 2 #define PWMCR2_PWM10E_MASK 4 #define PWMCR2_PWM11E_MASK 8 #define PWMCR2_PWM12E_MASK 16 #define PWMCR2_PWM13E_MASK 32 #define PWMCR2_PWM14E_MASK 64 #define PWMCR2_PWM15E_MASK 128 /*** ADSCR - ADC Status and Control Register; 0x0000005D ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x0000005D; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADR - ADC Data Register; 0x0000005E ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADRSTR; extern volatile ADRSTR _ADR @0x0000005E; #define ADR _ADR.Byte #define ADR_AD0 _ADR.Bits.AD0 #define ADR_AD1 _ADR.Bits.AD1 #define ADR_AD2 _ADR.Bits.AD2 #define ADR_AD3 _ADR.Bits.AD3 #define ADR_AD4 _ADR.Bits.AD4 #define ADR_AD5 _ADR.Bits.AD5 #define ADR_AD6 _ADR.Bits.AD6 #define ADR_AD7 _ADR.Bits.AD7 #define ADR_AD0_MASK 1 #define ADR_AD1_MASK 2 #define ADR_AD2_MASK 4 #define ADR_AD3_MASK 8 #define ADR_AD4_MASK 16 #define ADR_AD5_MASK 32 #define ADR_AD6_MASK 64 #define ADR_AD7_MASK 128 /*** ADICLK - ADC Input Clock Register; 0x0000005F ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte ADIV0 :1; /* ADC Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC Clock Prescaler Bit 1 */ byte ADIV2 :1; /* ADC Clock Prescaler Bit 2 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte grpADIV :3; } MergedBits; } ADICLKSTR; extern volatile ADICLKSTR _ADICLK @0x0000005F; #define ADICLK _ADICLK.Byte #define ADICLK_ADIV0 _ADICLK.Bits.ADIV0 #define ADICLK_ADIV1 _ADICLK.Bits.ADIV1 #define ADICLK_ADIV2 _ADICLK.Bits.ADIV2 #define ADICLK_ADIV _ADICLK.MergedBits.grpADIV #define ADICLK_ADIV0_MASK 32 #define ADICLK_ADIV1_MASK 64 #define ADICLK_ADIV2_MASK 128 #define ADICLK_ADIV_MASK 224 #define ADICLK_ADIV_BITNUM 5 /*** SBSR - SIM Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte SBSW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SBSRSTR; extern volatile SBSRSTR _SBSR @0x0000FE00; #define SBSR _SBSR.Byte #define SBSR_SBSW _SBSR.Bits.SBSW #define SBSR_SBSW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_PIN _SRSR.Bits.PIN #define SRSR_POR _SRSR.Bits.POR #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_PIN_MASK 64 #define SRSR_POR_MASK 128 /*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } SBFCRSTR; extern volatile SBFCRSTR _SBFCR @0x0000FE03; #define SBFCR _SBFCR.Byte #define SBFCR_BCFE _SBFCR.Bits.BCFE #define SBFCR_BCFE_MASK 128 /*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte IF1 :1; /* Interrupt Flag 1 */ byte IF2 :1; /* Interrupt Flag 2 */ byte IF3 :1; /* Interrupt Flag 3 */ byte IF4 :1; /* Interrupt Flag 4 */ byte IF5 :1; /* Interrupt Flag 5 */ byte IF6 :1; /* Interrupt Flag 6 */ } Bits; struct { byte :1; byte :1; byte grpIF_1 :6; } MergedBits; } INT1STR; extern volatile INT1STR _INT1 @0x0000FE04; #define INT1 _INT1.Byte #define INT1_IF1 _INT1.Bits.IF1 #define INT1_IF2 _INT1.Bits.IF2 #define INT1_IF3 _INT1.Bits.IF3 #define INT1_IF4 _INT1.Bits.IF4 #define INT1_IF5 _INT1.Bits.IF5 #define INT1_IF6 _INT1.Bits.IF6 #define INT1_IF_1 _INT1.MergedBits.grpIF_1 #define INT1_IF INT1_IF_1 #define INT1_IF1_MASK 4 #define INT1_IF2_MASK 8 #define INT1_IF3_MASK 16 #define INT1_IF4_MASK 32 #define INT1_IF5_MASK 64 #define INT1_IF6_MASK 128 #define INT1_IF_1_MASK 252 #define INT1_IF_1_BITNUM 2 /*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/ typedef union { byte Byte; struct { byte IF7 :1; /* Interrupt Flag 7 */ byte IF8 :1; /* Interrupt Flag 8 */ byte IF9 :1; /* Interrupt Flag 9 */ byte IF10 :1; /* Interrupt Flag 10 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpIF_7 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } INT2STR; extern volatile INT2STR _INT2 @0x0000FE05; #define INT2 _INT2.Byte #define INT2_IF7 _INT2.Bits.IF7 #define INT2_IF8 _INT2.Bits.IF8 #define INT2_IF9 _INT2.Bits.IF9 #define INT2_IF10 _INT2.Bits.IF10 #define INT2_IF_7 _INT2.MergedBits.grpIF_7 #define INT2_IF INT2_IF_7 #define INT2_IF7_MASK 1 #define INT2_IF8_MASK 2 #define INT2_IF9_MASK 4 #define INT2_IF10_MASK 8 #define INT2_IF_7_MASK 15 #define INT2_IF_7_BITNUM 0 /*** FLCR - FLASH Control Register; 0x0000FE07 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000FE07; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_ERASE _FLCR.Bits.ERASE #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_ERASE_MASK 2 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** FLBPR - FLASH Block Protect Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte :1; byte BPR1 :1; /* Flash Block Protect Bit 1 */ byte BPR2 :1; /* Flash Block Protect Bit 2 */ byte BPR3 :1; /* Flash Block Protect Bit 3 */ byte BPR4 :1; /* Flash Block Protect Bit 4 */ byte BPR5 :1; /* Flash Block Protect Bit 5 */ byte BPR6 :1; /* Flash Block Protect Bit 6 */ byte BPR7 :1; /* Flash Block Protect Bit 7 */ } Bits; struct { byte :1; byte grpBPR_1 :7; } MergedBits; } FLBPRSTR; extern volatile FLBPRSTR _FLBPR @0x0000FE08; #define FLBPR _FLBPR.Byte #define FLBPR_BPR1 _FLBPR.Bits.BPR1 #define FLBPR_BPR2 _FLBPR.Bits.BPR2 #define FLBPR_BPR3 _FLBPR.Bits.BPR3 #define FLBPR_BPR4 _FLBPR.Bits.BPR4 #define FLBPR_BPR5 _FLBPR.Bits.BPR5 #define FLBPR_BPR6 _FLBPR.Bits.BPR6 #define FLBPR_BPR7 _FLBPR.Bits.BPR7 #define FLBPR_BPR_1 _FLBPR.MergedBits.grpBPR_1 #define FLBPR_BPR FLBPR_BPR_1 #define FLBPR_BPR1_MASK 2 #define FLBPR_BPR2_MASK 4 #define FLBPR_BPR3_MASK 8 #define FLBPR_BPR4_MASK 16 #define FLBPR_BPR5_MASK 32 #define FLBPR_BPR6_MASK 64 #define FLBPR_BPR7_MASK 128 #define FLBPR_BPR_1_MASK 254 #define FLBPR_BPR_1_BITNUM 1 /*** BRK - Break Address Register; 0x0000FE0C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register High; 0x0000FE0C ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Bit 8 */ byte BIT9 :1; /* Break Address Bit 9 */ byte BIT10 :1; /* Break Address Bit 10 */ byte BIT11 :1; /* Break Address Bit 11 */ byte BIT12 :1; /* Break Address Bit 12 */ byte BIT13 :1; /* Break Address Bit 13 */ byte BIT14 :1; /* Break Address Bit 14 */ byte BIT15 :1; /* Break Address Bit 15 */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register; 0x0000FE0D ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Bit 0 */ byte BIT1 :1; /* Break Address Bit 1 */ byte BIT2 :1; /* Break Address Bit 2 */ byte BIT3 :1; /* Break Address Bit 3 */ byte BIT4 :1; /* Break Address Bit 4 */ byte BIT5 :1; /* Break Address Bit 5 */ byte BIT6 :1; /* Break Address Bit 6 */ byte BIT7 :1; /* Break Address Bit 7 */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE0C; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0E; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------------------------------- Exceptions in bit names of timer status and control registers due to backward compatibility with previous releases */ #define TSC0_CHxMAX _TSC0.Bits.CH0MAX #define TSC0_TOVx _TSC0.Bits.TOV0 #define TSC0_ELSxA _TSC0.Bits.ELS0A #define TSC0_ELSxB _TSC0.Bits.ELS0B #define TSC0_MSxA _TSC0.Bits.MS0A #define TSC0_MSxB _TSC0.Bits.MS0B #define TSC0_CHxIE _TSC0.Bits.CH0IE #define TSC0_CHxF _TSC0.Bits.CH0F #define TSC1_CHxMAX _TSC1.Bits.CH1MAX #define TSC1_TOVx _TSC1.Bits.TOV1 #define TSC1_ELSxA _TSC1.Bits.ELS1A #define TSC1_ELSxB _TSC1.Bits.ELS1B #define TSC1_MSxA _TSC1.Bits.MS1A #define TSC1_CHxIE _TSC1.Bits.CH1IE #define TSC1_CHxF _TSC1.Bits.CH1F /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 12:42:34 */ #define TCH_ARR This_symb_has_been_depreciated #endif