/* Based on CPU DB MC68HC908AZ60A, version 2.89.090 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908az60a.h ** Processor : MC68HC908AZ60ACFU ** FileFormat: V2.30 ** DataSheet : MC68HC908AZ60A Rev. 6 05/2006 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:07 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908AZ60A_H #define _MC68HC908AZ60A_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_TIMACH5 25 #define VectorNumber_TIMACH4 24 #define VectorNumber_ADC 23 #define VectorNumber_KBD 22 #define VectorNumber_SCITransmit 21 #define VectorNumber_SCIReceive 20 #define VectorNumber_SCIError 19 #define VectorNumber_CANTransmit 18 #define VectorNumber_CANReceive 17 #define VectorNumber_CANError 16 #define VectorNumber_CANWakeup 15 #define VectorNumber_SPITransmit 14 #define VectorNumber_SPIReceive 13 #define VectorNumber_TIMBOvr 12 #define VectorNumber_TIMBCH1 11 #define VectorNumber_TIMBCH0 10 #define VectorNumber_TIMAOvr 9 #define VectorNumber_TIMACH3 8 #define VectorNumber_TIMACH2 7 #define VectorNumber_TIMACH1 6 #define VectorNumber_TIMACH0 5 #define VectorNumber_PIT 4 #define VectorNumber_PLL 3 #define VectorNumber_IRQ1 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_TIMACH5 0x0000FFCC #define INT_TIMACH4 0x0000FFCE #define INT_ADC 0x0000FFD0 #define INT_KBD 0x0000FFD2 #define INT_SCITransmit 0x0000FFD4 #define INT_SCIReceive 0x0000FFD6 #define INT_SCIError 0x0000FFD8 #define INT_CANTransmit 0x0000FFDA #define INT_CANReceive 0x0000FFDC #define INT_CANError 0x0000FFDE #define INT_CANWakeup 0x0000FFE0 #define INT_SPITransmit 0x0000FFE2 #define INT_SPIReceive 0x0000FFE4 #define INT_TIMBOvr 0x0000FFE6 #define INT_TIMBCH1 0x0000FFE8 #define INT_TIMBCH0 0x0000FFEA #define INT_TIMAOvr 0x0000FFEC #define INT_TIMACH3 0x0000FFEE #define INT_TIMACH2 0x0000FFF0 #define INT_TIMACH1 0x0000FFF2 #define INT_TIMACH0 0x0000FFF4 #define INT_PIT 0x0000FFF6 #define INT_PLL 0x0000FFF8 #define INT_IRQ1 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte PTA6 :1; /* Port A Data Bit 6 */ byte PTA7 :1; /* Port A Data Bit 7 */ } Bits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_PTA6 _PTA.Bits.PTA6 #define PTA_PTA7 _PTA.Bits.PTA7 #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_PTA6_MASK 64 #define PTA_PTA7_MASK 128 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** PTC - Port C Data Register; 0x00000002 ***/ typedef union { byte Byte; struct { byte PTC0 :1; /* Port C Data Bit 0 */ byte PTC1 :1; /* Port C Data Bit 1 */ byte PTC2 :1; /* Port C Data Bit 2 */ byte PTC3 :1; /* Port C Data Bit 3 */ byte PTC4 :1; /* Port C Data Bit 4 */ byte PTC5 :1; /* Port C Data Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpPTC :6; byte :1; byte :1; } MergedBits; } PTCSTR; extern volatile PTCSTR _PTC @0x00000002; #define PTC _PTC.Byte #define PTC_PTC0 _PTC.Bits.PTC0 #define PTC_PTC1 _PTC.Bits.PTC1 #define PTC_PTC2 _PTC.Bits.PTC2 #define PTC_PTC3 _PTC.Bits.PTC3 #define PTC_PTC4 _PTC.Bits.PTC4 #define PTC_PTC5 _PTC.Bits.PTC5 #define PTC_PTC _PTC.MergedBits.grpPTC #define PTC_PTC0_MASK 1 #define PTC_PTC1_MASK 2 #define PTC_PTC2_MASK 4 #define PTC_PTC3_MASK 8 #define PTC_PTC4_MASK 16 #define PTC_PTC5_MASK 32 #define PTC_PTC_MASK 63 #define PTC_PTC_BITNUM 0 /*** PTD - Port D Data Register; 0x00000003 ***/ typedef union { byte Byte; struct { byte PTD0 :1; /* Port D Data Bit 0 */ byte PTD1 :1; /* Port D Data Bit 1 */ byte PTD2 :1; /* Port D Data Bit 2 */ byte PTD3 :1; /* Port D Data Bit 3 */ byte PTD4 :1; /* Port D Data Bit 4 */ byte PTD5 :1; /* Port D Data Bit 5 */ byte PTD6 :1; /* Port D Data Bit 6 */ byte PTD7 :1; /* Port D Data Bit 7 */ } Bits; } PTDSTR; extern volatile PTDSTR _PTD @0x00000003; #define PTD _PTD.Byte #define PTD_PTD0 _PTD.Bits.PTD0 #define PTD_PTD1 _PTD.Bits.PTD1 #define PTD_PTD2 _PTD.Bits.PTD2 #define PTD_PTD3 _PTD.Bits.PTD3 #define PTD_PTD4 _PTD.Bits.PTD4 #define PTD_PTD5 _PTD.Bits.PTD5 #define PTD_PTD6 _PTD.Bits.PTD6 #define PTD_PTD7 _PTD.Bits.PTD7 #define PTD_PTD0_MASK 1 #define PTD_PTD1_MASK 2 #define PTD_PTD2_MASK 4 #define PTD_PTD3_MASK 8 #define PTD_PTD4_MASK 16 #define PTD_PTD5_MASK 32 #define PTD_PTD6_MASK 64 #define PTD_PTD7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte DDRA6 :1; /* Data Direction Register A Bit 6 */ byte DDRA7 :1; /* Data Direction Register A Bit 7 */ } Bits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA6 _DDRA.Bits.DDRA6 #define DDRA_DDRA7 _DDRA.Bits.DDRA7 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA6_MASK 64 #define DDRA_DDRA7_MASK 128 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** DDRC - Data Direction Register C; 0x00000006 ***/ typedef union { byte Byte; struct { byte DDRC0 :1; /* Data Direction Register C Bit 0 */ byte DDRC1 :1; /* Data Direction Register C Bit 1 */ byte DDRC2 :1; /* Data Direction Register C Bit 2 */ byte DDRC3 :1; /* Data Direction Register C Bit 3 */ byte DDRC4 :1; /* Data Direction Register C Bit 4 */ byte DDRC5 :1; /* Data Direction Register C Bit 5 */ byte :1; byte MCLKEN :1; /* MCLK Enable Bit */ } Bits; struct { byte grpDDRC :6; byte :1; byte :1; } MergedBits; } DDRCSTR; extern volatile DDRCSTR _DDRC @0x00000006; #define DDRC _DDRC.Byte #define DDRC_DDRC0 _DDRC.Bits.DDRC0 #define DDRC_DDRC1 _DDRC.Bits.DDRC1 #define DDRC_DDRC2 _DDRC.Bits.DDRC2 #define DDRC_DDRC3 _DDRC.Bits.DDRC3 #define DDRC_DDRC4 _DDRC.Bits.DDRC4 #define DDRC_DDRC5 _DDRC.Bits.DDRC5 #define DDRC_MCLKEN _DDRC.Bits.MCLKEN #define DDRC_DDRC _DDRC.MergedBits.grpDDRC #define DDRC_DDRC0_MASK 1 #define DDRC_DDRC1_MASK 2 #define DDRC_DDRC2_MASK 4 #define DDRC_DDRC3_MASK 8 #define DDRC_DDRC4_MASK 16 #define DDRC_DDRC5_MASK 32 #define DDRC_MCLKEN_MASK 128 #define DDRC_DDRC_MASK 63 #define DDRC_DDRC_BITNUM 0 /*** DDRD - Data Direction Register D; 0x00000007 ***/ typedef union { byte Byte; struct { byte DDRD0 :1; /* Data Direction Register D Bit 0 */ byte DDRD1 :1; /* Data Direction Register D Bit 1 */ byte DDRD2 :1; /* Data Direction Register D Bit 2 */ byte DDRD3 :1; /* Data Direction Register D Bit 3 */ byte DDRD4 :1; /* Data Direction Register D Bit 4 */ byte DDRD5 :1; /* Data Direction Register D Bit 5 */ byte DDRD6 :1; /* Data Direction Register D Bit 6 */ byte DDRD7 :1; /* Data Direction Register D Bit 7 */ } Bits; } DDRDSTR; extern volatile DDRDSTR _DDRD @0x00000007; #define DDRD _DDRD.Byte #define DDRD_DDRD0 _DDRD.Bits.DDRD0 #define DDRD_DDRD1 _DDRD.Bits.DDRD1 #define DDRD_DDRD2 _DDRD.Bits.DDRD2 #define DDRD_DDRD3 _DDRD.Bits.DDRD3 #define DDRD_DDRD4 _DDRD.Bits.DDRD4 #define DDRD_DDRD5 _DDRD.Bits.DDRD5 #define DDRD_DDRD6 _DDRD.Bits.DDRD6 #define DDRD_DDRD7 _DDRD.Bits.DDRD7 #define DDRD_DDRD0_MASK 1 #define DDRD_DDRD1_MASK 2 #define DDRD_DDRD2_MASK 4 #define DDRD_DDRD3_MASK 8 #define DDRD_DDRD4_MASK 16 #define DDRD_DDRD5_MASK 32 #define DDRD_DDRD6_MASK 64 #define DDRD_DDRD7_MASK 128 /*** PTE - Port E Data Register; 0x00000008 ***/ typedef union { byte Byte; struct { byte PTE0 :1; /* Port E Data Bit 0 */ byte PTE1 :1; /* Port E Data Bit 1 */ byte PTE2 :1; /* Port E Data Bit 2 */ byte PTE3 :1; /* Port E Data Bit 3 */ byte PTE4 :1; /* Port E Data Bit 4 */ byte PTE5 :1; /* Port E Data Bit 5 */ byte PTE6 :1; /* Port E Data Bit 6 */ byte PTE7 :1; /* Port E Data Bit 7 */ } Bits; } PTESTR; extern volatile PTESTR _PTE @0x00000008; #define PTE _PTE.Byte #define PTE_PTE0 _PTE.Bits.PTE0 #define PTE_PTE1 _PTE.Bits.PTE1 #define PTE_PTE2 _PTE.Bits.PTE2 #define PTE_PTE3 _PTE.Bits.PTE3 #define PTE_PTE4 _PTE.Bits.PTE4 #define PTE_PTE5 _PTE.Bits.PTE5 #define PTE_PTE6 _PTE.Bits.PTE6 #define PTE_PTE7 _PTE.Bits.PTE7 #define PTE_PTE0_MASK 1 #define PTE_PTE1_MASK 2 #define PTE_PTE2_MASK 4 #define PTE_PTE3_MASK 8 #define PTE_PTE4_MASK 16 #define PTE_PTE5_MASK 32 #define PTE_PTE6_MASK 64 #define PTE_PTE7_MASK 128 /*** PTF - Port F Data Register; 0x00000009 ***/ typedef union { byte Byte; struct { byte PTF0 :1; /* Port F Data Bit 0 */ byte PTF1 :1; /* Port F Data Bit 1 */ byte PTF2 :1; /* Port F Data Bit 2 */ byte PTF3 :1; /* Port F Data Bit 3 */ byte PTF4 :1; /* Port F Data Bit 4 */ byte PTF5 :1; /* Port F Data Bit 5 */ byte PTF6 :1; /* Port F Data Bit 6 */ byte :1; } Bits; struct { byte grpPTF :7; byte :1; } MergedBits; } PTFSTR; extern volatile PTFSTR _PTF @0x00000009; #define PTF _PTF.Byte #define PTF_PTF0 _PTF.Bits.PTF0 #define PTF_PTF1 _PTF.Bits.PTF1 #define PTF_PTF2 _PTF.Bits.PTF2 #define PTF_PTF3 _PTF.Bits.PTF3 #define PTF_PTF4 _PTF.Bits.PTF4 #define PTF_PTF5 _PTF.Bits.PTF5 #define PTF_PTF6 _PTF.Bits.PTF6 #define PTF_PTF _PTF.MergedBits.grpPTF #define PTF_PTF0_MASK 1 #define PTF_PTF1_MASK 2 #define PTF_PTF2_MASK 4 #define PTF_PTF3_MASK 8 #define PTF_PTF4_MASK 16 #define PTF_PTF5_MASK 32 #define PTF_PTF6_MASK 64 #define PTF_PTF_MASK 127 #define PTF_PTF_BITNUM 0 /*** PTG - Port G Data Register; 0x0000000A ***/ typedef union { byte Byte; struct { byte PTG0 :1; /* Port G Data Bit 0 */ byte PTG1 :1; /* Port G Data Bit 1 */ byte PTG2 :1; /* Port G Data Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTG :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTGSTR; extern volatile PTGSTR _PTG @0x0000000A; #define PTG _PTG.Byte #define PTG_PTG0 _PTG.Bits.PTG0 #define PTG_PTG1 _PTG.Bits.PTG1 #define PTG_PTG2 _PTG.Bits.PTG2 #define PTG_PTG _PTG.MergedBits.grpPTG #define PTG_PTG0_MASK 1 #define PTG_PTG1_MASK 2 #define PTG_PTG2_MASK 4 #define PTG_PTG_MASK 7 #define PTG_PTG_BITNUM 0 /*** PTH - Port H Data Register; 0x0000000B ***/ typedef union { byte Byte; struct { byte PTH0 :1; /* Port H Data Bit 0 */ byte PTH1 :1; /* Port H Data Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTH :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTHSTR; extern volatile PTHSTR _PTH @0x0000000B; #define PTH _PTH.Byte #define PTH_PTH0 _PTH.Bits.PTH0 #define PTH_PTH1 _PTH.Bits.PTH1 #define PTH_PTH _PTH.MergedBits.grpPTH #define PTH_PTH0_MASK 1 #define PTH_PTH1_MASK 2 #define PTH_PTH_MASK 3 #define PTH_PTH_BITNUM 0 /*** DDRE - Data Direction Register E; 0x0000000C ***/ typedef union { byte Byte; struct { byte DDRE0 :1; /* Data Direction Register E Bit 0 */ byte DDRE1 :1; /* Data Direction Register E Bit 1 */ byte DDRE2 :1; /* Data Direction Register E Bit 2 */ byte DDRE3 :1; /* Data Direction Register E Bit 3 */ byte DDRE4 :1; /* Data Direction Register E Bit 4 */ byte DDRE5 :1; /* Data Direction Register E Bit 5 */ byte DDRE6 :1; /* Data Direction Register E Bit 6 */ byte DDRE7 :1; /* Data Direction Register E Bit 7 */ } Bits; } DDRESTR; extern volatile DDRESTR _DDRE @0x0000000C; #define DDRE _DDRE.Byte #define DDRE_DDRE0 _DDRE.Bits.DDRE0 #define DDRE_DDRE1 _DDRE.Bits.DDRE1 #define DDRE_DDRE2 _DDRE.Bits.DDRE2 #define DDRE_DDRE3 _DDRE.Bits.DDRE3 #define DDRE_DDRE4 _DDRE.Bits.DDRE4 #define DDRE_DDRE5 _DDRE.Bits.DDRE5 #define DDRE_DDRE6 _DDRE.Bits.DDRE6 #define DDRE_DDRE7 _DDRE.Bits.DDRE7 #define DDRE_DDRE0_MASK 1 #define DDRE_DDRE1_MASK 2 #define DDRE_DDRE2_MASK 4 #define DDRE_DDRE3_MASK 8 #define DDRE_DDRE4_MASK 16 #define DDRE_DDRE5_MASK 32 #define DDRE_DDRE6_MASK 64 #define DDRE_DDRE7_MASK 128 /*** DDRF - Data Direction Register F; 0x0000000D ***/ typedef union { byte Byte; struct { byte DDRF0 :1; /* Data Direction Register F Bit 0 */ byte DDRF1 :1; /* Data Direction Register F Bit 1 */ byte DDRF2 :1; /* Data Direction Register F Bit 2 */ byte DDRF3 :1; /* Data Direction Register F Bit 3 */ byte DDRF4 :1; /* Data Direction Register F Bit 4 */ byte DDRF5 :1; /* Data Direction Register F Bit 5 */ byte DDRF6 :1; /* Data Direction Register F Bit 6 */ byte :1; } Bits; struct { byte grpDDRF :7; byte :1; } MergedBits; } DDRFSTR; extern volatile DDRFSTR _DDRF @0x0000000D; #define DDRF _DDRF.Byte #define DDRF_DDRF0 _DDRF.Bits.DDRF0 #define DDRF_DDRF1 _DDRF.Bits.DDRF1 #define DDRF_DDRF2 _DDRF.Bits.DDRF2 #define DDRF_DDRF3 _DDRF.Bits.DDRF3 #define DDRF_DDRF4 _DDRF.Bits.DDRF4 #define DDRF_DDRF5 _DDRF.Bits.DDRF5 #define DDRF_DDRF6 _DDRF.Bits.DDRF6 #define DDRF_DDRF _DDRF.MergedBits.grpDDRF #define DDRF_DDRF0_MASK 1 #define DDRF_DDRF1_MASK 2 #define DDRF_DDRF2_MASK 4 #define DDRF_DDRF3_MASK 8 #define DDRF_DDRF4_MASK 16 #define DDRF_DDRF5_MASK 32 #define DDRF_DDRF6_MASK 64 #define DDRF_DDRF_MASK 127 #define DDRF_DDRF_BITNUM 0 /*** DDRG - Data Direction Register G; 0x0000000E ***/ typedef union { byte Byte; struct { byte DDRG0 :1; /* Data Direction Register G Bit 0 */ byte DDRG1 :1; /* Data Direction Register G Bit 1 */ byte DDRG2 :1; /* Data Direction Register G Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRG :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DDRGSTR; extern volatile DDRGSTR _DDRG @0x0000000E; #define DDRG _DDRG.Byte #define DDRG_DDRG0 _DDRG.Bits.DDRG0 #define DDRG_DDRG1 _DDRG.Bits.DDRG1 #define DDRG_DDRG2 _DDRG.Bits.DDRG2 #define DDRG_DDRG _DDRG.MergedBits.grpDDRG #define DDRG_DDRG0_MASK 1 #define DDRG_DDRG1_MASK 2 #define DDRG_DDRG2_MASK 4 #define DDRG_DDRG_MASK 7 #define DDRG_DDRG_BITNUM 0 /*** DDRH - Data Direction Register H; 0x0000000F ***/ typedef union { byte Byte; struct { byte DDRH0 :1; /* Data Direction Register H Bit 0 */ byte DDRH1 :1; /* Data Direction Register H Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRH :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DDRHSTR; extern volatile DDRHSTR _DDRH @0x0000000F; #define DDRH _DDRH.Byte #define DDRH_DDRH0 _DDRH.Bits.DDRH0 #define DDRH_DDRH1 _DDRH.Bits.DDRH1 #define DDRH_DDRH _DDRH.MergedBits.grpDDRH #define DDRH_DDRH0_MASK 1 #define DDRH_DDRH1_MASK 2 #define DDRH_DDRH_MASK 3 #define DDRH_DDRH_BITNUM 0 /*** SPCR - SPI Control Register; 0x00000010 ***/ typedef union { byte Byte; struct { byte SPTIE :1; /* SPI Transmit Interrupt Enable Bit */ byte SPE :1; /* SPI Enable Bit */ byte SPWOM :1; /* SPI Wired-OR Mode Bit */ byte CPHA :1; /* Clock Phase Bit */ byte CPOL :1; /* Clock Polarity Bit */ byte SPMSTR :1; /* SPI Master Bit */ byte :1; byte SPRIE :1; /* SPI Receiver Interrupt Enable Bit */ } Bits; } SPCRSTR; extern volatile SPCRSTR _SPCR @0x00000010; #define SPCR _SPCR.Byte #define SPCR_SPTIE _SPCR.Bits.SPTIE #define SPCR_SPE _SPCR.Bits.SPE #define SPCR_SPWOM _SPCR.Bits.SPWOM #define SPCR_CPHA _SPCR.Bits.CPHA #define SPCR_CPOL _SPCR.Bits.CPOL #define SPCR_SPMSTR _SPCR.Bits.SPMSTR #define SPCR_SPRIE _SPCR.Bits.SPRIE #define SPCR_SPTIE_MASK 1 #define SPCR_SPE_MASK 2 #define SPCR_SPWOM_MASK 4 #define SPCR_CPHA_MASK 8 #define SPCR_CPOL_MASK 16 #define SPCR_SPMSTR_MASK 32 #define SPCR_SPRIE_MASK 128 /*** SPSCR - SPI Status and Control Register; 0x00000011 ***/ typedef union { byte Byte; struct { byte SPR0 :1; /* SPI Baud Rate Select Bit 0 */ byte SPR1 :1; /* SPI Baud Rate Select Bit 1 */ byte MODFEN :1; /* Mode Fault Enable Bit */ byte SPTE :1; /* SPI Transmitter Empty Bit */ byte MODF :1; /* Mode Fault Bit */ byte OVRF :1; /* Overflow Bit */ byte ERRIE :1; /* Error Interrupt Enable Bit */ byte SPRF :1; /* SPI Receiver Full Bit */ } Bits; struct { byte grpSPR :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SPSCRSTR; extern volatile SPSCRSTR _SPSCR @0x00000011; #define SPSCR _SPSCR.Byte #define SPSCR_SPR0 _SPSCR.Bits.SPR0 #define SPSCR_SPR1 _SPSCR.Bits.SPR1 #define SPSCR_MODFEN _SPSCR.Bits.MODFEN #define SPSCR_SPTE _SPSCR.Bits.SPTE #define SPSCR_MODF _SPSCR.Bits.MODF #define SPSCR_OVRF _SPSCR.Bits.OVRF #define SPSCR_ERRIE _SPSCR.Bits.ERRIE #define SPSCR_SPRF _SPSCR.Bits.SPRF #define SPSCR_SPR _SPSCR.MergedBits.grpSPR #define SPSCR_SPR0_MASK 1 #define SPSCR_SPR1_MASK 2 #define SPSCR_MODFEN_MASK 4 #define SPSCR_SPTE_MASK 8 #define SPSCR_MODF_MASK 16 #define SPSCR_OVRF_MASK 32 #define SPSCR_ERRIE_MASK 64 #define SPSCR_SPRF_MASK 128 #define SPSCR_SPR_MASK 3 #define SPSCR_SPR_BITNUM 0 /*** SPDR - SPI Data Register; 0x00000012 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SPDRSTR; extern volatile SPDRSTR _SPDR @0x00000012; #define SPDR _SPDR.Byte #define SPDR_R0_T0 _SPDR.Bits.R0_T0 #define SPDR_R1_T1 _SPDR.Bits.R1_T1 #define SPDR_R2_T2 _SPDR.Bits.R2_T2 #define SPDR_R3_T3 _SPDR.Bits.R3_T3 #define SPDR_R4_T4 _SPDR.Bits.R4_T4 #define SPDR_R5_T5 _SPDR.Bits.R5_T5 #define SPDR_R6_T6 _SPDR.Bits.R6_T6 #define SPDR_R7_T7 _SPDR.Bits.R7_T7 #define SPDR_R0_T0_MASK 1 #define SPDR_R1_T1_MASK 2 #define SPDR_R2_T2_MASK 4 #define SPDR_R3_T3_MASK 8 #define SPDR_R4_T4_MASK 16 #define SPDR_R5_T5_MASK 32 #define SPDR_R6_T6_MASK 64 #define SPDR_R7_T7_MASK 128 /*** SCC1 - SCI Control Register 1; 0x00000013 ***/ typedef union { byte Byte; struct { byte PTY :1; /* Parity Bit */ byte PEN :1; /* Parity Enable Bit */ byte ILTY :1; /* Idle Line Type Bit */ byte WAKE :1; /* Wakeup Condition Bit */ byte M :1; /* Mode (Character Length) Bit */ byte TXINV :1; /* Transmit Inversion Bit */ byte ENSCI :1; /* Enable SCI Bit */ byte LOOPS :1; /* Loop Mode Select Bit */ } Bits; } SCC1STR; extern volatile SCC1STR _SCC1 @0x00000013; #define SCC1 _SCC1.Byte #define SCC1_PTY _SCC1.Bits.PTY #define SCC1_PEN _SCC1.Bits.PEN #define SCC1_ILTY _SCC1.Bits.ILTY #define SCC1_WAKE _SCC1.Bits.WAKE #define SCC1_M _SCC1.Bits.M #define SCC1_TXINV _SCC1.Bits.TXINV #define SCC1_ENSCI _SCC1.Bits.ENSCI #define SCC1_LOOPS _SCC1.Bits.LOOPS #define SCC1_PTY_MASK 1 #define SCC1_PEN_MASK 2 #define SCC1_ILTY_MASK 4 #define SCC1_WAKE_MASK 8 #define SCC1_M_MASK 16 #define SCC1_TXINV_MASK 32 #define SCC1_ENSCI_MASK 64 #define SCC1_LOOPS_MASK 128 /*** SCC2 - SCI Control Register 2; 0x00000014 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break Bit */ byte RWU :1; /* Receiver Wakeup Bit */ byte RE :1; /* Receiver Enable Bit */ byte TE :1; /* Transmitter Enable Bit */ byte ILIE :1; /* Idle Line Interrupt Enable Bit */ byte SCRIE :1; /* SCI Receive Interrupt Enable Bit */ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ byte SCTIE :1; /* SCI Transmit Interrupt Enable Bit */ } Bits; } SCC2STR; extern volatile SCC2STR _SCC2 @0x00000014; #define SCC2 _SCC2.Byte #define SCC2_SBK _SCC2.Bits.SBK #define SCC2_RWU _SCC2.Bits.RWU #define SCC2_RE _SCC2.Bits.RE #define SCC2_TE _SCC2.Bits.TE #define SCC2_ILIE _SCC2.Bits.ILIE #define SCC2_SCRIE _SCC2.Bits.SCRIE #define SCC2_TCIE _SCC2.Bits.TCIE #define SCC2_SCTIE _SCC2.Bits.SCTIE #define SCC2_SBK_MASK 1 #define SCC2_RWU_MASK 2 #define SCC2_RE_MASK 4 #define SCC2_TE_MASK 8 #define SCC2_ILIE_MASK 16 #define SCC2_SCRIE_MASK 32 #define SCC2_TCIE_MASK 64 #define SCC2_SCTIE_MASK 128 /*** SCC3 - SCI Control Register 3; 0x00000015 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Receiver Parity Error Interrupt Enable Bit */ byte FEIE :1; /* Receiver Framing Error Interrupt Enable Bit */ byte NEIE :1; /* Receiver Noise Error Interrupt Enable Bit */ byte ORIE :1; /* Receiver Overrun Interrupt Enable Bit */ byte :1; byte :1; byte T8 :1; /* Transmitted Bit 8 */ byte R8 :1; /* Received Bit 8 */ } Bits; } SCC3STR; extern volatile SCC3STR _SCC3 @0x00000015; #define SCC3 _SCC3.Byte #define SCC3_PEIE _SCC3.Bits.PEIE #define SCC3_FEIE _SCC3.Bits.FEIE #define SCC3_NEIE _SCC3.Bits.NEIE #define SCC3_ORIE _SCC3.Bits.ORIE #define SCC3_T8 _SCC3.Bits.T8 #define SCC3_R8 _SCC3.Bits.R8 #define SCC3_PEIE_MASK 1 #define SCC3_FEIE_MASK 2 #define SCC3_NEIE_MASK 4 #define SCC3_ORIE_MASK 8 #define SCC3_T8_MASK 64 #define SCC3_R8_MASK 128 /*** SCS1 - SCI Status Register 1; 0x00000016 ***/ typedef union { byte Byte; struct { byte PE :1; /* Receiver Parity Error Bit */ byte FE :1; /* Receiver Framing Error Bit */ byte NF :1; /* Receiver Noise Flag Bit */ byte OR :1; /* Receiver Overrun Bit */ byte IDLE :1; /* Receiver Idle Bit */ byte SCRF :1; /* SCI Receiver Full Bit */ byte TC :1; /* Transmission Complete Bit */ byte SCTE :1; /* SCI Transmitter Empty Bit */ } Bits; } SCS1STR; extern volatile SCS1STR _SCS1 @0x00000016; #define SCS1 _SCS1.Byte #define SCS1_PE _SCS1.Bits.PE #define SCS1_FE _SCS1.Bits.FE #define SCS1_NF _SCS1.Bits.NF #define SCS1_OR _SCS1.Bits.OR #define SCS1_IDLE _SCS1.Bits.IDLE #define SCS1_SCRF _SCS1.Bits.SCRF #define SCS1_TC _SCS1.Bits.TC #define SCS1_SCTE _SCS1.Bits.SCTE #define SCS1_PE_MASK 1 #define SCS1_FE_MASK 2 #define SCS1_NF_MASK 4 #define SCS1_OR_MASK 8 #define SCS1_IDLE_MASK 16 #define SCS1_SCRF_MASK 32 #define SCS1_TC_MASK 64 #define SCS1_SCTE_MASK 128 /*** SCS2 - SCI Status Register 2; 0x00000017 ***/ typedef union { byte Byte; struct { byte RPF :1; /* Reception in Progress Flag Bit */ byte BKF :1; /* Break Flag Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SCS2STR; extern volatile SCS2STR _SCS2 @0x00000017; #define SCS2 _SCS2.Byte #define SCS2_RPF _SCS2.Bits.RPF #define SCS2_BKF _SCS2.Bits.BKF #define SCS2_RPF_MASK 1 #define SCS2_BKF_MASK 2 /*** SCDR - SCI Data Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCDRSTR; extern volatile SCDRSTR _SCDR @0x00000018; #define SCDR _SCDR.Byte #define SCDR_R0_T0 _SCDR.Bits.R0_T0 #define SCDR_R1_T1 _SCDR.Bits.R1_T1 #define SCDR_R2_T2 _SCDR.Bits.R2_T2 #define SCDR_R3_T3 _SCDR.Bits.R3_T3 #define SCDR_R4_T4 _SCDR.Bits.R4_T4 #define SCDR_R5_T5 _SCDR.Bits.R5_T5 #define SCDR_R6_T6 _SCDR.Bits.R6_T6 #define SCDR_R7_T7 _SCDR.Bits.R7_T7 #define SCDR_R0_T0_MASK 1 #define SCDR_R1_T1_MASK 2 #define SCDR_R2_T2_MASK 4 #define SCDR_R3_T3_MASK 8 #define SCDR_R4_T4_MASK 16 #define SCDR_R5_T5_MASK 32 #define SCDR_R6_T6_MASK 64 #define SCDR_R7_T7_MASK 128 /*** SCBR - SCI Baud Rate Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte SCR0 :1; /* SCI Baud Rate Select Bit 0 */ byte SCR1 :1; /* SCI Baud Rate Select Bit 1 */ byte SCR2 :1; /* SCI Baud Rate Select Bit 2 */ byte :1; byte SCP0 :1; /* SCI Baud Rate Prescaler Bit 0 */ byte SCP1 :1; /* SCI Baud Rate Prescaler Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpSCR :3; byte :1; byte grpSCP :2; byte :1; byte :1; } MergedBits; } SCBRSTR; extern volatile SCBRSTR _SCBR @0x00000019; #define SCBR _SCBR.Byte #define SCBR_SCR0 _SCBR.Bits.SCR0 #define SCBR_SCR1 _SCBR.Bits.SCR1 #define SCBR_SCR2 _SCBR.Bits.SCR2 #define SCBR_SCP0 _SCBR.Bits.SCP0 #define SCBR_SCP1 _SCBR.Bits.SCP1 #define SCBR_SCR _SCBR.MergedBits.grpSCR #define SCBR_SCP _SCBR.MergedBits.grpSCP #define SCBR_SCR0_MASK 1 #define SCBR_SCR1_MASK 2 #define SCBR_SCR2_MASK 4 #define SCBR_SCP0_MASK 16 #define SCBR_SCP1_MASK 32 #define SCBR_SCR_MASK 7 #define SCBR_SCR_BITNUM 0 #define SCBR_SCP_MASK 48 #define SCBR_SCP_BITNUM 4 /*** ISCR - IRQ Status and Control Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte MODE :1; /* IRQ Edge/Level Select Bit */ byte IMASK :1; /* IRQ Interrupt Mask Bit */ byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */ byte IRQF :1; /* IRQ Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } ISCRSTR; extern volatile ISCRSTR _ISCR @0x0000001A; #define ISCR _ISCR.Byte #define ISCR_MODE _ISCR.Bits.MODE #define ISCR_IMASK _ISCR.Bits.IMASK #define ISCR_ACK _ISCR.Bits.ACK #define ISCR_IRQF _ISCR.Bits.IRQF #define ISCR_MODE_MASK 1 #define ISCR_IMASK_MASK 2 #define ISCR_ACK_MASK 4 #define ISCR_IRQF_MASK 8 /*** KBSCR - Keyboard Status and Control Register; 0x0000001B ***/ typedef union { byte Byte; struct { byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */ byte IMASKK :1; /* Keyboard Interrupt Mask Bit */ byte ACKK :1; /* Keyboard Acknowledge Bit */ byte KEYF :1; /* Keyboard Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBSCRSTR; extern volatile KBSCRSTR _KBSCR @0x0000001B; #define KBSCR _KBSCR.Byte #define KBSCR_MODEK _KBSCR.Bits.MODEK #define KBSCR_IMASKK _KBSCR.Bits.IMASKK #define KBSCR_ACKK _KBSCR.Bits.ACKK #define KBSCR_KEYF _KBSCR.Bits.KEYF #define KBSCR_MODEK_MASK 1 #define KBSCR_IMASKK_MASK 2 #define KBSCR_ACKK_MASK 4 #define KBSCR_KEYF_MASK 8 /*** PCTL - PLL Control Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte BCS :1; /* Base Clock Select Bit */ byte PLLON :1; /* PLL On Bit */ byte PLLF :1; /* PLL Flag Bit */ byte PLLIE :1; /* PLL Interrupt Enable Bit */ } Bits; } PCTLSTR; extern volatile PCTLSTR _PCTL @0x0000001C; #define PCTL _PCTL.Byte #define PCTL_BCS _PCTL.Bits.BCS #define PCTL_PLLON _PCTL.Bits.PLLON #define PCTL_PLLF _PCTL.Bits.PLLF #define PCTL_PLLIE _PCTL.Bits.PLLIE #define PCTL_BCS_MASK 16 #define PCTL_PLLON_MASK 32 #define PCTL_PLLF_MASK 64 #define PCTL_PLLIE_MASK 128 /*** PBWC - PLL Bandwidth Control Register; 0x0000001D ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte XLD :1; /* Crystal Loss Detect Bit */ byte ACQ :1; /* Acquisition Mode Bit */ byte LOCK :1; /* Lock Indicator Bit */ byte AUTO :1; /* Automatic Bandwidth Control Bit */ } Bits; } PBWCSTR; extern volatile PBWCSTR _PBWC @0x0000001D; #define PBWC _PBWC.Byte #define PBWC_XLD _PBWC.Bits.XLD #define PBWC_ACQ _PBWC.Bits.ACQ #define PBWC_LOCK _PBWC.Bits.LOCK #define PBWC_AUTO _PBWC.Bits.AUTO #define PBWC_XLD_MASK 16 #define PBWC_ACQ_MASK 32 #define PBWC_LOCK_MASK 64 #define PBWC_AUTO_MASK 128 /*** PPG - PLL Programming Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte VRS4 :1; /* VCO Range Select Bit 4 */ byte VRS5 :1; /* VCO Range Select Bit 5 */ byte VRS6 :1; /* VCO Range Select Bit 6 */ byte VRS7 :1; /* VCO Range Select Bit 7 */ byte MUL4 :1; /* Multiplier Select Bit 4 */ byte MUL5 :1; /* Multiplier Select Bit 5 */ byte MUL6 :1; /* Multiplier Select Bit 6 */ byte MUL7 :1; /* Multiplier Select Bit 7 */ } Bits; struct { byte grpVRS_4 :4; byte grpMUL_4 :4; } MergedBits; } PPGSTR; extern volatile PPGSTR _PPG @0x0000001E; #define PPG _PPG.Byte #define PPG_VRS4 _PPG.Bits.VRS4 #define PPG_VRS5 _PPG.Bits.VRS5 #define PPG_VRS6 _PPG.Bits.VRS6 #define PPG_VRS7 _PPG.Bits.VRS7 #define PPG_MUL4 _PPG.Bits.MUL4 #define PPG_MUL5 _PPG.Bits.MUL5 #define PPG_MUL6 _PPG.Bits.MUL6 #define PPG_MUL7 _PPG.Bits.MUL7 #define PPG_VRS_4 _PPG.MergedBits.grpVRS_4 #define PPG_MUL_4 _PPG.MergedBits.grpMUL_4 #define PPG_VRS PPG_VRS_4 #define PPG_MUL PPG_MUL_4 #define PPG_VRS4_MASK 1 #define PPG_VRS5_MASK 2 #define PPG_VRS6_MASK 4 #define PPG_VRS7_MASK 8 #define PPG_MUL4_MASK 16 #define PPG_MUL5_MASK 32 #define PPG_MUL6_MASK 64 #define PPG_MUL7_MASK 128 #define PPG_VRS_4_MASK 15 #define PPG_VRS_4_BITNUM 0 #define PPG_MUL_4_MASK 240 #define PPG_MUL_4_BITNUM 4 /*** CONFIG1 - Configuration Register; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte COPL :1; /* COP Long Timeout */ byte SSREC :1; /* Short Stop Recovery Bit */ byte LVIPWR :1; /* LVI Power Enable Bit */ byte LVIRST :1; /* LVI Reset Enable Bit */ byte :1; byte LVISTOP :1; /* LVI Stop Mode Enable Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_COPL _CONFIG1.Bits.COPL #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVIPWR _CONFIG1.Bits.LVIPWR #define CONFIG1_LVIRST _CONFIG1.Bits.LVIRST #define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_COPL_MASK 4 #define CONFIG1_SSREC_MASK 8 #define CONFIG1_LVIPWR_MASK 16 #define CONFIG1_LVIRST_MASK 32 #define CONFIG1_LVISTOP_MASK 128 /*** TASC - TIMA Status and Control Register; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIMA Reset Bit */ byte TSTOP :1; /* TIMA Stop Bit */ byte TOIE :1; /* TIMA Overflow Interrupt Enable Bit */ byte TOF :1; /* TIMA Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TASCSTR; extern volatile TASCSTR _TASC @0x00000020; #define TASC _TASC.Byte #define TASC_PS0 _TASC.Bits.PS0 #define TASC_PS1 _TASC.Bits.PS1 #define TASC_PS2 _TASC.Bits.PS2 #define TASC_TRST _TASC.Bits.TRST #define TASC_TSTOP _TASC.Bits.TSTOP #define TASC_TOIE _TASC.Bits.TOIE #define TASC_TOF _TASC.Bits.TOF #define TASC_PS _TASC.MergedBits.grpPS #define TASC_PS0_MASK 1 #define TASC_PS1_MASK 2 #define TASC_PS2_MASK 4 #define TASC_TRST_MASK 16 #define TASC_TSTOP_MASK 32 #define TASC_TOIE_MASK 64 #define TASC_TOF_MASK 128 #define TASC_PS_MASK 7 #define TASC_PS_BITNUM 0 /*** KBIER - Keyboard Interrupt Enable Register; 0x00000021 ***/ typedef union { byte Byte; struct { byte KBIE0 :1; /* Keyboard Interrupt Enable Bit 0 */ byte KBIE1 :1; /* Keyboard Interrupt Enable Bit 1 */ byte KBIE2 :1; /* Keyboard Interrupt Enable Bit 2 */ byte KBIE3 :1; /* Keyboard Interrupt Enable Bit 3 */ byte KBIE4 :1; /* Keyboard Interrupt Enable Bit 4 */ byte :1; byte :1; byte :1; } Bits; struct { byte grpKBIE :5; byte :1; byte :1; byte :1; } MergedBits; } KBIERSTR; extern volatile KBIERSTR _KBIER @0x00000021; #define KBIER _KBIER.Byte #define KBIER_KBIE0 _KBIER.Bits.KBIE0 #define KBIER_KBIE1 _KBIER.Bits.KBIE1 #define KBIER_KBIE2 _KBIER.Bits.KBIE2 #define KBIER_KBIE3 _KBIER.Bits.KBIE3 #define KBIER_KBIE4 _KBIER.Bits.KBIE4 #define KBIER_KBIE _KBIER.MergedBits.grpKBIE #define KBIER_KBIE0_MASK 1 #define KBIER_KBIE1_MASK 2 #define KBIER_KBIE2_MASK 4 #define KBIER_KBIE3_MASK 8 #define KBIER_KBIE4_MASK 16 #define KBIER_KBIE_MASK 31 #define KBIER_KBIE_BITNUM 0 /*** TACNT - TIMA Counter Register; 0x00000022 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACNTH - TIMA Counter Register; 0x00000022 ***/ union { byte Byte; } TACNTHSTR; #define TACNTH _TACNT.Overlap_STR.TACNTHSTR.Byte /*** TACNTL - TIMA Counter Register; 0x00000023 ***/ union { byte Byte; } TACNTLSTR; #define TACNTL _TACNT.Overlap_STR.TACNTLSTR.Byte } Overlap_STR; } TACNTSTR; extern volatile TACNTSTR _TACNT @0x00000022; #define TACNT _TACNT.Word /*** TAMOD - TIMA Counter Modulo Register; 0x00000024 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TAMODH - TIMA Counter Modulo Register; 0x00000024 ***/ union { byte Byte; } TAMODHSTR; #define TAMODH _TAMOD.Overlap_STR.TAMODHSTR.Byte /*** TAMODL - TIMA Counter Modulo Register; 0x00000025 ***/ union { byte Byte; } TAMODLSTR; #define TAMODL _TAMOD.Overlap_STR.TAMODLSTR.Byte } Overlap_STR; } TAMODSTR; extern volatile TAMODSTR _TAMOD @0x00000024; #define TAMOD _TAMOD.Word /*** TASC0 - TIMA Channel Status and Control Register; 0x00000026 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit */ byte ELS0B :1; /* Edge/Level Select Bit */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TASC0STR; extern volatile TASC0STR _TASC0 @0x00000026; #define TASC0 _TASC0.Byte #define TASC0_CH0MAX _TASC0.Bits.CH0MAX #define TASC0_TOV0 _TASC0.Bits.TOV0 #define TASC0_ELS0A _TASC0.Bits.ELS0A #define TASC0_ELS0B _TASC0.Bits.ELS0B #define TASC0_MS0A _TASC0.Bits.MS0A #define TASC0_MS0B _TASC0.Bits.MS0B #define TASC0_CH0IE _TASC0.Bits.CH0IE #define TASC0_CH0F _TASC0.Bits.CH0F #define TASC0_ELS0x _TASC0.MergedBits.grpELS0x #define TASC0_MS0x _TASC0.MergedBits.grpMS0x #define TASC0_CH0MAX_MASK 1 #define TASC0_TOV0_MASK 2 #define TASC0_ELS0A_MASK 4 #define TASC0_ELS0B_MASK 8 #define TASC0_MS0A_MASK 16 #define TASC0_MS0B_MASK 32 #define TASC0_CH0IE_MASK 64 #define TASC0_CH0F_MASK 128 #define TASC0_ELS0x_MASK 12 #define TASC0_ELS0x_BITNUM 2 #define TASC0_MS0x_MASK 48 #define TASC0_MS0x_BITNUM 4 /*** TACH0 - TIMA Channel Register; 0x00000027 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH0H - TIMA Channel Register; 0x00000027 ***/ union { byte Byte; } TACH0HSTR; #define TACH0H _TACH0.Overlap_STR.TACH0HSTR.Byte /*** TACH0L - TIMA Channel Register; 0x00000028 ***/ union { byte Byte; } TACH0LSTR; #define TACH0L _TACH0.Overlap_STR.TACH0LSTR.Byte } Overlap_STR; } TACH0STR; extern volatile TACH0STR _TACH0 @0x00000027; #define TACH0 _TACH0.Word /*** TASC1 - TIMA Channel Status and Control Register; 0x00000029 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit */ byte ELS1B :1; /* Edge/Level Select Bit */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } TASC1STR; extern volatile TASC1STR _TASC1 @0x00000029; #define TASC1 _TASC1.Byte #define TASC1_CH1MAX _TASC1.Bits.CH1MAX #define TASC1_TOV1 _TASC1.Bits.TOV1 #define TASC1_ELS1A _TASC1.Bits.ELS1A #define TASC1_ELS1B _TASC1.Bits.ELS1B #define TASC1_MS1A _TASC1.Bits.MS1A #define TASC1_CH1IE _TASC1.Bits.CH1IE #define TASC1_CH1F _TASC1.Bits.CH1F #define TASC1_ELS1x _TASC1.MergedBits.grpELS1x #define TASC1_CH1MAX_MASK 1 #define TASC1_TOV1_MASK 2 #define TASC1_ELS1A_MASK 4 #define TASC1_ELS1B_MASK 8 #define TASC1_MS1A_MASK 16 #define TASC1_CH1IE_MASK 64 #define TASC1_CH1F_MASK 128 #define TASC1_ELS1x_MASK 12 #define TASC1_ELS1x_BITNUM 2 /*** TACH1 - TIMA Channel Register; 0x0000002A ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH1H - TIMA Channel Register; 0x0000002A ***/ union { byte Byte; } TACH1HSTR; #define TACH1H _TACH1.Overlap_STR.TACH1HSTR.Byte /*** TACH1L - TIMA Channel Register; 0x0000002B ***/ union { byte Byte; } TACH1LSTR; #define TACH1L _TACH1.Overlap_STR.TACH1LSTR.Byte } Overlap_STR; } TACH1STR; extern volatile TACH1STR _TACH1 @0x0000002A; #define TACH1 _TACH1.Word /*** TASC2 - TIMA Channel Status and Control Register; 0x0000002C ***/ typedef union { byte Byte; struct { byte CH2MAX :1; /* Channel 2 Maximum Duty Cycle Bit */ byte TOV2 :1; /* Toggle-On-Overflow Bit */ byte ELS2A :1; /* Edge_Level Select Bits */ byte ELS2B :1; /* Edge_Level Select Bits */ byte MS2A :1; /* Mode Select Bit A */ byte MS2B :1; /* Mode Select Bit B */ byte CH2IE :1; /* Channel 2 Interrupt Enable Bit */ byte CH2F :1; /* Channel 2 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_2 :1; byte grpELS2x :2; byte grpMS2x :2; byte :1; byte :1; } MergedBits; } TASC2STR; extern volatile TASC2STR _TASC2 @0x0000002C; #define TASC2 _TASC2.Byte #define TASC2_CH2MAX _TASC2.Bits.CH2MAX #define TASC2_TOV2 _TASC2.Bits.TOV2 #define TASC2_ELS2A _TASC2.Bits.ELS2A #define TASC2_ELS2B _TASC2.Bits.ELS2B #define TASC2_MS2A _TASC2.Bits.MS2A #define TASC2_MS2B _TASC2.Bits.MS2B #define TASC2_CH2IE _TASC2.Bits.CH2IE #define TASC2_CH2F _TASC2.Bits.CH2F #define TASC2_ELS2x _TASC2.MergedBits.grpELS2x #define TASC2_MS2x _TASC2.MergedBits.grpMS2x #define TASC2_CH2MAX_MASK 1 #define TASC2_TOV2_MASK 2 #define TASC2_ELS2A_MASK 4 #define TASC2_ELS2B_MASK 8 #define TASC2_MS2A_MASK 16 #define TASC2_MS2B_MASK 32 #define TASC2_CH2IE_MASK 64 #define TASC2_CH2F_MASK 128 #define TASC2_ELS2x_MASK 12 #define TASC2_ELS2x_BITNUM 2 #define TASC2_MS2x_MASK 48 #define TASC2_MS2x_BITNUM 4 /*** TACH2 - TIMA Channel Register; 0x0000002D ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH2H - TIMA Channel Register; 0x0000002D ***/ union { byte Byte; } TACH2HSTR; #define TACH2H _TACH2.Overlap_STR.TACH2HSTR.Byte /*** TACH2L - TIMA Channel Register; 0x0000002E ***/ union { byte Byte; } TACH2LSTR; #define TACH2L _TACH2.Overlap_STR.TACH2LSTR.Byte } Overlap_STR; } TACH2STR; extern volatile TACH2STR _TACH2 @0x0000002D; #define TACH2 _TACH2.Word /*** TASC3 - TIMA Channel Status and Control Register; 0x0000002F ***/ typedef union { byte Byte; struct { byte CH3MAX :1; /* Channel 3 Maximum Duty Cycle Bit */ byte TOV3 :1; /* Toggle-On-Overflow Bit */ byte ELS3A :1; /* Edge_Level Select Bits */ byte ELS3B :1; /* Edge_Level Select Bits */ byte MS3A :1; /* Mode Select Bit A */ byte :1; byte CH3IE :1; /* Channel 3 Interrupt Enable Bit */ byte CH3F :1; /* Channel 3 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_3 :1; byte grpELS3x :2; byte grpMS3x :1; byte :1; byte :1; byte :1; } MergedBits; } TASC3STR; extern volatile TASC3STR _TASC3 @0x0000002F; #define TASC3 _TASC3.Byte #define TASC3_CH3MAX _TASC3.Bits.CH3MAX #define TASC3_TOV3 _TASC3.Bits.TOV3 #define TASC3_ELS3A _TASC3.Bits.ELS3A #define TASC3_ELS3B _TASC3.Bits.ELS3B #define TASC3_MS3A _TASC3.Bits.MS3A #define TASC3_CH3IE _TASC3.Bits.CH3IE #define TASC3_CH3F _TASC3.Bits.CH3F #define TASC3_ELS3x _TASC3.MergedBits.grpELS3x #define TASC3_CH3MAX_MASK 1 #define TASC3_TOV3_MASK 2 #define TASC3_ELS3A_MASK 4 #define TASC3_ELS3B_MASK 8 #define TASC3_MS3A_MASK 16 #define TASC3_CH3IE_MASK 64 #define TASC3_CH3F_MASK 128 #define TASC3_ELS3x_MASK 12 #define TASC3_ELS3x_BITNUM 2 /*** TACH3 - TIMA Channel Register; 0x00000030 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH3H - TIMA Channel Register; 0x00000030 ***/ union { byte Byte; } TACH3HSTR; #define TACH3H _TACH3.Overlap_STR.TACH3HSTR.Byte /*** TACH3L - TIMA Channel Register; 0x00000031 ***/ union { byte Byte; } TACH3LSTR; #define TACH3L _TACH3.Overlap_STR.TACH3LSTR.Byte } Overlap_STR; } TACH3STR; extern volatile TACH3STR _TACH3 @0x00000030; #define TACH3 _TACH3.Word /*** TASC4 - TIMA Channel Status and Control Register; 0x00000032 ***/ typedef union { byte Byte; struct { byte CH4MAX :1; /* Channel 4 Maximum Duty Cycle Bit */ byte TOV4 :1; /* Toggle-On-Overflow Bit */ byte ELS4A :1; /* Edge_Level Select Bits */ byte ELS4B :1; /* Edge_Level Select Bits */ byte MS4A :1; /* Mode Select Bit A */ byte MS4B :1; /* Mode Select Bit B */ byte CH4IE :1; /* Channel 4 Interrupt Enable Bit */ byte CH4F :1; /* Channel 4 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_4 :1; byte grpELS4x :2; byte grpMS4x :2; byte :1; byte :1; } MergedBits; } TASC4STR; extern volatile TASC4STR _TASC4 @0x00000032; #define TASC4 _TASC4.Byte #define TASC4_CH4MAX _TASC4.Bits.CH4MAX #define TASC4_TOV4 _TASC4.Bits.TOV4 #define TASC4_ELS4A _TASC4.Bits.ELS4A #define TASC4_ELS4B _TASC4.Bits.ELS4B #define TASC4_MS4A _TASC4.Bits.MS4A #define TASC4_MS4B _TASC4.Bits.MS4B #define TASC4_CH4IE _TASC4.Bits.CH4IE #define TASC4_CH4F _TASC4.Bits.CH4F #define TASC4_ELS4x _TASC4.MergedBits.grpELS4x #define TASC4_MS4x _TASC4.MergedBits.grpMS4x #define TASC4_CH4MAX_MASK 1 #define TASC4_TOV4_MASK 2 #define TASC4_ELS4A_MASK 4 #define TASC4_ELS4B_MASK 8 #define TASC4_MS4A_MASK 16 #define TASC4_MS4B_MASK 32 #define TASC4_CH4IE_MASK 64 #define TASC4_CH4F_MASK 128 #define TASC4_ELS4x_MASK 12 #define TASC4_ELS4x_BITNUM 2 #define TASC4_MS4x_MASK 48 #define TASC4_MS4x_BITNUM 4 /*** TACH4 - TIMA Channel Register; 0x00000033 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH4H - TIMA Channel Register; 0x00000033 ***/ union { byte Byte; } TACH4HSTR; #define TACH4H _TACH4.Overlap_STR.TACH4HSTR.Byte /*** TACH4L - TIMA Channel Register; 0x00000034 ***/ union { byte Byte; } TACH4LSTR; #define TACH4L _TACH4.Overlap_STR.TACH4LSTR.Byte } Overlap_STR; } TACH4STR; extern volatile TACH4STR _TACH4 @0x00000033; #define TACH4 _TACH4.Word /*** TASC5 - TIMA Channel Status and Control Register; 0x00000035 ***/ typedef union { byte Byte; struct { byte CH5MAX :1; /* Channel 5 Maximum Duty Cycle Bit */ byte TOV5 :1; /* Toggle-On-Overflow Bit */ byte ELS5A :1; /* Edge_Level Select Bits */ byte ELS5B :1; /* Edge_Level Select Bits */ byte MS5A :1; /* Mode Select Bit A */ byte :1; byte CH5IE :1; /* Channel 5 Interrupt Enable Bit */ byte CH5F :1; /* Channel 5 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_5 :1; byte grpELS5x :2; byte grpMS5x :1; byte :1; byte :1; byte :1; } MergedBits; } TASC5STR; extern volatile TASC5STR _TASC5 @0x00000035; #define TASC5 _TASC5.Byte #define TASC5_CH5MAX _TASC5.Bits.CH5MAX #define TASC5_TOV5 _TASC5.Bits.TOV5 #define TASC5_ELS5A _TASC5.Bits.ELS5A #define TASC5_ELS5B _TASC5.Bits.ELS5B #define TASC5_MS5A _TASC5.Bits.MS5A #define TASC5_CH5IE _TASC5.Bits.CH5IE #define TASC5_CH5F _TASC5.Bits.CH5F #define TASC5_ELS5x _TASC5.MergedBits.grpELS5x #define TASC5_CH5MAX_MASK 1 #define TASC5_TOV5_MASK 2 #define TASC5_ELS5A_MASK 4 #define TASC5_ELS5B_MASK 8 #define TASC5_MS5A_MASK 16 #define TASC5_CH5IE_MASK 64 #define TASC5_CH5F_MASK 128 #define TASC5_ELS5x_MASK 12 #define TASC5_ELS5x_BITNUM 2 /*** TACH5 - TIMA Channel Register; 0x00000036 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH5H - TIMA Channel Register; 0x00000036 ***/ union { byte Byte; } TACH5HSTR; #define TACH5H _TACH5.Overlap_STR.TACH5HSTR.Byte /*** TACH5L - TIMA Channel Register; 0x00000037 ***/ union { byte Byte; } TACH5LSTR; #define TACH5L _TACH5.Overlap_STR.TACH5LSTR.Byte } Overlap_STR; } TACH5STR; extern volatile TACH5STR _TACH5 @0x00000036; #define TACH5 _TACH5.Word /*** ADSCR - ADC Status and Control Register; 0x00000038 ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x00000038; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADR - ADC Data Register; 0x00000039 ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADRSTR; extern volatile ADRSTR _ADR @0x00000039; #define ADR _ADR.Byte #define ADR_AD0 _ADR.Bits.AD0 #define ADR_AD1 _ADR.Bits.AD1 #define ADR_AD2 _ADR.Bits.AD2 #define ADR_AD3 _ADR.Bits.AD3 #define ADR_AD4 _ADR.Bits.AD4 #define ADR_AD5 _ADR.Bits.AD5 #define ADR_AD6 _ADR.Bits.AD6 #define ADR_AD7 _ADR.Bits.AD7 #define ADR_AD0_MASK 1 #define ADR_AD1_MASK 2 #define ADR_AD2_MASK 4 #define ADR_AD3_MASK 8 #define ADR_AD4_MASK 16 #define ADR_AD5_MASK 32 #define ADR_AD6_MASK 64 #define ADR_AD7_MASK 128 /*** ADICLK - ADC Input Clock Register; 0x0000003A ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte ADICLK_BIT :1; /* ADC Input Clock Register Bit */ byte ADIV0 :1; /* ADC Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC Clock Prescaler Bit 1 */ byte ADIV2 :1; /* ADC Clock Prescaler Bit 2 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte grpADIV :3; } MergedBits; } ADICLKSTR; extern volatile ADICLKSTR _ADICLK @0x0000003A; #define ADICLK _ADICLK.Byte #define ADICLK_ADICLK_BIT _ADICLK.Bits.ADICLK_BIT #define ADICLK_ADIV0 _ADICLK.Bits.ADIV0 #define ADICLK_ADIV1 _ADICLK.Bits.ADIV1 #define ADICLK_ADIV2 _ADICLK.Bits.ADIV2 #define ADICLK_ADIV _ADICLK.MergedBits.grpADIV #define ADICLK_ADICLK_BIT_MASK 16 #define ADICLK_ADIV0_MASK 32 #define ADICLK_ADIV1_MASK 64 #define ADICLK_ADIV2_MASK 128 #define ADICLK_ADIV_MASK 224 #define ADICLK_ADIV_BITNUM 5 /*** TBSCR - TIMB Status and Control Register; 0x00000040 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit */ byte PS1 :1; /* Prescaler Select Bit */ byte PS2 :1; /* Prescaler Select Bit */ byte :1; byte TRST :1; /* TIMB Reset Bit */ byte TSTOP :1; /* TIMB Stop Bit */ byte TOIE :1; /* TIMB Overflow Interrupt Enable Bit */ byte TOF :1; /* TIMB Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TBSCRSTR; extern volatile TBSCRSTR _TBSCR @0x00000040; #define TBSCR _TBSCR.Byte #define TBSCR_PS0 _TBSCR.Bits.PS0 #define TBSCR_PS1 _TBSCR.Bits.PS1 #define TBSCR_PS2 _TBSCR.Bits.PS2 #define TBSCR_TRST _TBSCR.Bits.TRST #define TBSCR_TSTOP _TBSCR.Bits.TSTOP #define TBSCR_TOIE _TBSCR.Bits.TOIE #define TBSCR_TOF _TBSCR.Bits.TOF #define TBSCR_PS _TBSCR.MergedBits.grpPS #define TBSCR_PS0_MASK 1 #define TBSCR_PS1_MASK 2 #define TBSCR_PS2_MASK 4 #define TBSCR_TRST_MASK 16 #define TBSCR_TSTOP_MASK 32 #define TBSCR_TOIE_MASK 64 #define TBSCR_TOF_MASK 128 #define TBSCR_PS_MASK 7 #define TBSCR_PS_BITNUM 0 /*** TBCNT - TIMB Counter Register; 0x00000041 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TBCNTH - TIMB Counter Register; 0x00000041 ***/ union { byte Byte; } TBCNTHSTR; #define TBCNTH _TBCNT.Overlap_STR.TBCNTHSTR.Byte /*** TBCNTL - TIMB Counter Register; 0x00000042 ***/ union { byte Byte; } TBCNTLSTR; #define TBCNTL _TBCNT.Overlap_STR.TBCNTLSTR.Byte } Overlap_STR; } TBCNTSTR; extern volatile TBCNTSTR _TBCNT @0x00000041; #define TBCNT _TBCNT.Word /*** TBMOD - TIMB Counter Modulo Register; 0x00000043 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TBMODH - TIMB Counter Modulo Register; 0x00000043 ***/ union { byte Byte; } TBMODHSTR; #define TBMODH _TBMOD.Overlap_STR.TBMODHSTR.Byte /*** TBMODL - TIMB Counter Modulo Register; 0x00000044 ***/ union { byte Byte; } TBMODLSTR; #define TBMODL _TBMOD.Overlap_STR.TBMODLSTR.Byte } Overlap_STR; } TBMODSTR; extern volatile TBMODSTR _TBMOD @0x00000043; #define TBMOD _TBMOD.Word /*** TBSC0 - TIMB Channel Status and Control Register; 0x00000045 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit */ byte ELS0B :1; /* Edge/Level Select Bit */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TBSC0STR; extern volatile TBSC0STR _TBSC0 @0x00000045; #define TBSC0 _TBSC0.Byte #define TBSC0_CH0MAX _TBSC0.Bits.CH0MAX #define TBSC0_TOV0 _TBSC0.Bits.TOV0 #define TBSC0_ELS0A _TBSC0.Bits.ELS0A #define TBSC0_ELS0B _TBSC0.Bits.ELS0B #define TBSC0_MS0A _TBSC0.Bits.MS0A #define TBSC0_MS0B _TBSC0.Bits.MS0B #define TBSC0_CH0IE _TBSC0.Bits.CH0IE #define TBSC0_CH0F _TBSC0.Bits.CH0F #define TBSC0_ELS0x _TBSC0.MergedBits.grpELS0x #define TBSC0_MS0x _TBSC0.MergedBits.grpMS0x #define TBSC0_CH0MAX_MASK 1 #define TBSC0_TOV0_MASK 2 #define TBSC0_ELS0A_MASK 4 #define TBSC0_ELS0B_MASK 8 #define TBSC0_MS0A_MASK 16 #define TBSC0_MS0B_MASK 32 #define TBSC0_CH0IE_MASK 64 #define TBSC0_CH0F_MASK 128 #define TBSC0_ELS0x_MASK 12 #define TBSC0_ELS0x_BITNUM 2 #define TBSC0_MS0x_MASK 48 #define TBSC0_MS0x_BITNUM 4 /*** TBCH0 - TIMB Channel Register; 0x00000046 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TBCH0H - TIMB Channel Register; 0x00000046 ***/ union { byte Byte; } TBCH0HSTR; #define TBCH0H _TBCH0.Overlap_STR.TBCH0HSTR.Byte /*** TBCH0L - TIMB Channel Register; 0x00000047 ***/ union { byte Byte; } TBCH0LSTR; #define TBCH0L _TBCH0.Overlap_STR.TBCH0LSTR.Byte } Overlap_STR; } TBCH0STR; extern volatile TBCH0STR _TBCH0 @0x00000046; #define TBCH0 _TBCH0.Word /*** TBSC1 - IMB Channel Status and Control Register; 0x00000048 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit */ byte ELS1B :1; /* Edge/Level Select Bit */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } TBSC1STR; extern volatile TBSC1STR _TBSC1 @0x00000048; #define TBSC1 _TBSC1.Byte #define TBSC1_CH1MAX _TBSC1.Bits.CH1MAX #define TBSC1_TOV1 _TBSC1.Bits.TOV1 #define TBSC1_ELS1A _TBSC1.Bits.ELS1A #define TBSC1_ELS1B _TBSC1.Bits.ELS1B #define TBSC1_MS1A _TBSC1.Bits.MS1A #define TBSC1_CH1IE _TBSC1.Bits.CH1IE #define TBSC1_CH1F _TBSC1.Bits.CH1F #define TBSC1_ELS1x _TBSC1.MergedBits.grpELS1x #define TBSC1_CH1MAX_MASK 1 #define TBSC1_TOV1_MASK 2 #define TBSC1_ELS1A_MASK 4 #define TBSC1_ELS1B_MASK 8 #define TBSC1_MS1A_MASK 16 #define TBSC1_CH1IE_MASK 64 #define TBSC1_CH1F_MASK 128 #define TBSC1_ELS1x_MASK 12 #define TBSC1_ELS1x_BITNUM 2 /*** TBCH1 - TIMB Channel Register; 0x00000049 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TBCH1H - TIMB Channel Register; 0x00000049 ***/ union { byte Byte; } TBCH1HSTR; #define TBCH1H _TBCH1.Overlap_STR.TBCH1HSTR.Byte /*** TBCH1L - TIMB Channel Register; 0x0000004A ***/ union { byte Byte; } TBCH1LSTR; #define TBCH1L _TBCH1.Overlap_STR.TBCH1LSTR.Byte } Overlap_STR; } TBCH1STR; extern volatile TBCH1STR _TBCH1 @0x00000049; #define TBCH1 _TBCH1.Word /*** PSC - Timer Status & Control; 0x0000004B ***/ typedef union { byte Byte; struct { byte PPS0 :1; /* Prescaler Select Bit */ byte PPS1 :1; /* Prescaler Select Bit */ byte PPS2 :1; /* Prescaler Select Bit */ byte :1; byte PRST :1; /* PIT Reset Bit */ byte PSTOP :1; /* PIT Stop Bit */ byte PIE :1; /* PIT Overflow Interrupt Enable Bit */ byte POF :1; /* PIT Overflow Flag Bit */ } Bits; struct { byte grpPPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PSCSTR; extern volatile PSCSTR _PSC @0x0000004B; #define PSC _PSC.Byte #define PSC_PPS0 _PSC.Bits.PPS0 #define PSC_PPS1 _PSC.Bits.PPS1 #define PSC_PPS2 _PSC.Bits.PPS2 #define PSC_PRST _PSC.Bits.PRST #define PSC_PSTOP _PSC.Bits.PSTOP #define PSC_PIE _PSC.Bits.PIE #define PSC_POF _PSC.Bits.POF #define PSC_PPS _PSC.MergedBits.grpPPS #define PSC_PPS0_MASK 1 #define PSC_PPS1_MASK 2 #define PSC_PPS2_MASK 4 #define PSC_PRST_MASK 16 #define PSC_PSTOP_MASK 32 #define PSC_PIE_MASK 64 #define PSC_POF_MASK 128 #define PSC_PPS_MASK 7 #define PSC_PPS_BITNUM 0 /*** PCNT - PIT Counter Register; 0x0000004C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** PCNTH - PIT Counter Register; 0x0000004C ***/ union { byte Byte; } PCNTHSTR; #define PCNTH _PCNT.Overlap_STR.PCNTHSTR.Byte /*** PCNTL - PIT Counter Register; 0x0000004D ***/ union { byte Byte; } PCNTLSTR; #define PCNTL _PCNT.Overlap_STR.PCNTLSTR.Byte } Overlap_STR; } PCNTSTR; extern volatile PCNTSTR _PCNT @0x0000004C; #define PCNT _PCNT.Word /*** PMOD - PIT Counter Modulo Register; 0x0000004E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** PMODH - PIT Counter Modulo Register; 0x0000004E ***/ union { byte Byte; } PMODHSTR; #define PMODH _PMOD.Overlap_STR.PMODHSTR.Byte /*** PMODL - PIT Counter Modulo Register; 0x0000004F ***/ union { byte Byte; } PMODLSTR; #define PMODL _PMOD.Overlap_STR.PMODLSTR.Byte } Overlap_STR; } PMODSTR; extern volatile PMODSTR _PMOD @0x0000004E; #define PMOD _PMOD.Word /*** CMCR0 - Module Control Register 0; 0x00000500 ***/ typedef union { byte Byte; struct { byte SFTRES :1; /* Soft Reset */ byte SLPRQ :1; /* Sleep Request, Go to Internal Sleep Mode */ byte SLPAK :1; /* Sleep Mode Acknowledge */ byte TLNKEN :1; /* Timer Enable */ byte SYNCH :1; /* Synchronized Status */ byte :1; byte :1; byte :1; } Bits; } CMCR0STR; extern volatile CMCR0STR _CMCR0 @0x00000500; #define CMCR0 _CMCR0.Byte #define CMCR0_SFTRES _CMCR0.Bits.SFTRES #define CMCR0_SLPRQ _CMCR0.Bits.SLPRQ #define CMCR0_SLPAK _CMCR0.Bits.SLPAK #define CMCR0_TLNKEN _CMCR0.Bits.TLNKEN #define CMCR0_SYNCH _CMCR0.Bits.SYNCH /* CMCR_ARR: Access 2 CMCRx registers in an array */ #define CMCR_ARR ((volatile byte * __far) &CMCR0) #define CMCR0_SFTRES_MASK 1 #define CMCR0_SLPRQ_MASK 2 #define CMCR0_SLPAK_MASK 4 #define CMCR0_TLNKEN_MASK 8 #define CMCR0_SYNCH_MASK 16 /*** CMCR1 - Module Control Register 1; 0x00000501 ***/ typedef union { byte Byte; struct { byte CLKSRC :1; /* Clock Source */ byte WUPM :1; /* Wakeup Mode */ byte LOOPB :1; /* Loop Back Self-Test Mode */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } CMCR1STR; extern volatile CMCR1STR _CMCR1 @0x00000501; #define CMCR1 _CMCR1.Byte #define CMCR1_CLKSRC _CMCR1.Bits.CLKSRC #define CMCR1_WUPM _CMCR1.Bits.WUPM #define CMCR1_LOOPB _CMCR1.Bits.LOOPB #define CMCR1_CLKSRC_MASK 1 #define CMCR1_WUPM_MASK 2 #define CMCR1_LOOPB_MASK 4 /*** CBTR0 - Bus Timing Register 0; 0x00000502 ***/ typedef union { byte Byte; struct { byte BRP0 :1; /* Baud Rate Prescaler 0 */ byte BRP1 :1; /* Baud Rate Prescaler 1 */ byte BRP2 :1; /* Baud Rate Prescaler 2 */ byte BRP3 :1; /* Baud Rate Prescaler 3 */ byte BRP4 :1; /* Baud Rate Prescaler 4 */ byte BRP5 :1; /* Baud Rate Prescaler 5 */ byte SJW0 :1; /* Synchronization Jump Width 0 */ byte SJW1 :1; /* Synchronization Jump Width 1 */ } Bits; struct { byte grpBRP :6; byte grpSJW :2; } MergedBits; } CBTR0STR; extern volatile CBTR0STR _CBTR0 @0x00000502; #define CBTR0 _CBTR0.Byte #define CBTR0_BRP0 _CBTR0.Bits.BRP0 #define CBTR0_BRP1 _CBTR0.Bits.BRP1 #define CBTR0_BRP2 _CBTR0.Bits.BRP2 #define CBTR0_BRP3 _CBTR0.Bits.BRP3 #define CBTR0_BRP4 _CBTR0.Bits.BRP4 #define CBTR0_BRP5 _CBTR0.Bits.BRP5 #define CBTR0_SJW0 _CBTR0.Bits.SJW0 #define CBTR0_SJW1 _CBTR0.Bits.SJW1 /* CBTR_ARR: Access 2 CBTRx registers in an array */ #define CBTR_ARR ((volatile byte * __far) &CBTR0) #define CBTR0_BRP _CBTR0.MergedBits.grpBRP #define CBTR0_SJW _CBTR0.MergedBits.grpSJW #define CBTR0_BRP0_MASK 1 #define CBTR0_BRP1_MASK 2 #define CBTR0_BRP2_MASK 4 #define CBTR0_BRP3_MASK 8 #define CBTR0_BRP4_MASK 16 #define CBTR0_BRP5_MASK 32 #define CBTR0_SJW0_MASK 64 #define CBTR0_SJW1_MASK 128 #define CBTR0_BRP_MASK 63 #define CBTR0_BRP_BITNUM 0 #define CBTR0_SJW_MASK 192 #define CBTR0_SJW_BITNUM 6 /*** CBTR1 - Bus Timing Register 1; 0x00000503 ***/ typedef union { byte Byte; struct { byte TSEG10 :1; /* Time Segment 10 */ byte TSEG11 :1; /* Time Segment 11 */ byte TSEG12 :1; /* Time Segment 12 */ byte TSEG13 :1; /* Time Segment 13 */ byte TSEG20 :1; /* Time Segment 20 */ byte TSEG21 :1; /* Time Segment 21 */ byte TSEG22 :1; /* Time Segment 22 */ byte SAMP :1; /* Sampling */ } Bits; struct { byte grpTSEG_10 :4; byte grpTSEG_20 :3; byte :1; } MergedBits; } CBTR1STR; extern volatile CBTR1STR _CBTR1 @0x00000503; #define CBTR1 _CBTR1.Byte #define CBTR1_TSEG10 _CBTR1.Bits.TSEG10 #define CBTR1_TSEG11 _CBTR1.Bits.TSEG11 #define CBTR1_TSEG12 _CBTR1.Bits.TSEG12 #define CBTR1_TSEG13 _CBTR1.Bits.TSEG13 #define CBTR1_TSEG20 _CBTR1.Bits.TSEG20 #define CBTR1_TSEG21 _CBTR1.Bits.TSEG21 #define CBTR1_TSEG22 _CBTR1.Bits.TSEG22 #define CBTR1_SAMP _CBTR1.Bits.SAMP #define CBTR1_TSEG_10 _CBTR1.MergedBits.grpTSEG_10 #define CBTR1_TSEG_20 _CBTR1.MergedBits.grpTSEG_20 #define CBTR1_TSEG CBTR1_TSEG_10 #define CBTR1_TSEG10_MASK 1 #define CBTR1_TSEG11_MASK 2 #define CBTR1_TSEG12_MASK 4 #define CBTR1_TSEG13_MASK 8 #define CBTR1_TSEG20_MASK 16 #define CBTR1_TSEG21_MASK 32 #define CBTR1_TSEG22_MASK 64 #define CBTR1_SAMP_MASK 128 #define CBTR1_TSEG_10_MASK 15 #define CBTR1_TSEG_10_BITNUM 0 #define CBTR1_TSEG_20_MASK 112 #define CBTR1_TSEG_20_BITNUM 4 /*** CRFLG - Receiver Flag Register; 0x00000504 ***/ typedef union { byte Byte; struct { byte RXF :1; /* Receive Buffer Full */ byte OVRIF :1; /* Overrun Interrupt Flag */ byte BOFFIF :1; /* Bus-Off Interrupt Flag */ byte TERRIF :1; /* Transmitter Error Passive Interrupt Flag */ byte RERRIF :1; /* Receiver Error Passive Interrupt Flag */ byte TWRNIF :1; /* Transmitter Warning Interrupt Flag */ byte RWRNIF :1; /* Receiver Warning Interrupt Flag */ byte WUPIF :1; /* Wakeup Interrupt Flag */ } Bits; } CRFLGSTR; extern volatile CRFLGSTR _CRFLG @0x00000504; #define CRFLG _CRFLG.Byte #define CRFLG_RXF _CRFLG.Bits.RXF #define CRFLG_OVRIF _CRFLG.Bits.OVRIF #define CRFLG_BOFFIF _CRFLG.Bits.BOFFIF #define CRFLG_TERRIF _CRFLG.Bits.TERRIF #define CRFLG_RERRIF _CRFLG.Bits.RERRIF #define CRFLG_TWRNIF _CRFLG.Bits.TWRNIF #define CRFLG_RWRNIF _CRFLG.Bits.RWRNIF #define CRFLG_WUPIF _CRFLG.Bits.WUPIF #define CRFLG_RXF_MASK 1 #define CRFLG_OVRIF_MASK 2 #define CRFLG_BOFFIF_MASK 4 #define CRFLG_TERRIF_MASK 8 #define CRFLG_RERRIF_MASK 16 #define CRFLG_TWRNIF_MASK 32 #define CRFLG_RWRNIF_MASK 64 #define CRFLG_WUPIF_MASK 128 /*** CRIER - Receiver Interrupt Enable Register; 0x00000505 ***/ typedef union { byte Byte; struct { byte RXFIE :1; /* Receiver Full Interrupt Enable */ byte OVRIE :1; /* Overrun Interrupt Enable */ byte BOFFIE :1; /* Bus-Off Interrupt Enable */ byte TERRIE :1; /* Transmitter Error Passive Interrupt Enable */ byte RERRIE :1; /* Receiver Error Passive Interrupt Enable */ byte TWRNIE :1; /* Transmitter Warning Interrupt Enable */ byte RWRNIE :1; /* Receiver Warning Interrupt Enable */ byte WUPIE :1; /* Wakeup Interrupt Enable */ } Bits; } CRIERSTR; extern volatile CRIERSTR _CRIER @0x00000505; #define CRIER _CRIER.Byte #define CRIER_RXFIE _CRIER.Bits.RXFIE #define CRIER_OVRIE _CRIER.Bits.OVRIE #define CRIER_BOFFIE _CRIER.Bits.BOFFIE #define CRIER_TERRIE _CRIER.Bits.TERRIE #define CRIER_RERRIE _CRIER.Bits.RERRIE #define CRIER_TWRNIE _CRIER.Bits.TWRNIE #define CRIER_RWRNIE _CRIER.Bits.RWRNIE #define CRIER_WUPIE _CRIER.Bits.WUPIE #define CRIER_RXFIE_MASK 1 #define CRIER_OVRIE_MASK 2 #define CRIER_BOFFIE_MASK 4 #define CRIER_TERRIE_MASK 8 #define CRIER_RERRIE_MASK 16 #define CRIER_TWRNIE_MASK 32 #define CRIER_RWRNIE_MASK 64 #define CRIER_WUPIE_MASK 128 /*** CTFLG - Transmitter Flag Register; 0x00000506 ***/ typedef union { byte Byte; struct { byte TXE0 :1; /* Transmitter Empty 0 */ byte TXE1 :1; /* Transmitter Empty 1 */ byte TXE2 :1; /* Transmitter Empty 2 */ byte :1; byte ABTAK0 :1; /* Abort Acknowledge 0 */ byte ABTAK1 :1; /* Abort Acknowledge 1 */ byte ABTAK2 :1; /* Abort Acknowledge 2 */ byte :1; } Bits; struct { byte grpTXE :3; byte :1; byte grpABTAK :3; byte :1; } MergedBits; } CTFLGSTR; extern volatile CTFLGSTR _CTFLG @0x00000506; #define CTFLG _CTFLG.Byte #define CTFLG_TXE0 _CTFLG.Bits.TXE0 #define CTFLG_TXE1 _CTFLG.Bits.TXE1 #define CTFLG_TXE2 _CTFLG.Bits.TXE2 #define CTFLG_ABTAK0 _CTFLG.Bits.ABTAK0 #define CTFLG_ABTAK1 _CTFLG.Bits.ABTAK1 #define CTFLG_ABTAK2 _CTFLG.Bits.ABTAK2 #define CTFLG_TXE _CTFLG.MergedBits.grpTXE #define CTFLG_ABTAK _CTFLG.MergedBits.grpABTAK #define CTFLG_TXE0_MASK 1 #define CTFLG_TXE1_MASK 2 #define CTFLG_TXE2_MASK 4 #define CTFLG_ABTAK0_MASK 16 #define CTFLG_ABTAK1_MASK 32 #define CTFLG_ABTAK2_MASK 64 #define CTFLG_TXE_MASK 7 #define CTFLG_TXE_BITNUM 0 #define CTFLG_ABTAK_MASK 112 #define CTFLG_ABTAK_BITNUM 4 /*** CTCR - Transmitter Control Register; 0x00000507 ***/ typedef union { byte Byte; struct { byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ byte :1; byte ABTRQ0 :1; /* Abort Request 0 */ byte ABTRQ1 :1; /* Abort Request 1 */ byte ABTRQ2 :1; /* Abort Request 2 */ byte :1; } Bits; struct { byte grpTXEIE :3; byte :1; byte grpABTRQ :3; byte :1; } MergedBits; } CTCRSTR; extern volatile CTCRSTR _CTCR @0x00000507; #define CTCR _CTCR.Byte #define CTCR_TXEIE0 _CTCR.Bits.TXEIE0 #define CTCR_TXEIE1 _CTCR.Bits.TXEIE1 #define CTCR_TXEIE2 _CTCR.Bits.TXEIE2 #define CTCR_ABTRQ0 _CTCR.Bits.ABTRQ0 #define CTCR_ABTRQ1 _CTCR.Bits.ABTRQ1 #define CTCR_ABTRQ2 _CTCR.Bits.ABTRQ2 #define CTCR_TXEIE _CTCR.MergedBits.grpTXEIE #define CTCR_ABTRQ _CTCR.MergedBits.grpABTRQ #define CTCR_TXEIE0_MASK 1 #define CTCR_TXEIE1_MASK 2 #define CTCR_TXEIE2_MASK 4 #define CTCR_ABTRQ0_MASK 16 #define CTCR_ABTRQ1_MASK 32 #define CTCR_ABTRQ2_MASK 64 #define CTCR_TXEIE_MASK 7 #define CTCR_TXEIE_BITNUM 0 #define CTCR_ABTRQ_MASK 112 #define CTCR_ABTRQ_BITNUM 4 /*** CIDAC - Identifier Acceptance Control Register; 0x00000508 ***/ typedef union { byte Byte; struct { byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ byte :1; byte :1; byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ byte :1; byte :1; } Bits; struct { byte grpIDHIT :2; byte :1; byte :1; byte grpIDAM :2; byte :1; byte :1; } MergedBits; } CIDACSTR; extern volatile CIDACSTR _CIDAC @0x00000508; #define CIDAC _CIDAC.Byte #define CIDAC_IDHIT0 _CIDAC.Bits.IDHIT0 #define CIDAC_IDHIT1 _CIDAC.Bits.IDHIT1 #define CIDAC_IDAM0 _CIDAC.Bits.IDAM0 #define CIDAC_IDAM1 _CIDAC.Bits.IDAM1 #define CIDAC_IDHIT _CIDAC.MergedBits.grpIDHIT #define CIDAC_IDAM _CIDAC.MergedBits.grpIDAM #define CIDAC_IDHIT0_MASK 1 #define CIDAC_IDHIT1_MASK 2 #define CIDAC_IDAM0_MASK 16 #define CIDAC_IDAM1_MASK 32 #define CIDAC_IDHIT_MASK 3 #define CIDAC_IDHIT_BITNUM 0 #define CIDAC_IDAM_MASK 48 #define CIDAC_IDAM_BITNUM 4 /*** CRXERR - Receiver Error Counter Register; 0x0000050E ***/ typedef union { byte Byte; struct { byte RXERR0 :1; /* Receiver Error Counter Register Bit 0 */ byte RXERR1 :1; /* Receiver Error Counter Register Bit 1 */ byte RXERR2 :1; /* Receiver Error Counter Register Bit 2 */ byte RXERR3 :1; /* Receiver Error Counter Register Bit 3 */ byte RXERR4 :1; /* Receiver Error Counter Register Bit 4 */ byte RXERR5 :1; /* Receiver Error Counter Register Bit 5 */ byte RXERR6 :1; /* Receiver Error Counter Register Bit 6 */ byte RXERR7 :1; /* Receiver Error Counter Register Bit 7 */ } Bits; } CRXERRSTR; extern volatile CRXERRSTR _CRXERR @0x0000050E; #define CRXERR _CRXERR.Byte #define CRXERR_RXERR0 _CRXERR.Bits.RXERR0 #define CRXERR_RXERR1 _CRXERR.Bits.RXERR1 #define CRXERR_RXERR2 _CRXERR.Bits.RXERR2 #define CRXERR_RXERR3 _CRXERR.Bits.RXERR3 #define CRXERR_RXERR4 _CRXERR.Bits.RXERR4 #define CRXERR_RXERR5 _CRXERR.Bits.RXERR5 #define CRXERR_RXERR6 _CRXERR.Bits.RXERR6 #define CRXERR_RXERR7 _CRXERR.Bits.RXERR7 #define CRXERR_RXERR0_MASK 1 #define CRXERR_RXERR1_MASK 2 #define CRXERR_RXERR2_MASK 4 #define CRXERR_RXERR3_MASK 8 #define CRXERR_RXERR4_MASK 16 #define CRXERR_RXERR5_MASK 32 #define CRXERR_RXERR6_MASK 64 #define CRXERR_RXERR7_MASK 128 /*** CTXERR - Transmit Error Counter Register; 0x0000050F ***/ typedef union { byte Byte; struct { byte TXERR0 :1; /* Transmit Error Counter Register Bit 0 */ byte TXERR1 :1; /* Transmit Error Counter Register Bit 1 */ byte TXERR2 :1; /* Transmit Error Counter Register Bit 2 */ byte TXERR3 :1; /* Transmit Error Counter Register Bit 3 */ byte TXERR4 :1; /* Transmit Error Counter Register Bit 4 */ byte TXERR5 :1; /* Transmit Error Counter Register Bit 5 */ byte TXERR6 :1; /* Transmit Error Counter Register Bit 6 */ byte TXERR7 :1; /* Transmit Error Counter Register Bit 7 */ } Bits; } CTXERRSTR; extern volatile CTXERRSTR _CTXERR @0x0000050F; #define CTXERR _CTXERR.Byte #define CTXERR_TXERR0 _CTXERR.Bits.TXERR0 #define CTXERR_TXERR1 _CTXERR.Bits.TXERR1 #define CTXERR_TXERR2 _CTXERR.Bits.TXERR2 #define CTXERR_TXERR3 _CTXERR.Bits.TXERR3 #define CTXERR_TXERR4 _CTXERR.Bits.TXERR4 #define CTXERR_TXERR5 _CTXERR.Bits.TXERR5 #define CTXERR_TXERR6 _CTXERR.Bits.TXERR6 #define CTXERR_TXERR7 _CTXERR.Bits.TXERR7 #define CTXERR_TXERR0_MASK 1 #define CTXERR_TXERR1_MASK 2 #define CTXERR_TXERR2_MASK 4 #define CTXERR_TXERR3_MASK 8 #define CTXERR_TXERR4_MASK 16 #define CTXERR_TXERR5_MASK 32 #define CTXERR_TXERR6_MASK 64 #define CTXERR_TXERR7_MASK 128 /*** CIDAR - Identifier Acceptance Register; 0x00000510 ***/ typedef union { dword Dword; /* Overlapped registers: */ struct { /*** CIDAR0 - Identifier Acceptance Register 0; 0x00000510 ***/ union { byte Byte; struct { byte AC0 :1; /* Acceptance Code Bit 0 */ byte AC1 :1; /* Acceptance Code Bit 1 */ byte AC2 :1; /* Acceptance Code Bit 2 */ byte AC3 :1; /* Acceptance Code Bit 3 */ byte AC4 :1; /* Acceptance Code Bit 4 */ byte AC5 :1; /* Acceptance Code Bit 5 */ byte AC6 :1; /* Acceptance Code Bit 6 */ byte AC7 :1; /* Acceptance Code Bit 7 */ } Bits; } CIDAR0STR; #define CIDAR0 _CIDAR.Overlap_STR.CIDAR0STR.Byte #define CIDAR0_AC0 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC0 #define CIDAR0_AC1 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC1 #define CIDAR0_AC2 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC2 #define CIDAR0_AC3 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC3 #define CIDAR0_AC4 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC4 #define CIDAR0_AC5 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC5 #define CIDAR0_AC6 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC6 #define CIDAR0_AC7 _CIDAR.Overlap_STR.CIDAR0STR.Bits.AC7 /* CIDAR_ARR: Access 4 CIDARx registers in an array */ #define CIDAR_ARR ((volatile byte * __far) &CIDAR0) #define CIDAR0_AC0_MASK 1 #define CIDAR0_AC1_MASK 2 #define CIDAR0_AC2_MASK 4 #define CIDAR0_AC3_MASK 8 #define CIDAR0_AC4_MASK 16 #define CIDAR0_AC5_MASK 32 #define CIDAR0_AC6_MASK 64 #define CIDAR0_AC7_MASK 128 /*** CIDAR1 - Identifier Acceptance Register 1; 0x00000511 ***/ union { byte Byte; struct { byte AC0 :1; /* Acceptance Code Bit 0 */ byte AC1 :1; /* Acceptance Code Bit 1 */ byte AC2 :1; /* Acceptance Code Bit 2 */ byte AC3 :1; /* Acceptance Code Bit 3 */ byte AC4 :1; /* Acceptance Code Bit 4 */ byte AC5 :1; /* Acceptance Code Bit 5 */ byte AC6 :1; /* Acceptance Code Bit 6 */ byte AC7 :1; /* Acceptance Code Bit 7 */ } Bits; } CIDAR1STR; #define CIDAR1 _CIDAR.Overlap_STR.CIDAR1STR.Byte #define CIDAR1_AC0 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC0 #define CIDAR1_AC1 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC1 #define CIDAR1_AC2 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC2 #define CIDAR1_AC3 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC3 #define CIDAR1_AC4 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC4 #define CIDAR1_AC5 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC5 #define CIDAR1_AC6 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC6 #define CIDAR1_AC7 _CIDAR.Overlap_STR.CIDAR1STR.Bits.AC7 #define CIDAR1_AC0_MASK 1 #define CIDAR1_AC1_MASK 2 #define CIDAR1_AC2_MASK 4 #define CIDAR1_AC3_MASK 8 #define CIDAR1_AC4_MASK 16 #define CIDAR1_AC5_MASK 32 #define CIDAR1_AC6_MASK 64 #define CIDAR1_AC7_MASK 128 /*** CIDAR2 - Identifier Acceptance Register 2; 0x00000512 ***/ union { byte Byte; struct { byte AC0 :1; /* Acceptance Code Bit 0 */ byte AC1 :1; /* Acceptance Code Bit 1 */ byte AC2 :1; /* Acceptance Code Bit 2 */ byte AC3 :1; /* Acceptance Code Bit 3 */ byte AC4 :1; /* Acceptance Code Bit 4 */ byte AC5 :1; /* Acceptance Code Bit 5 */ byte AC6 :1; /* Acceptance Code Bit 6 */ byte AC7 :1; /* Acceptance Code Bit 7 */ } Bits; } CIDAR2STR; #define CIDAR2 _CIDAR.Overlap_STR.CIDAR2STR.Byte #define CIDAR2_AC0 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC0 #define CIDAR2_AC1 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC1 #define CIDAR2_AC2 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC2 #define CIDAR2_AC3 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC3 #define CIDAR2_AC4 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC4 #define CIDAR2_AC5 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC5 #define CIDAR2_AC6 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC6 #define CIDAR2_AC7 _CIDAR.Overlap_STR.CIDAR2STR.Bits.AC7 #define CIDAR2_AC0_MASK 1 #define CIDAR2_AC1_MASK 2 #define CIDAR2_AC2_MASK 4 #define CIDAR2_AC3_MASK 8 #define CIDAR2_AC4_MASK 16 #define CIDAR2_AC5_MASK 32 #define CIDAR2_AC6_MASK 64 #define CIDAR2_AC7_MASK 128 /*** CIDAR3 - Identifier Acceptance Register 3; 0x00000513 ***/ union { byte Byte; struct { byte AC0 :1; /* Acceptance Code Bit 0 */ byte AC1 :1; /* Acceptance Code Bit 1 */ byte AC2 :1; /* Acceptance Code Bit 2 */ byte AC3 :1; /* Acceptance Code Bit 3 */ byte AC4 :1; /* Acceptance Code Bit 4 */ byte AC5 :1; /* Acceptance Code Bit 5 */ byte AC6 :1; /* Acceptance Code Bit 6 */ byte AC7 :1; /* Acceptance Code Bit 7 */ } Bits; } CIDAR3STR; #define CIDAR3 _CIDAR.Overlap_STR.CIDAR3STR.Byte #define CIDAR3_AC0 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC0 #define CIDAR3_AC1 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC1 #define CIDAR3_AC2 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC2 #define CIDAR3_AC3 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC3 #define CIDAR3_AC4 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC4 #define CIDAR3_AC5 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC5 #define CIDAR3_AC6 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC6 #define CIDAR3_AC7 _CIDAR.Overlap_STR.CIDAR3STR.Bits.AC7 #define CIDAR3_AC0_MASK 1 #define CIDAR3_AC1_MASK 2 #define CIDAR3_AC2_MASK 4 #define CIDAR3_AC3_MASK 8 #define CIDAR3_AC4_MASK 16 #define CIDAR3_AC5_MASK 32 #define CIDAR3_AC6_MASK 64 #define CIDAR3_AC7_MASK 128 } Overlap_STR; } CIDARSTR; extern volatile CIDARSTR _CIDAR @0x00000510; #define CIDAR _CIDAR.Dword /*** CIDMR - Identifier Mask Register; 0x00000514 ***/ typedef union { dword Dword; /* Overlapped registers: */ struct { /*** CIDMR0 - Identifier Mask Register 0; 0x00000514 ***/ union { byte Byte; struct { byte AM0 :1; /* Acceptance Mask Bit 0 */ byte AM1 :1; /* Acceptance Mask Bit 1 */ byte AM2 :1; /* Acceptance Mask Bit 2 */ byte AM3 :1; /* Acceptance Mask Bit 3 */ byte AM4 :1; /* Acceptance Mask Bit 4 */ byte AM5 :1; /* Acceptance Mask Bit 5 */ byte AM6 :1; /* Acceptance Mask Bit 6 */ byte AM7 :1; /* Acceptance Mask Bit 7 */ } Bits; } CIDMR0STR; #define CIDMR0 _CIDMR.Overlap_STR.CIDMR0STR.Byte #define CIDMR0_AM0 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM0 #define CIDMR0_AM1 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM1 #define CIDMR0_AM2 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM2 #define CIDMR0_AM3 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM3 #define CIDMR0_AM4 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM4 #define CIDMR0_AM5 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM5 #define CIDMR0_AM6 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM6 #define CIDMR0_AM7 _CIDMR.Overlap_STR.CIDMR0STR.Bits.AM7 /* CIDMR_ARR: Access 4 CIDMRx registers in an array */ #define CIDMR_ARR ((volatile byte * __far) &CIDMR0) #define CIDMR0_AM0_MASK 1 #define CIDMR0_AM1_MASK 2 #define CIDMR0_AM2_MASK 4 #define CIDMR0_AM3_MASK 8 #define CIDMR0_AM4_MASK 16 #define CIDMR0_AM5_MASK 32 #define CIDMR0_AM6_MASK 64 #define CIDMR0_AM7_MASK 128 /*** CIDMR1 - Identifier Mask Register 1; 0x00000515 ***/ union { byte Byte; struct { byte AM0 :1; /* Acceptance Mask Bit 0 */ byte AM1 :1; /* Acceptance Mask Bit 1 */ byte AM2 :1; /* Acceptance Mask Bit 2 */ byte AM3 :1; /* Acceptance Mask Bit 3 */ byte AM4 :1; /* Acceptance Mask Bit 4 */ byte AM5 :1; /* Acceptance Mask Bit 5 */ byte AM6 :1; /* Acceptance Mask Bit 6 */ byte AM7 :1; /* Acceptance Mask Bit 7 */ } Bits; } CIDMR1STR; #define CIDMR1 _CIDMR.Overlap_STR.CIDMR1STR.Byte #define CIDMR1_AM0 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM0 #define CIDMR1_AM1 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM1 #define CIDMR1_AM2 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM2 #define CIDMR1_AM3 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM3 #define CIDMR1_AM4 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM4 #define CIDMR1_AM5 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM5 #define CIDMR1_AM6 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM6 #define CIDMR1_AM7 _CIDMR.Overlap_STR.CIDMR1STR.Bits.AM7 #define CIDMR1_AM0_MASK 1 #define CIDMR1_AM1_MASK 2 #define CIDMR1_AM2_MASK 4 #define CIDMR1_AM3_MASK 8 #define CIDMR1_AM4_MASK 16 #define CIDMR1_AM5_MASK 32 #define CIDMR1_AM6_MASK 64 #define CIDMR1_AM7_MASK 128 /*** CIDMR2 - Identifier Mask Register 2; 0x00000516 ***/ union { byte Byte; struct { byte AM0 :1; /* Acceptance Mask Bit 0 */ byte AM1 :1; /* Acceptance Mask Bit 1 */ byte AM2 :1; /* Acceptance Mask Bit 2 */ byte AM3 :1; /* Acceptance Mask Bit 3 */ byte AM4 :1; /* Acceptance Mask Bit 4 */ byte AM5 :1; /* Acceptance Mask Bit 5 */ byte AM6 :1; /* Acceptance Mask Bit 6 */ byte AM7 :1; /* Acceptance Mask Bit 7 */ } Bits; } CIDMR2STR; #define CIDMR2 _CIDMR.Overlap_STR.CIDMR2STR.Byte #define CIDMR2_AM0 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM0 #define CIDMR2_AM1 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM1 #define CIDMR2_AM2 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM2 #define CIDMR2_AM3 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM3 #define CIDMR2_AM4 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM4 #define CIDMR2_AM5 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM5 #define CIDMR2_AM6 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM6 #define CIDMR2_AM7 _CIDMR.Overlap_STR.CIDMR2STR.Bits.AM7 #define CIDMR2_AM0_MASK 1 #define CIDMR2_AM1_MASK 2 #define CIDMR2_AM2_MASK 4 #define CIDMR2_AM3_MASK 8 #define CIDMR2_AM4_MASK 16 #define CIDMR2_AM5_MASK 32 #define CIDMR2_AM6_MASK 64 #define CIDMR2_AM7_MASK 128 /*** CIDMR3 - Identifier Mask Register 3; 0x00000517 ***/ union { byte Byte; struct { byte AM0 :1; /* Acceptance Mask Bit 0 */ byte AM1 :1; /* Acceptance Mask Bit 1 */ byte AM2 :1; /* Acceptance Mask Bit 2 */ byte AM3 :1; /* Acceptance Mask Bit 3 */ byte AM4 :1; /* Acceptance Mask Bit 4 */ byte AM5 :1; /* Acceptance Mask Bit 5 */ byte AM6 :1; /* Acceptance Mask Bit 6 */ byte AM7 :1; /* Acceptance Mask Bit 7 */ } Bits; } CIDMR3STR; #define CIDMR3 _CIDMR.Overlap_STR.CIDMR3STR.Byte #define CIDMR3_AM0 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM0 #define CIDMR3_AM1 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM1 #define CIDMR3_AM2 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM2 #define CIDMR3_AM3 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM3 #define CIDMR3_AM4 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM4 #define CIDMR3_AM5 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM5 #define CIDMR3_AM6 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM6 #define CIDMR3_AM7 _CIDMR.Overlap_STR.CIDMR3STR.Bits.AM7 #define CIDMR3_AM0_MASK 1 #define CIDMR3_AM1_MASK 2 #define CIDMR3_AM2_MASK 4 #define CIDMR3_AM3_MASK 8 #define CIDMR3_AM4_MASK 16 #define CIDMR3_AM5_MASK 32 #define CIDMR3_AM6_MASK 64 #define CIDMR3_AM7_MASK 128 } Overlap_STR; } CIDMRSTR; extern volatile CIDMRSTR _CIDMR @0x00000514; #define CIDMR _CIDMR.Dword /*** REC_IDR - Receive Buffer Identifier Register; 0x00000540 ***/ typedef union { dword Dword; /* Overlapped registers: */ struct { /*** REC_IDR0 - Receive Buffer Identifier Register 0; 0x00000540 ***/ union { byte Byte; struct { byte ID21 :1; /* Identifier Register Bit */ byte ID22 :1; /* Identifier Register Bit */ byte ID23 :1; /* Identifier Register Bit */ byte ID24 :1; /* Identifier Register Bit */ byte ID25 :1; /* Identifier Register Bit */ byte ID26 :1; /* Identifier Register Bit */ byte ID27 :1; /* Identifier Register Bit */ byte ID28 :1; /* Identifier Register Bit */ } Bits; } REC_IDR0STR; #define REC_IDR0 _REC_IDR.Overlap_STR.REC_IDR0STR.Byte #define REC_IDR0_ID21 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID21 #define REC_IDR0_ID22 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID22 #define REC_IDR0_ID23 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID23 #define REC_IDR0_ID24 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID24 #define REC_IDR0_ID25 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID25 #define REC_IDR0_ID26 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID26 #define REC_IDR0_ID27 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID27 #define REC_IDR0_ID28 _REC_IDR.Overlap_STR.REC_IDR0STR.Bits.ID28 /* REC_IDR_ARR: Access 4 REC_IDRx registers in an array */ #define REC_IDR_ARR ((volatile byte * __far) &REC_IDR0) #define REC_IDR0_ID21_MASK 1 #define REC_IDR0_ID22_MASK 2 #define REC_IDR0_ID23_MASK 4 #define REC_IDR0_ID24_MASK 8 #define REC_IDR0_ID25_MASK 16 #define REC_IDR0_ID26_MASK 32 #define REC_IDR0_ID27_MASK 64 #define REC_IDR0_ID28_MASK 128 /*** REC_IDR1 - Receive Buffer Identifier Register 1; 0x00000541 ***/ union { byte Byte; struct { byte ID15 :1; /* Identifier Register Bit */ byte ID16 :1; /* Identifier Register Bit */ byte ID17 :1; /* Identifier Register Bit */ byte IDE :1; /* ID Extended */ byte SRR :1; /* Substitute Remote Request */ byte ID18 :1; /* Identifier Register Bit */ byte ID19 :1; /* Identifier Register Bit */ byte ID20 :1; /* Identifier Register Bit */ } Bits; struct { byte grpID_15 :3; byte :1; byte :1; byte grpID_18 :3; } MergedBits; } REC_IDR1STR; #define REC_IDR1 _REC_IDR.Overlap_STR.REC_IDR1STR.Byte #define REC_IDR1_ID15 _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.ID15 #define REC_IDR1_ID16 _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.ID16 #define REC_IDR1_ID17 _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.ID17 #define REC_IDR1_IDE _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.IDE #define REC_IDR1_SRR _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.SRR #define REC_IDR1_ID18 _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.ID18 #define REC_IDR1_ID19 _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.ID19 #define REC_IDR1_ID20 _REC_IDR.Overlap_STR.REC_IDR1STR.Bits.ID20 #define REC_IDR1_ID_15 _REC_IDR.Overlap_STR.REC_IDR1STR.MergedBits.grpID_15 #define REC_IDR1_ID_18 _REC_IDR.Overlap_STR.REC_IDR1STR.MergedBits.grpID_18 #define REC_IDR1_ID REC_IDR1_ID_15 #define REC_IDR1_ID15_MASK 1 #define REC_IDR1_ID16_MASK 2 #define REC_IDR1_ID17_MASK 4 #define REC_IDR1_IDE_MASK 8 #define REC_IDR1_SRR_MASK 16 #define REC_IDR1_ID18_MASK 32 #define REC_IDR1_ID19_MASK 64 #define REC_IDR1_ID20_MASK 128 #define REC_IDR1_ID_15_MASK 7 #define REC_IDR1_ID_15_BITNUM 0 #define REC_IDR1_ID_18_MASK 224 #define REC_IDR1_ID_18_BITNUM 5 /*** REC_IDR2 - Receive Buffer Identifier Register 2; 0x00000542 ***/ union { byte Byte; struct { byte ID7 :1; /* Identifier Register Bit */ byte ID8 :1; /* Identifier Register Bit */ byte ID9 :1; /* Identifier Register Bit */ byte ID10 :1; /* Identifier Register Bit */ byte ID11 :1; /* Identifier Register Bit */ byte ID12 :1; /* Identifier Register Bit */ byte ID13 :1; /* Identifier Register Bit */ byte ID14 :1; /* Identifier Register Bit */ } Bits; } REC_IDR2STR; #define REC_IDR2 _REC_IDR.Overlap_STR.REC_IDR2STR.Byte #define REC_IDR2_ID7 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID7 #define REC_IDR2_ID8 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID8 #define REC_IDR2_ID9 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID9 #define REC_IDR2_ID10 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID10 #define REC_IDR2_ID11 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID11 #define REC_IDR2_ID12 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID12 #define REC_IDR2_ID13 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID13 #define REC_IDR2_ID14 _REC_IDR.Overlap_STR.REC_IDR2STR.Bits.ID14 #define REC_IDR2_ID7_MASK 1 #define REC_IDR2_ID8_MASK 2 #define REC_IDR2_ID9_MASK 4 #define REC_IDR2_ID10_MASK 8 #define REC_IDR2_ID11_MASK 16 #define REC_IDR2_ID12_MASK 32 #define REC_IDR2_ID13_MASK 64 #define REC_IDR2_ID14_MASK 128 /*** REC_IDR3 - Receive Buffer Identifier Register 3; 0x00000543 ***/ union { byte Byte; struct { byte RTR :1; /* Remote Transmission Request */ byte ID0 :1; /* Identifier Register Bit */ byte ID1 :1; /* Identifier Register Bit */ byte ID2 :1; /* Identifier Register Bit */ byte ID3 :1; /* Identifier Register Bit */ byte ID4 :1; /* Identifier Register Bit */ byte ID5 :1; /* Identifier Register Bit */ byte ID6 :1; /* Identifier Register Bit */ } Bits; struct { byte :1; byte grpID :7; } MergedBits; } REC_IDR3STR; #define REC_IDR3 _REC_IDR.Overlap_STR.REC_IDR3STR.Byte #define REC_IDR3_RTR _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.RTR #define REC_IDR3_ID0 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID0 #define REC_IDR3_ID1 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID1 #define REC_IDR3_ID2 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID2 #define REC_IDR3_ID3 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID3 #define REC_IDR3_ID4 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID4 #define REC_IDR3_ID5 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID5 #define REC_IDR3_ID6 _REC_IDR.Overlap_STR.REC_IDR3STR.Bits.ID6 #define REC_IDR3_ID _REC_IDR.Overlap_STR.REC_IDR3STR.MergedBits.grpID #define REC_IDR3_RTR_MASK 1 #define REC_IDR3_ID0_MASK 2 #define REC_IDR3_ID1_MASK 4 #define REC_IDR3_ID2_MASK 8 #define REC_IDR3_ID3_MASK 16 #define REC_IDR3_ID4_MASK 32 #define REC_IDR3_ID5_MASK 64 #define REC_IDR3_ID6_MASK 128 #define REC_IDR3_ID_MASK 254 #define REC_IDR3_ID_BITNUM 1 } Overlap_STR; } REC_IDRSTR; extern volatile REC_IDRSTR _REC_IDR @0x00000540; #define REC_IDR _REC_IDR.Dword /*** REC_DSR0 - Receive Buffer Data Segment Register 0; 0x00000544 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR0STR; extern volatile REC_DSR0STR _REC_DSR0 @0x00000544; #define REC_DSR0 _REC_DSR0.Byte #define REC_DSR0_DB0 _REC_DSR0.Bits.DB0 #define REC_DSR0_DB1 _REC_DSR0.Bits.DB1 #define REC_DSR0_DB2 _REC_DSR0.Bits.DB2 #define REC_DSR0_DB3 _REC_DSR0.Bits.DB3 #define REC_DSR0_DB4 _REC_DSR0.Bits.DB4 #define REC_DSR0_DB5 _REC_DSR0.Bits.DB5 #define REC_DSR0_DB6 _REC_DSR0.Bits.DB6 #define REC_DSR0_DB7 _REC_DSR0.Bits.DB7 /* REC_DSR_ARR: Access 8 REC_DSRx registers in an array */ #define REC_DSR_ARR ((volatile byte * __far) &REC_DSR0) #define REC_DSR0_DB0_MASK 1 #define REC_DSR0_DB1_MASK 2 #define REC_DSR0_DB2_MASK 4 #define REC_DSR0_DB3_MASK 8 #define REC_DSR0_DB4_MASK 16 #define REC_DSR0_DB5_MASK 32 #define REC_DSR0_DB6_MASK 64 #define REC_DSR0_DB7_MASK 128 /*** REC_DSR1 - Receive Buffer Data Segment Register 1; 0x00000545 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR1STR; extern volatile REC_DSR1STR _REC_DSR1 @0x00000545; #define REC_DSR1 _REC_DSR1.Byte #define REC_DSR1_DB0 _REC_DSR1.Bits.DB0 #define REC_DSR1_DB1 _REC_DSR1.Bits.DB1 #define REC_DSR1_DB2 _REC_DSR1.Bits.DB2 #define REC_DSR1_DB3 _REC_DSR1.Bits.DB3 #define REC_DSR1_DB4 _REC_DSR1.Bits.DB4 #define REC_DSR1_DB5 _REC_DSR1.Bits.DB5 #define REC_DSR1_DB6 _REC_DSR1.Bits.DB6 #define REC_DSR1_DB7 _REC_DSR1.Bits.DB7 #define REC_DSR1_DB0_MASK 1 #define REC_DSR1_DB1_MASK 2 #define REC_DSR1_DB2_MASK 4 #define REC_DSR1_DB3_MASK 8 #define REC_DSR1_DB4_MASK 16 #define REC_DSR1_DB5_MASK 32 #define REC_DSR1_DB6_MASK 64 #define REC_DSR1_DB7_MASK 128 /*** REC_DSR2 - Receive Buffer Data Segment Register 2; 0x00000546 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR2STR; extern volatile REC_DSR2STR _REC_DSR2 @0x00000546; #define REC_DSR2 _REC_DSR2.Byte #define REC_DSR2_DB0 _REC_DSR2.Bits.DB0 #define REC_DSR2_DB1 _REC_DSR2.Bits.DB1 #define REC_DSR2_DB2 _REC_DSR2.Bits.DB2 #define REC_DSR2_DB3 _REC_DSR2.Bits.DB3 #define REC_DSR2_DB4 _REC_DSR2.Bits.DB4 #define REC_DSR2_DB5 _REC_DSR2.Bits.DB5 #define REC_DSR2_DB6 _REC_DSR2.Bits.DB6 #define REC_DSR2_DB7 _REC_DSR2.Bits.DB7 #define REC_DSR2_DB0_MASK 1 #define REC_DSR2_DB1_MASK 2 #define REC_DSR2_DB2_MASK 4 #define REC_DSR2_DB3_MASK 8 #define REC_DSR2_DB4_MASK 16 #define REC_DSR2_DB5_MASK 32 #define REC_DSR2_DB6_MASK 64 #define REC_DSR2_DB7_MASK 128 /*** REC_DSR3 - Receive Buffer Data Segment Register 3; 0x00000547 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR3STR; extern volatile REC_DSR3STR _REC_DSR3 @0x00000547; #define REC_DSR3 _REC_DSR3.Byte #define REC_DSR3_DB0 _REC_DSR3.Bits.DB0 #define REC_DSR3_DB1 _REC_DSR3.Bits.DB1 #define REC_DSR3_DB2 _REC_DSR3.Bits.DB2 #define REC_DSR3_DB3 _REC_DSR3.Bits.DB3 #define REC_DSR3_DB4 _REC_DSR3.Bits.DB4 #define REC_DSR3_DB5 _REC_DSR3.Bits.DB5 #define REC_DSR3_DB6 _REC_DSR3.Bits.DB6 #define REC_DSR3_DB7 _REC_DSR3.Bits.DB7 #define REC_DSR3_DB0_MASK 1 #define REC_DSR3_DB1_MASK 2 #define REC_DSR3_DB2_MASK 4 #define REC_DSR3_DB3_MASK 8 #define REC_DSR3_DB4_MASK 16 #define REC_DSR3_DB5_MASK 32 #define REC_DSR3_DB6_MASK 64 #define REC_DSR3_DB7_MASK 128 /*** REC_DSR4 - Receive Buffer Data Segment Register 4; 0x00000548 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR4STR; extern volatile REC_DSR4STR _REC_DSR4 @0x00000548; #define REC_DSR4 _REC_DSR4.Byte #define REC_DSR4_DB0 _REC_DSR4.Bits.DB0 #define REC_DSR4_DB1 _REC_DSR4.Bits.DB1 #define REC_DSR4_DB2 _REC_DSR4.Bits.DB2 #define REC_DSR4_DB3 _REC_DSR4.Bits.DB3 #define REC_DSR4_DB4 _REC_DSR4.Bits.DB4 #define REC_DSR4_DB5 _REC_DSR4.Bits.DB5 #define REC_DSR4_DB6 _REC_DSR4.Bits.DB6 #define REC_DSR4_DB7 _REC_DSR4.Bits.DB7 #define REC_DSR4_DB0_MASK 1 #define REC_DSR4_DB1_MASK 2 #define REC_DSR4_DB2_MASK 4 #define REC_DSR4_DB3_MASK 8 #define REC_DSR4_DB4_MASK 16 #define REC_DSR4_DB5_MASK 32 #define REC_DSR4_DB6_MASK 64 #define REC_DSR4_DB7_MASK 128 /*** REC_DSR5 - Receive Buffer Data Segment Register 5; 0x00000549 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR5STR; extern volatile REC_DSR5STR _REC_DSR5 @0x00000549; #define REC_DSR5 _REC_DSR5.Byte #define REC_DSR5_DB0 _REC_DSR5.Bits.DB0 #define REC_DSR5_DB1 _REC_DSR5.Bits.DB1 #define REC_DSR5_DB2 _REC_DSR5.Bits.DB2 #define REC_DSR5_DB3 _REC_DSR5.Bits.DB3 #define REC_DSR5_DB4 _REC_DSR5.Bits.DB4 #define REC_DSR5_DB5 _REC_DSR5.Bits.DB5 #define REC_DSR5_DB6 _REC_DSR5.Bits.DB6 #define REC_DSR5_DB7 _REC_DSR5.Bits.DB7 #define REC_DSR5_DB0_MASK 1 #define REC_DSR5_DB1_MASK 2 #define REC_DSR5_DB2_MASK 4 #define REC_DSR5_DB3_MASK 8 #define REC_DSR5_DB4_MASK 16 #define REC_DSR5_DB5_MASK 32 #define REC_DSR5_DB6_MASK 64 #define REC_DSR5_DB7_MASK 128 /*** REC_DSR6 - Receive Buffer Data Segment Register 6; 0x0000054A ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR6STR; extern volatile REC_DSR6STR _REC_DSR6 @0x0000054A; #define REC_DSR6 _REC_DSR6.Byte #define REC_DSR6_DB0 _REC_DSR6.Bits.DB0 #define REC_DSR6_DB1 _REC_DSR6.Bits.DB1 #define REC_DSR6_DB2 _REC_DSR6.Bits.DB2 #define REC_DSR6_DB3 _REC_DSR6.Bits.DB3 #define REC_DSR6_DB4 _REC_DSR6.Bits.DB4 #define REC_DSR6_DB5 _REC_DSR6.Bits.DB5 #define REC_DSR6_DB6 _REC_DSR6.Bits.DB6 #define REC_DSR6_DB7 _REC_DSR6.Bits.DB7 #define REC_DSR6_DB0_MASK 1 #define REC_DSR6_DB1_MASK 2 #define REC_DSR6_DB2_MASK 4 #define REC_DSR6_DB3_MASK 8 #define REC_DSR6_DB4_MASK 16 #define REC_DSR6_DB5_MASK 32 #define REC_DSR6_DB6_MASK 64 #define REC_DSR6_DB7_MASK 128 /*** REC_DSR7 - Receive Buffer Data Segment Register 7; 0x0000054B ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } REC_DSR7STR; extern volatile REC_DSR7STR _REC_DSR7 @0x0000054B; #define REC_DSR7 _REC_DSR7.Byte #define REC_DSR7_DB0 _REC_DSR7.Bits.DB0 #define REC_DSR7_DB1 _REC_DSR7.Bits.DB1 #define REC_DSR7_DB2 _REC_DSR7.Bits.DB2 #define REC_DSR7_DB3 _REC_DSR7.Bits.DB3 #define REC_DSR7_DB4 _REC_DSR7.Bits.DB4 #define REC_DSR7_DB5 _REC_DSR7.Bits.DB5 #define REC_DSR7_DB6 _REC_DSR7.Bits.DB6 #define REC_DSR7_DB7 _REC_DSR7.Bits.DB7 #define REC_DSR7_DB0_MASK 1 #define REC_DSR7_DB1_MASK 2 #define REC_DSR7_DB2_MASK 4 #define REC_DSR7_DB3_MASK 8 #define REC_DSR7_DB4_MASK 16 #define REC_DSR7_DB5_MASK 32 #define REC_DSR7_DB6_MASK 64 #define REC_DSR7_DB7_MASK 128 /*** REC_DLR - Receive Buffer Data Length Register; 0x0000054C ***/ typedef union { byte Byte; struct { byte DLC0 :1; /* Data Length Code Bit */ byte DLC1 :1; /* Data Length Code Bit */ byte DLC2 :1; /* Data Length Code Bit */ byte DLC3 :1; /* Data Length Code Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDLC :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } REC_DLRSTR; extern volatile REC_DLRSTR _REC_DLR @0x0000054C; #define REC_DLR _REC_DLR.Byte #define REC_DLR_DLC0 _REC_DLR.Bits.DLC0 #define REC_DLR_DLC1 _REC_DLR.Bits.DLC1 #define REC_DLR_DLC2 _REC_DLR.Bits.DLC2 #define REC_DLR_DLC3 _REC_DLR.Bits.DLC3 #define REC_DLR_DLC _REC_DLR.MergedBits.grpDLC #define REC_DLR_DLC0_MASK 1 #define REC_DLR_DLC1_MASK 2 #define REC_DLR_DLC2_MASK 4 #define REC_DLR_DLC3_MASK 8 #define REC_DLR_DLC_MASK 15 #define REC_DLR_DLC_BITNUM 0 /*** IDR0 - Transmit Buffer 0 Identifier Register; 0x00000550 ***/ typedef union { dword Dword; /* Overlapped registers: */ struct { /*** IDR00 - Transmit Buffer 0 Identifier Register 0; 0x00000550 ***/ union { byte Byte; struct { byte ID21 :1; /* Identifier Register Bit */ byte ID22 :1; /* Identifier Register Bit */ byte ID23 :1; /* Identifier Register Bit */ byte ID24 :1; /* Identifier Register Bit */ byte ID25 :1; /* Identifier Register Bit */ byte ID26 :1; /* Identifier Register Bit */ byte ID27 :1; /* Identifier Register Bit */ byte ID28 :1; /* Identifier Register Bit */ } Bits; } IDR00STR; #define IDR00 _IDR0.Overlap_STR.IDR00STR.Byte #define IDR00_ID21 _IDR0.Overlap_STR.IDR00STR.Bits.ID21 #define IDR00_ID22 _IDR0.Overlap_STR.IDR00STR.Bits.ID22 #define IDR00_ID23 _IDR0.Overlap_STR.IDR00STR.Bits.ID23 #define IDR00_ID24 _IDR0.Overlap_STR.IDR00STR.Bits.ID24 #define IDR00_ID25 _IDR0.Overlap_STR.IDR00STR.Bits.ID25 #define IDR00_ID26 _IDR0.Overlap_STR.IDR00STR.Bits.ID26 #define IDR00_ID27 _IDR0.Overlap_STR.IDR00STR.Bits.ID27 #define IDR00_ID28 _IDR0.Overlap_STR.IDR00STR.Bits.ID28 #define IDR00_ID21_MASK 1 #define IDR00_ID22_MASK 2 #define IDR00_ID23_MASK 4 #define IDR00_ID24_MASK 8 #define IDR00_ID25_MASK 16 #define IDR00_ID26_MASK 32 #define IDR00_ID27_MASK 64 #define IDR00_ID28_MASK 128 /*** IDR10 - Transmit Buffer 0 Identifier Register 1; 0x00000551 ***/ union { byte Byte; struct { byte ID15 :1; /* Identifier Register Bit */ byte ID16 :1; /* Identifier Register Bit */ byte ID17 :1; /* Identifier Register Bit */ byte IDE :1; /* ID Extended */ byte SRR :1; /* Substitute Remote Request */ byte ID18 :1; /* Identifier Register Bit */ byte ID19 :1; /* Identifier Register Bit */ byte ID20 :1; /* Identifier Register Bit */ } Bits; struct { byte grpID_15 :3; byte :1; byte :1; byte grpID_18 :3; } MergedBits; } IDR10STR; #define IDR10 _IDR0.Overlap_STR.IDR10STR.Byte #define IDR10_ID15 _IDR0.Overlap_STR.IDR10STR.Bits.ID15 #define IDR10_ID16 _IDR0.Overlap_STR.IDR10STR.Bits.ID16 #define IDR10_ID17 _IDR0.Overlap_STR.IDR10STR.Bits.ID17 #define IDR10_IDE _IDR0.Overlap_STR.IDR10STR.Bits.IDE #define IDR10_SRR _IDR0.Overlap_STR.IDR10STR.Bits.SRR #define IDR10_ID18 _IDR0.Overlap_STR.IDR10STR.Bits.ID18 #define IDR10_ID19 _IDR0.Overlap_STR.IDR10STR.Bits.ID19 #define IDR10_ID20 _IDR0.Overlap_STR.IDR10STR.Bits.ID20 #define IDR10_ID_15 _IDR0.Overlap_STR.IDR10STR.MergedBits.grpID_15 #define IDR10_ID_18 _IDR0.Overlap_STR.IDR10STR.MergedBits.grpID_18 #define IDR10_ID IDR10_ID_15 #define IDR10_ID15_MASK 1 #define IDR10_ID16_MASK 2 #define IDR10_ID17_MASK 4 #define IDR10_IDE_MASK 8 #define IDR10_SRR_MASK 16 #define IDR10_ID18_MASK 32 #define IDR10_ID19_MASK 64 #define IDR10_ID20_MASK 128 #define IDR10_ID_15_MASK 7 #define IDR10_ID_15_BITNUM 0 #define IDR10_ID_18_MASK 224 #define IDR10_ID_18_BITNUM 5 /*** IDR20 - Transmit Buffer 0 Identifier Register 2; 0x00000552 ***/ union { byte Byte; struct { byte ID7 :1; /* Identifier Register Bit */ byte ID8 :1; /* Identifier Register Bit */ byte ID9 :1; /* Identifier Register Bit */ byte ID10 :1; /* Identifier Register Bit */ byte ID11 :1; /* Identifier Register Bit */ byte ID12 :1; /* Identifier Register Bit */ byte ID13 :1; /* Identifier Register Bit */ byte ID14 :1; /* Identifier Register Bit */ } Bits; } IDR20STR; #define IDR20 _IDR0.Overlap_STR.IDR20STR.Byte #define IDR20_ID7 _IDR0.Overlap_STR.IDR20STR.Bits.ID7 #define IDR20_ID8 _IDR0.Overlap_STR.IDR20STR.Bits.ID8 #define IDR20_ID9 _IDR0.Overlap_STR.IDR20STR.Bits.ID9 #define IDR20_ID10 _IDR0.Overlap_STR.IDR20STR.Bits.ID10 #define IDR20_ID11 _IDR0.Overlap_STR.IDR20STR.Bits.ID11 #define IDR20_ID12 _IDR0.Overlap_STR.IDR20STR.Bits.ID12 #define IDR20_ID13 _IDR0.Overlap_STR.IDR20STR.Bits.ID13 #define IDR20_ID14 _IDR0.Overlap_STR.IDR20STR.Bits.ID14 #define IDR20_ID7_MASK 1 #define IDR20_ID8_MASK 2 #define IDR20_ID9_MASK 4 #define IDR20_ID10_MASK 8 #define IDR20_ID11_MASK 16 #define IDR20_ID12_MASK 32 #define IDR20_ID13_MASK 64 #define IDR20_ID14_MASK 128 /*** IDR30 - Transmit Buffer 0 Identifier Register 3; 0x00000553 ***/ union { byte Byte; struct { byte RTR :1; /* Remote Transmission Request */ byte ID0 :1; /* Identifier Register Bit */ byte ID1 :1; /* Identifier Register Bit */ byte ID2 :1; /* Identifier Register Bit */ byte ID3 :1; /* Identifier Register Bit */ byte ID4 :1; /* Identifier Register Bit */ byte ID5 :1; /* Identifier Register Bit */ byte ID6 :1; /* Identifier Register Bit */ } Bits; struct { byte :1; byte grpID :7; } MergedBits; } IDR30STR; #define IDR30 _IDR0.Overlap_STR.IDR30STR.Byte #define IDR30_RTR _IDR0.Overlap_STR.IDR30STR.Bits.RTR #define IDR30_ID0 _IDR0.Overlap_STR.IDR30STR.Bits.ID0 #define IDR30_ID1 _IDR0.Overlap_STR.IDR30STR.Bits.ID1 #define IDR30_ID2 _IDR0.Overlap_STR.IDR30STR.Bits.ID2 #define IDR30_ID3 _IDR0.Overlap_STR.IDR30STR.Bits.ID3 #define IDR30_ID4 _IDR0.Overlap_STR.IDR30STR.Bits.ID4 #define IDR30_ID5 _IDR0.Overlap_STR.IDR30STR.Bits.ID5 #define IDR30_ID6 _IDR0.Overlap_STR.IDR30STR.Bits.ID6 #define IDR30_ID _IDR0.Overlap_STR.IDR30STR.MergedBits.grpID #define IDR30_RTR_MASK 1 #define IDR30_ID0_MASK 2 #define IDR30_ID1_MASK 4 #define IDR30_ID2_MASK 8 #define IDR30_ID3_MASK 16 #define IDR30_ID4_MASK 32 #define IDR30_ID5_MASK 64 #define IDR30_ID6_MASK 128 #define IDR30_ID_MASK 254 #define IDR30_ID_BITNUM 1 } Overlap_STR; } IDR0STR; extern volatile IDR0STR _IDR0 @0x00000550; #define IDR0 _IDR0.Dword /*** DSR00 - Transmit Buffer 0 Data Segment Register 0; 0x00000554 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR00STR; extern volatile DSR00STR _DSR00 @0x00000554; #define DSR00 _DSR00.Byte #define DSR00_DB0 _DSR00.Bits.DB0 #define DSR00_DB1 _DSR00.Bits.DB1 #define DSR00_DB2 _DSR00.Bits.DB2 #define DSR00_DB3 _DSR00.Bits.DB3 #define DSR00_DB4 _DSR00.Bits.DB4 #define DSR00_DB5 _DSR00.Bits.DB5 #define DSR00_DB6 _DSR00.Bits.DB6 #define DSR00_DB7 _DSR00.Bits.DB7 #define DSR00_DB0_MASK 1 #define DSR00_DB1_MASK 2 #define DSR00_DB2_MASK 4 #define DSR00_DB3_MASK 8 #define DSR00_DB4_MASK 16 #define DSR00_DB5_MASK 32 #define DSR00_DB6_MASK 64 #define DSR00_DB7_MASK 128 /*** DSR10 - Transmit Buffer 0 Data Segment Register 1; 0x00000555 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR10STR; extern volatile DSR10STR _DSR10 @0x00000555; #define DSR10 _DSR10.Byte #define DSR10_DB0 _DSR10.Bits.DB0 #define DSR10_DB1 _DSR10.Bits.DB1 #define DSR10_DB2 _DSR10.Bits.DB2 #define DSR10_DB3 _DSR10.Bits.DB3 #define DSR10_DB4 _DSR10.Bits.DB4 #define DSR10_DB5 _DSR10.Bits.DB5 #define DSR10_DB6 _DSR10.Bits.DB6 #define DSR10_DB7 _DSR10.Bits.DB7 #define DSR10_DB0_MASK 1 #define DSR10_DB1_MASK 2 #define DSR10_DB2_MASK 4 #define DSR10_DB3_MASK 8 #define DSR10_DB4_MASK 16 #define DSR10_DB5_MASK 32 #define DSR10_DB6_MASK 64 #define DSR10_DB7_MASK 128 /*** DSR20 - Transmit Buffer 0 Data Segment Register 2; 0x00000556 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR20STR; extern volatile DSR20STR _DSR20 @0x00000556; #define DSR20 _DSR20.Byte #define DSR20_DB0 _DSR20.Bits.DB0 #define DSR20_DB1 _DSR20.Bits.DB1 #define DSR20_DB2 _DSR20.Bits.DB2 #define DSR20_DB3 _DSR20.Bits.DB3 #define DSR20_DB4 _DSR20.Bits.DB4 #define DSR20_DB5 _DSR20.Bits.DB5 #define DSR20_DB6 _DSR20.Bits.DB6 #define DSR20_DB7 _DSR20.Bits.DB7 #define DSR20_DB0_MASK 1 #define DSR20_DB1_MASK 2 #define DSR20_DB2_MASK 4 #define DSR20_DB3_MASK 8 #define DSR20_DB4_MASK 16 #define DSR20_DB5_MASK 32 #define DSR20_DB6_MASK 64 #define DSR20_DB7_MASK 128 /*** DSR30 - Transmit Buffer 0 Data Segment Register 3; 0x00000557 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR30STR; extern volatile DSR30STR _DSR30 @0x00000557; #define DSR30 _DSR30.Byte #define DSR30_DB0 _DSR30.Bits.DB0 #define DSR30_DB1 _DSR30.Bits.DB1 #define DSR30_DB2 _DSR30.Bits.DB2 #define DSR30_DB3 _DSR30.Bits.DB3 #define DSR30_DB4 _DSR30.Bits.DB4 #define DSR30_DB5 _DSR30.Bits.DB5 #define DSR30_DB6 _DSR30.Bits.DB6 #define DSR30_DB7 _DSR30.Bits.DB7 #define DSR30_DB0_MASK 1 #define DSR30_DB1_MASK 2 #define DSR30_DB2_MASK 4 #define DSR30_DB3_MASK 8 #define DSR30_DB4_MASK 16 #define DSR30_DB5_MASK 32 #define DSR30_DB6_MASK 64 #define DSR30_DB7_MASK 128 /*** DSR40 - Transmit Buffer 0 Data Segment Register 4; 0x00000558 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR40STR; extern volatile DSR40STR _DSR40 @0x00000558; #define DSR40 _DSR40.Byte #define DSR40_DB0 _DSR40.Bits.DB0 #define DSR40_DB1 _DSR40.Bits.DB1 #define DSR40_DB2 _DSR40.Bits.DB2 #define DSR40_DB3 _DSR40.Bits.DB3 #define DSR40_DB4 _DSR40.Bits.DB4 #define DSR40_DB5 _DSR40.Bits.DB5 #define DSR40_DB6 _DSR40.Bits.DB6 #define DSR40_DB7 _DSR40.Bits.DB7 #define DSR40_DB0_MASK 1 #define DSR40_DB1_MASK 2 #define DSR40_DB2_MASK 4 #define DSR40_DB3_MASK 8 #define DSR40_DB4_MASK 16 #define DSR40_DB5_MASK 32 #define DSR40_DB6_MASK 64 #define DSR40_DB7_MASK 128 /*** DSR50 - Transmit Buffer 0 Data Segment Register 5; 0x00000559 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR50STR; extern volatile DSR50STR _DSR50 @0x00000559; #define DSR50 _DSR50.Byte #define DSR50_DB0 _DSR50.Bits.DB0 #define DSR50_DB1 _DSR50.Bits.DB1 #define DSR50_DB2 _DSR50.Bits.DB2 #define DSR50_DB3 _DSR50.Bits.DB3 #define DSR50_DB4 _DSR50.Bits.DB4 #define DSR50_DB5 _DSR50.Bits.DB5 #define DSR50_DB6 _DSR50.Bits.DB6 #define DSR50_DB7 _DSR50.Bits.DB7 #define DSR50_DB0_MASK 1 #define DSR50_DB1_MASK 2 #define DSR50_DB2_MASK 4 #define DSR50_DB3_MASK 8 #define DSR50_DB4_MASK 16 #define DSR50_DB5_MASK 32 #define DSR50_DB6_MASK 64 #define DSR50_DB7_MASK 128 /*** DSR60 - Transmit Buffer 0 Data Segment Register 6; 0x0000055A ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR60STR; extern volatile DSR60STR _DSR60 @0x0000055A; #define DSR60 _DSR60.Byte #define DSR60_DB0 _DSR60.Bits.DB0 #define DSR60_DB1 _DSR60.Bits.DB1 #define DSR60_DB2 _DSR60.Bits.DB2 #define DSR60_DB3 _DSR60.Bits.DB3 #define DSR60_DB4 _DSR60.Bits.DB4 #define DSR60_DB5 _DSR60.Bits.DB5 #define DSR60_DB6 _DSR60.Bits.DB6 #define DSR60_DB7 _DSR60.Bits.DB7 #define DSR60_DB0_MASK 1 #define DSR60_DB1_MASK 2 #define DSR60_DB2_MASK 4 #define DSR60_DB3_MASK 8 #define DSR60_DB4_MASK 16 #define DSR60_DB5_MASK 32 #define DSR60_DB6_MASK 64 #define DSR60_DB7_MASK 128 /*** DSR70 - Transmit Buffer 0 Data Segment Register 7; 0x0000055B ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR70STR; extern volatile DSR70STR _DSR70 @0x0000055B; #define DSR70 _DSR70.Byte #define DSR70_DB0 _DSR70.Bits.DB0 #define DSR70_DB1 _DSR70.Bits.DB1 #define DSR70_DB2 _DSR70.Bits.DB2 #define DSR70_DB3 _DSR70.Bits.DB3 #define DSR70_DB4 _DSR70.Bits.DB4 #define DSR70_DB5 _DSR70.Bits.DB5 #define DSR70_DB6 _DSR70.Bits.DB6 #define DSR70_DB7 _DSR70.Bits.DB7 #define DSR70_DB0_MASK 1 #define DSR70_DB1_MASK 2 #define DSR70_DB2_MASK 4 #define DSR70_DB3_MASK 8 #define DSR70_DB4_MASK 16 #define DSR70_DB5_MASK 32 #define DSR70_DB6_MASK 64 #define DSR70_DB7_MASK 128 /*** DLR0 - Transmit Buffer 0 Data Length Register; 0x0000055C ***/ typedef union { byte Byte; struct { byte DLC0 :1; /* Data Length Code Bit */ byte DLC1 :1; /* Data Length Code Bit */ byte DLC2 :1; /* Data Length Code Bit */ byte DLC3 :1; /* Data Length Code Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDLC :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DLR0STR; extern volatile DLR0STR _DLR0 @0x0000055C; #define DLR0 _DLR0.Byte #define DLR0_DLC0 _DLR0.Bits.DLC0 #define DLR0_DLC1 _DLR0.Bits.DLC1 #define DLR0_DLC2 _DLR0.Bits.DLC2 #define DLR0_DLC3 _DLR0.Bits.DLC3 #define DLR0_DLC _DLR0.MergedBits.grpDLC #define DLR0_DLC0_MASK 1 #define DLR0_DLC1_MASK 2 #define DLR0_DLC2_MASK 4 #define DLR0_DLC3_MASK 8 #define DLR0_DLC_MASK 15 #define DLR0_DLC_BITNUM 0 /*** TBPR0 - Transmit Buffer 0 Priority Register; 0x0000055D ***/ typedef union { byte Byte; struct { byte PRIO0 :1; /* Local Priority */ byte PRIO1 :1; /* Local Priority */ byte PRIO2 :1; /* Local Priority */ byte PRIO3 :1; /* Local Priority */ byte PRIO4 :1; /* Local Priority */ byte PRIO5 :1; /* Local Priority */ byte PRIO6 :1; /* Local Priority */ byte PRIO7 :1; /* Local Priority */ } Bits; } TBPR0STR; extern volatile TBPR0STR _TBPR0 @0x0000055D; #define TBPR0 _TBPR0.Byte #define TBPR0_PRIO0 _TBPR0.Bits.PRIO0 #define TBPR0_PRIO1 _TBPR0.Bits.PRIO1 #define TBPR0_PRIO2 _TBPR0.Bits.PRIO2 #define TBPR0_PRIO3 _TBPR0.Bits.PRIO3 #define TBPR0_PRIO4 _TBPR0.Bits.PRIO4 #define TBPR0_PRIO5 _TBPR0.Bits.PRIO5 #define TBPR0_PRIO6 _TBPR0.Bits.PRIO6 #define TBPR0_PRIO7 _TBPR0.Bits.PRIO7 #define TBPR0_PRIO0_MASK 1 #define TBPR0_PRIO1_MASK 2 #define TBPR0_PRIO2_MASK 4 #define TBPR0_PRIO3_MASK 8 #define TBPR0_PRIO4_MASK 16 #define TBPR0_PRIO5_MASK 32 #define TBPR0_PRIO6_MASK 64 #define TBPR0_PRIO7_MASK 128 /*** IDR1 - Transmit Buffer 1 Identifier Register; 0x00000560 ***/ typedef union { dword Dword; /* Overlapped registers: */ struct { /*** IDR01 - Transmit Buffer 1 Identifier Register 0; 0x00000560 ***/ union { byte Byte; struct { byte ID21 :1; /* Identifier Register Bit */ byte ID22 :1; /* Identifier Register Bit */ byte ID23 :1; /* Identifier Register Bit */ byte ID24 :1; /* Identifier Register Bit */ byte ID25 :1; /* Identifier Register Bit */ byte ID26 :1; /* Identifier Register Bit */ byte ID27 :1; /* Identifier Register Bit */ byte ID28 :1; /* Identifier Register Bit */ } Bits; } IDR01STR; #define IDR01 _IDR1.Overlap_STR.IDR01STR.Byte #define IDR01_ID21 _IDR1.Overlap_STR.IDR01STR.Bits.ID21 #define IDR01_ID22 _IDR1.Overlap_STR.IDR01STR.Bits.ID22 #define IDR01_ID23 _IDR1.Overlap_STR.IDR01STR.Bits.ID23 #define IDR01_ID24 _IDR1.Overlap_STR.IDR01STR.Bits.ID24 #define IDR01_ID25 _IDR1.Overlap_STR.IDR01STR.Bits.ID25 #define IDR01_ID26 _IDR1.Overlap_STR.IDR01STR.Bits.ID26 #define IDR01_ID27 _IDR1.Overlap_STR.IDR01STR.Bits.ID27 #define IDR01_ID28 _IDR1.Overlap_STR.IDR01STR.Bits.ID28 #define IDR01_ID21_MASK 1 #define IDR01_ID22_MASK 2 #define IDR01_ID23_MASK 4 #define IDR01_ID24_MASK 8 #define IDR01_ID25_MASK 16 #define IDR01_ID26_MASK 32 #define IDR01_ID27_MASK 64 #define IDR01_ID28_MASK 128 /*** IDR11 - Transmit Buffer 1 Identifier Register 1; 0x00000561 ***/ union { byte Byte; struct { byte ID15 :1; /* Identifier Register Bit */ byte ID16 :1; /* Identifier Register Bit */ byte ID17 :1; /* Identifier Register Bit */ byte IDE :1; /* ID Extended */ byte SRR :1; /* Substitute Remote Request */ byte ID18 :1; /* Identifier Register Bit */ byte ID19 :1; /* Identifier Register Bit */ byte ID20 :1; /* Identifier Register Bit */ } Bits; struct { byte grpID_15 :3; byte :1; byte :1; byte grpID_18 :3; } MergedBits; } IDR11STR; #define IDR11 _IDR1.Overlap_STR.IDR11STR.Byte #define IDR11_ID15 _IDR1.Overlap_STR.IDR11STR.Bits.ID15 #define IDR11_ID16 _IDR1.Overlap_STR.IDR11STR.Bits.ID16 #define IDR11_ID17 _IDR1.Overlap_STR.IDR11STR.Bits.ID17 #define IDR11_IDE _IDR1.Overlap_STR.IDR11STR.Bits.IDE #define IDR11_SRR _IDR1.Overlap_STR.IDR11STR.Bits.SRR #define IDR11_ID18 _IDR1.Overlap_STR.IDR11STR.Bits.ID18 #define IDR11_ID19 _IDR1.Overlap_STR.IDR11STR.Bits.ID19 #define IDR11_ID20 _IDR1.Overlap_STR.IDR11STR.Bits.ID20 #define IDR11_ID_15 _IDR1.Overlap_STR.IDR11STR.MergedBits.grpID_15 #define IDR11_ID_18 _IDR1.Overlap_STR.IDR11STR.MergedBits.grpID_18 #define IDR11_ID IDR11_ID_15 #define IDR11_ID15_MASK 1 #define IDR11_ID16_MASK 2 #define IDR11_ID17_MASK 4 #define IDR11_IDE_MASK 8 #define IDR11_SRR_MASK 16 #define IDR11_ID18_MASK 32 #define IDR11_ID19_MASK 64 #define IDR11_ID20_MASK 128 #define IDR11_ID_15_MASK 7 #define IDR11_ID_15_BITNUM 0 #define IDR11_ID_18_MASK 224 #define IDR11_ID_18_BITNUM 5 /*** IDR21 - Transmit Buffer 1 Identifier Register 2; 0x00000562 ***/ union { byte Byte; struct { byte ID7 :1; /* Identifier Register Bit */ byte ID8 :1; /* Identifier Register Bit */ byte ID9 :1; /* Identifier Register Bit */ byte ID10 :1; /* Identifier Register Bit */ byte ID11 :1; /* Identifier Register Bit */ byte ID12 :1; /* Identifier Register Bit */ byte ID13 :1; /* Identifier Register Bit */ byte ID14 :1; /* Identifier Register Bit */ } Bits; } IDR21STR; #define IDR21 _IDR1.Overlap_STR.IDR21STR.Byte #define IDR21_ID7 _IDR1.Overlap_STR.IDR21STR.Bits.ID7 #define IDR21_ID8 _IDR1.Overlap_STR.IDR21STR.Bits.ID8 #define IDR21_ID9 _IDR1.Overlap_STR.IDR21STR.Bits.ID9 #define IDR21_ID10 _IDR1.Overlap_STR.IDR21STR.Bits.ID10 #define IDR21_ID11 _IDR1.Overlap_STR.IDR21STR.Bits.ID11 #define IDR21_ID12 _IDR1.Overlap_STR.IDR21STR.Bits.ID12 #define IDR21_ID13 _IDR1.Overlap_STR.IDR21STR.Bits.ID13 #define IDR21_ID14 _IDR1.Overlap_STR.IDR21STR.Bits.ID14 #define IDR21_ID7_MASK 1 #define IDR21_ID8_MASK 2 #define IDR21_ID9_MASK 4 #define IDR21_ID10_MASK 8 #define IDR21_ID11_MASK 16 #define IDR21_ID12_MASK 32 #define IDR21_ID13_MASK 64 #define IDR21_ID14_MASK 128 /*** IDR31 - Transmit Buffer 1 Identifier Register 3; 0x00000563 ***/ union { byte Byte; struct { byte RTR :1; /* Remote Transmission Request */ byte ID0 :1; /* Identifier Register Bit */ byte ID1 :1; /* Identifier Register Bit */ byte ID2 :1; /* Identifier Register Bit */ byte ID3 :1; /* Identifier Register Bit */ byte ID4 :1; /* Identifier Register Bit */ byte ID5 :1; /* Identifier Register Bit */ byte ID6 :1; /* Identifier Register Bit */ } Bits; struct { byte :1; byte grpID :7; } MergedBits; } IDR31STR; #define IDR31 _IDR1.Overlap_STR.IDR31STR.Byte #define IDR31_RTR _IDR1.Overlap_STR.IDR31STR.Bits.RTR #define IDR31_ID0 _IDR1.Overlap_STR.IDR31STR.Bits.ID0 #define IDR31_ID1 _IDR1.Overlap_STR.IDR31STR.Bits.ID1 #define IDR31_ID2 _IDR1.Overlap_STR.IDR31STR.Bits.ID2 #define IDR31_ID3 _IDR1.Overlap_STR.IDR31STR.Bits.ID3 #define IDR31_ID4 _IDR1.Overlap_STR.IDR31STR.Bits.ID4 #define IDR31_ID5 _IDR1.Overlap_STR.IDR31STR.Bits.ID5 #define IDR31_ID6 _IDR1.Overlap_STR.IDR31STR.Bits.ID6 #define IDR31_ID _IDR1.Overlap_STR.IDR31STR.MergedBits.grpID #define IDR31_RTR_MASK 1 #define IDR31_ID0_MASK 2 #define IDR31_ID1_MASK 4 #define IDR31_ID2_MASK 8 #define IDR31_ID3_MASK 16 #define IDR31_ID4_MASK 32 #define IDR31_ID5_MASK 64 #define IDR31_ID6_MASK 128 #define IDR31_ID_MASK 254 #define IDR31_ID_BITNUM 1 } Overlap_STR; } IDR1STR; extern volatile IDR1STR _IDR1 @0x00000560; #define IDR1 _IDR1.Dword /*** DSR01 - Transmit Buffer 1 Data Segment Register 0; 0x00000564 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR01STR; extern volatile DSR01STR _DSR01 @0x00000564; #define DSR01 _DSR01.Byte #define DSR01_DB0 _DSR01.Bits.DB0 #define DSR01_DB1 _DSR01.Bits.DB1 #define DSR01_DB2 _DSR01.Bits.DB2 #define DSR01_DB3 _DSR01.Bits.DB3 #define DSR01_DB4 _DSR01.Bits.DB4 #define DSR01_DB5 _DSR01.Bits.DB5 #define DSR01_DB6 _DSR01.Bits.DB6 #define DSR01_DB7 _DSR01.Bits.DB7 #define DSR01_DB0_MASK 1 #define DSR01_DB1_MASK 2 #define DSR01_DB2_MASK 4 #define DSR01_DB3_MASK 8 #define DSR01_DB4_MASK 16 #define DSR01_DB5_MASK 32 #define DSR01_DB6_MASK 64 #define DSR01_DB7_MASK 128 /*** DSR11 - Transmit Buffer 1 Data Segment Register 1; 0x00000565 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR11STR; extern volatile DSR11STR _DSR11 @0x00000565; #define DSR11 _DSR11.Byte #define DSR11_DB0 _DSR11.Bits.DB0 #define DSR11_DB1 _DSR11.Bits.DB1 #define DSR11_DB2 _DSR11.Bits.DB2 #define DSR11_DB3 _DSR11.Bits.DB3 #define DSR11_DB4 _DSR11.Bits.DB4 #define DSR11_DB5 _DSR11.Bits.DB5 #define DSR11_DB6 _DSR11.Bits.DB6 #define DSR11_DB7 _DSR11.Bits.DB7 #define DSR11_DB0_MASK 1 #define DSR11_DB1_MASK 2 #define DSR11_DB2_MASK 4 #define DSR11_DB3_MASK 8 #define DSR11_DB4_MASK 16 #define DSR11_DB5_MASK 32 #define DSR11_DB6_MASK 64 #define DSR11_DB7_MASK 128 /*** DSR21 - Transmit Buffer 1 Data Segment Register 2; 0x00000566 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR21STR; extern volatile DSR21STR _DSR21 @0x00000566; #define DSR21 _DSR21.Byte #define DSR21_DB0 _DSR21.Bits.DB0 #define DSR21_DB1 _DSR21.Bits.DB1 #define DSR21_DB2 _DSR21.Bits.DB2 #define DSR21_DB3 _DSR21.Bits.DB3 #define DSR21_DB4 _DSR21.Bits.DB4 #define DSR21_DB5 _DSR21.Bits.DB5 #define DSR21_DB6 _DSR21.Bits.DB6 #define DSR21_DB7 _DSR21.Bits.DB7 #define DSR21_DB0_MASK 1 #define DSR21_DB1_MASK 2 #define DSR21_DB2_MASK 4 #define DSR21_DB3_MASK 8 #define DSR21_DB4_MASK 16 #define DSR21_DB5_MASK 32 #define DSR21_DB6_MASK 64 #define DSR21_DB7_MASK 128 /*** DSR31 - Transmit Buffer 1 Data Segment Register 3; 0x00000567 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR31STR; extern volatile DSR31STR _DSR31 @0x00000567; #define DSR31 _DSR31.Byte #define DSR31_DB0 _DSR31.Bits.DB0 #define DSR31_DB1 _DSR31.Bits.DB1 #define DSR31_DB2 _DSR31.Bits.DB2 #define DSR31_DB3 _DSR31.Bits.DB3 #define DSR31_DB4 _DSR31.Bits.DB4 #define DSR31_DB5 _DSR31.Bits.DB5 #define DSR31_DB6 _DSR31.Bits.DB6 #define DSR31_DB7 _DSR31.Bits.DB7 #define DSR31_DB0_MASK 1 #define DSR31_DB1_MASK 2 #define DSR31_DB2_MASK 4 #define DSR31_DB3_MASK 8 #define DSR31_DB4_MASK 16 #define DSR31_DB5_MASK 32 #define DSR31_DB6_MASK 64 #define DSR31_DB7_MASK 128 /*** DSR41 - Transmit Buffer 1 Data Segment Register 4; 0x00000568 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR41STR; extern volatile DSR41STR _DSR41 @0x00000568; #define DSR41 _DSR41.Byte #define DSR41_DB0 _DSR41.Bits.DB0 #define DSR41_DB1 _DSR41.Bits.DB1 #define DSR41_DB2 _DSR41.Bits.DB2 #define DSR41_DB3 _DSR41.Bits.DB3 #define DSR41_DB4 _DSR41.Bits.DB4 #define DSR41_DB5 _DSR41.Bits.DB5 #define DSR41_DB6 _DSR41.Bits.DB6 #define DSR41_DB7 _DSR41.Bits.DB7 #define DSR41_DB0_MASK 1 #define DSR41_DB1_MASK 2 #define DSR41_DB2_MASK 4 #define DSR41_DB3_MASK 8 #define DSR41_DB4_MASK 16 #define DSR41_DB5_MASK 32 #define DSR41_DB6_MASK 64 #define DSR41_DB7_MASK 128 /*** DSR51 - Transmit Buffer 1 Data Segment Register 5; 0x00000569 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR51STR; extern volatile DSR51STR _DSR51 @0x00000569; #define DSR51 _DSR51.Byte #define DSR51_DB0 _DSR51.Bits.DB0 #define DSR51_DB1 _DSR51.Bits.DB1 #define DSR51_DB2 _DSR51.Bits.DB2 #define DSR51_DB3 _DSR51.Bits.DB3 #define DSR51_DB4 _DSR51.Bits.DB4 #define DSR51_DB5 _DSR51.Bits.DB5 #define DSR51_DB6 _DSR51.Bits.DB6 #define DSR51_DB7 _DSR51.Bits.DB7 #define DSR51_DB0_MASK 1 #define DSR51_DB1_MASK 2 #define DSR51_DB2_MASK 4 #define DSR51_DB3_MASK 8 #define DSR51_DB4_MASK 16 #define DSR51_DB5_MASK 32 #define DSR51_DB6_MASK 64 #define DSR51_DB7_MASK 128 /*** DSR61 - Transmit Buffer 1 Data Segment Register 6; 0x0000056A ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR61STR; extern volatile DSR61STR _DSR61 @0x0000056A; #define DSR61 _DSR61.Byte #define DSR61_DB0 _DSR61.Bits.DB0 #define DSR61_DB1 _DSR61.Bits.DB1 #define DSR61_DB2 _DSR61.Bits.DB2 #define DSR61_DB3 _DSR61.Bits.DB3 #define DSR61_DB4 _DSR61.Bits.DB4 #define DSR61_DB5 _DSR61.Bits.DB5 #define DSR61_DB6 _DSR61.Bits.DB6 #define DSR61_DB7 _DSR61.Bits.DB7 #define DSR61_DB0_MASK 1 #define DSR61_DB1_MASK 2 #define DSR61_DB2_MASK 4 #define DSR61_DB3_MASK 8 #define DSR61_DB4_MASK 16 #define DSR61_DB5_MASK 32 #define DSR61_DB6_MASK 64 #define DSR61_DB7_MASK 128 /*** DSR71 - Transmit Buffer 1 Data Segment Register 7; 0x0000056B ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR71STR; extern volatile DSR71STR _DSR71 @0x0000056B; #define DSR71 _DSR71.Byte #define DSR71_DB0 _DSR71.Bits.DB0 #define DSR71_DB1 _DSR71.Bits.DB1 #define DSR71_DB2 _DSR71.Bits.DB2 #define DSR71_DB3 _DSR71.Bits.DB3 #define DSR71_DB4 _DSR71.Bits.DB4 #define DSR71_DB5 _DSR71.Bits.DB5 #define DSR71_DB6 _DSR71.Bits.DB6 #define DSR71_DB7 _DSR71.Bits.DB7 #define DSR71_DB0_MASK 1 #define DSR71_DB1_MASK 2 #define DSR71_DB2_MASK 4 #define DSR71_DB3_MASK 8 #define DSR71_DB4_MASK 16 #define DSR71_DB5_MASK 32 #define DSR71_DB6_MASK 64 #define DSR71_DB7_MASK 128 /*** DLR1 - Transmit Buffer 1 Data Length Register; 0x0000056C ***/ typedef union { byte Byte; struct { byte DLC0 :1; /* Data Length Code Bit */ byte DLC1 :1; /* Data Length Code Bit */ byte DLC2 :1; /* Data Length Code Bit */ byte DLC3 :1; /* Data Length Code Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDLC :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DLR1STR; extern volatile DLR1STR _DLR1 @0x0000056C; #define DLR1 _DLR1.Byte #define DLR1_DLC0 _DLR1.Bits.DLC0 #define DLR1_DLC1 _DLR1.Bits.DLC1 #define DLR1_DLC2 _DLR1.Bits.DLC2 #define DLR1_DLC3 _DLR1.Bits.DLC3 #define DLR1_DLC _DLR1.MergedBits.grpDLC #define DLR1_DLC0_MASK 1 #define DLR1_DLC1_MASK 2 #define DLR1_DLC2_MASK 4 #define DLR1_DLC3_MASK 8 #define DLR1_DLC_MASK 15 #define DLR1_DLC_BITNUM 0 /*** TBPR1 - Transmit Buffer 1 Priority Register; 0x0000056D ***/ typedef union { byte Byte; struct { byte PRIO0 :1; /* Local Priority */ byte PRIO1 :1; /* Local Priority */ byte PRIO2 :1; /* Local Priority */ byte PRIO3 :1; /* Local Priority */ byte PRIO4 :1; /* Local Priority */ byte PRIO5 :1; /* Local Priority */ byte PRIO6 :1; /* Local Priority */ byte PRIO7 :1; /* Local Priority */ } Bits; } TBPR1STR; extern volatile TBPR1STR _TBPR1 @0x0000056D; #define TBPR1 _TBPR1.Byte #define TBPR1_PRIO0 _TBPR1.Bits.PRIO0 #define TBPR1_PRIO1 _TBPR1.Bits.PRIO1 #define TBPR1_PRIO2 _TBPR1.Bits.PRIO2 #define TBPR1_PRIO3 _TBPR1.Bits.PRIO3 #define TBPR1_PRIO4 _TBPR1.Bits.PRIO4 #define TBPR1_PRIO5 _TBPR1.Bits.PRIO5 #define TBPR1_PRIO6 _TBPR1.Bits.PRIO6 #define TBPR1_PRIO7 _TBPR1.Bits.PRIO7 #define TBPR1_PRIO0_MASK 1 #define TBPR1_PRIO1_MASK 2 #define TBPR1_PRIO2_MASK 4 #define TBPR1_PRIO3_MASK 8 #define TBPR1_PRIO4_MASK 16 #define TBPR1_PRIO5_MASK 32 #define TBPR1_PRIO6_MASK 64 #define TBPR1_PRIO7_MASK 128 /*** IDR2 - Transmit Buffer 2 Identifier Register; 0x00000570 ***/ typedef union { dword Dword; /* Overlapped registers: */ struct { /*** IDR02 - Transmit Buffer 2 Identifier Register 0; 0x00000570 ***/ union { byte Byte; struct { byte ID21 :1; /* Identifier Register Bit */ byte ID22 :1; /* Identifier Register Bit */ byte ID23 :1; /* Identifier Register Bit */ byte ID24 :1; /* Identifier Register Bit */ byte ID25 :1; /* Identifier Register Bit */ byte ID26 :1; /* Identifier Register Bit */ byte ID27 :1; /* Identifier Register Bit */ byte ID28 :1; /* Identifier Register Bit */ } Bits; } IDR02STR; #define IDR02 _IDR2.Overlap_STR.IDR02STR.Byte #define IDR02_ID21 _IDR2.Overlap_STR.IDR02STR.Bits.ID21 #define IDR02_ID22 _IDR2.Overlap_STR.IDR02STR.Bits.ID22 #define IDR02_ID23 _IDR2.Overlap_STR.IDR02STR.Bits.ID23 #define IDR02_ID24 _IDR2.Overlap_STR.IDR02STR.Bits.ID24 #define IDR02_ID25 _IDR2.Overlap_STR.IDR02STR.Bits.ID25 #define IDR02_ID26 _IDR2.Overlap_STR.IDR02STR.Bits.ID26 #define IDR02_ID27 _IDR2.Overlap_STR.IDR02STR.Bits.ID27 #define IDR02_ID28 _IDR2.Overlap_STR.IDR02STR.Bits.ID28 #define IDR02_ID21_MASK 1 #define IDR02_ID22_MASK 2 #define IDR02_ID23_MASK 4 #define IDR02_ID24_MASK 8 #define IDR02_ID25_MASK 16 #define IDR02_ID26_MASK 32 #define IDR02_ID27_MASK 64 #define IDR02_ID28_MASK 128 /*** IDR12 - Transmit Buffer 2 Identifier Register 1; 0x00000571 ***/ union { byte Byte; struct { byte ID15 :1; /* Identifier Register Bit */ byte ID16 :1; /* Identifier Register Bit */ byte ID17 :1; /* Identifier Register Bit */ byte IDE :1; /* ID Extended */ byte SRR :1; /* Substitute Remote Request */ byte ID18 :1; /* Identifier Register Bit */ byte ID19 :1; /* Identifier Register Bit */ byte ID20 :1; /* Identifier Register Bit */ } Bits; struct { byte grpID_15 :3; byte :1; byte :1; byte grpID_18 :3; } MergedBits; } IDR12STR; #define IDR12 _IDR2.Overlap_STR.IDR12STR.Byte #define IDR12_ID15 _IDR2.Overlap_STR.IDR12STR.Bits.ID15 #define IDR12_ID16 _IDR2.Overlap_STR.IDR12STR.Bits.ID16 #define IDR12_ID17 _IDR2.Overlap_STR.IDR12STR.Bits.ID17 #define IDR12_IDE _IDR2.Overlap_STR.IDR12STR.Bits.IDE #define IDR12_SRR _IDR2.Overlap_STR.IDR12STR.Bits.SRR #define IDR12_ID18 _IDR2.Overlap_STR.IDR12STR.Bits.ID18 #define IDR12_ID19 _IDR2.Overlap_STR.IDR12STR.Bits.ID19 #define IDR12_ID20 _IDR2.Overlap_STR.IDR12STR.Bits.ID20 #define IDR12_ID_15 _IDR2.Overlap_STR.IDR12STR.MergedBits.grpID_15 #define IDR12_ID_18 _IDR2.Overlap_STR.IDR12STR.MergedBits.grpID_18 #define IDR12_ID IDR12_ID_15 #define IDR12_ID15_MASK 1 #define IDR12_ID16_MASK 2 #define IDR12_ID17_MASK 4 #define IDR12_IDE_MASK 8 #define IDR12_SRR_MASK 16 #define IDR12_ID18_MASK 32 #define IDR12_ID19_MASK 64 #define IDR12_ID20_MASK 128 #define IDR12_ID_15_MASK 7 #define IDR12_ID_15_BITNUM 0 #define IDR12_ID_18_MASK 224 #define IDR12_ID_18_BITNUM 5 /*** IDR22 - Transmit Buffer 2 Identifier Register 2; 0x00000572 ***/ union { byte Byte; struct { byte ID7 :1; /* Identifier Register Bit */ byte ID8 :1; /* Identifier Register Bit */ byte ID9 :1; /* Identifier Register Bit */ byte ID10 :1; /* Identifier Register Bit */ byte ID11 :1; /* Identifier Register Bit */ byte ID12 :1; /* Identifier Register Bit */ byte ID13 :1; /* Identifier Register Bit */ byte ID14 :1; /* Identifier Register Bit */ } Bits; } IDR22STR; #define IDR22 _IDR2.Overlap_STR.IDR22STR.Byte #define IDR22_ID7 _IDR2.Overlap_STR.IDR22STR.Bits.ID7 #define IDR22_ID8 _IDR2.Overlap_STR.IDR22STR.Bits.ID8 #define IDR22_ID9 _IDR2.Overlap_STR.IDR22STR.Bits.ID9 #define IDR22_ID10 _IDR2.Overlap_STR.IDR22STR.Bits.ID10 #define IDR22_ID11 _IDR2.Overlap_STR.IDR22STR.Bits.ID11 #define IDR22_ID12 _IDR2.Overlap_STR.IDR22STR.Bits.ID12 #define IDR22_ID13 _IDR2.Overlap_STR.IDR22STR.Bits.ID13 #define IDR22_ID14 _IDR2.Overlap_STR.IDR22STR.Bits.ID14 #define IDR22_ID7_MASK 1 #define IDR22_ID8_MASK 2 #define IDR22_ID9_MASK 4 #define IDR22_ID10_MASK 8 #define IDR22_ID11_MASK 16 #define IDR22_ID12_MASK 32 #define IDR22_ID13_MASK 64 #define IDR22_ID14_MASK 128 /*** IDR32 - Transmit Buffer 2 Identifier Register 3; 0x00000573 ***/ union { byte Byte; struct { byte RTR :1; /* Remote Transmission Request */ byte ID0 :1; /* Identifier Register Bit */ byte ID1 :1; /* Identifier Register Bit */ byte ID2 :1; /* Identifier Register Bit */ byte ID3 :1; /* Identifier Register Bit */ byte ID4 :1; /* Identifier Register Bit */ byte ID5 :1; /* Identifier Register Bit */ byte ID6 :1; /* Identifier Register Bit */ } Bits; struct { byte :1; byte grpID :7; } MergedBits; } IDR32STR; #define IDR32 _IDR2.Overlap_STR.IDR32STR.Byte #define IDR32_RTR _IDR2.Overlap_STR.IDR32STR.Bits.RTR #define IDR32_ID0 _IDR2.Overlap_STR.IDR32STR.Bits.ID0 #define IDR32_ID1 _IDR2.Overlap_STR.IDR32STR.Bits.ID1 #define IDR32_ID2 _IDR2.Overlap_STR.IDR32STR.Bits.ID2 #define IDR32_ID3 _IDR2.Overlap_STR.IDR32STR.Bits.ID3 #define IDR32_ID4 _IDR2.Overlap_STR.IDR32STR.Bits.ID4 #define IDR32_ID5 _IDR2.Overlap_STR.IDR32STR.Bits.ID5 #define IDR32_ID6 _IDR2.Overlap_STR.IDR32STR.Bits.ID6 #define IDR32_ID _IDR2.Overlap_STR.IDR32STR.MergedBits.grpID #define IDR32_RTR_MASK 1 #define IDR32_ID0_MASK 2 #define IDR32_ID1_MASK 4 #define IDR32_ID2_MASK 8 #define IDR32_ID3_MASK 16 #define IDR32_ID4_MASK 32 #define IDR32_ID5_MASK 64 #define IDR32_ID6_MASK 128 #define IDR32_ID_MASK 254 #define IDR32_ID_BITNUM 1 } Overlap_STR; } IDR2STR; extern volatile IDR2STR _IDR2 @0x00000570; #define IDR2 _IDR2.Dword /*** DSR02 - Transmit Buffer 2 Data Segment Register 0; 0x00000574 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR02STR; extern volatile DSR02STR _DSR02 @0x00000574; #define DSR02 _DSR02.Byte #define DSR02_DB0 _DSR02.Bits.DB0 #define DSR02_DB1 _DSR02.Bits.DB1 #define DSR02_DB2 _DSR02.Bits.DB2 #define DSR02_DB3 _DSR02.Bits.DB3 #define DSR02_DB4 _DSR02.Bits.DB4 #define DSR02_DB5 _DSR02.Bits.DB5 #define DSR02_DB6 _DSR02.Bits.DB6 #define DSR02_DB7 _DSR02.Bits.DB7 #define DSR02_DB0_MASK 1 #define DSR02_DB1_MASK 2 #define DSR02_DB2_MASK 4 #define DSR02_DB3_MASK 8 #define DSR02_DB4_MASK 16 #define DSR02_DB5_MASK 32 #define DSR02_DB6_MASK 64 #define DSR02_DB7_MASK 128 /*** DSR12 - Transmit Buffer 2 Data Segment Register 1; 0x00000575 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR12STR; extern volatile DSR12STR _DSR12 @0x00000575; #define DSR12 _DSR12.Byte #define DSR12_DB0 _DSR12.Bits.DB0 #define DSR12_DB1 _DSR12.Bits.DB1 #define DSR12_DB2 _DSR12.Bits.DB2 #define DSR12_DB3 _DSR12.Bits.DB3 #define DSR12_DB4 _DSR12.Bits.DB4 #define DSR12_DB5 _DSR12.Bits.DB5 #define DSR12_DB6 _DSR12.Bits.DB6 #define DSR12_DB7 _DSR12.Bits.DB7 #define DSR12_DB0_MASK 1 #define DSR12_DB1_MASK 2 #define DSR12_DB2_MASK 4 #define DSR12_DB3_MASK 8 #define DSR12_DB4_MASK 16 #define DSR12_DB5_MASK 32 #define DSR12_DB6_MASK 64 #define DSR12_DB7_MASK 128 /*** DSR22 - Transmit Buffer 2 Data Segment Register 2; 0x00000576 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR22STR; extern volatile DSR22STR _DSR22 @0x00000576; #define DSR22 _DSR22.Byte #define DSR22_DB0 _DSR22.Bits.DB0 #define DSR22_DB1 _DSR22.Bits.DB1 #define DSR22_DB2 _DSR22.Bits.DB2 #define DSR22_DB3 _DSR22.Bits.DB3 #define DSR22_DB4 _DSR22.Bits.DB4 #define DSR22_DB5 _DSR22.Bits.DB5 #define DSR22_DB6 _DSR22.Bits.DB6 #define DSR22_DB7 _DSR22.Bits.DB7 #define DSR22_DB0_MASK 1 #define DSR22_DB1_MASK 2 #define DSR22_DB2_MASK 4 #define DSR22_DB3_MASK 8 #define DSR22_DB4_MASK 16 #define DSR22_DB5_MASK 32 #define DSR22_DB6_MASK 64 #define DSR22_DB7_MASK 128 /*** DSR32 - Transmit Buffer 2 Data Segment Register 3; 0x00000577 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR32STR; extern volatile DSR32STR _DSR32 @0x00000577; #define DSR32 _DSR32.Byte #define DSR32_DB0 _DSR32.Bits.DB0 #define DSR32_DB1 _DSR32.Bits.DB1 #define DSR32_DB2 _DSR32.Bits.DB2 #define DSR32_DB3 _DSR32.Bits.DB3 #define DSR32_DB4 _DSR32.Bits.DB4 #define DSR32_DB5 _DSR32.Bits.DB5 #define DSR32_DB6 _DSR32.Bits.DB6 #define DSR32_DB7 _DSR32.Bits.DB7 #define DSR32_DB0_MASK 1 #define DSR32_DB1_MASK 2 #define DSR32_DB2_MASK 4 #define DSR32_DB3_MASK 8 #define DSR32_DB4_MASK 16 #define DSR32_DB5_MASK 32 #define DSR32_DB6_MASK 64 #define DSR32_DB7_MASK 128 /*** DSR42 - Transmit Buffer 2 Data Segment Register 4; 0x00000578 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR42STR; extern volatile DSR42STR _DSR42 @0x00000578; #define DSR42 _DSR42.Byte #define DSR42_DB0 _DSR42.Bits.DB0 #define DSR42_DB1 _DSR42.Bits.DB1 #define DSR42_DB2 _DSR42.Bits.DB2 #define DSR42_DB3 _DSR42.Bits.DB3 #define DSR42_DB4 _DSR42.Bits.DB4 #define DSR42_DB5 _DSR42.Bits.DB5 #define DSR42_DB6 _DSR42.Bits.DB6 #define DSR42_DB7 _DSR42.Bits.DB7 #define DSR42_DB0_MASK 1 #define DSR42_DB1_MASK 2 #define DSR42_DB2_MASK 4 #define DSR42_DB3_MASK 8 #define DSR42_DB4_MASK 16 #define DSR42_DB5_MASK 32 #define DSR42_DB6_MASK 64 #define DSR42_DB7_MASK 128 /*** DSR52 - Transmit Buffer 2 Data Segment Register 5; 0x00000579 ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR52STR; extern volatile DSR52STR _DSR52 @0x00000579; #define DSR52 _DSR52.Byte #define DSR52_DB0 _DSR52.Bits.DB0 #define DSR52_DB1 _DSR52.Bits.DB1 #define DSR52_DB2 _DSR52.Bits.DB2 #define DSR52_DB3 _DSR52.Bits.DB3 #define DSR52_DB4 _DSR52.Bits.DB4 #define DSR52_DB5 _DSR52.Bits.DB5 #define DSR52_DB6 _DSR52.Bits.DB6 #define DSR52_DB7 _DSR52.Bits.DB7 #define DSR52_DB0_MASK 1 #define DSR52_DB1_MASK 2 #define DSR52_DB2_MASK 4 #define DSR52_DB3_MASK 8 #define DSR52_DB4_MASK 16 #define DSR52_DB5_MASK 32 #define DSR52_DB6_MASK 64 #define DSR52_DB7_MASK 128 /*** DSR62 - Transmit Buffer 2 Data Segment Register 6; 0x0000057A ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR62STR; extern volatile DSR62STR _DSR62 @0x0000057A; #define DSR62 _DSR62.Byte #define DSR62_DB0 _DSR62.Bits.DB0 #define DSR62_DB1 _DSR62.Bits.DB1 #define DSR62_DB2 _DSR62.Bits.DB2 #define DSR62_DB3 _DSR62.Bits.DB3 #define DSR62_DB4 _DSR62.Bits.DB4 #define DSR62_DB5 _DSR62.Bits.DB5 #define DSR62_DB6 _DSR62.Bits.DB6 #define DSR62_DB7 _DSR62.Bits.DB7 #define DSR62_DB0_MASK 1 #define DSR62_DB1_MASK 2 #define DSR62_DB2_MASK 4 #define DSR62_DB3_MASK 8 #define DSR62_DB4_MASK 16 #define DSR62_DB5_MASK 32 #define DSR62_DB6_MASK 64 #define DSR62_DB7_MASK 128 /*** DSR72 - Transmit Buffer 2 Data Segment Register 7; 0x0000057B ***/ typedef union { byte Byte; struct { byte DB0 :1; /* Data Segment Register Bit */ byte DB1 :1; /* Data Segment Register Bit */ byte DB2 :1; /* Data Segment Register Bit */ byte DB3 :1; /* Data Segment Register Bit */ byte DB4 :1; /* Data Segment Register Bit */ byte DB5 :1; /* Data Segment Register Bit */ byte DB6 :1; /* Data Segment Register Bit */ byte DB7 :1; /* Data Segment Register Bit */ } Bits; } DSR72STR; extern volatile DSR72STR _DSR72 @0x0000057B; #define DSR72 _DSR72.Byte #define DSR72_DB0 _DSR72.Bits.DB0 #define DSR72_DB1 _DSR72.Bits.DB1 #define DSR72_DB2 _DSR72.Bits.DB2 #define DSR72_DB3 _DSR72.Bits.DB3 #define DSR72_DB4 _DSR72.Bits.DB4 #define DSR72_DB5 _DSR72.Bits.DB5 #define DSR72_DB6 _DSR72.Bits.DB6 #define DSR72_DB7 _DSR72.Bits.DB7 #define DSR72_DB0_MASK 1 #define DSR72_DB1_MASK 2 #define DSR72_DB2_MASK 4 #define DSR72_DB3_MASK 8 #define DSR72_DB4_MASK 16 #define DSR72_DB5_MASK 32 #define DSR72_DB6_MASK 64 #define DSR72_DB7_MASK 128 /*** DLR2 - Transmit Buffer 2 Data Length Register; 0x0000057C ***/ typedef union { byte Byte; struct { byte DLC0 :1; /* Data Length Code Bit */ byte DLC1 :1; /* Data Length Code Bit */ byte DLC2 :1; /* Data Length Code Bit */ byte DLC3 :1; /* Data Length Code Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDLC :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DLR2STR; extern volatile DLR2STR _DLR2 @0x0000057C; #define DLR2 _DLR2.Byte #define DLR2_DLC0 _DLR2.Bits.DLC0 #define DLR2_DLC1 _DLR2.Bits.DLC1 #define DLR2_DLC2 _DLR2.Bits.DLC2 #define DLR2_DLC3 _DLR2.Bits.DLC3 #define DLR2_DLC _DLR2.MergedBits.grpDLC #define DLR2_DLC0_MASK 1 #define DLR2_DLC1_MASK 2 #define DLR2_DLC2_MASK 4 #define DLR2_DLC3_MASK 8 #define DLR2_DLC_MASK 15 #define DLR2_DLC_BITNUM 0 /*** TBPR2 - Transmit Buffer 2 Priority Register; 0x0000057D ***/ typedef union { byte Byte; struct { byte PRIO0 :1; /* Local Priority */ byte PRIO1 :1; /* Local Priority */ byte PRIO2 :1; /* Local Priority */ byte PRIO3 :1; /* Local Priority */ byte PRIO4 :1; /* Local Priority */ byte PRIO5 :1; /* Local Priority */ byte PRIO6 :1; /* Local Priority */ byte PRIO7 :1; /* Local Priority */ } Bits; } TBPR2STR; extern volatile TBPR2STR _TBPR2 @0x0000057D; #define TBPR2 _TBPR2.Byte #define TBPR2_PRIO0 _TBPR2.Bits.PRIO0 #define TBPR2_PRIO1 _TBPR2.Bits.PRIO1 #define TBPR2_PRIO2 _TBPR2.Bits.PRIO2 #define TBPR2_PRIO3 _TBPR2.Bits.PRIO3 #define TBPR2_PRIO4 _TBPR2.Bits.PRIO4 #define TBPR2_PRIO5 _TBPR2.Bits.PRIO5 #define TBPR2_PRIO6 _TBPR2.Bits.PRIO6 #define TBPR2_PRIO7 _TBPR2.Bits.PRIO7 #define TBPR2_PRIO0_MASK 1 #define TBPR2_PRIO1_MASK 2 #define TBPR2_PRIO2_MASK 4 #define TBPR2_PRIO3_MASK 8 #define TBPR2_PRIO4_MASK 16 #define TBPR2_PRIO5_MASK 32 #define TBPR2_PRIO6_MASK 64 #define TBPR2_PRIO7_MASK 128 /*** SBSR - SIM Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte BW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SBSRSTR; extern volatile SBSRSTR _SBSR @0x0000FE00; #define SBSR _SBSR.Byte #define SBSR_BW _SBSR.Bits.BW #define SBSR_BW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte :1; byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_LVI _SRSR.Bits.LVI #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_PIN _SRSR.Bits.PIN #define SRSR_POR _SRSR.Bits.POR #define SRSR_LVI_MASK 2 #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_PIN_MASK 64 #define SRSR_POR_MASK 128 /*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } SBFCRSTR; extern volatile SBFCRSTR _SBFCR @0x0000FE03; #define SBFCR _SBFCR.Byte #define SBFCR_BCFE _SBFCR.Bits.BCFE #define SBFCR_BCFE_MASK 128 /*** FL2CR - FLASH2 Control Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FL2CRSTR; extern volatile FL2CRSTR _FL2CR @0x0000FE08; #define FL2CR _FL2CR.Byte #define FL2CR_PGM _FL2CR.Bits.PGM #define FL2CR_ERASE _FL2CR.Bits.ERASE #define FL2CR_MASS _FL2CR.Bits.MASS #define FL2CR_HVEN _FL2CR.Bits.HVEN #define FL2CR_PGM_MASK 1 #define FL2CR_ERASE_MASK 2 #define FL2CR_MASS_MASK 4 #define FL2CR_HVEN_MASK 8 /*** CONFIG2 - Configuration Register; 0x0000FE09 ***/ typedef union { byte Byte; struct { byte AZxx :1; /* AZxx Emulator Enable Bit */ byte :1; byte :1; byte AT60A :1; /* Device indicator */ byte MSCAND :1; /* MSCAN Disable Bit */ byte :1; byte :1; byte EEDIVCLK :1; /* EEPROM Timebase Divider Clock select bit */ } Bits; } CONFIG2STR; extern volatile CONFIG2STR _CONFIG2 @0x0000FE09; #define CONFIG2 _CONFIG2.Byte #define CONFIG2_AZxx _CONFIG2.Bits.AZxx #define CONFIG2_AT60A _CONFIG2.Bits.AT60A #define CONFIG2_MSCAND _CONFIG2.Bits.MSCAND #define CONFIG2_EEDIVCLK _CONFIG2.Bits.EEDIVCLK #define CONFIG2_AZxx_MASK 1 #define CONFIG2_AT60A_MASK 8 #define CONFIG2_MSCAND_MASK 16 #define CONFIG2_EEDIVCLK_MASK 128 /*** BRK - Break Address Register; 0x0000FE0C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register; 0x0000FE0C ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Register Bit */ byte BIT9 :1; /* Break Address Register Bit */ byte BIT10 :1; /* Break Address Register Bit */ byte BIT11 :1; /* Break Address Register Bit */ byte BIT12 :1; /* Break Address Register Bit */ byte BIT13 :1; /* Break Address Register Bit */ byte BIT14 :1; /* Break Address Register Bit */ byte BIT15 :1; /* Break Address Register Bit */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register; 0x0000FE0D ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Register Bit */ byte BIT1 :1; /* Break Address Register Bit */ byte BIT2 :1; /* Break Address Register Bit */ byte BIT3 :1; /* Break Address Register Bit */ byte BIT4 :1; /* Break Address Register Bit */ byte BIT5 :1; /* Break Address Register Bit */ byte BIT6 :1; /* Break Address Register Bit */ byte BIT7 :1; /* Break Address Register Bit */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE0C; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0E; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** LVISR - LVI Status Register; 0x0000FE0F ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LVIOUT :1; /* LVI Output Bit */ } Bits; } LVISRSTR; extern volatile LVISRSTR _LVISR @0x0000FE0F; #define LVISR _LVISR.Byte #define LVISR_LVIOUT _LVISR.Bits.LVIOUT #define LVISR_LVIOUT_MASK 128 /*** EE1DIVHNVR - EE1DIV Hi Non-volatile Register; 0x0000FE10 ***/ typedef union { byte Byte; struct { byte EEDIV8 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV9 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV10 :1; /* EEPROM-1 timebase prescaler */ byte :1; byte :1; byte :1; byte :1; byte EEDIVSECD :1; /* EEPROM-1 Divider Security Disable */ } Bits; struct { byte grpEEDIV_8 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE1DIVHNVRSTR; /* Tip for register initialization in the user code: const byte EE1DIVHNVR_INIT @0x0000FE10 = ; */ #define _EE1DIVHNVR (*(const EE1DIVHNVRSTR * __far)0x0000FE10) #define EE1DIVHNVR _EE1DIVHNVR.Byte #define EE1DIVHNVR_EEDIV8 _EE1DIVHNVR.Bits.EEDIV8 #define EE1DIVHNVR_EEDIV9 _EE1DIVHNVR.Bits.EEDIV9 #define EE1DIVHNVR_EEDIV10 _EE1DIVHNVR.Bits.EEDIV10 #define EE1DIVHNVR_EEDIVSECD _EE1DIVHNVR.Bits.EEDIVSECD #define EE1DIVHNVR_EEDIV_8 _EE1DIVHNVR.MergedBits.grpEEDIV_8 #define EE1DIVHNVR_EEDIV EE1DIVHNVR_EEDIV_8 #define EE1DIVHNVR_EEDIV8_MASK 1 #define EE1DIVHNVR_EEDIV9_MASK 2 #define EE1DIVHNVR_EEDIV10_MASK 4 #define EE1DIVHNVR_EEDIVSECD_MASK 128 #define EE1DIVHNVR_EEDIV_8_MASK 7 #define EE1DIVHNVR_EEDIV_8_BITNUM 0 /*** EE1DIVLNVR - EE1DIV Lo Non-volatile Register; 0x0000FE11 ***/ typedef union { byte Byte; struct { byte EEDIV0 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV1 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV2 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV3 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV4 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV5 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV6 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV7 :1; /* EEPROM-1 timebase prescaler */ } Bits; } EE1DIVLNVRSTR; /* Tip for register initialization in the user code: const byte EE1DIVLNVR_INIT @0x0000FE11 = ; */ #define _EE1DIVLNVR (*(const EE1DIVLNVRSTR * __far)0x0000FE11) #define EE1DIVLNVR _EE1DIVLNVR.Byte #define EE1DIVLNVR_EEDIV0 _EE1DIVLNVR.Bits.EEDIV0 #define EE1DIVLNVR_EEDIV1 _EE1DIVLNVR.Bits.EEDIV1 #define EE1DIVLNVR_EEDIV2 _EE1DIVLNVR.Bits.EEDIV2 #define EE1DIVLNVR_EEDIV3 _EE1DIVLNVR.Bits.EEDIV3 #define EE1DIVLNVR_EEDIV4 _EE1DIVLNVR.Bits.EEDIV4 #define EE1DIVLNVR_EEDIV5 _EE1DIVLNVR.Bits.EEDIV5 #define EE1DIVLNVR_EEDIV6 _EE1DIVLNVR.Bits.EEDIV6 #define EE1DIVLNVR_EEDIV7 _EE1DIVLNVR.Bits.EEDIV7 #define EE1DIVLNVR_EEDIV0_MASK 1 #define EE1DIVLNVR_EEDIV1_MASK 2 #define EE1DIVLNVR_EEDIV2_MASK 4 #define EE1DIVLNVR_EEDIV3_MASK 8 #define EE1DIVLNVR_EEDIV4_MASK 16 #define EE1DIVLNVR_EEDIV5_MASK 32 #define EE1DIVLNVR_EEDIV6_MASK 64 #define EE1DIVLNVR_EEDIV7_MASK 128 /*** EE1DIVH - EE1DIV Divider High Register; 0x0000FE1A ***/ typedef union { byte Byte; struct { byte EEDIV8 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV9 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV10 :1; /* EEPROM-1 timebase prescaler */ byte :1; byte :1; byte :1; byte :1; byte EEDIVSECD :1; /* EEPROM-1 Divider Security Disable */ } Bits; struct { byte grpEEDIV_8 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE1DIVHSTR; extern volatile EE1DIVHSTR _EE1DIVH @0x0000FE1A; #define EE1DIVH _EE1DIVH.Byte #define EE1DIVH_EEDIV8 _EE1DIVH.Bits.EEDIV8 #define EE1DIVH_EEDIV9 _EE1DIVH.Bits.EEDIV9 #define EE1DIVH_EEDIV10 _EE1DIVH.Bits.EEDIV10 #define EE1DIVH_EEDIVSECD _EE1DIVH.Bits.EEDIVSECD #define EE1DIVH_EEDIV_8 _EE1DIVH.MergedBits.grpEEDIV_8 #define EE1DIVH_EEDIV EE1DIVH_EEDIV_8 #define EE1DIVH_EEDIV8_MASK 1 #define EE1DIVH_EEDIV9_MASK 2 #define EE1DIVH_EEDIV10_MASK 4 #define EE1DIVH_EEDIVSECD_MASK 128 #define EE1DIVH_EEDIV_8_MASK 7 #define EE1DIVH_EEDIV_8_BITNUM 0 /*** EE1DIVL - EE1DIV Divider Low Register; 0x0000FE1B ***/ typedef union { byte Byte; struct { byte EEDIV0 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV1 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV2 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV3 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV4 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV5 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV6 :1; /* EEPROM-1 timebase prescaler */ byte EEDIV7 :1; /* EEPROM-1 timebase prescaler */ } Bits; } EE1DIVLSTR; extern volatile EE1DIVLSTR _EE1DIVL @0x0000FE1B; #define EE1DIVL _EE1DIVL.Byte #define EE1DIVL_EEDIV0 _EE1DIVL.Bits.EEDIV0 #define EE1DIVL_EEDIV1 _EE1DIVL.Bits.EEDIV1 #define EE1DIVL_EEDIV2 _EE1DIVL.Bits.EEDIV2 #define EE1DIVL_EEDIV3 _EE1DIVL.Bits.EEDIV3 #define EE1DIVL_EEDIV4 _EE1DIVL.Bits.EEDIV4 #define EE1DIVL_EEDIV5 _EE1DIVL.Bits.EEDIV5 #define EE1DIVL_EEDIV6 _EE1DIVL.Bits.EEDIV6 #define EE1DIVL_EEDIV7 _EE1DIVL.Bits.EEDIV7 #define EE1DIVL_EEDIV0_MASK 1 #define EE1DIVL_EEDIV1_MASK 2 #define EE1DIVL_EEDIV2_MASK 4 #define EE1DIVL_EEDIV3_MASK 8 #define EE1DIVL_EEDIV4_MASK 16 #define EE1DIVL_EEDIV5_MASK 32 #define EE1DIVL_EEDIV6_MASK 64 #define EE1DIVL_EEDIV7_MASK 128 /*** EE1NVR - EEPROM1 Nonvolatile Register; 0x0000FE1C ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM-1 Block Protection Bit */ byte EEBP1 :1; /* EEPROM-1 Block Protection Bit */ byte EEBP2 :1; /* EEPROM-1 Block Protection Bit */ byte EEBP3 :1; /* EEPROM-1 Block Protection Bit */ byte EEPRTCT :1; /* EEPROM-1 Protection */ byte :1; byte :1; byte :1; } Bits; struct { byte grpEEBP :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE1NVRSTR; /* Tip for register initialization in the user code: const byte EE1NVR_INIT @0x0000FE1C = ; */ #define _EE1NVR (*(const EE1NVRSTR * __far)0x0000FE1C) #define EE1NVR _EE1NVR.Byte #define EE1NVR_EEBP0 _EE1NVR.Bits.EEBP0 #define EE1NVR_EEBP1 _EE1NVR.Bits.EEBP1 #define EE1NVR_EEBP2 _EE1NVR.Bits.EEBP2 #define EE1NVR_EEBP3 _EE1NVR.Bits.EEBP3 #define EE1NVR_EEPRTCT _EE1NVR.Bits.EEPRTCT #define EE1NVR_EEBP _EE1NVR.MergedBits.grpEEBP #define EE1NVR_EEBP0_MASK 1 #define EE1NVR_EEBP1_MASK 2 #define EE1NVR_EEBP2_MASK 4 #define EE1NVR_EEBP3_MASK 8 #define EE1NVR_EEPRTCT_MASK 16 #define EE1NVR_EEBP_MASK 15 #define EE1NVR_EEBP_BITNUM 0 /*** EE1CR - EEPROM1 Control Register; 0x0000FE1D ***/ typedef union { byte Byte; struct { byte EEPGM :1; /* EEPROM-1 Program/Erase Enable */ byte AUTO :1; /* Automatic termination of program/erase cycle */ byte EELAT :1; /* EEPROM-1 Latch Control */ byte EERAS0 :1; /* Erase Bit */ byte EERAS1 :1; /* Erase Bit */ byte EEOFF :1; /* EEPROM-1 Power Down */ byte :1; byte :1; } Bits; struct { byte :1; byte :1; byte :1; byte grpEERAS :2; byte :1; byte :1; byte :1; } MergedBits; } EE1CRSTR; extern volatile EE1CRSTR _EE1CR @0x0000FE1D; #define EE1CR _EE1CR.Byte #define EE1CR_EEPGM _EE1CR.Bits.EEPGM #define EE1CR_AUTO _EE1CR.Bits.AUTO #define EE1CR_EELAT _EE1CR.Bits.EELAT #define EE1CR_EERAS0 _EE1CR.Bits.EERAS0 #define EE1CR_EERAS1 _EE1CR.Bits.EERAS1 #define EE1CR_EEOFF _EE1CR.Bits.EEOFF #define EE1CR_EERAS _EE1CR.MergedBits.grpEERAS #define EE1CR_EEPGM_MASK 1 #define EE1CR_AUTO_MASK 2 #define EE1CR_EELAT_MASK 4 #define EE1CR_EERAS0_MASK 8 #define EE1CR_EERAS1_MASK 16 #define EE1CR_EEOFF_MASK 32 #define EE1CR_EERAS_MASK 24 #define EE1CR_EERAS_BITNUM 3 /*** EE1ACR - EEPROM1 Array Control Register; 0x0000FE1F ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM-1 Block Protection Bit */ byte EEBP1 :1; /* EEPROM-1 Block Protection Bit */ byte EEBP2 :1; /* EEPROM-1 Block Protection Bit */ byte EEBP3 :1; /* EEPROM-1 Block Protection Bit */ byte EEPRTCT :1; /* EEPROM-1 Protection */ byte :1; byte :1; byte :1; } Bits; struct { byte grpEEBP :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE1ACRSTR; extern volatile EE1ACRSTR _EE1ACR @0x0000FE1F; #define EE1ACR _EE1ACR.Byte #define EE1ACR_EEBP0 _EE1ACR.Bits.EEBP0 #define EE1ACR_EEBP1 _EE1ACR.Bits.EEBP1 #define EE1ACR_EEBP2 _EE1ACR.Bits.EEBP2 #define EE1ACR_EEBP3 _EE1ACR.Bits.EEBP3 #define EE1ACR_EEPRTCT _EE1ACR.Bits.EEPRTCT #define EE1ACR_EEBP _EE1ACR.MergedBits.grpEEBP #define EE1ACR_EEBP0_MASK 1 #define EE1ACR_EEBP1_MASK 2 #define EE1ACR_EEBP2_MASK 4 #define EE1ACR_EEBP3_MASK 8 #define EE1ACR_EEPRTCT_MASK 16 #define EE1ACR_EEBP_MASK 15 #define EE1ACR_EEBP_BITNUM 0 /*** EE2DIVHNVR - EE2DIV Hi Non-volatile Register; 0x0000FF70 ***/ typedef union { byte Byte; struct { byte EEDIV8 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV9 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV10 :1; /* EEPROM-2 timebase prescaler */ byte :1; byte :1; byte :1; byte :1; byte EEDIVSECD :1; /* EEPROM-2 Divider Security Disable */ } Bits; struct { byte grpEEDIV_8 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE2DIVHNVRSTR; /* Tip for register initialization in the user code: const byte EE2DIVHNVR_INIT @0x0000FF70 = ; */ #define _EE2DIVHNVR (*(const EE2DIVHNVRSTR * __far)0x0000FF70) #define EE2DIVHNVR _EE2DIVHNVR.Byte #define EE2DIVHNVR_EEDIV8 _EE2DIVHNVR.Bits.EEDIV8 #define EE2DIVHNVR_EEDIV9 _EE2DIVHNVR.Bits.EEDIV9 #define EE2DIVHNVR_EEDIV10 _EE2DIVHNVR.Bits.EEDIV10 #define EE2DIVHNVR_EEDIVSECD _EE2DIVHNVR.Bits.EEDIVSECD #define EE2DIVHNVR_EEDIV_8 _EE2DIVHNVR.MergedBits.grpEEDIV_8 #define EE2DIVHNVR_EEDIV EE2DIVHNVR_EEDIV_8 #define EE2DIVHNVR_EEDIV8_MASK 1 #define EE2DIVHNVR_EEDIV9_MASK 2 #define EE2DIVHNVR_EEDIV10_MASK 4 #define EE2DIVHNVR_EEDIVSECD_MASK 128 #define EE2DIVHNVR_EEDIV_8_MASK 7 #define EE2DIVHNVR_EEDIV_8_BITNUM 0 /*** EE2DIVLNVR - EE2DIV Lo Non-volatile Register; 0x0000FF71 ***/ typedef union { byte Byte; struct { byte EEDIV0 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV1 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV2 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV3 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV4 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV5 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV6 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV7 :1; /* EEPROM-2 timebase prescaler */ } Bits; } EE2DIVLNVRSTR; /* Tip for register initialization in the user code: const byte EE2DIVLNVR_INIT @0x0000FF71 = ; */ #define _EE2DIVLNVR (*(const EE2DIVLNVRSTR * __far)0x0000FF71) #define EE2DIVLNVR _EE2DIVLNVR.Byte #define EE2DIVLNVR_EEDIV0 _EE2DIVLNVR.Bits.EEDIV0 #define EE2DIVLNVR_EEDIV1 _EE2DIVLNVR.Bits.EEDIV1 #define EE2DIVLNVR_EEDIV2 _EE2DIVLNVR.Bits.EEDIV2 #define EE2DIVLNVR_EEDIV3 _EE2DIVLNVR.Bits.EEDIV3 #define EE2DIVLNVR_EEDIV4 _EE2DIVLNVR.Bits.EEDIV4 #define EE2DIVLNVR_EEDIV5 _EE2DIVLNVR.Bits.EEDIV5 #define EE2DIVLNVR_EEDIV6 _EE2DIVLNVR.Bits.EEDIV6 #define EE2DIVLNVR_EEDIV7 _EE2DIVLNVR.Bits.EEDIV7 #define EE2DIVLNVR_EEDIV0_MASK 1 #define EE2DIVLNVR_EEDIV1_MASK 2 #define EE2DIVLNVR_EEDIV2_MASK 4 #define EE2DIVLNVR_EEDIV3_MASK 8 #define EE2DIVLNVR_EEDIV4_MASK 16 #define EE2DIVLNVR_EEDIV5_MASK 32 #define EE2DIVLNVR_EEDIV6_MASK 64 #define EE2DIVLNVR_EEDIV7_MASK 128 /*** EE2DIVH - EE2DIV Divider High Register; 0x0000FF7A ***/ typedef union { byte Byte; struct { byte EEDIV8 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV9 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV10 :1; /* EEPROM-2 timebase prescaler */ byte :1; byte :1; byte :1; byte :1; byte EEDIVSECD :1; /* EEPROM-2 Divider Security Disable */ } Bits; struct { byte grpEEDIV_8 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE2DIVHSTR; extern volatile EE2DIVHSTR _EE2DIVH @0x0000FF7A; #define EE2DIVH _EE2DIVH.Byte #define EE2DIVH_EEDIV8 _EE2DIVH.Bits.EEDIV8 #define EE2DIVH_EEDIV9 _EE2DIVH.Bits.EEDIV9 #define EE2DIVH_EEDIV10 _EE2DIVH.Bits.EEDIV10 #define EE2DIVH_EEDIVSECD _EE2DIVH.Bits.EEDIVSECD #define EE2DIVH_EEDIV_8 _EE2DIVH.MergedBits.grpEEDIV_8 #define EE2DIVH_EEDIV EE2DIVH_EEDIV_8 #define EE2DIVH_EEDIV8_MASK 1 #define EE2DIVH_EEDIV9_MASK 2 #define EE2DIVH_EEDIV10_MASK 4 #define EE2DIVH_EEDIVSECD_MASK 128 #define EE2DIVH_EEDIV_8_MASK 7 #define EE2DIVH_EEDIV_8_BITNUM 0 /*** EE2DIVL - EE2DIV Divider Low Register; 0x0000FF7B ***/ typedef union { byte Byte; struct { byte EEDIV0 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV1 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV2 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV3 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV4 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV5 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV6 :1; /* EEPROM-2 timebase prescaler */ byte EEDIV7 :1; /* EEPROM-2 timebase prescaler */ } Bits; } EE2DIVLSTR; extern volatile EE2DIVLSTR _EE2DIVL @0x0000FF7B; #define EE2DIVL _EE2DIVL.Byte #define EE2DIVL_EEDIV0 _EE2DIVL.Bits.EEDIV0 #define EE2DIVL_EEDIV1 _EE2DIVL.Bits.EEDIV1 #define EE2DIVL_EEDIV2 _EE2DIVL.Bits.EEDIV2 #define EE2DIVL_EEDIV3 _EE2DIVL.Bits.EEDIV3 #define EE2DIVL_EEDIV4 _EE2DIVL.Bits.EEDIV4 #define EE2DIVL_EEDIV5 _EE2DIVL.Bits.EEDIV5 #define EE2DIVL_EEDIV6 _EE2DIVL.Bits.EEDIV6 #define EE2DIVL_EEDIV7 _EE2DIVL.Bits.EEDIV7 #define EE2DIVL_EEDIV0_MASK 1 #define EE2DIVL_EEDIV1_MASK 2 #define EE2DIVL_EEDIV2_MASK 4 #define EE2DIVL_EEDIV3_MASK 8 #define EE2DIVL_EEDIV4_MASK 16 #define EE2DIVL_EEDIV5_MASK 32 #define EE2DIVL_EEDIV6_MASK 64 #define EE2DIVL_EEDIV7_MASK 128 /*** EE2NVR - EEPROM2 Nonvolatile Register; 0x0000FF7C ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM-2 Block Protection Bit */ byte EEBP1 :1; /* EEPROM-2 Block Protection Bit */ byte EEBP2 :1; /* EEPROM-2 Block Protection Bit */ byte EEBP3 :1; /* EEPROM-2 Block Protection Bit */ byte EEPRTCT :1; /* EEPROM-2 Protect */ byte :1; byte :1; byte :1; } Bits; struct { byte grpEEBP :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE2NVRSTR; /* Tip for register initialization in the user code: const byte EE2NVR_INIT @0x0000FF7C = ; */ #define _EE2NVR (*(const EE2NVRSTR * __far)0x0000FF7C) #define EE2NVR _EE2NVR.Byte #define EE2NVR_EEBP0 _EE2NVR.Bits.EEBP0 #define EE2NVR_EEBP1 _EE2NVR.Bits.EEBP1 #define EE2NVR_EEBP2 _EE2NVR.Bits.EEBP2 #define EE2NVR_EEBP3 _EE2NVR.Bits.EEBP3 #define EE2NVR_EEPRTCT _EE2NVR.Bits.EEPRTCT #define EE2NVR_EEBP _EE2NVR.MergedBits.grpEEBP #define EE2NVR_EEBP0_MASK 1 #define EE2NVR_EEBP1_MASK 2 #define EE2NVR_EEBP2_MASK 4 #define EE2NVR_EEBP3_MASK 8 #define EE2NVR_EEPRTCT_MASK 16 #define EE2NVR_EEBP_MASK 15 #define EE2NVR_EEBP_BITNUM 0 /*** EE2CR - EEPROM2 Control Register; 0x0000FF7D ***/ typedef union { byte Byte; struct { byte EEPGM :1; /* EEPROM-2 Program/Erase Enable */ byte AUTO :1; /* Automatic termination of program/erase cycle */ byte EELAT :1; /* EEPROM-2 Latch Control */ byte EERAS0 :1; /* Erase Bit */ byte EERAS1 :1; /* Erase Bit */ byte EEOFF :1; /* EEPROM-2 Power Down */ byte :1; byte :1; } Bits; struct { byte :1; byte :1; byte :1; byte grpEERAS :2; byte :1; byte :1; byte :1; } MergedBits; } EE2CRSTR; extern volatile EE2CRSTR _EE2CR @0x0000FF7D; #define EE2CR _EE2CR.Byte #define EE2CR_EEPGM _EE2CR.Bits.EEPGM #define EE2CR_AUTO _EE2CR.Bits.AUTO #define EE2CR_EELAT _EE2CR.Bits.EELAT #define EE2CR_EERAS0 _EE2CR.Bits.EERAS0 #define EE2CR_EERAS1 _EE2CR.Bits.EERAS1 #define EE2CR_EEOFF _EE2CR.Bits.EEOFF #define EE2CR_EERAS _EE2CR.MergedBits.grpEERAS #define EE2CR_EEPGM_MASK 1 #define EE2CR_AUTO_MASK 2 #define EE2CR_EELAT_MASK 4 #define EE2CR_EERAS0_MASK 8 #define EE2CR_EERAS1_MASK 16 #define EE2CR_EEOFF_MASK 32 #define EE2CR_EERAS_MASK 24 #define EE2CR_EERAS_BITNUM 3 /*** EE2ACR - EEPROM2 Array Control Register; 0x0000FF7F ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM-2 Block Protection Bit */ byte EEBP1 :1; /* EEPROM-2 Block Protection Bit */ byte EEBP2 :1; /* EEPROM-2 Block Protection Bit */ byte EEBP3 :1; /* EEPROM-2 Block Protection Bit */ byte EEPRTCT :1; /* EEPROM-2 Protection */ byte :1; byte :1; byte :1; } Bits; struct { byte grpEEBP :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } EE2ACRSTR; extern volatile EE2ACRSTR _EE2ACR @0x0000FF7F; #define EE2ACR _EE2ACR.Byte #define EE2ACR_EEBP0 _EE2ACR.Bits.EEBP0 #define EE2ACR_EEBP1 _EE2ACR.Bits.EEBP1 #define EE2ACR_EEBP2 _EE2ACR.Bits.EEBP2 #define EE2ACR_EEBP3 _EE2ACR.Bits.EEBP3 #define EE2ACR_EEPRTCT _EE2ACR.Bits.EEPRTCT #define EE2ACR_EEBP _EE2ACR.MergedBits.grpEEBP #define EE2ACR_EEBP0_MASK 1 #define EE2ACR_EEBP1_MASK 2 #define EE2ACR_EEBP2_MASK 4 #define EE2ACR_EEBP3_MASK 8 #define EE2ACR_EEPRTCT_MASK 16 #define EE2ACR_EEBP_MASK 15 #define EE2ACR_EEBP_BITNUM 0 /*** FL1BPR - FLASH1 Block Protect Register; 0x0000FF80 ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* Block Protect Register Bit 0 */ byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte BPR4 :1; /* Block Protect Register Bit 4 */ byte BPR5 :1; /* Block Protect Register Bit 5 */ byte BPR6 :1; /* Block Protect Register Bit 6 */ byte BPR7 :1; /* Block Protect Register Bit 7 */ } Bits; } FL1BPRSTR; /* Tip for register initialization in the user code: const byte FL1BPR_INIT @0x0000FF80 = ; */ #define _FL1BPR (*(const FL1BPRSTR * __far)0x0000FF80) #define FL1BPR _FL1BPR.Byte #define FL1BPR_BPR0 _FL1BPR.Bits.BPR0 #define FL1BPR_BPR1 _FL1BPR.Bits.BPR1 #define FL1BPR_BPR2 _FL1BPR.Bits.BPR2 #define FL1BPR_BPR3 _FL1BPR.Bits.BPR3 #define FL1BPR_BPR4 _FL1BPR.Bits.BPR4 #define FL1BPR_BPR5 _FL1BPR.Bits.BPR5 #define FL1BPR_BPR6 _FL1BPR.Bits.BPR6 #define FL1BPR_BPR7 _FL1BPR.Bits.BPR7 #define FL1BPR_BPR0_MASK 1 #define FL1BPR_BPR1_MASK 2 #define FL1BPR_BPR2_MASK 4 #define FL1BPR_BPR3_MASK 8 #define FL1BPR_BPR4_MASK 16 #define FL1BPR_BPR5_MASK 32 #define FL1BPR_BPR6_MASK 64 #define FL1BPR_BPR7_MASK 128 /*** FL2BPR - FLASH2 Block Protect Register; 0x0000FF81 ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* Block Protect Register Bit 0 */ byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte BPR4 :1; /* Block Protect Register Bit 4 */ byte BPR5 :1; /* Block Protect Register Bit 5 */ byte BPR6 :1; /* Block Protect Register Bit 6 */ byte BPR7 :1; /* Block Protect Register Bit 7 */ } Bits; } FL2BPRSTR; /* Tip for register initialization in the user code: const byte FL2BPR_INIT @0x0000FF81 = ; */ #define _FL2BPR (*(const FL2BPRSTR * __far)0x0000FF81) #define FL2BPR _FL2BPR.Byte #define FL2BPR_BPR0 _FL2BPR.Bits.BPR0 #define FL2BPR_BPR1 _FL2BPR.Bits.BPR1 #define FL2BPR_BPR2 _FL2BPR.Bits.BPR2 #define FL2BPR_BPR3 _FL2BPR.Bits.BPR3 #define FL2BPR_BPR4 _FL2BPR.Bits.BPR4 #define FL2BPR_BPR5 _FL2BPR.Bits.BPR5 #define FL2BPR_BPR6 _FL2BPR.Bits.BPR6 #define FL2BPR_BPR7 _FL2BPR.Bits.BPR7 #define FL2BPR_BPR0_MASK 1 #define FL2BPR_BPR1_MASK 2 #define FL2BPR_BPR2_MASK 4 #define FL2BPR_BPR3_MASK 8 #define FL2BPR_BPR4_MASK 16 #define FL2BPR_BPR5_MASK 32 #define FL2BPR_BPR6_MASK 64 #define FL2BPR_BPR7_MASK 128 /*** FL1CR - FLASH1 Control Register; 0x0000FF88 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FL1CRSTR; extern volatile FL1CRSTR _FL1CR @0x0000FF88; #define FL1CR _FL1CR.Byte #define FL1CR_PGM _FL1CR.Bits.PGM #define FL1CR_ERASE _FL1CR.Bits.ERASE #define FL1CR_MASS _FL1CR.Bits.MASS #define FL1CR_HVEN _FL1CR.Bits.HVEN #define FL1CR_PGM_MASK 1 #define FL1CR_ERASE_MASK 2 #define FL1CR_MASS_MASK 4 #define FL1CR_HVEN_MASK 8 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------------------------------- Exceptions in bit names of timer status and control registers due to backward compatibility with previous releases */ #define TASC0_CHxMAX _TASC0.Bits.CH0MAX #define TASC0_TOVx _TASC0.Bits.TOV0 #define TASC0_ELSxA _TASC0.Bits.ELS0A #define TASC0_ELSxB _TASC0.Bits.ELS0B #define TASC0_MSxA _TASC0.Bits.MS0A #define TASC0_MSxB _TASC0.Bits.MS0B #define TASC0_CHxIE _TASC0.Bits.CH0IE #define TASC0_CHxF _TASC0.Bits.CH0F #define TASC1_CHxMAX _TASC1.Bits.CH1MAX #define TASC1_TOVx _TASC1.Bits.TOV1 #define TASC1_ELSxA _TASC1.Bits.ELS1A #define TASC1_ELSxB _TASC1.Bits.ELS1B #define TASC1_MSxA _TASC1.Bits.MS1A #define TASC1_CHxIE _TASC1.Bits.CH1IE #define TASC1_CHxF _TASC1.Bits.CH1F #define TASC2_CHxMAX _TASC2.Bits.CH2MAX #define TASC2_TOVx _TASC2.Bits.TOV2 #define TASC2_ELSxA _TASC2.Bits.ELS2A #define TASC2_ELSxB _TASC2.Bits.ELS2B #define TASC2_MSxA _TASC2.Bits.MS2A #define TASC2_MSxB _TASC2.Bits.MS2B #define TASC2_CHxIE _TASC2.Bits.CH2IE #define TASC2_CHxF _TASC2.Bits.CH2F #define TASC3_CHxMAX _TASC3.Bits.CH3MAX #define TASC3_TOVx _TASC3.Bits.TOV3 #define TASC3_ELSxA _TASC3.Bits.ELS3A #define TASC3_ELSxB _TASC3.Bits.ELS3B #define TASC3_MSxA _TASC3.Bits.MS3A #define TASC3_CHxIE _TASC3.Bits.CH3IE #define TASC3_CHxF _TASC3.Bits.CH3F #define TASC4_CHxMAX _TASC4.Bits.CH4MAX #define TASC4_TOVx _TASC4.Bits.TOV4 #define TASC4_ELSxA _TASC4.Bits.ELS4A #define TASC4_ELSxB _TASC4.Bits.ELS4B #define TASC4_MSxA _TASC4.Bits.MS4A #define TASC4_MSxB _TASC4.Bits.MS4B #define TASC4_CHxIE _TASC4.Bits.CH4IE #define TASC4_CHxF _TASC4.Bits.CH4F #define TASC5_CHxMAX _TASC5.Bits.CH5MAX #define TASC5_TOVx _TASC5.Bits.TOV5 #define TASC5_ELSxA _TASC5.Bits.ELS5A #define TASC5_ELSxB _TASC5.Bits.ELS5B #define TASC5_MSxA _TASC5.Bits.MS5A #define TASC5_CHxIE _TASC5.Bits.CH5IE #define TASC5_CHxF _TASC5.Bits.CH5F #define TBSC0_CHxMAX _TBSC0.Bits.CH0MAX #define TBSC0_TOVx _TBSC0.Bits.TOV0 #define TBSC0_ELSxA _TBSC0.Bits.ELS0A #define TBSC0_ELSxB _TBSC0.Bits.ELS0B #define TBSC0_MSxA _TBSC0.Bits.MS0A #define TBSC0_MSxB _TBSC0.Bits.MS0B #define TBSC0_CHxIE _TBSC0.Bits.CH0IE #define TBSC0_CHxF _TBSC0.Bits.CH0F #define TBSC1_CHxMAX _TBSC1.Bits.CH1MAX #define TBSC1_TOVx _TBSC1.Bits.TOV1 #define TBSC1_ELSxA _TBSC1.Bits.ELS1A #define TBSC1_ELSxB _TBSC1.Bits.ELS1B #define TBSC1_MSxA _TBSC1.Bits.MS1A #define TBSC1_CHxIE _TBSC1.Bits.CH1IE #define TBSC1_CHxF _TBSC1.Bits.CH1F /* MSCAN08 channel support */ extern volatile byte REC_DSR[8] @0x0544; /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 12:42:34 */ #define TACH_ARR This_symb_has_been_depreciated #define TBCH_ARR This_symb_has_been_depreciated #define IDR_ARR This_symb_has_been_depreciated #endif