/* Based on CPU DB MC68HC908AS60_64, version 2.89.024 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908as60.h ** Processor : MC68HC908AS60CFU ** FileFormat: V2.30 ** DataSheet : MC68HC908AS60/D REV 1 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:07 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908AS60_H #define _MC68HC908AS60_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_TIM 18 #define VectorNumber_BDLC 17 #define VectorNumber_ADC 16 #define VectorNumber_SCITransmit 15 #define VectorNumber_SCIReceive 14 #define VectorNumber_SCIError 13 #define VectorNumber_SPITransmit 12 #define VectorNumber_SPIReceive 11 #define VectorNumber_TIMAOvr 10 #define VectorNumber_TIMACH5 9 #define VectorNumber_TIMACH4 8 #define VectorNumber_TIMACH3 7 #define VectorNumber_TIMACH2 6 #define VectorNumber_TIMACH1 5 #define VectorNumber_TIMACH0 4 #define VectorNumber_PLL 3 #define VectorNumber_IRQ1 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_TIM 0x0000FFDA #define INT_BDLC 0x0000FFDC #define INT_ADC 0x0000FFDE #define INT_SCITransmit 0x0000FFE0 #define INT_SCIReceive 0x0000FFE2 #define INT_SCIError 0x0000FFE4 #define INT_SPITransmit 0x0000FFE6 #define INT_SPIReceive 0x0000FFE8 #define INT_TIMAOvr 0x0000FFEA #define INT_TIMACH5 0x0000FFEC #define INT_TIMACH4 0x0000FFEE #define INT_TIMACH3 0x0000FFF0 #define INT_TIMACH2 0x0000FFF2 #define INT_TIMACH1 0x0000FFF4 #define INT_TIMACH0 0x0000FFF6 #define INT_PLL 0x0000FFF8 #define INT_IRQ1 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte PTA6 :1; /* Port A Data Bit 6 */ byte PTA7 :1; /* Port A Data Bit 7 */ } Bits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_PTA6 _PTA.Bits.PTA6 #define PTA_PTA7 _PTA.Bits.PTA7 #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_PTA6_MASK 64 #define PTA_PTA7_MASK 128 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** PTC - Port C Data Register; 0x00000002 ***/ typedef union { byte Byte; struct { byte PTC0 :1; /* Port C Data Bit 0 */ byte PTC1 :1; /* Port C Data Bit 1 */ byte PTC2 :1; /* Port C Data Bit 2 */ byte PTC3 :1; /* Port C Data Bit 3 */ byte PTC4 :1; /* Port C Data Bit 4 */ byte PTC5 :1; /* Port C Data Bit 5 */ byte :1; byte :1; } Bits; struct { byte grpPTC :6; byte :1; byte :1; } MergedBits; } PTCSTR; extern volatile PTCSTR _PTC @0x00000002; #define PTC _PTC.Byte #define PTC_PTC0 _PTC.Bits.PTC0 #define PTC_PTC1 _PTC.Bits.PTC1 #define PTC_PTC2 _PTC.Bits.PTC2 #define PTC_PTC3 _PTC.Bits.PTC3 #define PTC_PTC4 _PTC.Bits.PTC4 #define PTC_PTC5 _PTC.Bits.PTC5 #define PTC_PTC _PTC.MergedBits.grpPTC #define PTC_PTC0_MASK 1 #define PTC_PTC1_MASK 2 #define PTC_PTC2_MASK 4 #define PTC_PTC3_MASK 8 #define PTC_PTC4_MASK 16 #define PTC_PTC5_MASK 32 #define PTC_PTC_MASK 63 #define PTC_PTC_BITNUM 0 /*** PTD - Port D Data Register; 0x00000003 ***/ typedef union { byte Byte; struct { byte PTD0 :1; /* Port D Data Bit 0 */ byte PTD1 :1; /* Port D Data Bit 1 */ byte PTD2 :1; /* Port D Data Bit 2 */ byte PTD3 :1; /* Port D Data Bit 3 */ byte PTD4 :1; /* Port D Data Bit 4 */ byte PTD5 :1; /* Port D Data Bit 5 */ byte PTD6 :1; /* Port D Data Bit 6 */ byte PTD7 :1; /* Port D Data Bit 7 */ } Bits; } PTDSTR; extern volatile PTDSTR _PTD @0x00000003; #define PTD _PTD.Byte #define PTD_PTD0 _PTD.Bits.PTD0 #define PTD_PTD1 _PTD.Bits.PTD1 #define PTD_PTD2 _PTD.Bits.PTD2 #define PTD_PTD3 _PTD.Bits.PTD3 #define PTD_PTD4 _PTD.Bits.PTD4 #define PTD_PTD5 _PTD.Bits.PTD5 #define PTD_PTD6 _PTD.Bits.PTD6 #define PTD_PTD7 _PTD.Bits.PTD7 #define PTD_PTD0_MASK 1 #define PTD_PTD1_MASK 2 #define PTD_PTD2_MASK 4 #define PTD_PTD3_MASK 8 #define PTD_PTD4_MASK 16 #define PTD_PTD5_MASK 32 #define PTD_PTD6_MASK 64 #define PTD_PTD7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte DDRA6 :1; /* Data Direction Register A Bit 6 */ byte DDRA7 :1; /* Data Direction Register A Bit 7 */ } Bits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA6 _DDRA.Bits.DDRA6 #define DDRA_DDRA7 _DDRA.Bits.DDRA7 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA6_MASK 64 #define DDRA_DDRA7_MASK 128 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** DDRC - Data Direction Register C; 0x00000006 ***/ typedef union { byte Byte; struct { byte DDRC0 :1; /* Data Direction Register C Bit 0 */ byte DDRC1 :1; /* Data Direction Register C Bit 1 */ byte DDRC2 :1; /* Data Direction Register C Bit 2 */ byte DDRC3 :1; /* Data Direction Register C Bit 3 */ byte DDRC4 :1; /* Data Direction Register C Bit 4 */ byte DDRC5 :1; /* Data Direction Register C Bit 5 */ byte :1; byte MCLKEN :1; /* MCLK Enable Bit */ } Bits; struct { byte grpDDRC :6; byte :1; byte :1; } MergedBits; } DDRCSTR; extern volatile DDRCSTR _DDRC @0x00000006; #define DDRC _DDRC.Byte #define DDRC_DDRC0 _DDRC.Bits.DDRC0 #define DDRC_DDRC1 _DDRC.Bits.DDRC1 #define DDRC_DDRC2 _DDRC.Bits.DDRC2 #define DDRC_DDRC3 _DDRC.Bits.DDRC3 #define DDRC_DDRC4 _DDRC.Bits.DDRC4 #define DDRC_DDRC5 _DDRC.Bits.DDRC5 #define DDRC_MCLKEN _DDRC.Bits.MCLKEN #define DDRC_DDRC _DDRC.MergedBits.grpDDRC #define DDRC_DDRC0_MASK 1 #define DDRC_DDRC1_MASK 2 #define DDRC_DDRC2_MASK 4 #define DDRC_DDRC3_MASK 8 #define DDRC_DDRC4_MASK 16 #define DDRC_DDRC5_MASK 32 #define DDRC_MCLKEN_MASK 128 #define DDRC_DDRC_MASK 63 #define DDRC_DDRC_BITNUM 0 /*** DDRD - Data Direction Register D; 0x00000007 ***/ typedef union { byte Byte; struct { byte DDRD0 :1; /* Data Direction Register D Bit 0 */ byte DDRD1 :1; /* Data Direction Register D Bit 1 */ byte DDRD2 :1; /* Data Direction Register D Bit 2 */ byte DDRD3 :1; /* Data Direction Register D Bit 3 */ byte DDRD4 :1; /* Data Direction Register D Bit 4 */ byte DDRD5 :1; /* Data Direction Register D Bit 5 */ byte DDRD6 :1; /* Data Direction Register D Bit 6 */ byte DDRD7 :1; /* Data Direction Register D Bit 7 */ } Bits; } DDRDSTR; extern volatile DDRDSTR _DDRD @0x00000007; #define DDRD _DDRD.Byte #define DDRD_DDRD0 _DDRD.Bits.DDRD0 #define DDRD_DDRD1 _DDRD.Bits.DDRD1 #define DDRD_DDRD2 _DDRD.Bits.DDRD2 #define DDRD_DDRD3 _DDRD.Bits.DDRD3 #define DDRD_DDRD4 _DDRD.Bits.DDRD4 #define DDRD_DDRD5 _DDRD.Bits.DDRD5 #define DDRD_DDRD6 _DDRD.Bits.DDRD6 #define DDRD_DDRD7 _DDRD.Bits.DDRD7 #define DDRD_DDRD0_MASK 1 #define DDRD_DDRD1_MASK 2 #define DDRD_DDRD2_MASK 4 #define DDRD_DDRD3_MASK 8 #define DDRD_DDRD4_MASK 16 #define DDRD_DDRD5_MASK 32 #define DDRD_DDRD6_MASK 64 #define DDRD_DDRD7_MASK 128 /*** PTE - Port E Data Register; 0x00000008 ***/ typedef union { byte Byte; struct { byte PTE0 :1; /* Port E Data Bit 0 */ byte PTE1 :1; /* Port E Data Bit 1 */ byte PTE2 :1; /* Port E Data Bit 2 */ byte PTE3 :1; /* Port E Data Bit 3 */ byte PTE4 :1; /* Port E Data Bit 4 */ byte PTE5 :1; /* Port E Data Bit 5 */ byte PTE6 :1; /* Port E Data Bit 6 */ byte PTE7 :1; /* Port E Data Bit 7 */ } Bits; } PTESTR; extern volatile PTESTR _PTE @0x00000008; #define PTE _PTE.Byte #define PTE_PTE0 _PTE.Bits.PTE0 #define PTE_PTE1 _PTE.Bits.PTE1 #define PTE_PTE2 _PTE.Bits.PTE2 #define PTE_PTE3 _PTE.Bits.PTE3 #define PTE_PTE4 _PTE.Bits.PTE4 #define PTE_PTE5 _PTE.Bits.PTE5 #define PTE_PTE6 _PTE.Bits.PTE6 #define PTE_PTE7 _PTE.Bits.PTE7 #define PTE_PTE0_MASK 1 #define PTE_PTE1_MASK 2 #define PTE_PTE2_MASK 4 #define PTE_PTE3_MASK 8 #define PTE_PTE4_MASK 16 #define PTE_PTE5_MASK 32 #define PTE_PTE6_MASK 64 #define PTE_PTE7_MASK 128 /*** PTF - Port F Data Register; 0x00000009 ***/ typedef union { byte Byte; struct { byte PTF0 :1; /* Port F Data Bit 0 */ byte PTF1 :1; /* Port F Data Bit 1 */ byte PTF2 :1; /* Port F Data Bit 2 */ byte PTF3 :1; /* Port F Data Bit 3 */ byte PTF4 :1; /* Port F Data Bit 4 */ byte PTF5 :1; /* Port F Data Bit 5 */ byte PTF6 :1; /* Port F Data Bit 6 */ byte :1; } Bits; struct { byte grpPTF :7; byte :1; } MergedBits; } PTFSTR; extern volatile PTFSTR _PTF @0x00000009; #define PTF _PTF.Byte #define PTF_PTF0 _PTF.Bits.PTF0 #define PTF_PTF1 _PTF.Bits.PTF1 #define PTF_PTF2 _PTF.Bits.PTF2 #define PTF_PTF3 _PTF.Bits.PTF3 #define PTF_PTF4 _PTF.Bits.PTF4 #define PTF_PTF5 _PTF.Bits.PTF5 #define PTF_PTF6 _PTF.Bits.PTF6 #define PTF_PTF _PTF.MergedBits.grpPTF #define PTF_PTF0_MASK 1 #define PTF_PTF1_MASK 2 #define PTF_PTF2_MASK 4 #define PTF_PTF3_MASK 8 #define PTF_PTF4_MASK 16 #define PTF_PTF5_MASK 32 #define PTF_PTF6_MASK 64 #define PTF_PTF_MASK 127 #define PTF_PTF_BITNUM 0 /*** PTG - Port G Data Register; 0x0000000A ***/ typedef union { byte Byte; struct { byte PTG0 :1; /* Port G Data Bit 0 */ byte PTG1 :1; /* Port G Data Bit 1 */ byte PTG2 :1; /* Port G Data Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTG :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTGSTR; extern volatile PTGSTR _PTG @0x0000000A; #define PTG _PTG.Byte #define PTG_PTG0 _PTG.Bits.PTG0 #define PTG_PTG1 _PTG.Bits.PTG1 #define PTG_PTG2 _PTG.Bits.PTG2 #define PTG_PTG _PTG.MergedBits.grpPTG #define PTG_PTG0_MASK 1 #define PTG_PTG1_MASK 2 #define PTG_PTG2_MASK 4 #define PTG_PTG_MASK 7 #define PTG_PTG_BITNUM 0 /*** PTH - Port H Data Register; 0x0000000B ***/ typedef union { byte Byte; struct { byte PTH0 :1; /* Port H Data Bit 0 */ byte PTH1 :1; /* Port H Data Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPTH :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PTHSTR; extern volatile PTHSTR _PTH @0x0000000B; #define PTH _PTH.Byte #define PTH_PTH0 _PTH.Bits.PTH0 #define PTH_PTH1 _PTH.Bits.PTH1 #define PTH_PTH _PTH.MergedBits.grpPTH #define PTH_PTH0_MASK 1 #define PTH_PTH1_MASK 2 #define PTH_PTH_MASK 3 #define PTH_PTH_BITNUM 0 /*** DDRE - Data Direction Register E; 0x0000000C ***/ typedef union { byte Byte; struct { byte DDRE0 :1; /* Data Direction Register E Bit 0 */ byte DDRE1 :1; /* Data Direction Register E Bit 1 */ byte DDRE2 :1; /* Data Direction Register E Bit 2 */ byte DDRE3 :1; /* Data Direction Register E Bit 3 */ byte DDRE4 :1; /* Data Direction Register E Bit 4 */ byte DDRE5 :1; /* Data Direction Register E Bit 5 */ byte DDRE6 :1; /* Data Direction Register E Bit 6 */ byte DDRE7 :1; /* Data Direction Register E Bit 7 */ } Bits; } DDRESTR; extern volatile DDRESTR _DDRE @0x0000000C; #define DDRE _DDRE.Byte #define DDRE_DDRE0 _DDRE.Bits.DDRE0 #define DDRE_DDRE1 _DDRE.Bits.DDRE1 #define DDRE_DDRE2 _DDRE.Bits.DDRE2 #define DDRE_DDRE3 _DDRE.Bits.DDRE3 #define DDRE_DDRE4 _DDRE.Bits.DDRE4 #define DDRE_DDRE5 _DDRE.Bits.DDRE5 #define DDRE_DDRE6 _DDRE.Bits.DDRE6 #define DDRE_DDRE7 _DDRE.Bits.DDRE7 #define DDRE_DDRE0_MASK 1 #define DDRE_DDRE1_MASK 2 #define DDRE_DDRE2_MASK 4 #define DDRE_DDRE3_MASK 8 #define DDRE_DDRE4_MASK 16 #define DDRE_DDRE5_MASK 32 #define DDRE_DDRE6_MASK 64 #define DDRE_DDRE7_MASK 128 /*** DDRF - Data Direction Register F; 0x0000000D ***/ typedef union { byte Byte; struct { byte DDRF0 :1; /* Data Direction Register F Bit 0 */ byte DDRF1 :1; /* Data Direction Register F Bit 1 */ byte DDRF2 :1; /* Data Direction Register F Bit 2 */ byte DDRF3 :1; /* Data Direction Register F Bit 3 */ byte DDRF4 :1; /* Data Direction Register F Bit 4 */ byte DDRF5 :1; /* Data Direction Register F Bit 5 */ byte DDRF6 :1; /* Data Direction Register F Bit 6 */ byte :1; } Bits; struct { byte grpDDRF :7; byte :1; } MergedBits; } DDRFSTR; extern volatile DDRFSTR _DDRF @0x0000000D; #define DDRF _DDRF.Byte #define DDRF_DDRF0 _DDRF.Bits.DDRF0 #define DDRF_DDRF1 _DDRF.Bits.DDRF1 #define DDRF_DDRF2 _DDRF.Bits.DDRF2 #define DDRF_DDRF3 _DDRF.Bits.DDRF3 #define DDRF_DDRF4 _DDRF.Bits.DDRF4 #define DDRF_DDRF5 _DDRF.Bits.DDRF5 #define DDRF_DDRF6 _DDRF.Bits.DDRF6 #define DDRF_DDRF _DDRF.MergedBits.grpDDRF #define DDRF_DDRF0_MASK 1 #define DDRF_DDRF1_MASK 2 #define DDRF_DDRF2_MASK 4 #define DDRF_DDRF3_MASK 8 #define DDRF_DDRF4_MASK 16 #define DDRF_DDRF5_MASK 32 #define DDRF_DDRF6_MASK 64 #define DDRF_DDRF_MASK 127 #define DDRF_DDRF_BITNUM 0 /*** DDRG - Data Direction Register G; 0x0000000E ***/ typedef union { byte Byte; struct { byte DDRG0 :1; /* Data Direction Register G Bit 0 */ byte DDRG1 :1; /* Data Direction Register G Bit 1 */ byte DDRG2 :1; /* Data Direction Register G Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRG :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DDRGSTR; extern volatile DDRGSTR _DDRG @0x0000000E; #define DDRG _DDRG.Byte #define DDRG_DDRG0 _DDRG.Bits.DDRG0 #define DDRG_DDRG1 _DDRG.Bits.DDRG1 #define DDRG_DDRG2 _DDRG.Bits.DDRG2 #define DDRG_DDRG _DDRG.MergedBits.grpDDRG #define DDRG_DDRG0_MASK 1 #define DDRG_DDRG1_MASK 2 #define DDRG_DDRG2_MASK 4 #define DDRG_DDRG_MASK 7 #define DDRG_DDRG_BITNUM 0 /*** DDRH - Data Direction Register H; 0x0000000F ***/ typedef union { byte Byte; struct { byte DDRH0 :1; /* Data Direction Register H Bit 0 */ byte DDRH1 :1; /* Data Direction Register H Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpDDRH :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } DDRHSTR; extern volatile DDRHSTR _DDRH @0x0000000F; #define DDRH _DDRH.Byte #define DDRH_DDRH0 _DDRH.Bits.DDRH0 #define DDRH_DDRH1 _DDRH.Bits.DDRH1 #define DDRH_DDRH _DDRH.MergedBits.grpDDRH #define DDRH_DDRH0_MASK 1 #define DDRH_DDRH1_MASK 2 #define DDRH_DDRH_MASK 3 #define DDRH_DDRH_BITNUM 0 /*** SPCR - SPI Control Register; 0x00000010 ***/ typedef union { byte Byte; struct { byte SPTIE :1; /* SPI Transmit Interrupt Enable Bit */ byte SPE :1; /* SPI Enable Bit */ byte SPWOM :1; /* SPI Wired-OR Mode Bit */ byte CPHA :1; /* Clock Phase Bit */ byte CPOL :1; /* Clock Polarity Bit */ byte SPMSTR :1; /* SPI Master Bit */ byte :1; byte SPRIE :1; /* SPI Receiver Interrupt Enable Bit */ } Bits; } SPCRSTR; extern volatile SPCRSTR _SPCR @0x00000010; #define SPCR _SPCR.Byte #define SPCR_SPTIE _SPCR.Bits.SPTIE #define SPCR_SPE _SPCR.Bits.SPE #define SPCR_SPWOM _SPCR.Bits.SPWOM #define SPCR_CPHA _SPCR.Bits.CPHA #define SPCR_CPOL _SPCR.Bits.CPOL #define SPCR_SPMSTR _SPCR.Bits.SPMSTR #define SPCR_SPRIE _SPCR.Bits.SPRIE #define SPCR_SPTIE_MASK 1 #define SPCR_SPE_MASK 2 #define SPCR_SPWOM_MASK 4 #define SPCR_CPHA_MASK 8 #define SPCR_CPOL_MASK 16 #define SPCR_SPMSTR_MASK 32 #define SPCR_SPRIE_MASK 128 /*** SPSCR - SPI Status and Control Register; 0x00000011 ***/ typedef union { byte Byte; struct { byte SPR0 :1; /* SPI Baud Rate Select Bit 0 */ byte SPR1 :1; /* SPI Baud Rate Select Bit 1 */ byte MODFEN :1; /* Mode Fault Enable Bit */ byte SPTE :1; /* SPI Transmitter Empty Bit */ byte MODF :1; /* Mode Fault Bit */ byte OVRF :1; /* Overflow Bit */ byte ERRIE :1; /* Error Interrupt Enable Bit */ byte SPRF :1; /* SPI Receiver Full Bit */ } Bits; struct { byte grpSPR :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SPSCRSTR; extern volatile SPSCRSTR _SPSCR @0x00000011; #define SPSCR _SPSCR.Byte #define SPSCR_SPR0 _SPSCR.Bits.SPR0 #define SPSCR_SPR1 _SPSCR.Bits.SPR1 #define SPSCR_MODFEN _SPSCR.Bits.MODFEN #define SPSCR_SPTE _SPSCR.Bits.SPTE #define SPSCR_MODF _SPSCR.Bits.MODF #define SPSCR_OVRF _SPSCR.Bits.OVRF #define SPSCR_ERRIE _SPSCR.Bits.ERRIE #define SPSCR_SPRF _SPSCR.Bits.SPRF #define SPSCR_SPR _SPSCR.MergedBits.grpSPR #define SPSCR_SPR0_MASK 1 #define SPSCR_SPR1_MASK 2 #define SPSCR_MODFEN_MASK 4 #define SPSCR_SPTE_MASK 8 #define SPSCR_MODF_MASK 16 #define SPSCR_OVRF_MASK 32 #define SPSCR_ERRIE_MASK 64 #define SPSCR_SPRF_MASK 128 #define SPSCR_SPR_MASK 3 #define SPSCR_SPR_BITNUM 0 /*** SPDR - SPI Data Register; 0x00000012 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SPDRSTR; extern volatile SPDRSTR _SPDR @0x00000012; #define SPDR _SPDR.Byte #define SPDR_R0_T0 _SPDR.Bits.R0_T0 #define SPDR_R1_T1 _SPDR.Bits.R1_T1 #define SPDR_R2_T2 _SPDR.Bits.R2_T2 #define SPDR_R3_T3 _SPDR.Bits.R3_T3 #define SPDR_R4_T4 _SPDR.Bits.R4_T4 #define SPDR_R5_T5 _SPDR.Bits.R5_T5 #define SPDR_R6_T6 _SPDR.Bits.R6_T6 #define SPDR_R7_T7 _SPDR.Bits.R7_T7 #define SPDR_R0_T0_MASK 1 #define SPDR_R1_T1_MASK 2 #define SPDR_R2_T2_MASK 4 #define SPDR_R3_T3_MASK 8 #define SPDR_R4_T4_MASK 16 #define SPDR_R5_T5_MASK 32 #define SPDR_R6_T6_MASK 64 #define SPDR_R7_T7_MASK 128 /*** SCC1 - SCI Control Register 1; 0x00000013 ***/ typedef union { byte Byte; struct { byte PTY :1; /* Parity Bit */ byte PEN :1; /* Parity Enable Bit */ byte ILTY :1; /* Idle Line Type Bit */ byte WAKE :1; /* Wakeup Condition Bit */ byte M :1; /* Mode (Character Length) Bit */ byte TXINV :1; /* Transmit Inversion Bit */ byte ENSCI :1; /* Enable SCI Bit */ byte LOOPS :1; /* Loop Mode Select Bit */ } Bits; } SCC1STR; extern volatile SCC1STR _SCC1 @0x00000013; #define SCC1 _SCC1.Byte #define SCC1_PTY _SCC1.Bits.PTY #define SCC1_PEN _SCC1.Bits.PEN #define SCC1_ILTY _SCC1.Bits.ILTY #define SCC1_WAKE _SCC1.Bits.WAKE #define SCC1_M _SCC1.Bits.M #define SCC1_TXINV _SCC1.Bits.TXINV #define SCC1_ENSCI _SCC1.Bits.ENSCI #define SCC1_LOOPS _SCC1.Bits.LOOPS #define SCC1_PTY_MASK 1 #define SCC1_PEN_MASK 2 #define SCC1_ILTY_MASK 4 #define SCC1_WAKE_MASK 8 #define SCC1_M_MASK 16 #define SCC1_TXINV_MASK 32 #define SCC1_ENSCI_MASK 64 #define SCC1_LOOPS_MASK 128 /*** SCC2 - SCI Control Register 2; 0x00000014 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break Bit */ byte RWU :1; /* Receiver Wakeup Bit */ byte RE :1; /* Receiver Enable Bit */ byte TE :1; /* Transmitter Enable Bit */ byte ILIE :1; /* Idle Line Interrupt Enable Bit */ byte SCRIE :1; /* SCI Receive Interrupt Enable Bit */ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ byte SCTIE :1; /* SCI Transmit Interrupt Enable Bit */ } Bits; } SCC2STR; extern volatile SCC2STR _SCC2 @0x00000014; #define SCC2 _SCC2.Byte #define SCC2_SBK _SCC2.Bits.SBK #define SCC2_RWU _SCC2.Bits.RWU #define SCC2_RE _SCC2.Bits.RE #define SCC2_TE _SCC2.Bits.TE #define SCC2_ILIE _SCC2.Bits.ILIE #define SCC2_SCRIE _SCC2.Bits.SCRIE #define SCC2_TCIE _SCC2.Bits.TCIE #define SCC2_SCTIE _SCC2.Bits.SCTIE #define SCC2_SBK_MASK 1 #define SCC2_RWU_MASK 2 #define SCC2_RE_MASK 4 #define SCC2_TE_MASK 8 #define SCC2_ILIE_MASK 16 #define SCC2_SCRIE_MASK 32 #define SCC2_TCIE_MASK 64 #define SCC2_SCTIE_MASK 128 /*** SCC3 - SCI Control Register 3; 0x00000015 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Receiver Parity Error Interrupt Enable Bit */ byte FEIE :1; /* Receiver Framing Error Interrupt Enable Bit */ byte NEIE :1; /* Receiver Noise Error Interrupt Enable Bit */ byte ORIE :1; /* Receiver Overrun Interrupt Enable Bit */ byte :1; byte :1; byte T8 :1; /* Transmitted Bit 8 */ byte R8 :1; /* Received Bit 8 */ } Bits; } SCC3STR; extern volatile SCC3STR _SCC3 @0x00000015; #define SCC3 _SCC3.Byte #define SCC3_PEIE _SCC3.Bits.PEIE #define SCC3_FEIE _SCC3.Bits.FEIE #define SCC3_NEIE _SCC3.Bits.NEIE #define SCC3_ORIE _SCC3.Bits.ORIE #define SCC3_T8 _SCC3.Bits.T8 #define SCC3_R8 _SCC3.Bits.R8 #define SCC3_PEIE_MASK 1 #define SCC3_FEIE_MASK 2 #define SCC3_NEIE_MASK 4 #define SCC3_ORIE_MASK 8 #define SCC3_T8_MASK 64 #define SCC3_R8_MASK 128 /*** SCS1 - SCI Status Register 1; 0x00000016 ***/ typedef union { byte Byte; struct { byte PE :1; /* Receiver Parity Error Bit */ byte FE :1; /* Receiver Framing Error Bit */ byte NF :1; /* Receiver Noise Flag Bit */ byte OR :1; /* Receiver Overrun Bit */ byte IDLE :1; /* Receiver Idle Bit */ byte SCRF :1; /* SCI Receiver Full Bit */ byte TC :1; /* Transmission Complete Bit */ byte SCTE :1; /* SCI Transmitter Empty Bit */ } Bits; } SCS1STR; extern volatile SCS1STR _SCS1 @0x00000016; #define SCS1 _SCS1.Byte #define SCS1_PE _SCS1.Bits.PE #define SCS1_FE _SCS1.Bits.FE #define SCS1_NF _SCS1.Bits.NF #define SCS1_OR _SCS1.Bits.OR #define SCS1_IDLE _SCS1.Bits.IDLE #define SCS1_SCRF _SCS1.Bits.SCRF #define SCS1_TC _SCS1.Bits.TC #define SCS1_SCTE _SCS1.Bits.SCTE #define SCS1_PE_MASK 1 #define SCS1_FE_MASK 2 #define SCS1_NF_MASK 4 #define SCS1_OR_MASK 8 #define SCS1_IDLE_MASK 16 #define SCS1_SCRF_MASK 32 #define SCS1_TC_MASK 64 #define SCS1_SCTE_MASK 128 /*** SCS2 - SCI Status Register 2; 0x00000017 ***/ typedef union { byte Byte; struct { byte RPF :1; /* Reception in Progress Flag Bit */ byte BKF :1; /* Break Flag Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SCS2STR; extern volatile SCS2STR _SCS2 @0x00000017; #define SCS2 _SCS2.Byte #define SCS2_RPF _SCS2.Bits.RPF #define SCS2_BKF _SCS2.Bits.BKF #define SCS2_RPF_MASK 1 #define SCS2_BKF_MASK 2 /*** SCDR - SCI Data Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCDRSTR; extern volatile SCDRSTR _SCDR @0x00000018; #define SCDR _SCDR.Byte #define SCDR_R0_T0 _SCDR.Bits.R0_T0 #define SCDR_R1_T1 _SCDR.Bits.R1_T1 #define SCDR_R2_T2 _SCDR.Bits.R2_T2 #define SCDR_R3_T3 _SCDR.Bits.R3_T3 #define SCDR_R4_T4 _SCDR.Bits.R4_T4 #define SCDR_R5_T5 _SCDR.Bits.R5_T5 #define SCDR_R6_T6 _SCDR.Bits.R6_T6 #define SCDR_R7_T7 _SCDR.Bits.R7_T7 #define SCDR_R0_T0_MASK 1 #define SCDR_R1_T1_MASK 2 #define SCDR_R2_T2_MASK 4 #define SCDR_R3_T3_MASK 8 #define SCDR_R4_T4_MASK 16 #define SCDR_R5_T5_MASK 32 #define SCDR_R6_T6_MASK 64 #define SCDR_R7_T7_MASK 128 /*** SCBR - SCI Baud Rate Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte SCR0 :1; /* SCI Baud Rate Select Bit 0 */ byte SCR1 :1; /* SCI Baud Rate Select Bit 1 */ byte SCR2 :1; /* SCI Baud Rate Select Bit 2 */ byte :1; byte SCP0 :1; /* SCI Baud Rate Prescaler Bit 0 */ byte SCP1 :1; /* SCI Baud Rate Prescaler Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpSCR :3; byte :1; byte grpSCP :2; byte :1; byte :1; } MergedBits; } SCBRSTR; extern volatile SCBRSTR _SCBR @0x00000019; #define SCBR _SCBR.Byte #define SCBR_SCR0 _SCBR.Bits.SCR0 #define SCBR_SCR1 _SCBR.Bits.SCR1 #define SCBR_SCR2 _SCBR.Bits.SCR2 #define SCBR_SCP0 _SCBR.Bits.SCP0 #define SCBR_SCP1 _SCBR.Bits.SCP1 #define SCBR_SCR _SCBR.MergedBits.grpSCR #define SCBR_SCP _SCBR.MergedBits.grpSCP #define SCBR_SCR0_MASK 1 #define SCBR_SCR1_MASK 2 #define SCBR_SCR2_MASK 4 #define SCBR_SCP0_MASK 16 #define SCBR_SCP1_MASK 32 #define SCBR_SCR_MASK 7 #define SCBR_SCR_BITNUM 0 #define SCBR_SCP_MASK 48 #define SCBR_SCP_BITNUM 4 /*** ISCR - IRQ Status and Control Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte MODE :1; /* IRQ Edge/Level Select Bit */ byte IMASK :1; /* IRQ Interrupt Mask Bit */ byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */ byte IRQF :1; /* IRQ Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } ISCRSTR; extern volatile ISCRSTR _ISCR @0x0000001A; #define ISCR _ISCR.Byte #define ISCR_MODE _ISCR.Bits.MODE #define ISCR_IMASK _ISCR.Bits.IMASK #define ISCR_ACK _ISCR.Bits.ACK #define ISCR_IRQF _ISCR.Bits.IRQF #define ISCR_MODE_MASK 1 #define ISCR_IMASK_MASK 2 #define ISCR_ACK_MASK 4 #define ISCR_IRQF_MASK 8 /*** PCTL - PLL Control Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte BCS :1; /* Base Clock Select Bit */ byte PLLON :1; /* PLL On Bit */ byte PLLF :1; /* PLL Flag Bit */ byte PLLIE :1; /* PLL Interrupt Enable Bit */ } Bits; } PCTLSTR; extern volatile PCTLSTR _PCTL @0x0000001C; #define PCTL _PCTL.Byte #define PCTL_BCS _PCTL.Bits.BCS #define PCTL_PLLON _PCTL.Bits.PLLON #define PCTL_PLLF _PCTL.Bits.PLLF #define PCTL_PLLIE _PCTL.Bits.PLLIE #define PCTL_BCS_MASK 16 #define PCTL_PLLON_MASK 32 #define PCTL_PLLF_MASK 64 #define PCTL_PLLIE_MASK 128 /*** PBWC - PLL Bandwidth Control Register; 0x0000001D ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte XLD :1; /* Crystal Loss Detect Bit */ byte ACQ :1; /* Acquisition Mode Bit */ byte LOCK :1; /* Lock Indicator Bit */ byte AUTO :1; /* Automatic Bandwidth Control Bit */ } Bits; } PBWCSTR; extern volatile PBWCSTR _PBWC @0x0000001D; #define PBWC _PBWC.Byte #define PBWC_XLD _PBWC.Bits.XLD #define PBWC_ACQ _PBWC.Bits.ACQ #define PBWC_LOCK _PBWC.Bits.LOCK #define PBWC_AUTO _PBWC.Bits.AUTO #define PBWC_XLD_MASK 16 #define PBWC_ACQ_MASK 32 #define PBWC_LOCK_MASK 64 #define PBWC_AUTO_MASK 128 /*** PPG - PLL Programming Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte VRS4 :1; /* VCO Range Select Bit 4 */ byte VRS5 :1; /* VCO Range Select Bit 5 */ byte VRS6 :1; /* VCO Range Select Bit 6 */ byte VRS7 :1; /* VCO Range Select Bit 7 */ byte MUL4 :1; /* Multiplier Select Bit 4 */ byte MUL5 :1; /* Multiplier Select Bit 5 */ byte MUL6 :1; /* Multiplier Select Bit 6 */ byte MUL7 :1; /* Multiplier Select Bit 7 */ } Bits; struct { byte grpVRS_4 :4; byte grpMUL_4 :4; } MergedBits; } PPGSTR; extern volatile PPGSTR _PPG @0x0000001E; #define PPG _PPG.Byte #define PPG_VRS4 _PPG.Bits.VRS4 #define PPG_VRS5 _PPG.Bits.VRS5 #define PPG_VRS6 _PPG.Bits.VRS6 #define PPG_VRS7 _PPG.Bits.VRS7 #define PPG_MUL4 _PPG.Bits.MUL4 #define PPG_MUL5 _PPG.Bits.MUL5 #define PPG_MUL6 _PPG.Bits.MUL6 #define PPG_MUL7 _PPG.Bits.MUL7 #define PPG_VRS_4 _PPG.MergedBits.grpVRS_4 #define PPG_MUL_4 _PPG.MergedBits.grpMUL_4 #define PPG_VRS PPG_VRS_4 #define PPG_MUL PPG_MUL_4 #define PPG_VRS4_MASK 1 #define PPG_VRS5_MASK 2 #define PPG_VRS6_MASK 4 #define PPG_VRS7_MASK 8 #define PPG_MUL4_MASK 16 #define PPG_MUL5_MASK 32 #define PPG_MUL6_MASK 64 #define PPG_MUL7_MASK 128 #define PPG_VRS_4_MASK 15 #define PPG_VRS_4_BITNUM 0 #define PPG_MUL_4_MASK 240 #define PPG_MUL_4_BITNUM 4 /*** CONFIG1 - Configuration Register; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte COPL :1; /* COP Long Timeout */ byte SSREC :1; /* Short Stop Recovery Bit */ byte LVIPWR :1; /* LVI Power Enable Bit */ byte LVIRST :1; /* LVI Reset Enable Bit */ byte :1; byte LVISTOP :1; /* LVI Stop Mode Enable Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_COPL _CONFIG1.Bits.COPL #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVIPWR _CONFIG1.Bits.LVIPWR #define CONFIG1_LVIRST _CONFIG1.Bits.LVIRST #define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_COPL_MASK 4 #define CONFIG1_SSREC_MASK 8 #define CONFIG1_LVIPWR_MASK 16 #define CONFIG1_LVIRST_MASK 32 #define CONFIG1_LVISTOP_MASK 128 /*** TASC - TIMA Status and Control Register; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIMA Reset Bit */ byte TSTOP :1; /* TIMA Stop Bit */ byte TOIE :1; /* TIMA Overflow Interrupt Enable Bit */ byte TOF :1; /* TIMA Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TASCSTR; extern volatile TASCSTR _TASC @0x00000020; #define TASC _TASC.Byte #define TASC_PS0 _TASC.Bits.PS0 #define TASC_PS1 _TASC.Bits.PS1 #define TASC_PS2 _TASC.Bits.PS2 #define TASC_TRST _TASC.Bits.TRST #define TASC_TSTOP _TASC.Bits.TSTOP #define TASC_TOIE _TASC.Bits.TOIE #define TASC_TOF _TASC.Bits.TOF #define TASC_PS _TASC.MergedBits.grpPS #define TASC_PS0_MASK 1 #define TASC_PS1_MASK 2 #define TASC_PS2_MASK 4 #define TASC_TRST_MASK 16 #define TASC_TSTOP_MASK 32 #define TASC_TOIE_MASK 64 #define TASC_TOF_MASK 128 #define TASC_PS_MASK 7 #define TASC_PS_BITNUM 0 /*** TACNT - TIMA Counter Register; 0x00000022 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACNTH - TIMA Counter Register; 0x00000022 ***/ union { byte Byte; } TACNTHSTR; #define TACNTH _TACNT.Overlap_STR.TACNTHSTR.Byte /*** TACNTL - TIMA Counter Register; 0x00000023 ***/ union { byte Byte; } TACNTLSTR; #define TACNTL _TACNT.Overlap_STR.TACNTLSTR.Byte } Overlap_STR; } TACNTSTR; extern volatile TACNTSTR _TACNT @0x00000022; #define TACNT _TACNT.Word /*** TAMOD - TIMA Counter Modulo Register; 0x00000024 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TAMODH - TIMA Counter Modulo Register; 0x00000024 ***/ union { byte Byte; } TAMODHSTR; #define TAMODH _TAMOD.Overlap_STR.TAMODHSTR.Byte /*** TAMODL - TIMA Counter Modulo Register; 0x00000025 ***/ union { byte Byte; } TAMODLSTR; #define TAMODL _TAMOD.Overlap_STR.TAMODLSTR.Byte } Overlap_STR; } TAMODSTR; extern volatile TAMODSTR _TAMOD @0x00000024; #define TAMOD _TAMOD.Word /*** TASC0 - TIMA Channel Status and Control Register; 0x00000026 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit */ byte ELS0B :1; /* Edge/Level Select Bit */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TASC0STR; extern volatile TASC0STR _TASC0 @0x00000026; #define TASC0 _TASC0.Byte #define TASC0_CH0MAX _TASC0.Bits.CH0MAX #define TASC0_TOV0 _TASC0.Bits.TOV0 #define TASC0_ELS0A _TASC0.Bits.ELS0A #define TASC0_ELS0B _TASC0.Bits.ELS0B #define TASC0_MS0A _TASC0.Bits.MS0A #define TASC0_MS0B _TASC0.Bits.MS0B #define TASC0_CH0IE _TASC0.Bits.CH0IE #define TASC0_CH0F _TASC0.Bits.CH0F #define TASC0_ELS0x _TASC0.MergedBits.grpELS0x #define TASC0_MS0x _TASC0.MergedBits.grpMS0x #define TASC0_CH0MAX_MASK 1 #define TASC0_TOV0_MASK 2 #define TASC0_ELS0A_MASK 4 #define TASC0_ELS0B_MASK 8 #define TASC0_MS0A_MASK 16 #define TASC0_MS0B_MASK 32 #define TASC0_CH0IE_MASK 64 #define TASC0_CH0F_MASK 128 #define TASC0_ELS0x_MASK 12 #define TASC0_ELS0x_BITNUM 2 #define TASC0_MS0x_MASK 48 #define TASC0_MS0x_BITNUM 4 /*** TACH0 - TIMA Channel Register; 0x00000027 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH0H - TIMA Channel Register; 0x00000027 ***/ union { byte Byte; } TACH0HSTR; #define TACH0H _TACH0.Overlap_STR.TACH0HSTR.Byte /*** TACH0L - TIMA Channel Register; 0x00000028 ***/ union { byte Byte; } TACH0LSTR; #define TACH0L _TACH0.Overlap_STR.TACH0LSTR.Byte } Overlap_STR; } TACH0STR; extern volatile TACH0STR _TACH0 @0x00000027; #define TACH0 _TACH0.Word /*** TASC1 - TIMA Channel Status and Control Register; 0x00000029 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit */ byte ELS1B :1; /* Edge/Level Select Bit */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } TASC1STR; extern volatile TASC1STR _TASC1 @0x00000029; #define TASC1 _TASC1.Byte #define TASC1_CH1MAX _TASC1.Bits.CH1MAX #define TASC1_TOV1 _TASC1.Bits.TOV1 #define TASC1_ELS1A _TASC1.Bits.ELS1A #define TASC1_ELS1B _TASC1.Bits.ELS1B #define TASC1_MS1A _TASC1.Bits.MS1A #define TASC1_CH1IE _TASC1.Bits.CH1IE #define TASC1_CH1F _TASC1.Bits.CH1F #define TASC1_ELS1x _TASC1.MergedBits.grpELS1x #define TASC1_CH1MAX_MASK 1 #define TASC1_TOV1_MASK 2 #define TASC1_ELS1A_MASK 4 #define TASC1_ELS1B_MASK 8 #define TASC1_MS1A_MASK 16 #define TASC1_CH1IE_MASK 64 #define TASC1_CH1F_MASK 128 #define TASC1_ELS1x_MASK 12 #define TASC1_ELS1x_BITNUM 2 /*** TACH1 - TIMA Channel Register; 0x0000002A ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH1H - TIMA Channel Register; 0x0000002A ***/ union { byte Byte; } TACH1HSTR; #define TACH1H _TACH1.Overlap_STR.TACH1HSTR.Byte /*** TACH1L - TIMA Channel Register; 0x0000002B ***/ union { byte Byte; } TACH1LSTR; #define TACH1L _TACH1.Overlap_STR.TACH1LSTR.Byte } Overlap_STR; } TACH1STR; extern volatile TACH1STR _TACH1 @0x0000002A; #define TACH1 _TACH1.Word /*** TASC2 - TIMA Channel Status and Control Register; 0x0000002C ***/ typedef union { byte Byte; struct { byte CH2MAX :1; /* Channel 2 Maximum Duty Cycle Bit */ byte TOV2 :1; /* Toggle-On-Overflow Bit */ byte ELS2A :1; /* Edge_Level Select Bits */ byte ELS2B :1; /* Edge_Level Select Bits */ byte MS2A :1; /* Mode Select Bit A */ byte MS2B :1; /* Mode Select Bit B */ byte CH2IE :1; /* Channel 2 Interrupt Enable Bit */ byte CH2F :1; /* Channel 2 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_2 :1; byte grpELS2x :2; byte grpMS2x :2; byte :1; byte :1; } MergedBits; } TASC2STR; extern volatile TASC2STR _TASC2 @0x0000002C; #define TASC2 _TASC2.Byte #define TASC2_CH2MAX _TASC2.Bits.CH2MAX #define TASC2_TOV2 _TASC2.Bits.TOV2 #define TASC2_ELS2A _TASC2.Bits.ELS2A #define TASC2_ELS2B _TASC2.Bits.ELS2B #define TASC2_MS2A _TASC2.Bits.MS2A #define TASC2_MS2B _TASC2.Bits.MS2B #define TASC2_CH2IE _TASC2.Bits.CH2IE #define TASC2_CH2F _TASC2.Bits.CH2F #define TASC2_ELS2x _TASC2.MergedBits.grpELS2x #define TASC2_MS2x _TASC2.MergedBits.grpMS2x #define TASC2_CH2MAX_MASK 1 #define TASC2_TOV2_MASK 2 #define TASC2_ELS2A_MASK 4 #define TASC2_ELS2B_MASK 8 #define TASC2_MS2A_MASK 16 #define TASC2_MS2B_MASK 32 #define TASC2_CH2IE_MASK 64 #define TASC2_CH2F_MASK 128 #define TASC2_ELS2x_MASK 12 #define TASC2_ELS2x_BITNUM 2 #define TASC2_MS2x_MASK 48 #define TASC2_MS2x_BITNUM 4 /*** TACH2 - TIMA Channel Register; 0x0000002D ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH2H - TIMA Channel Register; 0x0000002D ***/ union { byte Byte; } TACH2HSTR; #define TACH2H _TACH2.Overlap_STR.TACH2HSTR.Byte /*** TACH2L - TIMA Channel Register; 0x0000002E ***/ union { byte Byte; } TACH2LSTR; #define TACH2L _TACH2.Overlap_STR.TACH2LSTR.Byte } Overlap_STR; } TACH2STR; extern volatile TACH2STR _TACH2 @0x0000002D; #define TACH2 _TACH2.Word /*** TASC3 - TIMA Channel Status and Control Register; 0x0000002F ***/ typedef union { byte Byte; struct { byte CH3MAX :1; /* Channel 3 Maximum Duty Cycle Bit */ byte TOV3 :1; /* Toggle-On-Overflow Bit */ byte ELS3A :1; /* Edge_Level Select Bits */ byte ELS3B :1; /* Edge_Level Select Bits */ byte MS3A :1; /* Mode Select Bit A */ byte :1; byte CH3IE :1; /* Channel 3 Interrupt Enable Bit */ byte CH3F :1; /* Channel 3 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_3 :1; byte grpELS3x :2; byte grpMS3x :1; byte :1; byte :1; byte :1; } MergedBits; } TASC3STR; extern volatile TASC3STR _TASC3 @0x0000002F; #define TASC3 _TASC3.Byte #define TASC3_CH3MAX _TASC3.Bits.CH3MAX #define TASC3_TOV3 _TASC3.Bits.TOV3 #define TASC3_ELS3A _TASC3.Bits.ELS3A #define TASC3_ELS3B _TASC3.Bits.ELS3B #define TASC3_MS3A _TASC3.Bits.MS3A #define TASC3_CH3IE _TASC3.Bits.CH3IE #define TASC3_CH3F _TASC3.Bits.CH3F #define TASC3_ELS3x _TASC3.MergedBits.grpELS3x #define TASC3_CH3MAX_MASK 1 #define TASC3_TOV3_MASK 2 #define TASC3_ELS3A_MASK 4 #define TASC3_ELS3B_MASK 8 #define TASC3_MS3A_MASK 16 #define TASC3_CH3IE_MASK 64 #define TASC3_CH3F_MASK 128 #define TASC3_ELS3x_MASK 12 #define TASC3_ELS3x_BITNUM 2 /*** TACH3 - TIMA Channel Register; 0x00000030 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH3H - TIMA Channel Register; 0x00000030 ***/ union { byte Byte; } TACH3HSTR; #define TACH3H _TACH3.Overlap_STR.TACH3HSTR.Byte /*** TACH3L - TIMA Channel Register; 0x00000031 ***/ union { byte Byte; } TACH3LSTR; #define TACH3L _TACH3.Overlap_STR.TACH3LSTR.Byte } Overlap_STR; } TACH3STR; extern volatile TACH3STR _TACH3 @0x00000030; #define TACH3 _TACH3.Word /*** TASC4 - TIMA Channel Status and Control Register; 0x00000032 ***/ typedef union { byte Byte; struct { byte CH4MAX :1; /* Channel 4 Maximum Duty Cycle Bit */ byte TOV4 :1; /* Toggle-On-Overflow Bit */ byte ELS4A :1; /* Edge_Level Select Bits */ byte ELS4B :1; /* Edge_Level Select Bits */ byte MS4A :1; /* Mode Select Bit A */ byte MS4B :1; /* Mode Select Bit B */ byte CH4IE :1; /* Channel 4 Interrupt Enable Bit */ byte CH4F :1; /* Channel 4 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_4 :1; byte grpELS4x :2; byte grpMS4x :2; byte :1; byte :1; } MergedBits; } TASC4STR; extern volatile TASC4STR _TASC4 @0x00000032; #define TASC4 _TASC4.Byte #define TASC4_CH4MAX _TASC4.Bits.CH4MAX #define TASC4_TOV4 _TASC4.Bits.TOV4 #define TASC4_ELS4A _TASC4.Bits.ELS4A #define TASC4_ELS4B _TASC4.Bits.ELS4B #define TASC4_MS4A _TASC4.Bits.MS4A #define TASC4_MS4B _TASC4.Bits.MS4B #define TASC4_CH4IE _TASC4.Bits.CH4IE #define TASC4_CH4F _TASC4.Bits.CH4F #define TASC4_ELS4x _TASC4.MergedBits.grpELS4x #define TASC4_MS4x _TASC4.MergedBits.grpMS4x #define TASC4_CH4MAX_MASK 1 #define TASC4_TOV4_MASK 2 #define TASC4_ELS4A_MASK 4 #define TASC4_ELS4B_MASK 8 #define TASC4_MS4A_MASK 16 #define TASC4_MS4B_MASK 32 #define TASC4_CH4IE_MASK 64 #define TASC4_CH4F_MASK 128 #define TASC4_ELS4x_MASK 12 #define TASC4_ELS4x_BITNUM 2 #define TASC4_MS4x_MASK 48 #define TASC4_MS4x_BITNUM 4 /*** TACH4 - TIMA Channel Register; 0x00000033 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH4H - TIMA Channel Register; 0x00000033 ***/ union { byte Byte; } TACH4HSTR; #define TACH4H _TACH4.Overlap_STR.TACH4HSTR.Byte /*** TACH4L - TIMA Channel Register; 0x00000034 ***/ union { byte Byte; } TACH4LSTR; #define TACH4L _TACH4.Overlap_STR.TACH4LSTR.Byte } Overlap_STR; } TACH4STR; extern volatile TACH4STR _TACH4 @0x00000033; #define TACH4 _TACH4.Word /*** TASC5 - TIMA Channel Status and Control Register; 0x00000035 ***/ typedef union { byte Byte; struct { byte CH5MAX :1; /* Channel 5 Maximum Duty Cycle Bit */ byte TOV5 :1; /* Toggle-On-Overflow Bit */ byte ELS5A :1; /* Edge_Level Select Bits */ byte ELS5B :1; /* Edge_Level Select Bits */ byte MS5A :1; /* Mode Select Bit A */ byte :1; byte CH5IE :1; /* Channel 5 Interrupt Enable Bit */ byte CH5F :1; /* Channel 5 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_5 :1; byte grpELS5x :2; byte grpMS5x :1; byte :1; byte :1; byte :1; } MergedBits; } TASC5STR; extern volatile TASC5STR _TASC5 @0x00000035; #define TASC5 _TASC5.Byte #define TASC5_CH5MAX _TASC5.Bits.CH5MAX #define TASC5_TOV5 _TASC5.Bits.TOV5 #define TASC5_ELS5A _TASC5.Bits.ELS5A #define TASC5_ELS5B _TASC5.Bits.ELS5B #define TASC5_MS5A _TASC5.Bits.MS5A #define TASC5_CH5IE _TASC5.Bits.CH5IE #define TASC5_CH5F _TASC5.Bits.CH5F #define TASC5_ELS5x _TASC5.MergedBits.grpELS5x #define TASC5_CH5MAX_MASK 1 #define TASC5_TOV5_MASK 2 #define TASC5_ELS5A_MASK 4 #define TASC5_ELS5B_MASK 8 #define TASC5_MS5A_MASK 16 #define TASC5_CH5IE_MASK 64 #define TASC5_CH5F_MASK 128 #define TASC5_ELS5x_MASK 12 #define TASC5_ELS5x_BITNUM 2 /*** TACH5 - TIMA Channel Register; 0x00000036 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TACH5H - TIMA Channel Register; 0x00000036 ***/ union { byte Byte; } TACH5HSTR; #define TACH5H _TACH5.Overlap_STR.TACH5HSTR.Byte /*** TACH5L - TIMA Channel Register; 0x00000037 ***/ union { byte Byte; } TACH5LSTR; #define TACH5L _TACH5.Overlap_STR.TACH5LSTR.Byte } Overlap_STR; } TACH5STR; extern volatile TACH5STR _TACH5 @0x00000036; #define TACH5 _TACH5.Word /*** ADSCR - ADC Status and Control Register; 0x00000038 ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x00000038; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADR - ADC Data Register; 0x00000039 ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADRSTR; extern volatile ADRSTR _ADR @0x00000039; #define ADR _ADR.Byte #define ADR_AD0 _ADR.Bits.AD0 #define ADR_AD1 _ADR.Bits.AD1 #define ADR_AD2 _ADR.Bits.AD2 #define ADR_AD3 _ADR.Bits.AD3 #define ADR_AD4 _ADR.Bits.AD4 #define ADR_AD5 _ADR.Bits.AD5 #define ADR_AD6 _ADR.Bits.AD6 #define ADR_AD7 _ADR.Bits.AD7 #define ADR_AD0_MASK 1 #define ADR_AD1_MASK 2 #define ADR_AD2_MASK 4 #define ADR_AD3_MASK 8 #define ADR_AD4_MASK 16 #define ADR_AD5_MASK 32 #define ADR_AD6_MASK 64 #define ADR_AD7_MASK 128 /*** ADICLK - ADC Input Clock Register; 0x0000003A ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte ADICLK_BIT :1; /* ADC Input Clock Register Bit */ byte ADIV0 :1; /* ADC Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC Clock Prescaler Bit 1 */ byte ADIV2 :1; /* ADC Clock Prescaler Bit 2 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte grpADIV :3; } MergedBits; } ADICLKSTR; extern volatile ADICLKSTR _ADICLK @0x0000003A; #define ADICLK _ADICLK.Byte #define ADICLK_ADICLK_BIT _ADICLK.Bits.ADICLK_BIT #define ADICLK_ADIV0 _ADICLK.Bits.ADIV0 #define ADICLK_ADIV1 _ADICLK.Bits.ADIV1 #define ADICLK_ADIV2 _ADICLK.Bits.ADIV2 #define ADICLK_ADIV _ADICLK.MergedBits.grpADIV #define ADICLK_ADICLK_BIT_MASK 16 #define ADICLK_ADIV0_MASK 32 #define ADICLK_ADIV1_MASK 64 #define ADICLK_ADIV2_MASK 128 #define ADICLK_ADIV_MASK 224 #define ADICLK_ADIV_BITNUM 5 /*** BARD - BDLC Analog and Roundtrip Delay Register; 0x0000003B ***/ typedef union { byte Byte; struct { byte BO0 :1; /* BARD Offset Bit */ byte BO1 :1; /* BARD Offset Bit */ byte BO2 :1; /* BARD Offset Bit */ byte BO3 :1; /* BARD Offset Bit */ byte :1; byte :1; byte RXPOL :1; /* Receive Pin Polarity Bit */ byte ATE :1; /* Analog Transceiver Enable Bit */ } Bits; struct { byte grpBO :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } BARDSTR; extern volatile BARDSTR _BARD @0x0000003B; #define BARD _BARD.Byte #define BARD_BO0 _BARD.Bits.BO0 #define BARD_BO1 _BARD.Bits.BO1 #define BARD_BO2 _BARD.Bits.BO2 #define BARD_BO3 _BARD.Bits.BO3 #define BARD_RXPOL _BARD.Bits.RXPOL #define BARD_ATE _BARD.Bits.ATE #define BARD_BO _BARD.MergedBits.grpBO #define BARD_BO0_MASK 1 #define BARD_BO1_MASK 2 #define BARD_BO2_MASK 4 #define BARD_BO3_MASK 8 #define BARD_RXPOL_MASK 64 #define BARD_ATE_MASK 128 #define BARD_BO_MASK 15 #define BARD_BO_BITNUM 0 /*** BCR1 - BDLC Control Register 1; 0x0000003C ***/ typedef union { byte Byte; struct { byte WCM :1; /* Wait Clock Mode Bit */ byte IE :1; /* Interrupt Enable Bit */ byte :1; byte :1; byte R0 :1; /* Rate Select Bit */ byte R1 :1; /* Rate Select Bit */ byte CLKS :1; /* Clock Bit */ byte IMSG :1; /* Ignore Message Bit */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpR :2; byte :1; byte :1; } MergedBits; } BCR1STR; extern volatile BCR1STR _BCR1 @0x0000003C; #define BCR1 _BCR1.Byte #define BCR1_WCM _BCR1.Bits.WCM #define BCR1_IE _BCR1.Bits.IE #define BCR1_R0 _BCR1.Bits.R0 #define BCR1_R1 _BCR1.Bits.R1 #define BCR1_CLKS _BCR1.Bits.CLKS #define BCR1_IMSG _BCR1.Bits.IMSG #define BCR1_R _BCR1.MergedBits.grpR #define BCR1_WCM_MASK 1 #define BCR1_IE_MASK 2 #define BCR1_R0_MASK 16 #define BCR1_R1_MASK 32 #define BCR1_CLKS_MASK 64 #define BCR1_IMSG_MASK 128 #define BCR1_R_MASK 48 #define BCR1_R_BITNUM 4 /*** BCR2 - BDLC Control Register 2; 0x0000003D ***/ typedef union { byte Byte; struct { byte TMIFR0 :1; /* Transmit In-Frame Response Control Bit */ byte TMIFR1 :1; /* Transmit In-Frame Response Control Bit */ byte TSIFR :1; /* Transmit In-Frame Response Control Bit */ byte TEOD :1; /* Transmit End-of-Data Bit */ byte NBFS :1; /* Normalization Bit Format select Bit */ byte RX4XE :1; /* Receive 4X Enable Bit */ byte DLOOP :1; /* Digital Loopback Mode Bit */ byte ALOOP :1; /* Analog Loopback Mode Bit */ } Bits; struct { byte grpTMIFR :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } BCR2STR; extern volatile BCR2STR _BCR2 @0x0000003D; #define BCR2 _BCR2.Byte #define BCR2_TMIFR0 _BCR2.Bits.TMIFR0 #define BCR2_TMIFR1 _BCR2.Bits.TMIFR1 #define BCR2_TSIFR _BCR2.Bits.TSIFR #define BCR2_TEOD _BCR2.Bits.TEOD #define BCR2_NBFS _BCR2.Bits.NBFS #define BCR2_RX4XE _BCR2.Bits.RX4XE #define BCR2_DLOOP _BCR2.Bits.DLOOP #define BCR2_ALOOP _BCR2.Bits.ALOOP #define BCR2_TMIFR _BCR2.MergedBits.grpTMIFR #define BCR2_TMIFR0_MASK 1 #define BCR2_TMIFR1_MASK 2 #define BCR2_TSIFR_MASK 4 #define BCR2_TEOD_MASK 8 #define BCR2_NBFS_MASK 16 #define BCR2_RX4XE_MASK 32 #define BCR2_DLOOP_MASK 64 #define BCR2_ALOOP_MASK 128 #define BCR2_TMIFR_MASK 3 #define BCR2_TMIFR_BITNUM 0 /*** BSVR - BDLC State Vector Register; 0x0000003E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte I0 :1; /* Interrupt Source Bit */ byte I1 :1; /* Interrupt Source Bit */ byte I2 :1; /* Interrupt Source Bit */ byte I3 :1; /* Interrupt Source Bit */ byte :1; byte :1; } Bits; struct { byte :1; byte :1; byte grpI :4; byte :1; byte :1; } MergedBits; } BSVRSTR; extern volatile BSVRSTR _BSVR @0x0000003E; #define BSVR _BSVR.Byte #define BSVR_I0 _BSVR.Bits.I0 #define BSVR_I1 _BSVR.Bits.I1 #define BSVR_I2 _BSVR.Bits.I2 #define BSVR_I3 _BSVR.Bits.I3 #define BSVR_I _BSVR.MergedBits.grpI #define BSVR_I0_MASK 4 #define BSVR_I1_MASK 8 #define BSVR_I2_MASK 16 #define BSVR_I3_MASK 32 #define BSVR_I_MASK 60 #define BSVR_I_BITNUM 2 /*** BDR - BDLC Data Register; 0x0000003F ***/ typedef union { byte Byte; struct { byte BD0 :1; /* BDLC Data Bit 0 */ byte BD1 :1; /* BDLC Data Bit 1 */ byte BD2 :1; /* BDLC Data Bit 2 */ byte BD3 :1; /* BDLC Data Bit 3 */ byte BD4 :1; /* BDLC Data Bit 4 */ byte BD5 :1; /* BDLC Data Bit 5 */ byte BD6 :1; /* BDLC Data Bit 6 */ byte BD7 :1; /* BDLC Data Bit 7 */ } Bits; } BDRSTR; extern volatile BDRSTR _BDR @0x0000003F; #define BDR _BDR.Byte #define BDR_BD0 _BDR.Bits.BD0 #define BDR_BD1 _BDR.Bits.BD1 #define BDR_BD2 _BDR.Bits.BD2 #define BDR_BD3 _BDR.Bits.BD3 #define BDR_BD4 _BDR.Bits.BD4 #define BDR_BD5 _BDR.Bits.BD5 #define BDR_BD6 _BDR.Bits.BD6 #define BDR_BD7 _BDR.Bits.BD7 #define BDR_BD0_MASK 1 #define BDR_BD1_MASK 2 #define BDR_BD2_MASK 4 #define BDR_BD3_MASK 8 #define BDR_BD4_MASK 16 #define BDR_BD5_MASK 32 #define BDR_BD6_MASK 64 #define BDR_BD7_MASK 128 /*** TSC - Timer Status & Control; 0x0000004B ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit */ byte PS1 :1; /* Prescaler Select Bit */ byte PS2 :1; /* Prescaler Select Bit */ byte :1; byte TRST :1; /* TIM Reset Bit */ byte TSTOP :1; /* TIM Stop Bit */ byte TOIE :1; /* TIM Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } TSCSTR; extern volatile TSCSTR _TSC @0x0000004B; #define TSC _TSC.Byte #define TSC_PS0 _TSC.Bits.PS0 #define TSC_PS1 _TSC.Bits.PS1 #define TSC_PS2 _TSC.Bits.PS2 #define TSC_TRST _TSC.Bits.TRST #define TSC_TSTOP _TSC.Bits.TSTOP #define TSC_TOIE _TSC.Bits.TOIE #define TSC_TOF _TSC.Bits.TOF #define TSC_PS _TSC.MergedBits.grpPS #define TSC_PS0_MASK 1 #define TSC_PS1_MASK 2 #define TSC_PS2_MASK 4 #define TSC_TRST_MASK 16 #define TSC_TSTOP_MASK 32 #define TSC_TOIE_MASK 64 #define TSC_TOF_MASK 128 #define TSC_PS_MASK 7 #define TSC_PS_BITNUM 0 /*** TCNT - TIM Counter Register; 0x0000004C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TCNTH - TIM Counter Register; 0x0000004C ***/ union { byte Byte; } TCNTHSTR; #define TCNTH _TCNT.Overlap_STR.TCNTHSTR.Byte /*** TCNTL - TIM Counter Register; 0x0000004D ***/ union { byte Byte; } TCNTLSTR; #define TCNTL _TCNT.Overlap_STR.TCNTLSTR.Byte } Overlap_STR; } TCNTSTR; extern volatile TCNTSTR _TCNT @0x0000004C; #define TCNT _TCNT.Word /*** TMOD - TIM Counter Modulo Register; 0x0000004E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TMODH - TIM Counter Modulo Register; 0x0000004E ***/ union { byte Byte; } TMODHSTR; #define TMODH _TMOD.Overlap_STR.TMODHSTR.Byte /*** TMODL - TIM Counter Modulo Register; 0x0000004F ***/ union { byte Byte; } TMODLSTR; #define TMODL _TMOD.Overlap_STR.TMODLSTR.Byte } Overlap_STR; } TMODSTR; extern volatile TMODSTR _TMOD @0x0000004E; #define TMOD _TMOD.Word /*** SBSR - SIM Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte BW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SBSRSTR; extern volatile SBSRSTR _SBSR @0x0000FE00; #define SBSR _SBSR.Byte #define SBSR_BW _SBSR.Bits.BW #define SBSR_BW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte :1; byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_LVI _SRSR.Bits.LVI #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_PIN _SRSR.Bits.PIN #define SRSR_POR _SRSR.Bits.POR #define SRSR_LVI_MASK 2 #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_PIN_MASK 64 #define SRSR_POR_MASK 128 /*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } SBFCRSTR; extern volatile SBFCRSTR _SBFCR @0x0000FE03; #define SBFCR _SBFCR.Byte #define SBFCR_BCFE _SBFCR.Bits.BCFE #define SBFCR_BCFE_MASK 128 /*** FLCR1 - FLASH1 Control Register; 0x0000FE0B ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MARGIN :1; /* Margin Read Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte BLK0 :1; /* Block Erase Control Bit */ byte BLK1 :1; /* Block Erase Control Bit */ byte FDIV0 :1; /* Frequency Divide Control Bit */ byte FDIV1 :1; /* Frequency Divide Control Bit */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpBLK :2; byte grpFDIV :2; } MergedBits; } FLCR1STR; extern volatile FLCR1STR _FLCR1 @0x0000FE0B; #define FLCR1 _FLCR1.Byte #define FLCR1_PGM _FLCR1.Bits.PGM #define FLCR1_ERASE _FLCR1.Bits.ERASE #define FLCR1_MARGIN _FLCR1.Bits.MARGIN #define FLCR1_HVEN _FLCR1.Bits.HVEN #define FLCR1_BLK0 _FLCR1.Bits.BLK0 #define FLCR1_BLK1 _FLCR1.Bits.BLK1 #define FLCR1_FDIV0 _FLCR1.Bits.FDIV0 #define FLCR1_FDIV1 _FLCR1.Bits.FDIV1 #define FLCR1_BLK _FLCR1.MergedBits.grpBLK #define FLCR1_FDIV _FLCR1.MergedBits.grpFDIV #define FLCR1_PGM_MASK 1 #define FLCR1_ERASE_MASK 2 #define FLCR1_MARGIN_MASK 4 #define FLCR1_HVEN_MASK 8 #define FLCR1_BLK0_MASK 16 #define FLCR1_BLK1_MASK 32 #define FLCR1_FDIV0_MASK 64 #define FLCR1_FDIV1_MASK 128 #define FLCR1_BLK_MASK 48 #define FLCR1_BLK_BITNUM 4 #define FLCR1_FDIV_MASK 192 #define FLCR1_FDIV_BITNUM 6 /*** BRK - Break Address Register; 0x0000FE0C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address Register; 0x0000FE0C ***/ union { byte Byte; struct { byte BIT8 :1; /* Break Address Register Bit */ byte BIT9 :1; /* Break Address Register Bit */ byte BIT10 :1; /* Break Address Register Bit */ byte BIT11 :1; /* Break Address Register Bit */ byte BIT12 :1; /* Break Address Register Bit */ byte BIT13 :1; /* Break Address Register Bit */ byte BIT14 :1; /* Break Address Register Bit */ byte BIT15 :1; /* Break Address Register Bit */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_BIT8 _BRK.Overlap_STR.BRKHSTR.Bits.BIT8 #define BRKH_BIT9 _BRK.Overlap_STR.BRKHSTR.Bits.BIT9 #define BRKH_BIT10 _BRK.Overlap_STR.BRKHSTR.Bits.BIT10 #define BRKH_BIT11 _BRK.Overlap_STR.BRKHSTR.Bits.BIT11 #define BRKH_BIT12 _BRK.Overlap_STR.BRKHSTR.Bits.BIT12 #define BRKH_BIT13 _BRK.Overlap_STR.BRKHSTR.Bits.BIT13 #define BRKH_BIT14 _BRK.Overlap_STR.BRKHSTR.Bits.BIT14 #define BRKH_BIT15 _BRK.Overlap_STR.BRKHSTR.Bits.BIT15 #define BRKH_BIT8_MASK 1 #define BRKH_BIT9_MASK 2 #define BRKH_BIT10_MASK 4 #define BRKH_BIT11_MASK 8 #define BRKH_BIT12_MASK 16 #define BRKH_BIT13_MASK 32 #define BRKH_BIT14_MASK 64 #define BRKH_BIT15_MASK 128 /*** BRKL - Break Address Register; 0x0000FE0D ***/ union { byte Byte; struct { byte BIT0 :1; /* Break Address Register Bit */ byte BIT1 :1; /* Break Address Register Bit */ byte BIT2 :1; /* Break Address Register Bit */ byte BIT3 :1; /* Break Address Register Bit */ byte BIT4 :1; /* Break Address Register Bit */ byte BIT5 :1; /* Break Address Register Bit */ byte BIT6 :1; /* Break Address Register Bit */ byte BIT7 :1; /* Break Address Register Bit */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_BIT0 _BRK.Overlap_STR.BRKLSTR.Bits.BIT0 #define BRKL_BIT1 _BRK.Overlap_STR.BRKLSTR.Bits.BIT1 #define BRKL_BIT2 _BRK.Overlap_STR.BRKLSTR.Bits.BIT2 #define BRKL_BIT3 _BRK.Overlap_STR.BRKLSTR.Bits.BIT3 #define BRKL_BIT4 _BRK.Overlap_STR.BRKLSTR.Bits.BIT4 #define BRKL_BIT5 _BRK.Overlap_STR.BRKLSTR.Bits.BIT5 #define BRKL_BIT6 _BRK.Overlap_STR.BRKLSTR.Bits.BIT6 #define BRKL_BIT7 _BRK.Overlap_STR.BRKLSTR.Bits.BIT7 #define BRKL_BIT0_MASK 1 #define BRKL_BIT1_MASK 2 #define BRKL_BIT2_MASK 4 #define BRKL_BIT3_MASK 8 #define BRKL_BIT4_MASK 16 #define BRKL_BIT5_MASK 32 #define BRKL_BIT6_MASK 64 #define BRKL_BIT7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE0C; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0E; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** LVISR - LVI Status Register; 0x0000FE0F ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LVIOUT :1; /* LVI Output Bit */ } Bits; } LVISRSTR; extern volatile LVISRSTR _LVISR @0x0000FE0F; #define LVISR _LVISR.Byte #define LVISR_LVIOUT _LVISR.Bits.LVIOUT #define LVISR_LVIOUT_MASK 128 /*** FLCR2 - FLASH2 Control Register; 0x0000FE11 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MARGIN :1; /* Margin Read Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte BLK0 :1; /* Block Erase Control Bit */ byte BLK1 :1; /* Block Erase Control Bit */ byte FDIV0 :1; /* Frequency Divide Control Bit */ byte FDIV1 :1; /* Frequency Divide Control Bit */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpBLK :2; byte grpFDIV :2; } MergedBits; } FLCR2STR; extern volatile FLCR2STR _FLCR2 @0x0000FE11; #define FLCR2 _FLCR2.Byte #define FLCR2_PGM _FLCR2.Bits.PGM #define FLCR2_ERASE _FLCR2.Bits.ERASE #define FLCR2_MARGIN _FLCR2.Bits.MARGIN #define FLCR2_HVEN _FLCR2.Bits.HVEN #define FLCR2_BLK0 _FLCR2.Bits.BLK0 #define FLCR2_BLK1 _FLCR2.Bits.BLK1 #define FLCR2_FDIV0 _FLCR2.Bits.FDIV0 #define FLCR2_FDIV1 _FLCR2.Bits.FDIV1 #define FLCR2_BLK _FLCR2.MergedBits.grpBLK #define FLCR2_FDIV _FLCR2.MergedBits.grpFDIV #define FLCR2_PGM_MASK 1 #define FLCR2_ERASE_MASK 2 #define FLCR2_MARGIN_MASK 4 #define FLCR2_HVEN_MASK 8 #define FLCR2_BLK0_MASK 16 #define FLCR2_BLK1_MASK 32 #define FLCR2_FDIV0_MASK 64 #define FLCR2_FDIV1_MASK 128 #define FLCR2_BLK_MASK 48 #define FLCR2_BLK_BITNUM 4 #define FLCR2_FDIV_MASK 192 #define FLCR2_FDIV_BITNUM 6 /*** EENVR2 - EEPROM2 Nonvolatile Register; 0x0000FE18 ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM Block Protection Bit */ byte EEBP1 :1; /* EEPROM Block Protection Bit */ byte EEBP2 :1; /* EEPROM Block Protection Bit */ byte EEBP3 :1; /* EEPROM Block Protection Bit */ byte EEPRTCT :1; /* EEPROM Protect */ byte CON1 :1; /* MCU Configuration Bit */ byte CON2 :1; /* MCU Configuration Bit */ byte EERA :1; /* EEPROM Redundant Array */ } Bits; struct { byte grpEEBP :4; byte :1; byte grpCON_1 :2; byte grpEERx :1; } MergedBits; } EENVR2STR; /* Tip for register initialization in the user code: const byte EENVR2_INIT @0x0000FE18 = ; */ #define _EENVR2 (*(const EENVR2STR * __far)0x0000FE18) #define EENVR2 _EENVR2.Byte #define EENVR2_EEBP0 _EENVR2.Bits.EEBP0 #define EENVR2_EEBP1 _EENVR2.Bits.EEBP1 #define EENVR2_EEBP2 _EENVR2.Bits.EEBP2 #define EENVR2_EEBP3 _EENVR2.Bits.EEBP3 #define EENVR2_EEPRTCT _EENVR2.Bits.EEPRTCT #define EENVR2_CON1 _EENVR2.Bits.CON1 #define EENVR2_CON2 _EENVR2.Bits.CON2 #define EENVR2_EERA _EENVR2.Bits.EERA #define EENVR2_EEBP _EENVR2.MergedBits.grpEEBP #define EENVR2_CON_1 _EENVR2.MergedBits.grpCON_1 #define EENVR2_CON EENVR2_CON_1 #define EENVR2_EEBP0_MASK 1 #define EENVR2_EEBP1_MASK 2 #define EENVR2_EEBP2_MASK 4 #define EENVR2_EEBP3_MASK 8 #define EENVR2_EEPRTCT_MASK 16 #define EENVR2_CON1_MASK 32 #define EENVR2_CON2_MASK 64 #define EENVR2_EERA_MASK 128 #define EENVR2_EEBP_MASK 15 #define EENVR2_EEBP_BITNUM 0 #define EENVR2_CON_1_MASK 96 #define EENVR2_CON_1_BITNUM 5 /*** EECR2 - EEPROM2 Control Register; 0x0000FE19 ***/ typedef union { byte Byte; struct { byte EEPGM :1; /* EEPROM Program/Erase Enable */ byte :1; byte EELAT :1; /* EEPROM Latch Control */ byte EERAS0 :1; /* Erase Bit */ byte EERAS1 :1; /* Erase Bit */ byte EEOFF :1; /* EEPROM Power Down */ byte :1; byte EEBCLK :1; /* EEPROM Bus Clock Enable */ } Bits; struct { byte :1; byte :1; byte :1; byte grpEERAS :2; byte :1; byte :1; byte :1; } MergedBits; } EECR2STR; extern volatile EECR2STR _EECR2 @0x0000FE19; #define EECR2 _EECR2.Byte #define EECR2_EEPGM _EECR2.Bits.EEPGM #define EECR2_EELAT _EECR2.Bits.EELAT #define EECR2_EERAS0 _EECR2.Bits.EERAS0 #define EECR2_EERAS1 _EECR2.Bits.EERAS1 #define EECR2_EEOFF _EECR2.Bits.EEOFF #define EECR2_EEBCLK _EECR2.Bits.EEBCLK #define EECR2_EERAS _EECR2.MergedBits.grpEERAS #define EECR2_EEPGM_MASK 1 #define EECR2_EELAT_MASK 4 #define EECR2_EERAS0_MASK 8 #define EECR2_EERAS1_MASK 16 #define EECR2_EEOFF_MASK 32 #define EECR2_EEBCLK_MASK 128 #define EECR2_EERAS_MASK 24 #define EECR2_EERAS_BITNUM 3 /*** EEACR2 - EEPROM2 Array Control Register; 0x0000FE1B ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM Block Protection Bit */ byte EEBP1 :1; /* EEPROM Block Protection Bit */ byte EEBP2 :1; /* EEPROM Block Protection Bit */ byte EEBP3 :1; /* EEPROM Block Protection Bit */ byte EEPRTCT :1; /* EEPROM Protection */ byte CON1 :1; /* MCU Configuration Bit */ byte CON2 :1; /* MCU Configuration Bit */ byte EERA :1; /* EEPROM Redundant Array */ } Bits; struct { byte grpEEBP :4; byte :1; byte grpCON_1 :2; byte grpEERx :1; } MergedBits; } EEACR2STR; extern volatile EEACR2STR _EEACR2 @0x0000FE1B; #define EEACR2 _EEACR2.Byte #define EEACR2_EEBP0 _EEACR2.Bits.EEBP0 #define EEACR2_EEBP1 _EEACR2.Bits.EEBP1 #define EEACR2_EEBP2 _EEACR2.Bits.EEBP2 #define EEACR2_EEBP3 _EEACR2.Bits.EEBP3 #define EEACR2_EEPRTCT _EEACR2.Bits.EEPRTCT #define EEACR2_CON1 _EEACR2.Bits.CON1 #define EEACR2_CON2 _EEACR2.Bits.CON2 #define EEACR2_EERA _EEACR2.Bits.EERA #define EEACR2_EEBP _EEACR2.MergedBits.grpEEBP #define EEACR2_CON_1 _EEACR2.MergedBits.grpCON_1 #define EEACR2_CON EEACR2_CON_1 #define EEACR2_EEBP0_MASK 1 #define EEACR2_EEBP1_MASK 2 #define EEACR2_EEBP2_MASK 4 #define EEACR2_EEBP3_MASK 8 #define EEACR2_EEPRTCT_MASK 16 #define EEACR2_CON1_MASK 32 #define EEACR2_CON2_MASK 64 #define EEACR2_EERA_MASK 128 #define EEACR2_EEBP_MASK 15 #define EEACR2_EEBP_BITNUM 0 #define EEACR2_CON_1_MASK 96 #define EEACR2_CON_1_BITNUM 5 /*** EENVR1 - EEPROM1 Nonvolatile Register; 0x0000FE1C ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM Block Protection Bit */ byte EEBP1 :1; /* EEPROM Block Protection Bit */ byte EEBP2 :1; /* EEPROM Block Protection Bit */ byte EEBP3 :1; /* EEPROM Block Protection Bit */ byte EEPRTCT :1; /* EEPROM Protection */ byte CON1 :1; /* MCU Configuration Bit */ byte CON2 :1; /* MCU Configuration Bit */ byte EERA :1; /* EEPROM Redundant Array */ } Bits; struct { byte grpEEBP :4; byte :1; byte grpCON_1 :2; byte grpEERx :1; } MergedBits; } EENVR1STR; /* Tip for register initialization in the user code: const byte EENVR1_INIT @0x0000FE1C = ; */ #define _EENVR1 (*(const EENVR1STR * __far)0x0000FE1C) #define EENVR1 _EENVR1.Byte #define EENVR1_EEBP0 _EENVR1.Bits.EEBP0 #define EENVR1_EEBP1 _EENVR1.Bits.EEBP1 #define EENVR1_EEBP2 _EENVR1.Bits.EEBP2 #define EENVR1_EEBP3 _EENVR1.Bits.EEBP3 #define EENVR1_EEPRTCT _EENVR1.Bits.EEPRTCT #define EENVR1_CON1 _EENVR1.Bits.CON1 #define EENVR1_CON2 _EENVR1.Bits.CON2 #define EENVR1_EERA _EENVR1.Bits.EERA #define EENVR1_EEBP _EENVR1.MergedBits.grpEEBP #define EENVR1_CON_1 _EENVR1.MergedBits.grpCON_1 #define EENVR1_CON EENVR1_CON_1 #define EENVR1_EEBP0_MASK 1 #define EENVR1_EEBP1_MASK 2 #define EENVR1_EEBP2_MASK 4 #define EENVR1_EEBP3_MASK 8 #define EENVR1_EEPRTCT_MASK 16 #define EENVR1_CON1_MASK 32 #define EENVR1_CON2_MASK 64 #define EENVR1_EERA_MASK 128 #define EENVR1_EEBP_MASK 15 #define EENVR1_EEBP_BITNUM 0 #define EENVR1_CON_1_MASK 96 #define EENVR1_CON_1_BITNUM 5 /*** EECR1 - EEPROM1 Control Register; 0x0000FE1D ***/ typedef union { byte Byte; struct { byte EEPGM :1; /* EEPROM Program/Erase Enable */ byte :1; byte EELAT :1; /* EEPROM Latch Control */ byte EERAS0 :1; /* Erase Bit */ byte EERAS1 :1; /* Erase Bit */ byte EEOFF :1; /* EEPROM Power Down */ byte :1; byte EEBCLK :1; /* EEPROM Bus Clock Enable */ } Bits; struct { byte :1; byte :1; byte :1; byte grpEERAS :2; byte :1; byte :1; byte :1; } MergedBits; } EECR1STR; extern volatile EECR1STR _EECR1 @0x0000FE1D; #define EECR1 _EECR1.Byte #define EECR1_EEPGM _EECR1.Bits.EEPGM #define EECR1_EELAT _EECR1.Bits.EELAT #define EECR1_EERAS0 _EECR1.Bits.EERAS0 #define EECR1_EERAS1 _EECR1.Bits.EERAS1 #define EECR1_EEOFF _EECR1.Bits.EEOFF #define EECR1_EEBCLK _EECR1.Bits.EEBCLK #define EECR1_EERAS _EECR1.MergedBits.grpEERAS #define EECR1_EEPGM_MASK 1 #define EECR1_EELAT_MASK 4 #define EECR1_EERAS0_MASK 8 #define EECR1_EERAS1_MASK 16 #define EECR1_EEOFF_MASK 32 #define EECR1_EEBCLK_MASK 128 #define EECR1_EERAS_MASK 24 #define EECR1_EERAS_BITNUM 3 /*** EEACR1 - EEPROM1 Array Control Register; 0x0000FE1F ***/ typedef union { byte Byte; struct { byte EEBP0 :1; /* EEPROM Block Protection Bit */ byte EEBP1 :1; /* EEPROM Block Protection Bit */ byte EEBP2 :1; /* EEPROM Block Protection Bit */ byte EEBP3 :1; /* EEPROM Block Protection Bit */ byte EEPRTCT :1; /* EEPROM Protection */ byte CON1 :1; /* MCU Configuration Bit */ byte CON2 :1; /* MCU Configuration Bit */ byte EERA :1; /* EEPROM Redundant Array */ } Bits; struct { byte grpEEBP :4; byte :1; byte grpCON_1 :2; byte grpEERx :1; } MergedBits; } EEACR1STR; extern volatile EEACR1STR _EEACR1 @0x0000FE1F; #define EEACR1 _EEACR1.Byte #define EEACR1_EEBP0 _EEACR1.Bits.EEBP0 #define EEACR1_EEBP1 _EEACR1.Bits.EEBP1 #define EEACR1_EEBP2 _EEACR1.Bits.EEBP2 #define EEACR1_EEBP3 _EEACR1.Bits.EEBP3 #define EEACR1_EEPRTCT _EEACR1.Bits.EEPRTCT #define EEACR1_CON1 _EEACR1.Bits.CON1 #define EEACR1_CON2 _EEACR1.Bits.CON2 #define EEACR1_EERA _EEACR1.Bits.EERA #define EEACR1_EEBP _EEACR1.MergedBits.grpEEBP #define EEACR1_CON_1 _EEACR1.MergedBits.grpCON_1 #define EEACR1_CON EEACR1_CON_1 #define EEACR1_EEBP0_MASK 1 #define EEACR1_EEBP1_MASK 2 #define EEACR1_EEBP2_MASK 4 #define EEACR1_EEBP3_MASK 8 #define EEACR1_EEPRTCT_MASK 16 #define EEACR1_CON1_MASK 32 #define EEACR1_CON2_MASK 64 #define EEACR1_EERA_MASK 128 #define EEACR1_EEBP_MASK 15 #define EEACR1_EEBP_BITNUM 0 #define EEACR1_CON_1_MASK 96 #define EEACR1_CON_1_BITNUM 5 /*** FLBPR1 - FLASH1 Block Protect Register; 0x0000FF80 ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* Block Protect Register Bit 0 */ byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpBPR :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } FLBPR1STR; /* Tip for register initialization in the user code: const byte FLBPR1_INIT @0x0000FF80 = ; */ #define _FLBPR1 (*(const FLBPR1STR * __far)0x0000FF80) #define FLBPR1 _FLBPR1.Byte #define FLBPR1_BPR0 _FLBPR1.Bits.BPR0 #define FLBPR1_BPR1 _FLBPR1.Bits.BPR1 #define FLBPR1_BPR2 _FLBPR1.Bits.BPR2 #define FLBPR1_BPR3 _FLBPR1.Bits.BPR3 #define FLBPR1_BPR _FLBPR1.MergedBits.grpBPR #define FLBPR1_BPR0_MASK 1 #define FLBPR1_BPR1_MASK 2 #define FLBPR1_BPR2_MASK 4 #define FLBPR1_BPR3_MASK 8 #define FLBPR1_BPR_MASK 15 #define FLBPR1_BPR_BITNUM 0 /*** FLBPR2 - FLASH2 Block Protect Register; 0x0000FF81 ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* Block Protect Register Bit 0 */ byte BPR1 :1; /* Block Protect Register Bit 1 */ byte BPR2 :1; /* Block Protect Register Bit 2 */ byte BPR3 :1; /* Block Protect Register Bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpBPR :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } FLBPR2STR; /* Tip for register initialization in the user code: const byte FLBPR2_INIT @0x0000FF81 = ; */ #define _FLBPR2 (*(const FLBPR2STR * __far)0x0000FF81) #define FLBPR2 _FLBPR2.Byte #define FLBPR2_BPR0 _FLBPR2.Bits.BPR0 #define FLBPR2_BPR1 _FLBPR2.Bits.BPR1 #define FLBPR2_BPR2 _FLBPR2.Bits.BPR2 #define FLBPR2_BPR3 _FLBPR2.Bits.BPR3 #define FLBPR2_BPR _FLBPR2.MergedBits.grpBPR #define FLBPR2_BPR0_MASK 1 #define FLBPR2_BPR1_MASK 2 #define FLBPR2_BPR2_MASK 4 #define FLBPR2_BPR3_MASK 8 #define FLBPR2_BPR_MASK 15 #define FLBPR2_BPR_BITNUM 0 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 11:40:31 */ #define TACH_ARR This_symb_has_been_depreciated #endif