/* Based on CPU DB MC68HC908AP64_48, version 2.89.111 (RegistersPrg V2.30) */ /* ** ################################################################### ** Filename : mc68hc908ap32a.h ** Processor : MC68HC908AP32ACFA ** FileFormat: V2.30 ** DataSheet : MC68HC908AP64 Rev. 4 1/2007 / MC68HC908AP64A Rev. 3 10/2007 ** Compiler : CodeWarrior compiler ** Date/Time : 11.9.2009, 14:07 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - none ** ** File-Format-Revisions: ** - 14.11.2005, V2.00 : ** - Deprecated symbols added for backward compatibility (section at the end of this file) ** - 15.11.2005, V2.01 : ** - Changes have not affected this file (because they are related to another family) ** - 17.12.2005, V2.02 : ** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ** - 16.01.2006, V2.03 : ** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ** - 08.03.2006, V2.04 : ** - Support for bit(s) names duplicated with any register name in .h header files ** - 24.03.2006, V2.05 : ** - Changes have not affected this file (because they are related to another family) ** - 26.04.2006, V2.06 : ** - Absolute assembly supported (depreciated symbols are not defined) ** - 27.04.2006, V2.07 : ** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ** - 07.06.2006, V2.08 : ** - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ** - 03.07.2006, V2.09 : ** - Flash commands constants supported ** - 27.10.2006, V2.10 : ** - __RESET_WATCHDOG improved formating and re-definition ** - 23.11.2006, V2.11 : ** - Changes have not affected this file (because they are related to another family) ** - 22.01.2007, V2.12 : ** - Changes have not affected this file (because they are related to another family) ** - 01.03.2007, V2.13 : ** - Flash commands constants values converted to HEX format ** - 02.03.2007, V2.14 : ** - Interrupt vector numbers added into .H, see VectorNumber_* ** - 26.03.2007, V2.15 : ** - Changes have not affected this file (because they are related to another family) ** - 10.05.2007, V2.16 : ** - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ** - 05.06.2007, V2.17 : ** - Changes have not affected this file (because they are related to another family) ** - 19.07.2007, V2.18 : ** - Improved number of blanked lines inside register structures ** - 06.08.2007, V2.19 : ** - CPUDB revisions generated ahead of the file-format revisions. ** - 11.09.2007, V2.20 : ** - Added comment about initialization of unbonded pins. ** - 02.01.2008, V2.21 : ** - Changes have not affected this file (because they are related to another family) ** - 13.02.2008, V2.22 : ** - Changes have not affected this file (because they are related to another family) ** - 20.02.2008, V2.23 : ** - Changes have not affected this file (because they are related to another family) ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MC68HC908AP32A_H #define _MC68HC908AP32A_H /* Types definition */ typedef unsigned char byte; typedef unsigned int word; typedef unsigned long dword; typedef unsigned long dlong[2]; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() {asm sta COPCTL;} #endif #endif /* __RESET_WATCHDOG */ #define REG_BASE 0x0000 /* Base address for the I/O register block */ #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ /**************** interrupt vector numbers ****************/ #define VectorNumber_TBM 22 #define VectorNumber_IRSCITransmit 21 #define VectorNumber_IRSCIReceive 20 #define VectorNumber_IRSCIError 19 #define VectorNumber_SPITransmit 18 #define VectorNumber_SPIReceive 17 #define VectorNumber_ADC 16 #define VectorNumber_KBD 15 #define VectorNumber_SCITransmit 14 #define VectorNumber_SCIReceive 13 #define VectorNumber_SCIError 12 #define VectorNumber_MMIIC 11 #define VectorNumber_TIM2Ovr 10 #define VectorNumber_TIM2CH1 9 #define VectorNumber_TIM2CH0 8 #define VectorNumber_TIM1Ovr 7 #define VectorNumber_TIM1CH1 6 #define VectorNumber_TIM1CH0 5 #define VectorNumber_PLL 4 #define VectorNumber_IRQ2 3 #define VectorNumber_IRQ1 2 #define VectorNumber_SWI 1 #define VectorNumber_RESET 0 /**************** interrupt vector table ****************/ #define INT_TBM 0x0000FFD2 #define INT_IRSCITransmit 0x0000FFD4 #define INT_IRSCIReceive 0x0000FFD6 #define INT_IRSCIError 0x0000FFD8 #define INT_SPITransmit 0x0000FFDA #define INT_SPIReceive 0x0000FFDC #define INT_ADC 0x0000FFDE #define INT_KBD 0x0000FFE0 #define INT_SCITransmit 0x0000FFE2 #define INT_SCIReceive 0x0000FFE4 #define INT_SCIError 0x0000FFE6 #define INT_MMIIC 0x0000FFE8 #define INT_TIM2Ovr 0x0000FFEA #define INT_TIM2CH1 0x0000FFEC #define INT_TIM2CH0 0x0000FFEE #define INT_TIM1Ovr 0x0000FFF0 #define INT_TIM1CH1 0x0000FFF2 #define INT_TIM1CH0 0x0000FFF4 #define INT_PLL 0x0000FFF6 #define INT_IRQ2 0x0000FFF8 #define INT_IRQ1 0x0000FFFA #define INT_SWI 0x0000FFFC #define INT_RESET 0x0000FFFE /**************** registers I/O map ****************/ /*** PTA - Port A Data Register; 0x00000000 ***/ typedef union { byte Byte; struct { byte PTA0 :1; /* Port A Data Bit 0 */ byte PTA1 :1; /* Port A Data Bit 1 */ byte PTA2 :1; /* Port A Data Bit 2 */ byte PTA3 :1; /* Port A Data Bit 3 */ byte PTA4 :1; /* Port A Data Bit 4 */ byte PTA5 :1; /* Port A Data Bit 5 */ byte PTA6 :1; /* Port A Data Bit 6 */ byte PTA7 :1; /* Port A Data Bit 7 */ } Bits; } PTASTR; extern volatile PTASTR _PTA @0x00000000; #define PTA _PTA.Byte #define PTA_PTA0 _PTA.Bits.PTA0 #define PTA_PTA1 _PTA.Bits.PTA1 #define PTA_PTA2 _PTA.Bits.PTA2 #define PTA_PTA3 _PTA.Bits.PTA3 #define PTA_PTA4 _PTA.Bits.PTA4 #define PTA_PTA5 _PTA.Bits.PTA5 #define PTA_PTA6 _PTA.Bits.PTA6 #define PTA_PTA7 _PTA.Bits.PTA7 #define PTA_PTA0_MASK 1 #define PTA_PTA1_MASK 2 #define PTA_PTA2_MASK 4 #define PTA_PTA3_MASK 8 #define PTA_PTA4_MASK 16 #define PTA_PTA5_MASK 32 #define PTA_PTA6_MASK 64 #define PTA_PTA7_MASK 128 /*** PTB - Port B Data Register; 0x00000001 ***/ typedef union { byte Byte; struct { byte PTB0 :1; /* Port B Data Bit 0 */ byte PTB1 :1; /* Port B Data Bit 1 */ byte PTB2 :1; /* Port B Data Bit 2 */ byte PTB3 :1; /* Port B Data Bit 3 */ byte PTB4 :1; /* Port B Data Bit 4 */ byte PTB5 :1; /* Port B Data Bit 5 */ byte PTB6 :1; /* Port B Data Bit 6 */ byte PTB7 :1; /* Port B Data Bit 7 */ } Bits; } PTBSTR; extern volatile PTBSTR _PTB @0x00000001; #define PTB _PTB.Byte #define PTB_PTB0 _PTB.Bits.PTB0 #define PTB_PTB1 _PTB.Bits.PTB1 #define PTB_PTB2 _PTB.Bits.PTB2 #define PTB_PTB3 _PTB.Bits.PTB3 #define PTB_PTB4 _PTB.Bits.PTB4 #define PTB_PTB5 _PTB.Bits.PTB5 #define PTB_PTB6 _PTB.Bits.PTB6 #define PTB_PTB7 _PTB.Bits.PTB7 #define PTB_PTB0_MASK 1 #define PTB_PTB1_MASK 2 #define PTB_PTB2_MASK 4 #define PTB_PTB3_MASK 8 #define PTB_PTB4_MASK 16 #define PTB_PTB5_MASK 32 #define PTB_PTB6_MASK 64 #define PTB_PTB7_MASK 128 /*** PTC - Port C Data Register; 0x00000002 ***/ typedef union { byte Byte; struct { byte PTC0 :1; /* Port C Data Bit 0 */ byte PTC1 :1; /* Port C Data Bit 1 */ byte PTC2 :1; /* Port C Data Bit 2 */ byte PTC3 :1; /* Port C Data Bit 3 */ byte PTC4 :1; /* Port C Data Bit 4 */ byte PTC5 :1; /* Port C Data Bit 5 */ byte PTC6 :1; /* Port C Data Bit 6 */ byte PTC7 :1; /* Port C Data Bit 7 */ } Bits; } PTCSTR; extern volatile PTCSTR _PTC @0x00000002; #define PTC _PTC.Byte #define PTC_PTC0 _PTC.Bits.PTC0 #define PTC_PTC1 _PTC.Bits.PTC1 #define PTC_PTC2 _PTC.Bits.PTC2 #define PTC_PTC3 _PTC.Bits.PTC3 #define PTC_PTC4 _PTC.Bits.PTC4 #define PTC_PTC5 _PTC.Bits.PTC5 #define PTC_PTC6 _PTC.Bits.PTC6 #define PTC_PTC7 _PTC.Bits.PTC7 #define PTC_PTC0_MASK 1 #define PTC_PTC1_MASK 2 #define PTC_PTC2_MASK 4 #define PTC_PTC3_MASK 8 #define PTC_PTC4_MASK 16 #define PTC_PTC5_MASK 32 #define PTC_PTC6_MASK 64 #define PTC_PTC7_MASK 128 /*** PTD - Port D Data Register; 0x00000003 ***/ typedef union { byte Byte; struct { byte PTD0 :1; /* Port D Data Bit 0 */ byte PTD1 :1; /* Port D Data Bit 1 */ byte PTD2 :1; /* Port D Data Bit 2 */ byte PTD3 :1; /* Port D Data Bit 3 */ byte PTD4 :1; /* Port D Data Bit 4 */ byte PTD5 :1; /* Port D Data Bit 5 */ byte PTD6 :1; /* Port D Data Bit 6 */ byte PTD7 :1; /* Port D Data Bit 7 */ } Bits; } PTDSTR; extern volatile PTDSTR _PTD @0x00000003; #define PTD _PTD.Byte #define PTD_PTD0 _PTD.Bits.PTD0 #define PTD_PTD1 _PTD.Bits.PTD1 #define PTD_PTD2 _PTD.Bits.PTD2 #define PTD_PTD3 _PTD.Bits.PTD3 #define PTD_PTD4 _PTD.Bits.PTD4 #define PTD_PTD5 _PTD.Bits.PTD5 #define PTD_PTD6 _PTD.Bits.PTD6 #define PTD_PTD7 _PTD.Bits.PTD7 #define PTD_PTD0_MASK 1 #define PTD_PTD1_MASK 2 #define PTD_PTD2_MASK 4 #define PTD_PTD3_MASK 8 #define PTD_PTD4_MASK 16 #define PTD_PTD5_MASK 32 #define PTD_PTD6_MASK 64 #define PTD_PTD7_MASK 128 /*** DDRA - Data Direction Register A; 0x00000004 ***/ typedef union { byte Byte; struct { byte DDRA0 :1; /* Data Direction Register A Bit 0 */ byte DDRA1 :1; /* Data Direction Register A Bit 1 */ byte DDRA2 :1; /* Data Direction Register A Bit 2 */ byte DDRA3 :1; /* Data Direction Register A Bit 3 */ byte DDRA4 :1; /* Data Direction Register A Bit 4 */ byte DDRA5 :1; /* Data Direction Register A Bit 5 */ byte DDRA6 :1; /* Data Direction Register A Bit 6 */ byte DDRA7 :1; /* Data Direction Register A Bit 7 */ } Bits; } DDRASTR; extern volatile DDRASTR _DDRA @0x00000004; #define DDRA _DDRA.Byte #define DDRA_DDRA0 _DDRA.Bits.DDRA0 #define DDRA_DDRA1 _DDRA.Bits.DDRA1 #define DDRA_DDRA2 _DDRA.Bits.DDRA2 #define DDRA_DDRA3 _DDRA.Bits.DDRA3 #define DDRA_DDRA4 _DDRA.Bits.DDRA4 #define DDRA_DDRA5 _DDRA.Bits.DDRA5 #define DDRA_DDRA6 _DDRA.Bits.DDRA6 #define DDRA_DDRA7 _DDRA.Bits.DDRA7 #define DDRA_DDRA0_MASK 1 #define DDRA_DDRA1_MASK 2 #define DDRA_DDRA2_MASK 4 #define DDRA_DDRA3_MASK 8 #define DDRA_DDRA4_MASK 16 #define DDRA_DDRA5_MASK 32 #define DDRA_DDRA6_MASK 64 #define DDRA_DDRA7_MASK 128 /*** DDRB - Data Direction Register B; 0x00000005 ***/ typedef union { byte Byte; struct { byte DDRB0 :1; /* Data Direction Register B Bit 0 */ byte DDRB1 :1; /* Data Direction Register B Bit 1 */ byte DDRB2 :1; /* Data Direction Register B Bit 2 */ byte DDRB3 :1; /* Data Direction Register B Bit 3 */ byte DDRB4 :1; /* Data Direction Register B Bit 4 */ byte DDRB5 :1; /* Data Direction Register B Bit 5 */ byte DDRB6 :1; /* Data Direction Register B Bit 6 */ byte DDRB7 :1; /* Data Direction Register B Bit 7 */ } Bits; } DDRBSTR; extern volatile DDRBSTR _DDRB @0x00000005; #define DDRB _DDRB.Byte #define DDRB_DDRB0 _DDRB.Bits.DDRB0 #define DDRB_DDRB1 _DDRB.Bits.DDRB1 #define DDRB_DDRB2 _DDRB.Bits.DDRB2 #define DDRB_DDRB3 _DDRB.Bits.DDRB3 #define DDRB_DDRB4 _DDRB.Bits.DDRB4 #define DDRB_DDRB5 _DDRB.Bits.DDRB5 #define DDRB_DDRB6 _DDRB.Bits.DDRB6 #define DDRB_DDRB7 _DDRB.Bits.DDRB7 #define DDRB_DDRB0_MASK 1 #define DDRB_DDRB1_MASK 2 #define DDRB_DDRB2_MASK 4 #define DDRB_DDRB3_MASK 8 #define DDRB_DDRB4_MASK 16 #define DDRB_DDRB5_MASK 32 #define DDRB_DDRB6_MASK 64 #define DDRB_DDRB7_MASK 128 /*** DDRC - Data Direction Register C; 0x00000006 ***/ typedef union { byte Byte; struct { byte DDRC0 :1; /* Data Direction Register C Bit 0 */ byte DDRC1 :1; /* Data Direction Register C Bit 1 */ byte DDRC2 :1; /* Data Direction Register C Bit 2 */ byte DDRC3 :1; /* Data Direction Register C Bit 3 */ byte DDRC4 :1; /* Data Direction Register C Bit 4 */ byte DDRC5 :1; /* Data Direction Register C Bit 5 */ byte DDRC6 :1; /* Data Direction Register C Bit 6 */ byte DDRC7 :1; /* Data Direction Register C Bit 7 */ } Bits; } DDRCSTR; extern volatile DDRCSTR _DDRC @0x00000006; #define DDRC _DDRC.Byte #define DDRC_DDRC0 _DDRC.Bits.DDRC0 #define DDRC_DDRC1 _DDRC.Bits.DDRC1 #define DDRC_DDRC2 _DDRC.Bits.DDRC2 #define DDRC_DDRC3 _DDRC.Bits.DDRC3 #define DDRC_DDRC4 _DDRC.Bits.DDRC4 #define DDRC_DDRC5 _DDRC.Bits.DDRC5 #define DDRC_DDRC6 _DDRC.Bits.DDRC6 #define DDRC_DDRC7 _DDRC.Bits.DDRC7 #define DDRC_DDRC0_MASK 1 #define DDRC_DDRC1_MASK 2 #define DDRC_DDRC2_MASK 4 #define DDRC_DDRC3_MASK 8 #define DDRC_DDRC4_MASK 16 #define DDRC_DDRC5_MASK 32 #define DDRC_DDRC6_MASK 64 #define DDRC_DDRC7_MASK 128 /*** DDRD - Data Direction Register D; 0x00000007 ***/ typedef union { byte Byte; struct { byte DDRD0 :1; /* Data Direction Register D Bit 0 */ byte DDRD1 :1; /* Data Direction Register D Bit 1 */ byte DDRD2 :1; /* Data Direction Register D Bit 2 */ byte DDRD3 :1; /* Data Direction Register D Bit 3 */ byte DDRD4 :1; /* Data Direction Register D Bit 4 */ byte DDRD5 :1; /* Data Direction Register D Bit 5 */ byte DDRD6 :1; /* Data Direction Register D Bit 6 */ byte DDRD7 :1; /* Data Direction Register D Bit 7 */ } Bits; } DDRDSTR; extern volatile DDRDSTR _DDRD @0x00000007; #define DDRD _DDRD.Byte #define DDRD_DDRD0 _DDRD.Bits.DDRD0 #define DDRD_DDRD1 _DDRD.Bits.DDRD1 #define DDRD_DDRD2 _DDRD.Bits.DDRD2 #define DDRD_DDRD3 _DDRD.Bits.DDRD3 #define DDRD_DDRD4 _DDRD.Bits.DDRD4 #define DDRD_DDRD5 _DDRD.Bits.DDRD5 #define DDRD_DDRD6 _DDRD.Bits.DDRD6 #define DDRD_DDRD7 _DDRD.Bits.DDRD7 #define DDRD_DDRD0_MASK 1 #define DDRD_DDRD1_MASK 2 #define DDRD_DDRD2_MASK 4 #define DDRD_DDRD3_MASK 8 #define DDRD_DDRD4_MASK 16 #define DDRD_DDRD5_MASK 32 #define DDRD_DDRD6_MASK 64 #define DDRD_DDRD7_MASK 128 /*** LEDA - Port-A LED Control; 0x0000000C ***/ typedef union { byte Byte; struct { byte LEDA0 :1; /* Port A LED Drive Enable Bit 0 */ byte LEDA1 :1; /* Port A LED Drive Enable Bit 1 */ byte LEDA2 :1; /* Port A LED Drive Enable Bit 2 */ byte LEDA3 :1; /* Port A LED Drive Enable Bit 3 */ byte LEDA4 :1; /* Port A LED Drive Enable Bit 4 */ byte LEDA5 :1; /* Port A LED Drive Enable Bit 5 */ byte LEDA6 :1; /* Port A LED Drive Enable Bit 6 */ byte LEDA7 :1; /* Port A LED Drive Enable Bit 7 */ } Bits; } LEDASTR; extern volatile LEDASTR _LEDA @0x0000000C; #define LEDA _LEDA.Byte #define LEDA_LEDA0 _LEDA.Bits.LEDA0 #define LEDA_LEDA1 _LEDA.Bits.LEDA1 #define LEDA_LEDA2 _LEDA.Bits.LEDA2 #define LEDA_LEDA3 _LEDA.Bits.LEDA3 #define LEDA_LEDA4 _LEDA.Bits.LEDA4 #define LEDA_LEDA5 _LEDA.Bits.LEDA5 #define LEDA_LEDA6 _LEDA.Bits.LEDA6 #define LEDA_LEDA7 _LEDA.Bits.LEDA7 #define LEDA_LEDA0_MASK 1 #define LEDA_LEDA1_MASK 2 #define LEDA_LEDA2_MASK 4 #define LEDA_LEDA3_MASK 8 #define LEDA_LEDA4_MASK 16 #define LEDA_LEDA5_MASK 32 #define LEDA_LEDA6_MASK 64 #define LEDA_LEDA7_MASK 128 /*** SPCR - SPI Control Register; 0x00000010 ***/ typedef union { byte Byte; struct { byte SPTIE :1; /* SPI Transmit Interrupt Enable Bit */ byte SPE :1; /* SPI Enable Bit */ byte SPWOM :1; /* SPI Wired-OR Mode Bit */ byte CPHA :1; /* Clock Phase Bit */ byte CPOL :1; /* Clock Polarity Bit */ byte SPMSTR :1; /* SPI Master Bit */ byte :1; byte SPRIE :1; /* SPI Receiver Interrupt Enable Bit */ } Bits; } SPCRSTR; extern volatile SPCRSTR _SPCR @0x00000010; #define SPCR _SPCR.Byte #define SPCR_SPTIE _SPCR.Bits.SPTIE #define SPCR_SPE _SPCR.Bits.SPE #define SPCR_SPWOM _SPCR.Bits.SPWOM #define SPCR_CPHA _SPCR.Bits.CPHA #define SPCR_CPOL _SPCR.Bits.CPOL #define SPCR_SPMSTR _SPCR.Bits.SPMSTR #define SPCR_SPRIE _SPCR.Bits.SPRIE #define SPCR_SPTIE_MASK 1 #define SPCR_SPE_MASK 2 #define SPCR_SPWOM_MASK 4 #define SPCR_CPHA_MASK 8 #define SPCR_CPOL_MASK 16 #define SPCR_SPMSTR_MASK 32 #define SPCR_SPRIE_MASK 128 /*** SPSCR - SPI Status and Control Register; 0x00000011 ***/ typedef union { byte Byte; struct { byte SPR0 :1; /* SPI Baud Rate Select Bit 0 */ byte SPR1 :1; /* SPI Baud Rate Select Bit 1 */ byte MODFEN :1; /* Mode Fault Enable Bit */ byte SPTE :1; /* SPI Transmitter Empty Bit */ byte MODF :1; /* Mode Fault Bit */ byte OVRF :1; /* Overflow Bit */ byte ERRIE :1; /* Error Interrupt Enable Bit */ byte SPRF :1; /* SPI Receiver Full Bit */ } Bits; struct { byte grpSPR :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SPSCRSTR; extern volatile SPSCRSTR _SPSCR @0x00000011; #define SPSCR _SPSCR.Byte #define SPSCR_SPR0 _SPSCR.Bits.SPR0 #define SPSCR_SPR1 _SPSCR.Bits.SPR1 #define SPSCR_MODFEN _SPSCR.Bits.MODFEN #define SPSCR_SPTE _SPSCR.Bits.SPTE #define SPSCR_MODF _SPSCR.Bits.MODF #define SPSCR_OVRF _SPSCR.Bits.OVRF #define SPSCR_ERRIE _SPSCR.Bits.ERRIE #define SPSCR_SPRF _SPSCR.Bits.SPRF #define SPSCR_SPR _SPSCR.MergedBits.grpSPR #define SPSCR_SPR0_MASK 1 #define SPSCR_SPR1_MASK 2 #define SPSCR_MODFEN_MASK 4 #define SPSCR_SPTE_MASK 8 #define SPSCR_MODF_MASK 16 #define SPSCR_OVRF_MASK 32 #define SPSCR_ERRIE_MASK 64 #define SPSCR_SPRF_MASK 128 #define SPSCR_SPR_MASK 3 #define SPSCR_SPR_BITNUM 0 /*** SPDR - SPI Data Register; 0x00000012 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SPDRSTR; extern volatile SPDRSTR _SPDR @0x00000012; #define SPDR _SPDR.Byte #define SPDR_R0_T0 _SPDR.Bits.R0_T0 #define SPDR_R1_T1 _SPDR.Bits.R1_T1 #define SPDR_R2_T2 _SPDR.Bits.R2_T2 #define SPDR_R3_T3 _SPDR.Bits.R3_T3 #define SPDR_R4_T4 _SPDR.Bits.R4_T4 #define SPDR_R5_T5 _SPDR.Bits.R5_T5 #define SPDR_R6_T6 _SPDR.Bits.R6_T6 #define SPDR_R7_T7 _SPDR.Bits.R7_T7 #define SPDR_R0_T0_MASK 1 #define SPDR_R1_T1_MASK 2 #define SPDR_R2_T2_MASK 4 #define SPDR_R3_T3_MASK 8 #define SPDR_R4_T4_MASK 16 #define SPDR_R5_T5_MASK 32 #define SPDR_R6_T6_MASK 64 #define SPDR_R7_T7_MASK 128 /*** SCC1 - SCI Control Register 1; 0x00000013 ***/ typedef union { byte Byte; struct { byte PTY :1; /* Parity Bit */ byte PEN :1; /* Parity Enable Bit */ byte ILTY :1; /* Idle Line Type Bit */ byte WAKE :1; /* Wakeup Condition Bit */ byte M :1; /* Mode (Character Length) Bit */ byte TXINV :1; /* Transmit Inversion Bit */ byte ENSCI :1; /* Enable SCI Bit */ byte LOOPS :1; /* Loop Mode Select Bit */ } Bits; } SCC1STR; extern volatile SCC1STR _SCC1 @0x00000013; #define SCC1 _SCC1.Byte #define SCC1_PTY _SCC1.Bits.PTY #define SCC1_PEN _SCC1.Bits.PEN #define SCC1_ILTY _SCC1.Bits.ILTY #define SCC1_WAKE _SCC1.Bits.WAKE #define SCC1_M _SCC1.Bits.M #define SCC1_TXINV _SCC1.Bits.TXINV #define SCC1_ENSCI _SCC1.Bits.ENSCI #define SCC1_LOOPS _SCC1.Bits.LOOPS #define SCC1_PTY_MASK 1 #define SCC1_PEN_MASK 2 #define SCC1_ILTY_MASK 4 #define SCC1_WAKE_MASK 8 #define SCC1_M_MASK 16 #define SCC1_TXINV_MASK 32 #define SCC1_ENSCI_MASK 64 #define SCC1_LOOPS_MASK 128 /*** SCC2 - SCI Control Register 2; 0x00000014 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break Bit */ byte RWU :1; /* Receiver Wakeup Bit */ byte RE :1; /* Receiver Enable Bit */ byte TE :1; /* Transmitter Enable Bit */ byte ILIE :1; /* Idle Line Interrupt Enable Bit */ byte SCRIE :1; /* SCI Receive Interrupt Enable Bit */ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ byte SCTIE :1; /* SCI Transmit Interrupt Enable Bit */ } Bits; } SCC2STR; extern volatile SCC2STR _SCC2 @0x00000014; #define SCC2 _SCC2.Byte #define SCC2_SBK _SCC2.Bits.SBK #define SCC2_RWU _SCC2.Bits.RWU #define SCC2_RE _SCC2.Bits.RE #define SCC2_TE _SCC2.Bits.TE #define SCC2_ILIE _SCC2.Bits.ILIE #define SCC2_SCRIE _SCC2.Bits.SCRIE #define SCC2_TCIE _SCC2.Bits.TCIE #define SCC2_SCTIE _SCC2.Bits.SCTIE #define SCC2_SBK_MASK 1 #define SCC2_RWU_MASK 2 #define SCC2_RE_MASK 4 #define SCC2_TE_MASK 8 #define SCC2_ILIE_MASK 16 #define SCC2_SCRIE_MASK 32 #define SCC2_TCIE_MASK 64 #define SCC2_SCTIE_MASK 128 /*** SCC3 - SCI Control Register 3; 0x00000015 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Receiver Parity Error Interrupt Enable Bit */ byte FEIE :1; /* Receiver Framing Error Interrupt Enable Bit */ byte NEIE :1; /* Receiver Noise Error Interrupt Enable Bit */ byte ORIE :1; /* Receiver Overrun Interrupt Enable Bit */ byte :1; byte :1; byte T8 :1; /* Transmitted Bit 8 */ byte R8 :1; /* Received Bit 8 */ } Bits; } SCC3STR; extern volatile SCC3STR _SCC3 @0x00000015; #define SCC3 _SCC3.Byte #define SCC3_PEIE _SCC3.Bits.PEIE #define SCC3_FEIE _SCC3.Bits.FEIE #define SCC3_NEIE _SCC3.Bits.NEIE #define SCC3_ORIE _SCC3.Bits.ORIE #define SCC3_T8 _SCC3.Bits.T8 #define SCC3_R8 _SCC3.Bits.R8 #define SCC3_PEIE_MASK 1 #define SCC3_FEIE_MASK 2 #define SCC3_NEIE_MASK 4 #define SCC3_ORIE_MASK 8 #define SCC3_T8_MASK 64 #define SCC3_R8_MASK 128 /*** SCS1 - SCI Status Register 1; 0x00000016 ***/ typedef union { byte Byte; struct { byte PE :1; /* Receiver Parity Error Bit */ byte FE :1; /* Receiver Framing Error Bit */ byte NF :1; /* Receiver Noise Flag Bit */ byte OR :1; /* Receiver Overrun Bit */ byte IDLE :1; /* Receiver Idle Bit */ byte SCRF :1; /* SCI Receiver Full Bit */ byte TC :1; /* Transmission Complete Bit */ byte SCTE :1; /* SCI Transmitter Empty Bit */ } Bits; } SCS1STR; extern volatile SCS1STR _SCS1 @0x00000016; #define SCS1 _SCS1.Byte #define SCS1_PE _SCS1.Bits.PE #define SCS1_FE _SCS1.Bits.FE #define SCS1_NF _SCS1.Bits.NF #define SCS1_OR _SCS1.Bits.OR #define SCS1_IDLE _SCS1.Bits.IDLE #define SCS1_SCRF _SCS1.Bits.SCRF #define SCS1_TC _SCS1.Bits.TC #define SCS1_SCTE _SCS1.Bits.SCTE #define SCS1_PE_MASK 1 #define SCS1_FE_MASK 2 #define SCS1_NF_MASK 4 #define SCS1_OR_MASK 8 #define SCS1_IDLE_MASK 16 #define SCS1_SCRF_MASK 32 #define SCS1_TC_MASK 64 #define SCS1_SCTE_MASK 128 /*** SCS2 - SCI Status Register 2; 0x00000017 ***/ typedef union { byte Byte; struct { byte RPF :1; /* Reception in Progress Flag Bit */ byte BKF :1; /* Break Flag Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SCS2STR; extern volatile SCS2STR _SCS2 @0x00000017; #define SCS2 _SCS2.Byte #define SCS2_RPF _SCS2.Bits.RPF #define SCS2_BKF _SCS2.Bits.BKF #define SCS2_RPF_MASK 1 #define SCS2_BKF_MASK 2 /*** SCDR - SCI Data Register; 0x00000018 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCDRSTR; extern volatile SCDRSTR _SCDR @0x00000018; #define SCDR _SCDR.Byte #define SCDR_R0_T0 _SCDR.Bits.R0_T0 #define SCDR_R1_T1 _SCDR.Bits.R1_T1 #define SCDR_R2_T2 _SCDR.Bits.R2_T2 #define SCDR_R3_T3 _SCDR.Bits.R3_T3 #define SCDR_R4_T4 _SCDR.Bits.R4_T4 #define SCDR_R5_T5 _SCDR.Bits.R5_T5 #define SCDR_R6_T6 _SCDR.Bits.R6_T6 #define SCDR_R7_T7 _SCDR.Bits.R7_T7 #define SCDR_R0_T0_MASK 1 #define SCDR_R1_T1_MASK 2 #define SCDR_R2_T2_MASK 4 #define SCDR_R3_T3_MASK 8 #define SCDR_R4_T4_MASK 16 #define SCDR_R5_T5_MASK 32 #define SCDR_R6_T6_MASK 64 #define SCDR_R7_T7_MASK 128 /*** SCBR - SCI Baud Rate Register; 0x00000019 ***/ typedef union { byte Byte; struct { byte SCR0 :1; /* SCI Baud Rate Select Bit 0 */ byte SCR1 :1; /* SCI Baud Rate Select Bit 1 */ byte SCR2 :1; /* SCI Baud Rate Select Bit 2 */ byte :1; byte SCP0 :1; /* SCI Baud Rate Prescaler Bit 0 */ byte SCP1 :1; /* SCI Baud Rate Prescaler Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpSCR :3; byte :1; byte grpSCP :2; byte :1; byte :1; } MergedBits; } SCBRSTR; extern volatile SCBRSTR _SCBR @0x00000019; #define SCBR _SCBR.Byte #define SCBR_SCR0 _SCBR.Bits.SCR0 #define SCBR_SCR1 _SCBR.Bits.SCR1 #define SCBR_SCR2 _SCBR.Bits.SCR2 #define SCBR_SCP0 _SCBR.Bits.SCP0 #define SCBR_SCP1 _SCBR.Bits.SCP1 #define SCBR_SCR _SCBR.MergedBits.grpSCR #define SCBR_SCP _SCBR.MergedBits.grpSCP #define SCBR_SCR0_MASK 1 #define SCBR_SCR1_MASK 2 #define SCBR_SCR2_MASK 4 #define SCBR_SCP0_MASK 16 #define SCBR_SCP1_MASK 32 #define SCBR_SCR_MASK 7 #define SCBR_SCR_BITNUM 0 #define SCBR_SCP_MASK 48 #define SCBR_SCP_BITNUM 4 /*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***/ typedef union { byte Byte; struct { byte MODE :1; /* Keyboard Triggering Sensitivity Bit */ byte IMASK :1; /* Keyboard Interrupt Mask Bit */ byte ACK :1; /* Keyboard Acknowledge Bit */ byte KEYF :1; /* Keyboard Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBSCRSTR; extern volatile KBSCRSTR _KBSCR @0x0000001A; #define KBSCR _KBSCR.Byte #define KBSCR_MODE _KBSCR.Bits.MODE #define KBSCR_IMASK _KBSCR.Bits.IMASK #define KBSCR_ACK _KBSCR.Bits.ACK #define KBSCR_KEYF _KBSCR.Bits.KEYF #define KBSCR_MODE_MASK 1 #define KBSCR_IMASK_MASK 2 #define KBSCR_ACK_MASK 4 #define KBSCR_KEYF_MASK 8 /*** KBIER - Keyobard Interrupt Enable Register; 0x0000001B ***/ typedef union { byte Byte; struct { byte KBIE0 :1; /* Keyboard Interrut Enable Bit 0 */ byte KBIE1 :1; /* Keyboard Interrut Enable Bit 1 */ byte KBIE2 :1; /* Keyboard Interrut Enable Bit 2 */ byte KBIE3 :1; /* Keyboard Interrut Enable Bit 3 */ byte KBIE4 :1; /* Keyboard Interrut Enable Bit 4 */ byte KBIE5 :1; /* Keyboard Interrut Enable Bit 5 */ byte KBIE6 :1; /* Keyboard Interrut Enable Bit 6 */ byte KBIE7 :1; /* Keyboard Interrut Enable Bit 7 */ } Bits; } KBIERSTR; extern volatile KBIERSTR _KBIER @0x0000001B; #define KBIER _KBIER.Byte #define KBIER_KBIE0 _KBIER.Bits.KBIE0 #define KBIER_KBIE1 _KBIER.Bits.KBIE1 #define KBIER_KBIE2 _KBIER.Bits.KBIE2 #define KBIER_KBIE3 _KBIER.Bits.KBIE3 #define KBIER_KBIE4 _KBIER.Bits.KBIE4 #define KBIER_KBIE5 _KBIER.Bits.KBIE5 #define KBIER_KBIE6 _KBIER.Bits.KBIE6 #define KBIER_KBIE7 _KBIER.Bits.KBIE7 #define KBIER_KBIE0_MASK 1 #define KBIER_KBIE1_MASK 2 #define KBIER_KBIE2_MASK 4 #define KBIER_KBIE3_MASK 8 #define KBIER_KBIE4_MASK 16 #define KBIER_KBIE5_MASK 32 #define KBIER_KBIE6_MASK 64 #define KBIER_KBIE7_MASK 128 /*** INTSCR2 - IRQ2 Status and Control Register; 0x0000001C ***/ typedef union { byte Byte; struct { byte MODE2 :1; /* IRQ2 Edge/Level Select Bit */ byte IMASK2 :1; /* IRQ2 Interrupt Mask Bit */ byte ACK2 :1; /* IRQ2 Interrupt Request Acknowledge Bit */ byte IRQ2F :1; /* IRQ2 Flag Bit */ byte :1; byte :1; byte PUC0ENB :1; /* IRQ2 Pin Pullup Enable Bit */ byte :1; } Bits; } INTSCR2STR; extern volatile INTSCR2STR _INTSCR2 @0x0000001C; #define INTSCR2 _INTSCR2.Byte #define INTSCR2_MODE2 _INTSCR2.Bits.MODE2 #define INTSCR2_IMASK2 _INTSCR2.Bits.IMASK2 #define INTSCR2_ACK2 _INTSCR2.Bits.ACK2 #define INTSCR2_IRQ2F _INTSCR2.Bits.IRQ2F #define INTSCR2_PUC0ENB _INTSCR2.Bits.PUC0ENB #define INTSCR2_MODE2_MASK 1 #define INTSCR2_IMASK2_MASK 2 #define INTSCR2_ACK2_MASK 4 #define INTSCR2_IRQ2F_MASK 8 #define INTSCR2_PUC0ENB_MASK 64 /*** CONFIG2 - Configuration Register 2; 0x0000001D ***/ typedef union { byte Byte; struct { byte SCIBDSRC :1; /* SCI Baud Rate Clock Source Bit */ byte :1; byte :1; byte OSCCLK0 :1; /* Oscillator Output Control Bit 0 */ byte OSCCLK1 :1; /* Oscillator Output Control Bit 1 */ byte STOP_XCLKEN :1; /* Crystal Oscillator Stop Mode Enable */ byte STOP_RCLKEN :1; /* RC Oscillator Stop Mode Enable */ byte STOP_ICLKDIS :1; /* Internal Oscillator Stop Mode Disable */ } Bits; struct { byte :1; byte :1; byte :1; byte grpOSCCLK :2; byte :1; byte :1; byte :1; } MergedBits; } CONFIG2STR; extern volatile CONFIG2STR _CONFIG2 @0x0000001D; #define CONFIG2 _CONFIG2.Byte #define CONFIG2_SCIBDSRC _CONFIG2.Bits.SCIBDSRC #define CONFIG2_OSCCLK0 _CONFIG2.Bits.OSCCLK0 #define CONFIG2_OSCCLK1 _CONFIG2.Bits.OSCCLK1 #define CONFIG2_STOP_XCLKEN _CONFIG2.Bits.STOP_XCLKEN #define CONFIG2_STOP_RCLKEN _CONFIG2.Bits.STOP_RCLKEN #define CONFIG2_STOP_ICLKDIS _CONFIG2.Bits.STOP_ICLKDIS #define CONFIG2_OSCCLK _CONFIG2.MergedBits.grpOSCCLK #define CONFIG2_SCIBDSRC_MASK 1 #define CONFIG2_OSCCLK0_MASK 8 #define CONFIG2_OSCCLK1_MASK 16 #define CONFIG2_STOP_XCLKEN_MASK 32 #define CONFIG2_STOP_RCLKEN_MASK 64 #define CONFIG2_STOP_ICLKDIS_MASK 128 #define CONFIG2_OSCCLK_MASK 24 #define CONFIG2_OSCCLK_BITNUM 3 /*** INTSCR1 - IRQ1 Status and Control Register; 0x0000001E ***/ typedef union { byte Byte; struct { byte MODE1 :1; /* IRQ1 Edge/Level Select Bit */ byte IMASK1 :1; /* IRQ1 Interrupt Mask Bit */ byte ACK1 :1; /* IRQ1 Interrupt Request Acknowledge Bit */ byte IRQ1F :1; /* IRQ1 Flag Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } INTSCR1STR; extern volatile INTSCR1STR _INTSCR1 @0x0000001E; #define INTSCR1 _INTSCR1.Byte #define INTSCR1_MODE1 _INTSCR1.Bits.MODE1 #define INTSCR1_IMASK1 _INTSCR1.Bits.IMASK1 #define INTSCR1_ACK1 _INTSCR1.Bits.ACK1 #define INTSCR1_IRQ1F _INTSCR1.Bits.IRQ1F #define INTSCR1_MODE1_MASK 1 #define INTSCR1_IMASK1_MASK 2 #define INTSCR1_ACK1_MASK 4 #define INTSCR1_IRQ1F_MASK 8 /*** CONFIG1 - Configuration Register 1; 0x0000001F ***/ typedef union { byte Byte; struct { byte COPD :1; /* COP Disable Bit */ byte STOP :1; /* STOP Instruction Enable Bit */ byte SSREC :1; /* Short Stop Recovery Bit */ byte LVIREGD :1; /* VREG LVI Circuit Disable Bit */ byte LVIPWRD :1; /* LVI Power Disable Bit */ byte LVIRSTD :1; /* LVI Reset Disable Bit */ byte LVISTOP :1; /* LVI Enable in Stop Mode Bit */ byte COPRS :1; /* COP rate Select Bit */ } Bits; } CONFIG1STR; extern volatile CONFIG1STR _CONFIG1 @0x0000001F; #define CONFIG1 _CONFIG1.Byte #define CONFIG1_COPD _CONFIG1.Bits.COPD #define CONFIG1_STOP _CONFIG1.Bits.STOP #define CONFIG1_SSREC _CONFIG1.Bits.SSREC #define CONFIG1_LVIREGD _CONFIG1.Bits.LVIREGD #define CONFIG1_LVIPWRD _CONFIG1.Bits.LVIPWRD #define CONFIG1_LVIRSTD _CONFIG1.Bits.LVIRSTD #define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP #define CONFIG1_COPRS _CONFIG1.Bits.COPRS #define CONFIG1_COPD_MASK 1 #define CONFIG1_STOP_MASK 2 #define CONFIG1_SSREC_MASK 4 #define CONFIG1_LVIREGD_MASK 8 #define CONFIG1_LVIPWRD_MASK 16 #define CONFIG1_LVIRSTD_MASK 32 #define CONFIG1_LVISTOP_MASK 64 #define CONFIG1_COPRS_MASK 128 /*** T1SC - TIM1 Status and Control Register; 0x00000020 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM1 Reset Bit */ byte TSTOP :1; /* TIM1 Stop Bit */ byte TOIE :1; /* TIM1 Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM1 Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } T1SCSTR; extern volatile T1SCSTR _T1SC @0x00000020; #define T1SC _T1SC.Byte #define T1SC_PS0 _T1SC.Bits.PS0 #define T1SC_PS1 _T1SC.Bits.PS1 #define T1SC_PS2 _T1SC.Bits.PS2 #define T1SC_TRST _T1SC.Bits.TRST #define T1SC_TSTOP _T1SC.Bits.TSTOP #define T1SC_TOIE _T1SC.Bits.TOIE #define T1SC_TOF _T1SC.Bits.TOF #define T1SC_PS _T1SC.MergedBits.grpPS #define T1SC_PS0_MASK 1 #define T1SC_PS1_MASK 2 #define T1SC_PS2_MASK 4 #define T1SC_TRST_MASK 16 #define T1SC_TSTOP_MASK 32 #define T1SC_TOIE_MASK 64 #define T1SC_TOF_MASK 128 #define T1SC_PS_MASK 7 #define T1SC_PS_BITNUM 0 /*** T1CNT - TIM1 Counter Register; 0x00000021 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CNTH - TIM1 Counter High Register; 0x00000021 ***/ union { byte Byte; } T1CNTHSTR; #define T1CNTH _T1CNT.Overlap_STR.T1CNTHSTR.Byte /*** T1CNTL - TIM1 Counter Low Register; 0x00000022 ***/ union { byte Byte; } T1CNTLSTR; #define T1CNTL _T1CNT.Overlap_STR.T1CNTLSTR.Byte } Overlap_STR; } T1CNTSTR; extern volatile T1CNTSTR _T1CNT @0x00000021; #define T1CNT _T1CNT.Word /*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1MODH - TIM1 Counter Modulo High Register; 0x00000023 ***/ union { byte Byte; } T1MODHSTR; #define T1MODH _T1MOD.Overlap_STR.T1MODHSTR.Byte /*** T1MODL - TIM1 Counter Modulo Low Register; 0x00000024 ***/ union { byte Byte; } T1MODLSTR; #define T1MODL _T1MOD.Overlap_STR.T1MODLSTR.Byte } Overlap_STR; } T1MODSTR; extern volatile T1MODSTR _T1MOD @0x00000023; #define T1MOD _T1MOD.Word /*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } T1SC0STR; extern volatile T1SC0STR _T1SC0 @0x00000025; #define T1SC0 _T1SC0.Byte #define T1SC0_CH0MAX _T1SC0.Bits.CH0MAX #define T1SC0_TOV0 _T1SC0.Bits.TOV0 #define T1SC0_ELS0A _T1SC0.Bits.ELS0A #define T1SC0_ELS0B _T1SC0.Bits.ELS0B #define T1SC0_MS0A _T1SC0.Bits.MS0A #define T1SC0_MS0B _T1SC0.Bits.MS0B #define T1SC0_CH0IE _T1SC0.Bits.CH0IE #define T1SC0_CH0F _T1SC0.Bits.CH0F #define T1SC0_ELS0x _T1SC0.MergedBits.grpELS0x #define T1SC0_MS0x _T1SC0.MergedBits.grpMS0x #define T1SC0_CH0MAX_MASK 1 #define T1SC0_TOV0_MASK 2 #define T1SC0_ELS0A_MASK 4 #define T1SC0_ELS0B_MASK 8 #define T1SC0_MS0A_MASK 16 #define T1SC0_MS0B_MASK 32 #define T1SC0_CH0IE_MASK 64 #define T1SC0_CH0F_MASK 128 #define T1SC0_ELS0x_MASK 12 #define T1SC0_ELS0x_BITNUM 2 #define T1SC0_MS0x_MASK 48 #define T1SC0_MS0x_BITNUM 4 /*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CH0H - TIM1 Channel 0 High Register; 0x00000026 ***/ union { byte Byte; } T1CH0HSTR; #define T1CH0H _T1CH0.Overlap_STR.T1CH0HSTR.Byte /*** T1CH0L - TIM1 Channel 0 Low Register; 0x00000027 ***/ union { byte Byte; } T1CH0LSTR; #define T1CH0L _T1CH0.Overlap_STR.T1CH0LSTR.Byte } Overlap_STR; } T1CH0STR; extern volatile T1CH0STR _T1CH0 @0x00000026; #define T1CH0 _T1CH0.Word /*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } T1SC1STR; extern volatile T1SC1STR _T1SC1 @0x00000028; #define T1SC1 _T1SC1.Byte #define T1SC1_CH1MAX _T1SC1.Bits.CH1MAX #define T1SC1_TOV1 _T1SC1.Bits.TOV1 #define T1SC1_ELS1A _T1SC1.Bits.ELS1A #define T1SC1_ELS1B _T1SC1.Bits.ELS1B #define T1SC1_MS1A _T1SC1.Bits.MS1A #define T1SC1_CH1IE _T1SC1.Bits.CH1IE #define T1SC1_CH1F _T1SC1.Bits.CH1F #define T1SC1_ELS1x _T1SC1.MergedBits.grpELS1x #define T1SC1_CH1MAX_MASK 1 #define T1SC1_TOV1_MASK 2 #define T1SC1_ELS1A_MASK 4 #define T1SC1_ELS1B_MASK 8 #define T1SC1_MS1A_MASK 16 #define T1SC1_CH1IE_MASK 64 #define T1SC1_CH1F_MASK 128 #define T1SC1_ELS1x_MASK 12 #define T1SC1_ELS1x_BITNUM 2 /*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T1CH1H - TIM1 Channel 1 High Register; 0x00000029 ***/ union { byte Byte; } T1CH1HSTR; #define T1CH1H _T1CH1.Overlap_STR.T1CH1HSTR.Byte /*** T1CH1L - TIM1 Channel 1 Low Register; 0x0000002A ***/ union { byte Byte; } T1CH1LSTR; #define T1CH1L _T1CH1.Overlap_STR.T1CH1LSTR.Byte } Overlap_STR; } T1CH1STR; extern volatile T1CH1STR _T1CH1 @0x00000029; #define T1CH1 _T1CH1.Word /*** T2SC - TIM2 Status and Control Register; 0x0000002B ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescaler Select Bit 0 */ byte PS1 :1; /* Prescaler Select Bit 1 */ byte PS2 :1; /* Prescaler Select Bit 2 */ byte :1; byte TRST :1; /* TIM2 Reset Bit */ byte TSTOP :1; /* TIM2 Stop Bit */ byte TOIE :1; /* TIM2 Overflow Interrupt Enable Bit */ byte TOF :1; /* TIM2 Overflow Flag Bit */ } Bits; struct { byte grpPS :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } T2SCSTR; extern volatile T2SCSTR _T2SC @0x0000002B; #define T2SC _T2SC.Byte #define T2SC_PS0 _T2SC.Bits.PS0 #define T2SC_PS1 _T2SC.Bits.PS1 #define T2SC_PS2 _T2SC.Bits.PS2 #define T2SC_TRST _T2SC.Bits.TRST #define T2SC_TSTOP _T2SC.Bits.TSTOP #define T2SC_TOIE _T2SC.Bits.TOIE #define T2SC_TOF _T2SC.Bits.TOF #define T2SC_PS _T2SC.MergedBits.grpPS #define T2SC_PS0_MASK 1 #define T2SC_PS1_MASK 2 #define T2SC_PS2_MASK 4 #define T2SC_TRST_MASK 16 #define T2SC_TSTOP_MASK 32 #define T2SC_TOIE_MASK 64 #define T2SC_TOF_MASK 128 #define T2SC_PS_MASK 7 #define T2SC_PS_BITNUM 0 /*** T2CNT - TIM2 Counter Register; 0x0000002C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CNTH - TIM2 Counter High Register; 0x0000002C ***/ union { byte Byte; } T2CNTHSTR; #define T2CNTH _T2CNT.Overlap_STR.T2CNTHSTR.Byte /*** T2CNTL - TIM2 Counter Low Register; 0x0000002D ***/ union { byte Byte; } T2CNTLSTR; #define T2CNTL _T2CNT.Overlap_STR.T2CNTLSTR.Byte } Overlap_STR; } T2CNTSTR; extern volatile T2CNTSTR _T2CNT @0x0000002C; #define T2CNT _T2CNT.Word /*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2MODH - TIM2 Counter Modulo High Register; 0x0000002E ***/ union { byte Byte; } T2MODHSTR; #define T2MODH _T2MOD.Overlap_STR.T2MODHSTR.Byte /*** T2MODL - TIM2 Counter Modulo Low Register; 0x0000002F ***/ union { byte Byte; } T2MODLSTR; #define T2MODL _T2MOD.Overlap_STR.T2MODLSTR.Byte } Overlap_STR; } T2MODSTR; extern volatile T2MODSTR _T2MOD @0x0000002E; #define T2MOD _T2MOD.Word /*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000030 ***/ typedef union { byte Byte; struct { byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */ byte TOV0 :1; /* Toggle-On-Overflow Bit */ byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select Bit A */ byte MS0B :1; /* Mode Select Bit B */ byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */ byte CH0F :1; /* Channel 0 Flag Bit */ } Bits; struct { byte :1; byte grpTOV :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } T2SC0STR; extern volatile T2SC0STR _T2SC0 @0x00000030; #define T2SC0 _T2SC0.Byte #define T2SC0_CH0MAX _T2SC0.Bits.CH0MAX #define T2SC0_TOV0 _T2SC0.Bits.TOV0 #define T2SC0_ELS0A _T2SC0.Bits.ELS0A #define T2SC0_ELS0B _T2SC0.Bits.ELS0B #define T2SC0_MS0A _T2SC0.Bits.MS0A #define T2SC0_MS0B _T2SC0.Bits.MS0B #define T2SC0_CH0IE _T2SC0.Bits.CH0IE #define T2SC0_CH0F _T2SC0.Bits.CH0F #define T2SC0_ELS0x _T2SC0.MergedBits.grpELS0x #define T2SC0_MS0x _T2SC0.MergedBits.grpMS0x #define T2SC0_CH0MAX_MASK 1 #define T2SC0_TOV0_MASK 2 #define T2SC0_ELS0A_MASK 4 #define T2SC0_ELS0B_MASK 8 #define T2SC0_MS0A_MASK 16 #define T2SC0_MS0B_MASK 32 #define T2SC0_CH0IE_MASK 64 #define T2SC0_CH0F_MASK 128 #define T2SC0_ELS0x_MASK 12 #define T2SC0_ELS0x_BITNUM 2 #define T2SC0_MS0x_MASK 48 #define T2SC0_MS0x_BITNUM 4 /*** T2CH0 - TIM2 Channel 0 Register; 0x00000031 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CH0H - TIM2 Channel 0 High Register; 0x00000031 ***/ union { byte Byte; } T2CH0HSTR; #define T2CH0H _T2CH0.Overlap_STR.T2CH0HSTR.Byte /*** T2CH0L - TIM2 Channel 0 Low Register; 0x00000032 ***/ union { byte Byte; } T2CH0LSTR; #define T2CH0L _T2CH0.Overlap_STR.T2CH0LSTR.Byte } Overlap_STR; } T2CH0STR; extern volatile T2CH0STR _T2CH0 @0x00000031; #define T2CH0 _T2CH0.Word /*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000033 ***/ typedef union { byte Byte; struct { byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */ byte TOV1 :1; /* Toggle-On-Overflow Bit */ byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select Bit A */ byte :1; byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */ byte CH1F :1; /* Channel 1 Flag Bit */ } Bits; struct { byte :1; byte grpTOV_1 :1; byte grpELS1x :2; byte grpMS1x :1; byte :1; byte :1; byte :1; } MergedBits; } T2SC1STR; extern volatile T2SC1STR _T2SC1 @0x00000033; #define T2SC1 _T2SC1.Byte #define T2SC1_CH1MAX _T2SC1.Bits.CH1MAX #define T2SC1_TOV1 _T2SC1.Bits.TOV1 #define T2SC1_ELS1A _T2SC1.Bits.ELS1A #define T2SC1_ELS1B _T2SC1.Bits.ELS1B #define T2SC1_MS1A _T2SC1.Bits.MS1A #define T2SC1_CH1IE _T2SC1.Bits.CH1IE #define T2SC1_CH1F _T2SC1.Bits.CH1F #define T2SC1_ELS1x _T2SC1.MergedBits.grpELS1x #define T2SC1_CH1MAX_MASK 1 #define T2SC1_TOV1_MASK 2 #define T2SC1_ELS1A_MASK 4 #define T2SC1_ELS1B_MASK 8 #define T2SC1_MS1A_MASK 16 #define T2SC1_CH1IE_MASK 64 #define T2SC1_CH1F_MASK 128 #define T2SC1_ELS1x_MASK 12 #define T2SC1_ELS1x_BITNUM 2 /*** T2CH1 - TIM2 Channel 1 Register; 0x00000034 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** T2CH1H - TIM2 Channel 1 High Register; 0x00000034 ***/ union { byte Byte; } T2CH1HSTR; #define T2CH1H _T2CH1.Overlap_STR.T2CH1HSTR.Byte /*** T2CH1L - TIM2 Channel 1 Low Register; 0x00000035 ***/ union { byte Byte; } T2CH1LSTR; #define T2CH1L _T2CH1.Overlap_STR.T2CH1LSTR.Byte } Overlap_STR; } T2CH1STR; extern volatile T2CH1STR _T2CH1 @0x00000034; #define T2CH1 _T2CH1.Word /*** PCTL - PLL Control Register; 0x00000036 ***/ typedef union { byte Byte; struct { byte VPR0 :1; /* VCO Power-of-Two Range Select Bit 0 */ byte VPR1 :1; /* VCO Power-of-Two Range Select Bit 1 */ byte PRE0 :1; /* Prescaler Program Bit 0 */ byte PRE1 :1; /* Prescaler Program Bit 1 */ byte BCS :1; /* Base Clock Select Bit */ byte PLLON :1; /* PLL On Bit */ byte PLLF :1; /* PLL Flag Bit */ byte PLLIE :1; /* PLL Interrupt Enable Bit */ } Bits; struct { byte grpVPR :2; byte grpPRE :2; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PCTLSTR; extern volatile PCTLSTR _PCTL @0x00000036; #define PCTL _PCTL.Byte #define PCTL_VPR0 _PCTL.Bits.VPR0 #define PCTL_VPR1 _PCTL.Bits.VPR1 #define PCTL_PRE0 _PCTL.Bits.PRE0 #define PCTL_PRE1 _PCTL.Bits.PRE1 #define PCTL_BCS _PCTL.Bits.BCS #define PCTL_PLLON _PCTL.Bits.PLLON #define PCTL_PLLF _PCTL.Bits.PLLF #define PCTL_PLLIE _PCTL.Bits.PLLIE #define PCTL_VPR _PCTL.MergedBits.grpVPR #define PCTL_PRE _PCTL.MergedBits.grpPRE #define PCTL_VPR0_MASK 1 #define PCTL_VPR1_MASK 2 #define PCTL_PRE0_MASK 4 #define PCTL_PRE1_MASK 8 #define PCTL_BCS_MASK 16 #define PCTL_PLLON_MASK 32 #define PCTL_PLLF_MASK 64 #define PCTL_PLLIE_MASK 128 #define PCTL_VPR_MASK 3 #define PCTL_VPR_BITNUM 0 #define PCTL_PRE_MASK 12 #define PCTL_PRE_BITNUM 2 /*** PBWC - PLL Bandwidth Control Register; 0x00000037 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte ACQ :1; /* Automatic Bandwidth Control Bit */ byte LOCK :1; /* Lock Indicator Bit */ byte AUTO :1; /* Acquisiton Mode Bit */ } Bits; } PBWCSTR; extern volatile PBWCSTR _PBWC @0x00000037; #define PBWC _PBWC.Byte #define PBWC_ACQ _PBWC.Bits.ACQ #define PBWC_LOCK _PBWC.Bits.LOCK #define PBWC_AUTO _PBWC.Bits.AUTO #define PBWC_ACQ_MASK 32 #define PBWC_LOCK_MASK 64 #define PBWC_AUTO_MASK 128 /*** PMS - PLL Multiplier Select Register; 0x00000038 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** PMSH - PLL Multiplier Select Register High; 0x00000038 ***/ union { byte Byte; struct { byte MUL8 :1; /* PLL Multiplier Select Bit 8 */ byte MUL9 :1; /* PLL Multiplier Select Bit 9 */ byte MUL10 :1; /* PLL Multiplier Select Bit 10 */ byte MUL11 :1; /* PLL Multiplier Select Bit 11 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpMUL_8 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PMSHSTR; #define PMSH _PMS.Overlap_STR.PMSHSTR.Byte #define PMSH_MUL8 _PMS.Overlap_STR.PMSHSTR.Bits.MUL8 #define PMSH_MUL9 _PMS.Overlap_STR.PMSHSTR.Bits.MUL9 #define PMSH_MUL10 _PMS.Overlap_STR.PMSHSTR.Bits.MUL10 #define PMSH_MUL11 _PMS.Overlap_STR.PMSHSTR.Bits.MUL11 #define PMSH_MUL_8 _PMS.Overlap_STR.PMSHSTR.MergedBits.grpMUL_8 #define PMSH_MUL PMSH_MUL_8 #define PMSH_MUL8_MASK 1 #define PMSH_MUL9_MASK 2 #define PMSH_MUL10_MASK 4 #define PMSH_MUL11_MASK 8 #define PMSH_MUL_8_MASK 15 #define PMSH_MUL_8_BITNUM 0 /*** PMSL - PLL Multiplier Select Register Low; 0x00000039 ***/ union { byte Byte; struct { byte MUL0 :1; /* PLL Multiplier Select Bit 0 */ byte MUL1 :1; /* PLL Multiplier Select Bit 1 */ byte MUL2 :1; /* PLL Multiplier Select Bit 2 */ byte MUL3 :1; /* PLL Multiplier Select Bit 3 */ byte MUL4 :1; /* PLL Multiplier Select Bit 4 */ byte MUL5 :1; /* PLL Multiplier Select Bit 5 */ byte MUL6 :1; /* PLL Multiplier Select Bit 6 */ byte MUL7 :1; /* PLL Multiplier Select Bit 7 */ } Bits; } PMSLSTR; #define PMSL _PMS.Overlap_STR.PMSLSTR.Byte #define PMSL_MUL0 _PMS.Overlap_STR.PMSLSTR.Bits.MUL0 #define PMSL_MUL1 _PMS.Overlap_STR.PMSLSTR.Bits.MUL1 #define PMSL_MUL2 _PMS.Overlap_STR.PMSLSTR.Bits.MUL2 #define PMSL_MUL3 _PMS.Overlap_STR.PMSLSTR.Bits.MUL3 #define PMSL_MUL4 _PMS.Overlap_STR.PMSLSTR.Bits.MUL4 #define PMSL_MUL5 _PMS.Overlap_STR.PMSLSTR.Bits.MUL5 #define PMSL_MUL6 _PMS.Overlap_STR.PMSLSTR.Bits.MUL6 #define PMSL_MUL7 _PMS.Overlap_STR.PMSLSTR.Bits.MUL7 #define PMSL_MUL0_MASK 1 #define PMSL_MUL1_MASK 2 #define PMSL_MUL2_MASK 4 #define PMSL_MUL3_MASK 8 #define PMSL_MUL4_MASK 16 #define PMSL_MUL5_MASK 32 #define PMSL_MUL6_MASK 64 #define PMSL_MUL7_MASK 128 } Overlap_STR; } PMSSTR; extern volatile PMSSTR _PMS @0x00000038; #define PMS _PMS.Word /*** PMRS - PLL VCO Range Select; 0x0000003A ***/ typedef union { byte Byte; struct { byte VRS0 :1; /* VCO Range Select Bit 0 */ byte VRS1 :1; /* VCO Range Select Bit 1 */ byte VRS2 :1; /* VCO Range Select Bit 2 */ byte VRS3 :1; /* VCO Range Select Bit 3 */ byte VRS4 :1; /* VCO Range Select Bit 4 */ byte VRS5 :1; /* VCO Range Select Bit 5 */ byte VRS6 :1; /* VCO Range Select Bit 6 */ byte VRS7 :1; /* VCO Range Select Bit 7 */ } Bits; } PMRSSTR; extern volatile PMRSSTR _PMRS @0x0000003A; #define PMRS _PMRS.Byte #define PMRS_VRS0 _PMRS.Bits.VRS0 #define PMRS_VRS1 _PMRS.Bits.VRS1 #define PMRS_VRS2 _PMRS.Bits.VRS2 #define PMRS_VRS3 _PMRS.Bits.VRS3 #define PMRS_VRS4 _PMRS.Bits.VRS4 #define PMRS_VRS5 _PMRS.Bits.VRS5 #define PMRS_VRS6 _PMRS.Bits.VRS6 #define PMRS_VRS7 _PMRS.Bits.VRS7 #define PMRS_VRS0_MASK 1 #define PMRS_VRS1_MASK 2 #define PMRS_VRS2_MASK 4 #define PMRS_VRS3_MASK 8 #define PMRS_VRS4_MASK 16 #define PMRS_VRS5_MASK 32 #define PMRS_VRS6_MASK 64 #define PMRS_VRS7_MASK 128 /*** PMDS - PLL Reference Divider Select Register; 0x0000003B ***/ typedef union { byte Byte; struct { byte RDS0 :1; /* Reference Divider Select Bit 0 */ byte RDS1 :1; /* Reference Divider Select Bit 1 */ byte RDS2 :1; /* Reference Divider Select Bit 2 */ byte RDS3 :1; /* Reference Divider Select Bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpRDS :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PMDSSTR; extern volatile PMDSSTR _PMDS @0x0000003B; #define PMDS _PMDS.Byte #define PMDS_RDS0 _PMDS.Bits.RDS0 #define PMDS_RDS1 _PMDS.Bits.RDS1 #define PMDS_RDS2 _PMDS.Bits.RDS2 #define PMDS_RDS3 _PMDS.Bits.RDS3 #define PMDS_RDS _PMDS.MergedBits.grpRDS #define PMDS_RDS0_MASK 1 #define PMDS_RDS1_MASK 2 #define PMDS_RDS2_MASK 4 #define PMDS_RDS3_MASK 8 #define PMDS_RDS_MASK 15 #define PMDS_RDS_BITNUM 0 /*** IRSCC1 - IRSCI Control Register 1; 0x00000040 ***/ typedef union { byte Byte; struct { byte PTY :1; /* Parity Bit */ byte PEN :1; /* Parity Enable Bit */ byte ILTY :1; /* Idle Line Type Bit */ byte WAKE :1; /* Wakeup Condition Bit */ byte M :1; /* Mode (Character Length) Bit */ byte :1; byte ENSCI :1; /* Enable SCI Bit */ byte LOOPS :1; /* Loop Mode Select Bit */ } Bits; } IRSCC1STR; extern volatile IRSCC1STR _IRSCC1 @0x00000040; #define IRSCC1 _IRSCC1.Byte #define IRSCC1_PTY _IRSCC1.Bits.PTY #define IRSCC1_PEN _IRSCC1.Bits.PEN #define IRSCC1_ILTY _IRSCC1.Bits.ILTY #define IRSCC1_WAKE _IRSCC1.Bits.WAKE #define IRSCC1_M _IRSCC1.Bits.M #define IRSCC1_ENSCI _IRSCC1.Bits.ENSCI #define IRSCC1_LOOPS _IRSCC1.Bits.LOOPS #define IRSCC1_PTY_MASK 1 #define IRSCC1_PEN_MASK 2 #define IRSCC1_ILTY_MASK 4 #define IRSCC1_WAKE_MASK 8 #define IRSCC1_M_MASK 16 #define IRSCC1_ENSCI_MASK 64 #define IRSCC1_LOOPS_MASK 128 /*** IRSCC2 - IRSCI Control Register 2; 0x00000041 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break Bit */ byte RWU :1; /* Receiver Wakeup Bit */ byte RE :1; /* Receiver Enable Bit */ byte TE :1; /* Transmitter Enable Bit */ byte ILIE :1; /* Idle Line Interrupt Enable Bit */ byte SCRIE :1; /* SCI Receive Interrupt Enable Bit */ byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ byte SCTIE :1; /* SCI Transmit Interrupt Enable Bit */ } Bits; } IRSCC2STR; extern volatile IRSCC2STR _IRSCC2 @0x00000041; #define IRSCC2 _IRSCC2.Byte #define IRSCC2_SBK _IRSCC2.Bits.SBK #define IRSCC2_RWU _IRSCC2.Bits.RWU #define IRSCC2_RE _IRSCC2.Bits.RE #define IRSCC2_TE _IRSCC2.Bits.TE #define IRSCC2_ILIE _IRSCC2.Bits.ILIE #define IRSCC2_SCRIE _IRSCC2.Bits.SCRIE #define IRSCC2_TCIE _IRSCC2.Bits.TCIE #define IRSCC2_SCTIE _IRSCC2.Bits.SCTIE #define IRSCC2_SBK_MASK 1 #define IRSCC2_RWU_MASK 2 #define IRSCC2_RE_MASK 4 #define IRSCC2_TE_MASK 8 #define IRSCC2_ILIE_MASK 16 #define IRSCC2_SCRIE_MASK 32 #define IRSCC2_TCIE_MASK 64 #define IRSCC2_SCTIE_MASK 128 /*** IRSCC3 - IRSCI Control Register 3; 0x00000042 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Receiver Parity Error Interrupt Enable Bit */ byte FEIE :1; /* Receiver Framing Error Interrupt Enable Bit */ byte NEIE :1; /* Receiver Noise Error Interrupt Enable Bit */ byte ORIE :1; /* Receiver Overrun Interrupt Enable Bit */ byte :1; byte :1; byte T8 :1; /* Transmitted Bit 8 */ byte R8 :1; /* Received Bit 8 */ } Bits; } IRSCC3STR; extern volatile IRSCC3STR _IRSCC3 @0x00000042; #define IRSCC3 _IRSCC3.Byte #define IRSCC3_PEIE _IRSCC3.Bits.PEIE #define IRSCC3_FEIE _IRSCC3.Bits.FEIE #define IRSCC3_NEIE _IRSCC3.Bits.NEIE #define IRSCC3_ORIE _IRSCC3.Bits.ORIE #define IRSCC3_T8 _IRSCC3.Bits.T8 #define IRSCC3_R8 _IRSCC3.Bits.R8 #define IRSCC3_PEIE_MASK 1 #define IRSCC3_FEIE_MASK 2 #define IRSCC3_NEIE_MASK 4 #define IRSCC3_ORIE_MASK 8 #define IRSCC3_T8_MASK 64 #define IRSCC3_R8_MASK 128 /*** IRSCS1 - IRSCI Status Register 1; 0x00000043 ***/ typedef union { byte Byte; struct { byte PE :1; /* Receiver Parity Error Bit */ byte FE :1; /* Receiver Framing Error Bit */ byte NF :1; /* Receiver Noise Flag Bit */ byte OR :1; /* Receiver Overrun Bit */ byte IDLE :1; /* Receiver Idle Bit */ byte SCRF :1; /* SCI Receiver Full Bit */ byte TC :1; /* Transmission Complete Bit */ byte SCTE :1; /* SCI Transmitter Empty Bit */ } Bits; } IRSCS1STR; extern volatile IRSCS1STR _IRSCS1 @0x00000043; #define IRSCS1 _IRSCS1.Byte #define IRSCS1_PE _IRSCS1.Bits.PE #define IRSCS1_FE _IRSCS1.Bits.FE #define IRSCS1_NF _IRSCS1.Bits.NF #define IRSCS1_OR _IRSCS1.Bits.OR #define IRSCS1_IDLE _IRSCS1.Bits.IDLE #define IRSCS1_SCRF _IRSCS1.Bits.SCRF #define IRSCS1_TC _IRSCS1.Bits.TC #define IRSCS1_SCTE _IRSCS1.Bits.SCTE #define IRSCS1_PE_MASK 1 #define IRSCS1_FE_MASK 2 #define IRSCS1_NF_MASK 4 #define IRSCS1_OR_MASK 8 #define IRSCS1_IDLE_MASK 16 #define IRSCS1_SCRF_MASK 32 #define IRSCS1_TC_MASK 64 #define IRSCS1_SCTE_MASK 128 /*** IRSCS2 - IRSCI Status Register 2; 0x00000044 ***/ typedef union { byte Byte; struct { byte RPF :1; /* Reception in Progress Flag Bit */ byte BKF :1; /* Break Flag Bit */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } IRSCS2STR; extern volatile IRSCS2STR _IRSCS2 @0x00000044; #define IRSCS2 _IRSCS2.Byte #define IRSCS2_RPF _IRSCS2.Bits.RPF #define IRSCS2_BKF _IRSCS2.Bits.BKF #define IRSCS2_RPF_MASK 1 #define IRSCS2_BKF_MASK 2 /*** IRSCDR - IRSCI Data Register; 0x00000045 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } IRSCDRSTR; extern volatile IRSCDRSTR _IRSCDR @0x00000045; #define IRSCDR _IRSCDR.Byte #define IRSCDR_R0_T0 _IRSCDR.Bits.R0_T0 #define IRSCDR_R1_T1 _IRSCDR.Bits.R1_T1 #define IRSCDR_R2_T2 _IRSCDR.Bits.R2_T2 #define IRSCDR_R3_T3 _IRSCDR.Bits.R3_T3 #define IRSCDR_R4_T4 _IRSCDR.Bits.R4_T4 #define IRSCDR_R5_T5 _IRSCDR.Bits.R5_T5 #define IRSCDR_R6_T6 _IRSCDR.Bits.R6_T6 #define IRSCDR_R7_T7 _IRSCDR.Bits.R7_T7 #define IRSCDR_R0_T0_MASK 1 #define IRSCDR_R1_T1_MASK 2 #define IRSCDR_R2_T2_MASK 4 #define IRSCDR_R3_T3_MASK 8 #define IRSCDR_R4_T4_MASK 16 #define IRSCDR_R5_T5_MASK 32 #define IRSCDR_R6_T6_MASK 64 #define IRSCDR_R7_T7_MASK 128 /*** IRSCBR - IRSCI Baud Rate Register; 0x00000046 ***/ typedef union { byte Byte; struct { byte SCR0 :1; /* SCI Baud Rate Select Bit 0 */ byte SCR1 :1; /* SCI Baud Rate Select Bit 1 */ byte SCR2 :1; /* SCI Baud Rate Select Bit 2 */ byte :1; byte SCP0 :1; /* SCI Baud Rate Prescaler Bit 0 */ byte SCP1 :1; /* SCI Baud Rate Prescaler Bit 1 */ byte :1; byte CKS :1; /* Baud Clock Input Select */ } Bits; struct { byte grpSCR :3; byte :1; byte grpSCP :2; byte :1; byte :1; } MergedBits; } IRSCBRSTR; extern volatile IRSCBRSTR _IRSCBR @0x00000046; #define IRSCBR _IRSCBR.Byte #define IRSCBR_SCR0 _IRSCBR.Bits.SCR0 #define IRSCBR_SCR1 _IRSCBR.Bits.SCR1 #define IRSCBR_SCR2 _IRSCBR.Bits.SCR2 #define IRSCBR_SCP0 _IRSCBR.Bits.SCP0 #define IRSCBR_SCP1 _IRSCBR.Bits.SCP1 #define IRSCBR_CKS _IRSCBR.Bits.CKS #define IRSCBR_SCR _IRSCBR.MergedBits.grpSCR #define IRSCBR_SCP _IRSCBR.MergedBits.grpSCP #define IRSCBR_SCR0_MASK 1 #define IRSCBR_SCR1_MASK 2 #define IRSCBR_SCR2_MASK 4 #define IRSCBR_SCP0_MASK 16 #define IRSCBR_SCP1_MASK 32 #define IRSCBR_CKS_MASK 128 #define IRSCBR_SCR_MASK 7 #define IRSCBR_SCR_BITNUM 0 #define IRSCBR_SCP_MASK 48 #define IRSCBR_SCP_BITNUM 4 /*** IRSCIRCR - IRSCI Infra-ref Control Register; 0x00000047 ***/ typedef union { byte Byte; struct { byte IREN :1; /* IR Enable Bit */ byte TNP0 :1; /* Transmitter Narrow Pulse Bit 0 */ byte TNP1 :1; /* Transmitter Narrow Pulse Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte :1; byte grpTNP :2; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } IRSCIRCRSTR; extern volatile IRSCIRCRSTR _IRSCIRCR @0x00000047; #define IRSCIRCR _IRSCIRCR.Byte #define IRSCIRCR_IREN _IRSCIRCR.Bits.IREN #define IRSCIRCR_TNP0 _IRSCIRCR.Bits.TNP0 #define IRSCIRCR_TNP1 _IRSCIRCR.Bits.TNP1 #define IRSCIRCR_TNP _IRSCIRCR.MergedBits.grpTNP #define IRSCIRCR_IREN_MASK 1 #define IRSCIRCR_TNP0_MASK 2 #define IRSCIRCR_TNP1_MASK 4 #define IRSCIRCR_TNP_MASK 6 #define IRSCIRCR_TNP_BITNUM 1 /*** MMADR - Multi-Master IIC Address Register; 0x00000048 ***/ typedef union { byte Byte; struct { byte MMEXTAD :1; /* Multi-Master Expanded Address */ byte MMAD1 :1; /* Multi-Master Address Bit 1 */ byte MMAD2 :1; /* Multi-Master Address Bit 2 */ byte MMAD3 :1; /* Multi-Master Address Bit 3 */ byte MMAD4 :1; /* Multi-Master Address Bit 4 */ byte MMAD5 :1; /* Multi-Master Address Bit 5 */ byte MMAD6 :1; /* Multi-Master Address Bit 6 */ byte MMAD7 :1; /* Multi-Master Address Bit 7 */ } Bits; struct { byte :1; byte grpMMAD_1 :7; } MergedBits; } MMADRSTR; extern volatile MMADRSTR _MMADR @0x00000048; #define MMADR _MMADR.Byte #define MMADR_MMEXTAD _MMADR.Bits.MMEXTAD #define MMADR_MMAD1 _MMADR.Bits.MMAD1 #define MMADR_MMAD2 _MMADR.Bits.MMAD2 #define MMADR_MMAD3 _MMADR.Bits.MMAD3 #define MMADR_MMAD4 _MMADR.Bits.MMAD4 #define MMADR_MMAD5 _MMADR.Bits.MMAD5 #define MMADR_MMAD6 _MMADR.Bits.MMAD6 #define MMADR_MMAD7 _MMADR.Bits.MMAD7 #define MMADR_MMAD_1 _MMADR.MergedBits.grpMMAD_1 #define MMADR_MMAD MMADR_MMAD_1 #define MMADR_MMEXTAD_MASK 1 #define MMADR_MMAD1_MASK 2 #define MMADR_MMAD2_MASK 4 #define MMADR_MMAD3_MASK 8 #define MMADR_MMAD4_MASK 16 #define MMADR_MMAD5_MASK 32 #define MMADR_MMAD6_MASK 64 #define MMADR_MMAD7_MASK 128 #define MMADR_MMAD_1_MASK 254 #define MMADR_MMAD_1_BITNUM 1 /*** MMCR1 - Multi-Master IIC Control Register 1; 0x00000049 ***/ typedef union { byte Byte; struct { byte :1; byte MMCRCBYTE :1; /* Multi-Master IIC CRC Byte */ byte REPSEN :1; /* Repeated Start Enable */ byte MMTXAK :1; /* Transmit Acknowledge Enable */ byte :1; byte MMCLRBB :1; /* Multi-Master IIC Clear Busy Bit */ byte MMIEN :1; /* Multi-Master IIC Interrupt Enable */ byte MMEN :1; /* Multi-Master IIC Enable */ } Bits; } MMCR1STR; extern volatile MMCR1STR _MMCR1 @0x00000049; #define MMCR1 _MMCR1.Byte #define MMCR1_MMCRCBYTE _MMCR1.Bits.MMCRCBYTE #define MMCR1_REPSEN _MMCR1.Bits.REPSEN #define MMCR1_MMTXAK _MMCR1.Bits.MMTXAK #define MMCR1_MMCLRBB _MMCR1.Bits.MMCLRBB #define MMCR1_MMIEN _MMCR1.Bits.MMIEN #define MMCR1_MMEN _MMCR1.Bits.MMEN #define MMCR1_MMCRCBYTE_MASK 2 #define MMCR1_REPSEN_MASK 4 #define MMCR1_MMTXAK_MASK 8 #define MMCR1_MMCLRBB_MASK 32 #define MMCR1_MMIEN_MASK 64 #define MMCR1_MMEN_MASK 128 /*** MMCR2 - Multi-Master IIC Control Register 2; 0x0000004A ***/ typedef union { byte Byte; struct { byte MMCRCEF :1; /* Multi-Master IIC CRC Error Flag */ byte :1; byte :1; byte MMRW :1; /* Multi-Master IIC Master Read/Write */ byte MMAST :1; /* Multi-Master IIC Master Control */ byte MMBB :1; /* Multi-Master IIC Bus Busy Flag */ byte MMNAKIF :1; /* No Acnknowledge Interrupt Flag */ byte MMALIF :1; /* Arbitration Loss Interrupt Flag */ } Bits; } MMCR2STR; extern volatile MMCR2STR _MMCR2 @0x0000004A; #define MMCR2 _MMCR2.Byte #define MMCR2_MMCRCEF _MMCR2.Bits.MMCRCEF #define MMCR2_MMRW _MMCR2.Bits.MMRW #define MMCR2_MMAST _MMCR2.Bits.MMAST #define MMCR2_MMBB _MMCR2.Bits.MMBB #define MMCR2_MMNAKIF _MMCR2.Bits.MMNAKIF #define MMCR2_MMALIF _MMCR2.Bits.MMALIF #define MMCR2_MMCRCEF_MASK 1 #define MMCR2_MMRW_MASK 8 #define MMCR2_MMAST_MASK 16 #define MMCR2_MMBB_MASK 32 #define MMCR2_MMNAKIF_MASK 64 #define MMCR2_MMALIF_MASK 128 /*** MMSR - Multi-Master IIC Status Register; 0x0000004B ***/ typedef union { byte Byte; struct { byte MMRXBF :1; /* Multi-Master Receive Buffer Full */ byte MMTXBE :1; /* Multi-Master Transmit Buffer Empty */ byte MMCRCBF :1; /* CRC Data Buffer Full Flag */ byte MMRXAK :1; /* Multi-Master Receive Acknowledge */ byte MMSRW :1; /* Multi-Master Slave Read/Write */ byte MMATCH :1; /* Multi-Master Address Match */ byte MMTXIF :1; /* Multi-Master Transmit Interrupt Flag */ byte MMRXIF :1; /* Multi-Master IIC Receive Interrupt Flag */ } Bits; } MMSRSTR; extern volatile MMSRSTR _MMSR @0x0000004B; #define MMSR _MMSR.Byte #define MMSR_MMRXBF _MMSR.Bits.MMRXBF #define MMSR_MMTXBE _MMSR.Bits.MMTXBE #define MMSR_MMCRCBF _MMSR.Bits.MMCRCBF #define MMSR_MMRXAK _MMSR.Bits.MMRXAK #define MMSR_MMSRW _MMSR.Bits.MMSRW #define MMSR_MMATCH _MMSR.Bits.MMATCH #define MMSR_MMTXIF _MMSR.Bits.MMTXIF #define MMSR_MMRXIF _MMSR.Bits.MMRXIF #define MMSR_MMRXBF_MASK 1 #define MMSR_MMTXBE_MASK 2 #define MMSR_MMCRCBF_MASK 4 #define MMSR_MMRXAK_MASK 8 #define MMSR_MMSRW_MASK 16 #define MMSR_MMATCH_MASK 32 #define MMSR_MMTXIF_MASK 64 #define MMSR_MMRXIF_MASK 128 /*** MMDTR - Multi-Master IIC Data Transmit Register; 0x0000004C ***/ typedef union { byte Byte; struct { byte MMTD0 :1; /* Multi-Master IIC Transmit Data Bit 0 */ byte MMTD1 :1; /* Multi-Master IIC Transmit Data Bit 1 */ byte MMTD2 :1; /* Multi-Master IIC Transmit Data Bit 2 */ byte MMTD3 :1; /* Multi-Master IIC Transmit Data Bit 3 */ byte MMTD4 :1; /* Multi-Master IIC Transmit Data Bit 4 */ byte MMTD5 :1; /* Multi-Master IIC Transmit Data Bit 5 */ byte MMTD6 :1; /* Multi-Master IIC Transmit Data Bit 6 */ byte MMTD7 :1; /* Multi-Master IIC Transmit Data Bit 7 */ } Bits; } MMDTRSTR; extern volatile MMDTRSTR _MMDTR @0x0000004C; #define MMDTR _MMDTR.Byte #define MMDTR_MMTD0 _MMDTR.Bits.MMTD0 #define MMDTR_MMTD1 _MMDTR.Bits.MMTD1 #define MMDTR_MMTD2 _MMDTR.Bits.MMTD2 #define MMDTR_MMTD3 _MMDTR.Bits.MMTD3 #define MMDTR_MMTD4 _MMDTR.Bits.MMTD4 #define MMDTR_MMTD5 _MMDTR.Bits.MMTD5 #define MMDTR_MMTD6 _MMDTR.Bits.MMTD6 #define MMDTR_MMTD7 _MMDTR.Bits.MMTD7 #define MMDTR_MMTD0_MASK 1 #define MMDTR_MMTD1_MASK 2 #define MMDTR_MMTD2_MASK 4 #define MMDTR_MMTD3_MASK 8 #define MMDTR_MMTD4_MASK 16 #define MMDTR_MMTD5_MASK 32 #define MMDTR_MMTD6_MASK 64 #define MMDTR_MMTD7_MASK 128 /*** MMDRR - Multi-Master IIC Data Receive Register; 0x0000004D ***/ typedef union { byte Byte; struct { byte MMRD0 :1; /* Multi-Master IIC Receive Data Bit 0 */ byte MMRD1 :1; /* Multi-Master IIC Receive Data Bit 1 */ byte MMRD2 :1; /* Multi-Master IIC Receive Data Bit 2 */ byte MMRD3 :1; /* Multi-Master IIC Receive Data Bit 3 */ byte MMRD4 :1; /* Multi-Master IIC Receive Data Bit 4 */ byte MMRD5 :1; /* Multi-Master IIC Receive Data Bit 5 */ byte MMRD6 :1; /* Multi-Master IIC Receive Data Bit 6 */ byte MMRD7 :1; /* Multi-Master IIC Receive Data Bit 7 */ } Bits; } MMDRRSTR; extern volatile MMDRRSTR _MMDRR @0x0000004D; #define MMDRR _MMDRR.Byte #define MMDRR_MMRD0 _MMDRR.Bits.MMRD0 #define MMDRR_MMRD1 _MMDRR.Bits.MMRD1 #define MMDRR_MMRD2 _MMDRR.Bits.MMRD2 #define MMDRR_MMRD3 _MMDRR.Bits.MMRD3 #define MMDRR_MMRD4 _MMDRR.Bits.MMRD4 #define MMDRR_MMRD5 _MMDRR.Bits.MMRD5 #define MMDRR_MMRD6 _MMDRR.Bits.MMRD6 #define MMDRR_MMRD7 _MMDRR.Bits.MMRD7 #define MMDRR_MMRD0_MASK 1 #define MMDRR_MMRD1_MASK 2 #define MMDRR_MMRD2_MASK 4 #define MMDRR_MMRD3_MASK 8 #define MMDRR_MMRD4_MASK 16 #define MMDRR_MMRD5_MASK 32 #define MMDRR_MMRD6_MASK 64 #define MMDRR_MMRD7_MASK 128 /*** MMCRDR - Multi-Master IIC CRC Data Register; 0x0000004E ***/ typedef union { byte Byte; struct { byte MMCRCD0 :1; /* Multi-Master IIC CRC Data Bit 0 */ byte MMCRCD1 :1; /* Multi-Master IIC CRC Data Bit 1 */ byte MMCRCD2 :1; /* Multi-Master IIC CRC Data Bit 2 */ byte MMCRCD3 :1; /* Multi-Master IIC CRC Data Bit 3 */ byte MMCRCD4 :1; /* Multi-Master IIC CRC Data Bit 4 */ byte MMCRCD5 :1; /* Multi-Master IIC CRC Data Bit 5 */ byte MMCRCD6 :1; /* Multi-Master IIC CRC Data Bit 6 */ byte MMCRCD7 :1; /* Multi-Master IIC CRC Data Bit 7 */ } Bits; } MMCRDRSTR; extern volatile MMCRDRSTR _MMCRDR @0x0000004E; #define MMCRDR _MMCRDR.Byte #define MMCRDR_MMCRCD0 _MMCRDR.Bits.MMCRCD0 #define MMCRDR_MMCRCD1 _MMCRDR.Bits.MMCRCD1 #define MMCRDR_MMCRCD2 _MMCRDR.Bits.MMCRCD2 #define MMCRDR_MMCRCD3 _MMCRDR.Bits.MMCRCD3 #define MMCRDR_MMCRCD4 _MMCRDR.Bits.MMCRCD4 #define MMCRDR_MMCRCD5 _MMCRDR.Bits.MMCRCD5 #define MMCRDR_MMCRCD6 _MMCRDR.Bits.MMCRCD6 #define MMCRDR_MMCRCD7 _MMCRDR.Bits.MMCRCD7 #define MMCRDR_MMCRCD0_MASK 1 #define MMCRDR_MMCRCD1_MASK 2 #define MMCRDR_MMCRCD2_MASK 4 #define MMCRDR_MMCRCD3_MASK 8 #define MMCRDR_MMCRCD4_MASK 16 #define MMCRDR_MMCRCD5_MASK 32 #define MMCRDR_MMCRCD6_MASK 64 #define MMCRDR_MMCRCD7_MASK 128 /*** MMFDR - Multi-Master IIC Frequency Divider Register; 0x0000004F ***/ typedef union { byte Byte; struct { byte MMBR0 :1; /* Frequency Divider Bit 0 */ byte MMBR1 :1; /* Frequency Divider Bit 1 */ byte MMBR2 :1; /* Frequency Divider Bit 2 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpMMBR :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } MMFDRSTR; extern volatile MMFDRSTR _MMFDR @0x0000004F; #define MMFDR _MMFDR.Byte #define MMFDR_MMBR0 _MMFDR.Bits.MMBR0 #define MMFDR_MMBR1 _MMFDR.Bits.MMBR1 #define MMFDR_MMBR2 _MMFDR.Bits.MMBR2 #define MMFDR_MMBR _MMFDR.MergedBits.grpMMBR #define MMFDR_MMBR0_MASK 1 #define MMFDR_MMBR1_MASK 2 #define MMFDR_MMBR2_MASK 4 #define MMFDR_MMBR_MASK 7 #define MMFDR_MMBR_BITNUM 0 /*** TBCR - Timebase Control Register; 0x00000051 ***/ typedef union { byte Byte; struct { byte :1; byte TBON :1; /* Timebase Enabled */ byte TBIE :1; /* Timebase Interrupt Enable */ byte TACK :1; /* Timebase ACKnowledge */ byte TBR0 :1; /* Timebase Rate Selection Bit 0 */ byte TBR1 :1; /* Timebase Rate Selection Bit 1 */ byte TBR2 :1; /* Timebase Rate Selection Bit 2 */ byte TBIF :1; /* Timebase Interrupt Flag */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte grpTBR :3; byte :1; } MergedBits; } TBCRSTR; extern volatile TBCRSTR _TBCR @0x00000051; #define TBCR _TBCR.Byte #define TBCR_TBON _TBCR.Bits.TBON #define TBCR_TBIE _TBCR.Bits.TBIE #define TBCR_TACK _TBCR.Bits.TACK #define TBCR_TBR0 _TBCR.Bits.TBR0 #define TBCR_TBR1 _TBCR.Bits.TBR1 #define TBCR_TBR2 _TBCR.Bits.TBR2 #define TBCR_TBIF _TBCR.Bits.TBIF #define TBCR_TBR _TBCR.MergedBits.grpTBR #define TBCR_TBON_MASK 2 #define TBCR_TBIE_MASK 4 #define TBCR_TACK_MASK 8 #define TBCR_TBR0_MASK 16 #define TBCR_TBR1_MASK 32 #define TBCR_TBR2_MASK 64 #define TBCR_TBIF_MASK 128 #define TBCR_TBR_MASK 112 #define TBCR_TBR_BITNUM 4 /*** ADSCR - ADC Status and Control Register; 0x00000057 ***/ typedef union { byte Byte; struct { byte ADCH0 :1; /* ADC Channel Select Bit 0 */ byte ADCH1 :1; /* ADC Channel Select Bit 1 */ byte ADCH2 :1; /* ADC Channel Select Bit 2 */ byte ADCH3 :1; /* ADC Channel Select Bit 3 */ byte ADCH4 :1; /* ADC Channel Select Bit 4 */ byte ADCO :1; /* ADC Continuous Conversion Bit */ byte AIEN :1; /* ADC Interrupt Enable Bit */ byte COCO :1; /* Conversions Complete Bit */ } Bits; struct { byte grpADCH :5; byte :1; byte :1; byte :1; } MergedBits; } ADSCRSTR; extern volatile ADSCRSTR _ADSCR @0x00000057; #define ADSCR _ADSCR.Byte #define ADSCR_ADCH0 _ADSCR.Bits.ADCH0 #define ADSCR_ADCH1 _ADSCR.Bits.ADCH1 #define ADSCR_ADCH2 _ADSCR.Bits.ADCH2 #define ADSCR_ADCH3 _ADSCR.Bits.ADCH3 #define ADSCR_ADCH4 _ADSCR.Bits.ADCH4 #define ADSCR_ADCO _ADSCR.Bits.ADCO #define ADSCR_AIEN _ADSCR.Bits.AIEN #define ADSCR_COCO _ADSCR.Bits.COCO #define ADSCR_ADCH _ADSCR.MergedBits.grpADCH #define ADSCR_ADCH0_MASK 1 #define ADSCR_ADCH1_MASK 2 #define ADSCR_ADCH2_MASK 4 #define ADSCR_ADCH3_MASK 8 #define ADSCR_ADCH4_MASK 16 #define ADSCR_ADCO_MASK 32 #define ADSCR_AIEN_MASK 64 #define ADSCR_COCO_MASK 128 #define ADSCR_ADCH_MASK 31 #define ADSCR_ADCH_BITNUM 0 /*** ADICLK - ADC Input Clock Register; 0x00000058 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte MODE0 :1; /* Mode of Result Justification Bit 0 */ byte MODE1 :1; /* Mode of Result Justification Bit 1 */ byte ADICLK_BIT :1; /* ADC Input Clock Register Bit */ byte ADIV0 :1; /* ADC Clock Prescaler Bit 0 */ byte ADIV1 :1; /* ADC Clock Prescaler Bit 1 */ byte ADIV2 :1; /* ADC Clock Prescaler Bit 2 */ } Bits; struct { byte :1; byte :1; byte grpMODE :2; byte :1; byte grpADIV :3; } MergedBits; } ADICLKSTR; extern volatile ADICLKSTR _ADICLK @0x00000058; #define ADICLK _ADICLK.Byte #define ADICLK_MODE0 _ADICLK.Bits.MODE0 #define ADICLK_MODE1 _ADICLK.Bits.MODE1 #define ADICLK_ADICLK_BIT _ADICLK.Bits.ADICLK_BIT #define ADICLK_ADIV0 _ADICLK.Bits.ADIV0 #define ADICLK_ADIV1 _ADICLK.Bits.ADIV1 #define ADICLK_ADIV2 _ADICLK.Bits.ADIV2 #define ADICLK_MODE _ADICLK.MergedBits.grpMODE #define ADICLK_ADIV _ADICLK.MergedBits.grpADIV #define ADICLK_MODE0_MASK 4 #define ADICLK_MODE1_MASK 8 #define ADICLK_ADICLK_BIT_MASK 16 #define ADICLK_ADIV0_MASK 32 #define ADICLK_ADIV1_MASK 64 #define ADICLK_ADIV2_MASK 128 #define ADICLK_MODE_MASK 12 #define ADICLK_MODE_BITNUM 2 #define ADICLK_ADIV_MASK 224 #define ADICLK_ADIV_BITNUM 5 /*** ADR0 - ADC Data Register High; 0x00000059 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADR0H - ADC Data Register High 0; 0x00000059 ***/ union { byte Byte; struct { byte AD8 :1; /* ADC Data Bit 8 */ byte AD9 :1; /* ADC Data Bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpAD_8 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADR0HSTR; #define ADR0H _ADR0.Overlap_STR.ADR0HSTR.Byte #define ADR0H_AD8 _ADR0.Overlap_STR.ADR0HSTR.Bits.AD8 #define ADR0H_AD9 _ADR0.Overlap_STR.ADR0HSTR.Bits.AD9 #define ADR0H_AD_8 _ADR0.Overlap_STR.ADR0HSTR.MergedBits.grpAD_8 #define ADR0H_AD ADR0H_AD_8 #define ADR0H_AD8_MASK 1 #define ADR0H_AD9_MASK 2 #define ADR0H_AD_8_MASK 3 #define ADR0H_AD_8_BITNUM 0 /*** ADR0L - ADC Data Register Low 0; 0x0000005A ***/ union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADR0LSTR; #define ADR0L _ADR0.Overlap_STR.ADR0LSTR.Byte #define ADR0L_AD0 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD0 #define ADR0L_AD1 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD1 #define ADR0L_AD2 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD2 #define ADR0L_AD3 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD3 #define ADR0L_AD4 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD4 #define ADR0L_AD5 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD5 #define ADR0L_AD6 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD6 #define ADR0L_AD7 _ADR0.Overlap_STR.ADR0LSTR.Bits.AD7 #define ADR0L_AD0_MASK 1 #define ADR0L_AD1_MASK 2 #define ADR0L_AD2_MASK 4 #define ADR0L_AD3_MASK 8 #define ADR0L_AD4_MASK 16 #define ADR0L_AD5_MASK 32 #define ADR0L_AD6_MASK 64 #define ADR0L_AD7_MASK 128 } Overlap_STR; } ADR0STR; extern volatile ADR0STR _ADR0 @0x00000059; #define ADR0 _ADR0.Word /*** ADR1L - ADC Data Register Low 1; 0x0000005B ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADR1LSTR; extern volatile ADR1LSTR _ADR1L @0x0000005B; #define ADR1L _ADR1L.Byte #define ADR1L_AD0 _ADR1L.Bits.AD0 #define ADR1L_AD1 _ADR1L.Bits.AD1 #define ADR1L_AD2 _ADR1L.Bits.AD2 #define ADR1L_AD3 _ADR1L.Bits.AD3 #define ADR1L_AD4 _ADR1L.Bits.AD4 #define ADR1L_AD5 _ADR1L.Bits.AD5 #define ADR1L_AD6 _ADR1L.Bits.AD6 #define ADR1L_AD7 _ADR1L.Bits.AD7 #define ADR1L_AD0_MASK 1 #define ADR1L_AD1_MASK 2 #define ADR1L_AD2_MASK 4 #define ADR1L_AD3_MASK 8 #define ADR1L_AD4_MASK 16 #define ADR1L_AD5_MASK 32 #define ADR1L_AD6_MASK 64 #define ADR1L_AD7_MASK 128 /*** ADR2L - ADC Data Register Low 2; 0x0000005C ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADR2LSTR; extern volatile ADR2LSTR _ADR2L @0x0000005C; #define ADR2L _ADR2L.Byte #define ADR2L_AD0 _ADR2L.Bits.AD0 #define ADR2L_AD1 _ADR2L.Bits.AD1 #define ADR2L_AD2 _ADR2L.Bits.AD2 #define ADR2L_AD3 _ADR2L.Bits.AD3 #define ADR2L_AD4 _ADR2L.Bits.AD4 #define ADR2L_AD5 _ADR2L.Bits.AD5 #define ADR2L_AD6 _ADR2L.Bits.AD6 #define ADR2L_AD7 _ADR2L.Bits.AD7 #define ADR2L_AD0_MASK 1 #define ADR2L_AD1_MASK 2 #define ADR2L_AD2_MASK 4 #define ADR2L_AD3_MASK 8 #define ADR2L_AD4_MASK 16 #define ADR2L_AD5_MASK 32 #define ADR2L_AD6_MASK 64 #define ADR2L_AD7_MASK 128 /*** ADR3L - ADC Data Register Low 3; 0x0000005D ***/ typedef union { byte Byte; struct { byte AD0 :1; /* ADC Data Bit 0 */ byte AD1 :1; /* ADC Data Bit 1 */ byte AD2 :1; /* ADC Data Bit 2 */ byte AD3 :1; /* ADC Data Bit 3 */ byte AD4 :1; /* ADC Data Bit 4 */ byte AD5 :1; /* ADC Data Bit 5 */ byte AD6 :1; /* ADC Data Bit 6 */ byte AD7 :1; /* ADC Data Bit 7 */ } Bits; } ADR3LSTR; extern volatile ADR3LSTR _ADR3L @0x0000005D; #define ADR3L _ADR3L.Byte #define ADR3L_AD0 _ADR3L.Bits.AD0 #define ADR3L_AD1 _ADR3L.Bits.AD1 #define ADR3L_AD2 _ADR3L.Bits.AD2 #define ADR3L_AD3 _ADR3L.Bits.AD3 #define ADR3L_AD4 _ADR3L.Bits.AD4 #define ADR3L_AD5 _ADR3L.Bits.AD5 #define ADR3L_AD6 _ADR3L.Bits.AD6 #define ADR3L_AD7 _ADR3L.Bits.AD7 #define ADR3L_AD0_MASK 1 #define ADR3L_AD1_MASK 2 #define ADR3L_AD2_MASK 4 #define ADR3L_AD3_MASK 8 #define ADR3L_AD4_MASK 16 #define ADR3L_AD5_MASK 32 #define ADR3L_AD6_MASK 64 #define ADR3L_AD7_MASK 128 /*** ADASCR - ADC Auto-Scan Control Register; 0x0000005E ***/ typedef union { byte Byte; struct { byte ASCAN :1; /* Auto-Scan Mode Enable */ byte AUTO0 :1; /* Auto-Scan Mode Channel Select Bit 0 */ byte AUTO1 :1; /* Auto-Scan Mode Channel Select Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte :1; byte grpAUTO :2; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADASCRSTR; extern volatile ADASCRSTR _ADASCR @0x0000005E; #define ADASCR _ADASCR.Byte #define ADASCR_ASCAN _ADASCR.Bits.ASCAN #define ADASCR_AUTO0 _ADASCR.Bits.AUTO0 #define ADASCR_AUTO1 _ADASCR.Bits.AUTO1 #define ADASCR_AUTO _ADASCR.MergedBits.grpAUTO #define ADASCR_ASCAN_MASK 1 #define ADASCR_AUTO0_MASK 2 #define ADASCR_AUTO1_MASK 4 #define ADASCR_AUTO_MASK 6 #define ADASCR_AUTO_BITNUM 1 /*** SBSR - SIM Break Status Register; 0x0000FE00 ***/ typedef union { byte Byte; struct { byte :1; byte SBSW :1; /* SIM Break Stop/Wait */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } SBSRSTR; extern volatile SBSRSTR _SBSR @0x0000FE00; #define SBSR _SBSR.Byte #define SBSR_SBSW _SBSR.Bits.SBSW #define SBSR_SBSW_MASK 2 /*** SRSR - SIM Reset Status Register; 0x0000FE01 ***/ typedef union { byte Byte; struct { byte :1; byte LVI :1; /* Low-Voltage Inhibit Reset Bit */ byte MODRST :1; /* Monitor Mode Entry Module Reset Bit */ byte ILAD :1; /* Illegal Address Reset Bit */ byte ILOP :1; /* Illegal Opcode Reset Bit */ byte COP :1; /* Computer Operating Properly Reset Bit */ byte PIN :1; /* External Reset Bit */ byte POR :1; /* Power-On Reset Bit */ } Bits; } SRSRSTR; extern volatile SRSRSTR _SRSR @0x0000FE01; #define SRSR _SRSR.Byte #define SRSR_LVI _SRSR.Bits.LVI #define SRSR_MODRST _SRSR.Bits.MODRST #define SRSR_ILAD _SRSR.Bits.ILAD #define SRSR_ILOP _SRSR.Bits.ILOP #define SRSR_COP _SRSR.Bits.COP #define SRSR_PIN _SRSR.Bits.PIN #define SRSR_POR _SRSR.Bits.POR #define SRSR_LVI_MASK 2 #define SRSR_MODRST_MASK 4 #define SRSR_ILAD_MASK 8 #define SRSR_ILOP_MASK 16 #define SRSR_COP_MASK 32 #define SRSR_PIN_MASK 64 #define SRSR_POR_MASK 128 /*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BCFE :1; /* Break Clear Flag Enable Bit */ } Bits; } SBFCRSTR; extern volatile SBFCRSTR _SBFCR @0x0000FE03; #define SBFCR _SBFCR.Byte #define SBFCR_BCFE _SBFCR.Bits.BCFE #define SBFCR_BCFE_MASK 128 /*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte IF1 :1; /* Interrupt Flag 1 */ byte IF2 :1; /* Interrupt Flag 2 */ byte IF3 :1; /* Interrupt Flag 3 */ byte IF4 :1; /* Interrupt Flag 4 */ byte IF5 :1; /* Interrupt Flag 5 */ byte IF6 :1; /* Interrupt Flag 6 */ } Bits; struct { byte :1; byte :1; byte grpIF_1 :6; } MergedBits; } INT1STR; extern volatile INT1STR _INT1 @0x0000FE04; #define INT1 _INT1.Byte #define INT1_IF1 _INT1.Bits.IF1 #define INT1_IF2 _INT1.Bits.IF2 #define INT1_IF3 _INT1.Bits.IF3 #define INT1_IF4 _INT1.Bits.IF4 #define INT1_IF5 _INT1.Bits.IF5 #define INT1_IF6 _INT1.Bits.IF6 #define INT1_IF_1 _INT1.MergedBits.grpIF_1 #define INT1_IF INT1_IF_1 #define INT1_IF1_MASK 4 #define INT1_IF2_MASK 8 #define INT1_IF3_MASK 16 #define INT1_IF4_MASK 32 #define INT1_IF5_MASK 64 #define INT1_IF6_MASK 128 #define INT1_IF_1_MASK 252 #define INT1_IF_1_BITNUM 2 /*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***/ typedef union { byte Byte; struct { byte IF7 :1; /* Interrupt Flag 7 */ byte IF8 :1; /* Interrupt Flag 8 */ byte IF9 :1; /* Interrupt Flag 9 */ byte IF10 :1; /* Interrupt Flag 10 */ byte IF11 :1; /* Interrupt Flag 11 */ byte IF12 :1; /* Interrupt Flag 12 */ byte IF13 :1; /* Interrupt Flag 13 */ byte IF14 :1; /* Interrupt Flag 14 */ } Bits; } INT2STR; extern volatile INT2STR _INT2 @0x0000FE05; #define INT2 _INT2.Byte #define INT2_IF7 _INT2.Bits.IF7 #define INT2_IF8 _INT2.Bits.IF8 #define INT2_IF9 _INT2.Bits.IF9 #define INT2_IF10 _INT2.Bits.IF10 #define INT2_IF11 _INT2.Bits.IF11 #define INT2_IF12 _INT2.Bits.IF12 #define INT2_IF13 _INT2.Bits.IF13 #define INT2_IF14 _INT2.Bits.IF14 #define INT2_IF7_MASK 1 #define INT2_IF8_MASK 2 #define INT2_IF9_MASK 4 #define INT2_IF10_MASK 8 #define INT2_IF11_MASK 16 #define INT2_IF12_MASK 32 #define INT2_IF13_MASK 64 #define INT2_IF14_MASK 128 /*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***/ typedef union { byte Byte; struct { byte IF15 :1; /* Interrupt Flag 15 */ byte IF16 :1; /* Interrupt Flag 16 */ byte IF17 :1; /* Interrupt Flag 17 */ byte IF18 :1; /* Interrupt Flag 18 */ byte IF19 :1; /* Interrupt Flag 19 */ byte IF20 :1; /* Interrupt Flag 20 */ byte IF21 :1; /* Interrupt Flag 21 */ byte :1; } Bits; struct { byte grpIF_15 :7; byte :1; } MergedBits; } INT3STR; extern volatile INT3STR _INT3 @0x0000FE06; #define INT3 _INT3.Byte #define INT3_IF15 _INT3.Bits.IF15 #define INT3_IF16 _INT3.Bits.IF16 #define INT3_IF17 _INT3.Bits.IF17 #define INT3_IF18 _INT3.Bits.IF18 #define INT3_IF19 _INT3.Bits.IF19 #define INT3_IF20 _INT3.Bits.IF20 #define INT3_IF21 _INT3.Bits.IF21 #define INT3_IF_15 _INT3.MergedBits.grpIF_15 #define INT3_IF INT3_IF_15 #define INT3_IF15_MASK 1 #define INT3_IF16_MASK 2 #define INT3_IF17_MASK 4 #define INT3_IF18_MASK 8 #define INT3_IF19_MASK 16 #define INT3_IF20_MASK 32 #define INT3_IF21_MASK 64 #define INT3_IF_15_MASK 127 #define INT3_IF_15_BITNUM 0 /*** FLCR - FLASH Control Register; 0x0000FE08 ***/ typedef union { byte Byte; struct { byte PGM :1; /* Program Control Bit */ byte ERASE :1; /* Erase Control Bit */ byte MASS :1; /* Mass Erase Control Bit */ byte HVEN :1; /* High-Voltage Enable Bit */ byte :1; byte :1; byte :1; byte :1; } Bits; } FLCRSTR; extern volatile FLCRSTR _FLCR @0x0000FE08; #define FLCR _FLCR.Byte #define FLCR_PGM _FLCR.Bits.PGM #define FLCR_ERASE _FLCR.Bits.ERASE #define FLCR_MASS _FLCR.Bits.MASS #define FLCR_HVEN _FLCR.Bits.HVEN #define FLCR_PGM_MASK 1 #define FLCR_ERASE_MASK 2 #define FLCR_MASS_MASK 4 #define FLCR_HVEN_MASK 8 /*** FLBPR - FLASH Block Protect Register; 0x0000FE09 ***/ typedef union { byte Byte; struct { byte BPR0 :1; /* FLASH Block Protect Bit 0 */ byte BPR1 :1; /* FLASH Block Protect Bit 1 */ byte BPR2 :1; /* FLASH Block Protect Bit 2 */ byte BPR3 :1; /* FLASH Block Protect Bit 3 */ byte BPR4 :1; /* FLASH Block Protect Bit 4 */ byte BPR5 :1; /* FLASH Block Protect Bit 5 */ byte BPR6 :1; /* FLASH Block Protect Bit 6 */ byte BPR7 :1; /* FLASH Block Protect Bit 7 */ } Bits; } FLBPRSTR; extern volatile FLBPRSTR _FLBPR @0x0000FE09; #define FLBPR _FLBPR.Byte #define FLBPR_BPR0 _FLBPR.Bits.BPR0 #define FLBPR_BPR1 _FLBPR.Bits.BPR1 #define FLBPR_BPR2 _FLBPR.Bits.BPR2 #define FLBPR_BPR3 _FLBPR.Bits.BPR3 #define FLBPR_BPR4 _FLBPR.Bits.BPR4 #define FLBPR_BPR5 _FLBPR.Bits.BPR5 #define FLBPR_BPR6 _FLBPR.Bits.BPR6 #define FLBPR_BPR7 _FLBPR.Bits.BPR7 #define FLBPR_BPR0_MASK 1 #define FLBPR_BPR1_MASK 2 #define FLBPR_BPR2_MASK 4 #define FLBPR_BPR3_MASK 8 #define FLBPR_BPR4_MASK 16 #define FLBPR_BPR5_MASK 32 #define FLBPR_BPR6_MASK 64 #define FLBPR_BPR7_MASK 128 /*** BRK - Break Address Register; 0x0000FE0C ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** BRKH - Break Address High Register; 0x0000FE0C ***/ union { byte Byte; struct { byte MUL8 :1; /* Break Address Register Bit 8 */ byte MUL9 :1; /* Break Address Register Bit 9 */ byte MUL10 :1; /* Break Address Register Bit 10 */ byte MUL11 :1; /* Break Address Register Bit 11 */ byte MUL12 :1; /* Break Address Register Bit 12 */ byte MUL13 :1; /* Break Address Register Bit 13 */ byte MUL14 :1; /* Break Address Register Bit 14 */ byte MUL15 :1; /* Break Address Register Bit 15 */ } Bits; } BRKHSTR; #define BRKH _BRK.Overlap_STR.BRKHSTR.Byte #define BRKH_MUL8 _BRK.Overlap_STR.BRKHSTR.Bits.MUL8 #define BRKH_MUL9 _BRK.Overlap_STR.BRKHSTR.Bits.MUL9 #define BRKH_MUL10 _BRK.Overlap_STR.BRKHSTR.Bits.MUL10 #define BRKH_MUL11 _BRK.Overlap_STR.BRKHSTR.Bits.MUL11 #define BRKH_MUL12 _BRK.Overlap_STR.BRKHSTR.Bits.MUL12 #define BRKH_MUL13 _BRK.Overlap_STR.BRKHSTR.Bits.MUL13 #define BRKH_MUL14 _BRK.Overlap_STR.BRKHSTR.Bits.MUL14 #define BRKH_MUL15 _BRK.Overlap_STR.BRKHSTR.Bits.MUL15 #define BRKH_MUL8_MASK 1 #define BRKH_MUL9_MASK 2 #define BRKH_MUL10_MASK 4 #define BRKH_MUL11_MASK 8 #define BRKH_MUL12_MASK 16 #define BRKH_MUL13_MASK 32 #define BRKH_MUL14_MASK 64 #define BRKH_MUL15_MASK 128 /*** BRKL - Break Address Low Register; 0x0000FE0D ***/ union { byte Byte; struct { byte MUL0 :1; /* Break Address Register Bit 0 */ byte MUL1 :1; /* Break Address Register Bit 1 */ byte MUL2 :1; /* Break Address Register Bit 2 */ byte MUL3 :1; /* Break Address Register Bit 3 */ byte MUL4 :1; /* Break Address Register Bit 4 */ byte MUL5 :1; /* Break Address Register Bit 5 */ byte MUL6 :1; /* Break Address Register Bit 6 */ byte MUL7 :1; /* Break Address Register Bit 7 */ } Bits; } BRKLSTR; #define BRKL _BRK.Overlap_STR.BRKLSTR.Byte #define BRKL_MUL0 _BRK.Overlap_STR.BRKLSTR.Bits.MUL0 #define BRKL_MUL1 _BRK.Overlap_STR.BRKLSTR.Bits.MUL1 #define BRKL_MUL2 _BRK.Overlap_STR.BRKLSTR.Bits.MUL2 #define BRKL_MUL3 _BRK.Overlap_STR.BRKLSTR.Bits.MUL3 #define BRKL_MUL4 _BRK.Overlap_STR.BRKLSTR.Bits.MUL4 #define BRKL_MUL5 _BRK.Overlap_STR.BRKLSTR.Bits.MUL5 #define BRKL_MUL6 _BRK.Overlap_STR.BRKLSTR.Bits.MUL6 #define BRKL_MUL7 _BRK.Overlap_STR.BRKLSTR.Bits.MUL7 #define BRKL_MUL0_MASK 1 #define BRKL_MUL1_MASK 2 #define BRKL_MUL2_MASK 4 #define BRKL_MUL3_MASK 8 #define BRKL_MUL4_MASK 16 #define BRKL_MUL5_MASK 32 #define BRKL_MUL6_MASK 64 #define BRKL_MUL7_MASK 128 } Overlap_STR; } BRKSTR; extern volatile BRKSTR _BRK @0x0000FE0C; #define BRK _BRK.Word /*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte BRKA :1; /* Break Active Bit */ byte BRKE :1; /* Break Enable Bit */ } Bits; } BRKSCRSTR; extern volatile BRKSCRSTR _BRKSCR @0x0000FE0E; #define BRKSCR _BRKSCR.Byte #define BRKSCR_BRKA _BRKSCR.Bits.BRKA #define BRKSCR_BRKE _BRKSCR.Bits.BRKE #define BRKSCR_BRKA_MASK 64 #define BRKSCR_BRKE_MASK 128 /*** LVISR - LVI Status Register; 0x0000FE0F ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LVIOUT :1; /* LVI Output Bit */ } Bits; } LVISRSTR; extern volatile LVISRSTR _LVISR @0x0000FE0F; #define LVISR _LVISR.Byte #define LVISR_LVIOUT _LVISR.Bits.LVIOUT #define LVISR_LVIOUT_MASK 128 /*** MOR - Mask Option Register; 0x0000FFCF ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte OSCSEL0 :1; /* Oscillator Selection Bit 0 */ byte OSCSEL1 :1; /* Oscillator Selection Bit 1 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte grpOSCSEL :2; } MergedBits; } MORSTR; /* Tip for register initialization in the user code: const byte MOR_INIT @0x0000FFCF = ; */ #define _MOR (*(const MORSTR * __far)0x0000FFCF) #define MOR _MOR.Byte #define MOR_OSCSEL0 _MOR.Bits.OSCSEL0 #define MOR_OSCSEL1 _MOR.Bits.OSCSEL1 #define MOR_OSCSEL _MOR.MergedBits.grpOSCSEL #define MOR_OSCSEL0_MASK 64 #define MOR_OSCSEL1_MASK 128 #define MOR_OSCSEL_MASK 192 #define MOR_OSCSEL_BITNUM 6 /*** COPCTL - COP Control Register; 0x0000FFFF ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Bit 0 */ byte BIT1 :1; /* Bit 1 */ byte BIT2 :1; /* Bit 2 */ byte BIT3 :1; /* Bit 3 */ byte BIT4 :1; /* Bit 4 */ byte BIT5 :1; /* Bit 5 */ byte BIT6 :1; /* Bit 6 */ byte BIT7 :1; /* Bit 7 */ } Bits; } COPCTLSTR; extern volatile COPCTLSTR _COPCTL @0x0000FFFF; #define COPCTL _COPCTL.Byte #define COPCTL_BIT0 _COPCTL.Bits.BIT0 #define COPCTL_BIT1 _COPCTL.Bits.BIT1 #define COPCTL_BIT2 _COPCTL.Bits.BIT2 #define COPCTL_BIT3 _COPCTL.Bits.BIT3 #define COPCTL_BIT4 _COPCTL.Bits.BIT4 #define COPCTL_BIT5 _COPCTL.Bits.BIT5 #define COPCTL_BIT6 _COPCTL.Bits.BIT6 #define COPCTL_BIT7 _COPCTL.Bits.BIT7 #define COPCTL_BIT0_MASK 1 #define COPCTL_BIT1_MASK 2 #define COPCTL_BIT2_MASK 4 #define COPCTL_BIT3_MASK 8 #define COPCTL_BIT4_MASK 16 #define COPCTL_BIT5_MASK 32 #define COPCTL_BIT6_MASK 64 #define COPCTL_BIT7_MASK 128 /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------------------------------- Exceptions in bit names of timer status and control registers due to backward compatibility with previous releases */ #define T1SC0_CHxMAX _T1SC0.Bits.CH0MAX #define T1SC0_TOVx _T1SC0.Bits.TOV0 #define T1SC0_ELSxA _T1SC0.Bits.ELS0A #define T1SC0_ELSxB _T1SC0.Bits.ELS0B #define T1SC0_MSxA _T1SC0.Bits.MS0A #define T1SC0_MSxB _T1SC0.Bits.MS0B #define T1SC0_CHxIE _T1SC0.Bits.CH0IE #define T1SC0_CHxF _T1SC0.Bits.CH0F #define T1SC1_CHxMAX _T1SC1.Bits.CH1MAX #define T1SC1_TOVx _T1SC1.Bits.TOV1 #define T1SC1_ELSxA _T1SC1.Bits.ELS1A #define T1SC1_ELSxB _T1SC1.Bits.ELS1B #define T1SC1_MSxA _T1SC1.Bits.MS1A #define T1SC1_CHxIE _T1SC1.Bits.CH1IE #define T1SC1_CHxF _T1SC1.Bits.CH1F #define T2SC0_CHxMAX _T2SC0.Bits.CH0MAX #define T2SC0_TOVx _T2SC0.Bits.TOV0 #define T2SC0_ELSxA _T2SC0.Bits.ELS0A #define T2SC0_ELSxB _T2SC0.Bits.ELS0B #define T2SC0_MSxA _T2SC0.Bits.MS0A #define T2SC0_MSxB _T2SC0.Bits.MS0B #define T2SC0_CHxIE _T2SC0.Bits.CH0IE #define T2SC0_CHxF _T2SC0.Bits.CH0F #define T2SC1_CHxMAX _T2SC1.Bits.CH1MAX #define T2SC1_TOVx _T2SC1.Bits.TOV1 #define T2SC1_ELSxA _T2SC1.Bits.ELS1A #define T2SC1_ELSxB _T2SC1.Bits.ELS1B #define T2SC1_MSxA _T2SC1.Bits.MS1A #define T2SC1_CHxIE _T2SC1.Bits.CH1IE #define T2SC1_CHxF _T2SC1.Bits.CH1F /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 11.9.2009 12:42:32 */ #define T1CH_ARR This_symb_has_been_depreciated #define T2CH_ARR This_symb_has_been_depreciated #endif