; Based on CPU DB SC9S08IA4_8, version 3.00.000 (RegistersPrg V2.29) ; ################################################################### ; Filename : sc9s08ia4.inc ; Processor : SC9S08IA4CSC ; FileFormat: V2.29 ; DataSheet : SC9S08IA4 Rev. 1 7/2009 ; Compiler : CodeWarrior compiler ; Date/Time : 25.8.2009, 15:42 ; Abstract : ; This header implements the mapping of I/O devices. ; ; Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ; ; http : www.freescale.com ; mail : support@freescale.com ; ; CPU Registers Revisions: ; - none ; ; File-Format-Revisions: ; - none ; ; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ; derivative device. To avoid extra current drain from floating input pins, the user’s reset ; initialization routine in the application program must either enable on-chip pull-up devices ; or change the direction of unconnected pins to outputs so the pins do not float. ; ################################################################### ;*** Memory Map and Interrupt Vectors ;****************************************** ROMStart: equ $0000F000 ROMEnd: equ $0000FFA9 Z_RAMStart: equ $00000060 Z_RAMEnd: equ $000000FF RAMStart: equ $00000100 RAMEnd: equ $0000015F ROM1Start: equ $0000FFC0 ROM1End: equ $0000FFCF ; Vrti: equ $0000FFD0 VReserved22: equ $0000FFD2 VReserved21: equ $0000FFD4 VReserved20: equ $0000FFD6 Vadc1: equ $0000FFD8 Vkeyboard1: equ $0000FFDA VReserved17: equ $0000FFDC VReserved16: equ $0000FFDE VReserved15: equ $0000FFE0 VReserved14: equ $0000FFE2 VReserved13: equ $0000FFE4 VReserved12: equ $0000FFE6 VReserved11: equ $0000FFE8 Vtpm2ovf: equ $0000FFEA VReserved9: equ $0000FFEC Vtpm2ch0: equ $0000FFEE Vtpm1ovf: equ $0000FFF0 Vtpm1ch1: equ $0000FFF2 Vtpm1ch0: equ $0000FFF4 VReserved4: equ $0000FFF6 Virq: equ $0000FFF8 Vlvd: equ $0000FFFA Vswi: equ $0000FFFC Vreset: equ $0000FFFE ; ;*** PTAD - Port A Data Register; 0x00000000 *** PTAD: equ $00000000 ;*** PTAD - Port A Data Register; 0x00000000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0 PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1 PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2 PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3 PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4 PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5 ; bit position masks mPTAD_PTAD0: equ %00000001 mPTAD_PTAD1: equ %00000010 mPTAD_PTAD2: equ %00000100 mPTAD_PTAD3: equ %00001000 mPTAD_PTAD4: equ %00010000 mPTAD_PTAD5: equ %00100000 ;*** PTADD - Port A Data Direction Register; 0x00000001 *** PTADD: equ $00000001 ;*** PTADD - Port A Data Direction Register; 0x00000001 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0 PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1 PTADD_PTADD2: equ 2 ; Data Direction for Port A Bit 2 PTADD_PTADD3: equ 3 ; Data Direction for Port A Bit 3 PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4 PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5 ; bit position masks mPTADD_PTADD0: equ %00000001 mPTADD_PTADD1: equ %00000010 mPTADD_PTADD2: equ %00000100 mPTADD_PTADD3: equ %00001000 mPTADD_PTADD4: equ %00010000 mPTADD_PTADD5: equ %00100000 ;*** KBISC - KBI Status and Control Register; 0x0000000C *** KBISC: equ $0000000C ;*** KBISC - KBI Status and Control Register; 0x0000000C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBISC_KBIMOD: equ 0 ; Keyboard Detection Mode KBISC_KBIE: equ 1 ; Keyboard Interrupt Enable KBISC_KBACK: equ 2 ; Keyboard Interrupt Acknowledge KBISC_KBF: equ 3 ; Keyboard Interrupt Flag ; bit position masks mKBISC_KBIMOD: equ %00000001 mKBISC_KBIE: equ %00000010 mKBISC_KBACK: equ %00000100 mKBISC_KBF: equ %00001000 ;*** KBIPE - KBI Pin Enable Register; 0x0000000D *** KBIPE: equ $0000000D ;*** KBIPE - KBI Pin Enable Register; 0x0000000D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBIPE_KBIPE0: equ 0 ; Keyboard Pin Enable for KBI Port Bit 0 KBIPE_KBIPE1: equ 1 ; Keyboard Pin Enable for KBI Port Bit 1 KBIPE_KBIPE2: equ 2 ; Keyboard Pin Enable for KBI Port Bit 2 KBIPE_KBIPE3: equ 3 ; Keyboard Pin Enable for KBI Port Bit 3 KBIPE_KBIPE4: equ 4 ; Keyboard Pin Enable for KBI Port Bit 4 KBIPE_KBIPE5: equ 5 ; Keyboard Pin Enable for KBI Port Bit 5 KBIPE_KBIPE6: equ 6 ; Keyboard Pin Enable for KBI Port Bit 6 KBIPE_KBIPE7: equ 7 ; Keyboard Pin Enable for KBI Port Bit 7 ; bit position masks mKBIPE_KBIPE0: equ %00000001 mKBIPE_KBIPE1: equ %00000010 mKBIPE_KBIPE2: equ %00000100 mKBIPE_KBIPE3: equ %00001000 mKBIPE_KBIPE4: equ %00010000 mKBIPE_KBIPE5: equ %00100000 mKBIPE_KBIPE6: equ %01000000 mKBIPE_KBIPE7: equ %10000000 ;*** KBIES - KBI Edge Select Register; 0x0000000E *** KBIES: equ $0000000E ;*** KBIES - KBI Edge Select Register; 0x0000000E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBIES_KBEDG0: equ 0 ; Keyboard Edge Select Bit 0 KBIES_KBEDG1: equ 1 ; Keyboard Edge Select Bit 1 KBIES_KBEDG2: equ 2 ; Keyboard Edge Select Bit 2 KBIES_KBEDG3: equ 3 ; Keyboard Edge Select Bit 3 KBIES_KBEDG4: equ 4 ; Keyboard Edge Select Bit 4 KBIES_KBEDG5: equ 5 ; Keyboard Edge Select Bit 5 KBIES_KBEDG6: equ 6 ; Keyboard Edge Select Bit 6 KBIES_KBEDG7: equ 7 ; Keyboard Edge Select Bit 7 ; bit position masks mKBIES_KBEDG0: equ %00000001 mKBIES_KBEDG1: equ %00000010 mKBIES_KBEDG2: equ %00000100 mKBIES_KBEDG3: equ %00001000 mKBIES_KBEDG4: equ %00010000 mKBIES_KBEDG5: equ %00100000 mKBIES_KBEDG6: equ %01000000 mKBIES_KBEDG7: equ %10000000 ;*** IRQSC - Interrupt request status and control register; 0x0000000F *** IRQSC: equ $0000000F ;*** IRQSC - Interrupt request status and control register; 0x0000000F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRQSC_IRQMOD: equ 0 ; IRQ Detection Mode IRQSC_IRQIE: equ 1 ; IRQ Interrupt Enable IRQSC_IRQACK: equ 2 ; IRQ Acknowledge IRQSC_IRQF: equ 3 ; IRQ Flag IRQSC_IRQPE: equ 4 ; IRQ Pin Enable IRQSC_IRQEDG: equ 5 ; IRQ Edge Select IRQSC_IRQPDD: equ 6 ; IRQ Pull Device Disable ; bit position masks mIRQSC_IRQMOD: equ %00000001 mIRQSC_IRQIE: equ %00000010 mIRQSC_IRQACK: equ %00000100 mIRQSC_IRQF: equ %00001000 mIRQSC_IRQPE: equ %00010000 mIRQSC_IRQEDG: equ %00100000 mIRQSC_IRQPDD: equ %01000000 ;*** ADCSC1 - Status and Control Register 1; 0x00000010 *** ADCSC1: equ $00000010 ;*** ADCSC1 - Status and Control Register 1; 0x00000010 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC1_ADCH0: equ 0 ; Input Channel Select Bit 0 ADCSC1_ADCH1: equ 1 ; Input Channel Select Bit 1 ADCSC1_ADCH2: equ 2 ; Input Channel Select Bit 2 ADCSC1_ADCH3: equ 3 ; Input Channel Select Bit 3 ADCSC1_ADCH4: equ 4 ; Input Channel Select Bit 4 ADCSC1_ADCO: equ 5 ; Continuous Conversion Enable - ADCO is used to enable continuous conversions ADCSC1_AIEN: equ 6 ; Interrupt Enable - AIEN is used to enable conversion complete interrupts. When COCO becomes set while AIEN is high, an interrupt is asserted ADCSC1_COCO: equ 7 ; Conversion Complete Flag ; bit position masks mADCSC1_ADCH0: equ %00000001 mADCSC1_ADCH1: equ %00000010 mADCSC1_ADCH2: equ %00000100 mADCSC1_ADCH3: equ %00001000 mADCSC1_ADCH4: equ %00010000 mADCSC1_ADCO: equ %00100000 mADCSC1_AIEN: equ %01000000 mADCSC1_COCO: equ %10000000 ;*** ADCSC2 - Status and Control Register 2; 0x00000011 *** ADCSC2: equ $00000011 ;*** ADCSC2 - Status and Control Register 2; 0x00000011 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC2_ACFGT: equ 4 ; Compare Function Greater Than Enable ADCSC2_ACFE: equ 5 ; Compare Function Enable - ACFE is used to enable the compare function ADCSC2_ADTRG: equ 6 ; Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion ADCSC2_ADACT: equ 7 ; Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted ; bit position masks mADCSC2_ACFGT: equ %00010000 mADCSC2_ACFE: equ %00100000 mADCSC2_ADTRG: equ %01000000 mADCSC2_ADACT: equ %10000000 ;*** ADCR - Data Result Register; 0x00000012 *** ADCR: equ $00000012 ;*** ADCR - Data Result Register; 0x00000012 *** ;*** ADCRH - Data Result High Register; 0x00000012 *** ADCRH: equ $00000012 ;*** ADCRH - Data Result High Register; 0x00000012 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCRH_ADR8: equ 0 ; ADC Result Data Bit 8 ADCRH_ADR9: equ 1 ; ADC Result Data Bit 9 ; bit position masks mADCRH_ADR8: equ %00000001 mADCRH_ADR9: equ %00000010 ;*** ADCRL - Data Result Low Register; 0x00000013 *** ADCRL: equ $00000013 ;*** ADCRL - Data Result Low Register; 0x00000013 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCRL_ADR0: equ 0 ; ADC Result Data Bit 0 ADCRL_ADR1: equ 1 ; ADC Result Data Bit 1 ADCRL_ADR2: equ 2 ; ADC Result Data Bit 2 ADCRL_ADR3: equ 3 ; ADC Result Data Bit 3 ADCRL_ADR4: equ 4 ; ADC Result Data Bit 4 ADCRL_ADR5: equ 5 ; ADC Result Data Bit 5 ADCRL_ADR6: equ 6 ; ADC Result Data Bit 6 ADCRL_ADR7: equ 7 ; ADC Result Data Bit 7 ; bit position masks mADCRL_ADR0: equ %00000001 mADCRL_ADR1: equ %00000010 mADCRL_ADR2: equ %00000100 mADCRL_ADR3: equ %00001000 mADCRL_ADR4: equ %00010000 mADCRL_ADR5: equ %00100000 mADCRL_ADR6: equ %01000000 mADCRL_ADR7: equ %10000000 ;*** ADCCV - Compare Value Register; 0x00000014 *** ADCCV: equ $00000014 ;*** ADCCV - Compare Value Register; 0x00000014 *** ;*** ADCCVH - Compare Value High Register; 0x00000014 *** ADCCVH: equ $00000014 ;*** ADCCVH - Compare Value High Register; 0x00000014 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCVH_ADCV8: equ 0 ; Compare Function Value 8 ADCCVH_ADCV9: equ 1 ; Compare Function Value 9 ; bit position masks mADCCVH_ADCV8: equ %00000001 mADCCVH_ADCV9: equ %00000010 ;*** ADCCVL - Compare Value Low Register; 0x00000015 *** ADCCVL: equ $00000015 ;*** ADCCVL - Compare Value Low Register; 0x00000015 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCVL_ADCV0: equ 0 ; Compare Function Value 0 ADCCVL_ADCV1: equ 1 ; Compare Function Value 1 ADCCVL_ADCV2: equ 2 ; Compare Function Value 2 ADCCVL_ADCV3: equ 3 ; Compare Function Value 3 ADCCVL_ADCV4: equ 4 ; Compare Function Value 4 ADCCVL_ADCV5: equ 5 ; Compare Function Value 5 ADCCVL_ADCV6: equ 6 ; Compare Function Value 6 ADCCVL_ADCV7: equ 7 ; Compare Function Value 7 ; bit position masks mADCCVL_ADCV0: equ %00000001 mADCCVL_ADCV1: equ %00000010 mADCCVL_ADCV2: equ %00000100 mADCCVL_ADCV3: equ %00001000 mADCCVL_ADCV4: equ %00010000 mADCCVL_ADCV5: equ %00100000 mADCCVL_ADCV6: equ %01000000 mADCCVL_ADCV7: equ %10000000 ;*** ADCCFG - Configuration Register; 0x00000016 *** ADCCFG: equ $00000016 ;*** ADCCFG - Configuration Register; 0x00000016 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCFG_ADICLK0: equ 0 ; Input Clock Select Bit 0 ADCCFG_ADICLK1: equ 1 ; Input Clock Select Bit 1 ADCCFG_MODE0: equ 2 ; Conversion Mode Selection Bit 0 ADCCFG_MODE1: equ 3 ; Conversion Mode Selection Bit 1 ADCCFG_ADLSMP: equ 4 ; Long Sample Time Configuration ADCCFG_ADIV0: equ 5 ; Clock Divide Select Bit 0 ADCCFG_ADIV1: equ 6 ; Clock Divide Select Bit 1 ADCCFG_ADLPC: equ 7 ; Low Power Configuration ; bit position masks mADCCFG_ADICLK0: equ %00000001 mADCCFG_ADICLK1: equ %00000010 mADCCFG_MODE0: equ %00000100 mADCCFG_MODE1: equ %00001000 mADCCFG_ADLSMP: equ %00010000 mADCCFG_ADIV0: equ %00100000 mADCCFG_ADIV1: equ %01000000 mADCCFG_ADLPC: equ %10000000 ;*** APCTL1 - Pin Control 1 Register; 0x00000017 *** APCTL1: equ $00000017 ;*** APCTL1 - Pin Control 1 Register; 0x00000017 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET APCTL1_ADPC0: equ 0 ; ADC Pin Control 0 - ADPC0 is used to control the pin associated with channel AD0 APCTL1_ADPC1: equ 1 ; ADC Pin Control 1 - ADPC1 is used to control the pin associated with channel AD1 APCTL1_ADPC2: equ 2 ; ADC Pin Control 2 - ADPC2 is used to control the pin associated with channel AD2 APCTL1_ADPC3: equ 3 ; ADC Pin Control 3 - ADPC3 is used to control the pin associated with channel AD3 ; bit position masks mAPCTL1_ADPC0: equ %00000001 mAPCTL1_ADPC1: equ %00000010 mAPCTL1_ADPC2: equ %00000100 mAPCTL1_ADPC3: equ %00001000 ;*** TPM2SC - TPM2 Status and Control Register; 0x00000020 *** TPM2SC: equ $00000020 ;*** TPM2SC - TPM2 Status and Control Register; 0x00000020 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2SC_PS0: equ 0 ; Prescale Divisor Select Bit 0 TPM2SC_PS1: equ 1 ; Prescale Divisor Select Bit 1 TPM2SC_PS2: equ 2 ; Prescale Divisor Select Bit 2 TPM2SC_CLKSA: equ 3 ; Clock Source Select A TPM2SC_CLKSB: equ 4 ; Clock Source Select B TPM2SC_CPWMS: equ 5 ; Center-Aligned PWM Select TPM2SC_TOIE: equ 6 ; Timer Overflow Interrupt Enable TPM2SC_TOF: equ 7 ; Timer Overflow Flag ; bit position masks mTPM2SC_PS0: equ %00000001 mTPM2SC_PS1: equ %00000010 mTPM2SC_PS2: equ %00000100 mTPM2SC_CLKSA: equ %00001000 mTPM2SC_CLKSB: equ %00010000 mTPM2SC_CPWMS: equ %00100000 mTPM2SC_TOIE: equ %01000000 mTPM2SC_TOF: equ %10000000 ;*** TPM2CNT - TPM2 Timer Counter Register; 0x00000021 *** TPM2CNT: equ $00000021 ;*** TPM2CNT - TPM2 Timer Counter Register; 0x00000021 *** ;*** TPM2CNTH - TPM2 Timer Counter Register High; 0x00000021 *** TPM2CNTH: equ $00000021 ;*** TPM2CNTH - TPM2 Timer Counter Register High; 0x00000021 *** ;*** TPM2CNTL - TPM2 Timer Counter Register Low; 0x00000022 *** TPM2CNTL: equ $00000022 ;*** TPM2CNTL - TPM2 Timer Counter Register Low; 0x00000022 *** ;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000023 *** TPM2MOD: equ $00000023 ;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000023 *** ;*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0x00000023 *** TPM2MODH: equ $00000023 ;*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0x00000023 *** ;*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0x00000024 *** TPM2MODL: equ $00000024 ;*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0x00000024 *** ;*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0x00000025 *** TPM2C0SC: equ $00000025 ;*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0x00000025 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C0SC_ELS0A: equ 2 ; Edge/Level Select Bit A TPM2C0SC_ELS0B: equ 3 ; Edge/Level Select Bit B TPM2C0SC_MS0A: equ 4 ; Mode Select A for TPM Channel 0 TPM2C0SC_MS0B: equ 5 ; Mode Select B for TPM Channel 0 TPM2C0SC_CH0IE: equ 6 ; Channel 0 Interrupt Enable TPM2C0SC_CH0F: equ 7 ; Channel 0 Flag ; bit position masks mTPM2C0SC_ELS0A: equ %00000100 mTPM2C0SC_ELS0B: equ %00001000 mTPM2C0SC_MS0A: equ %00010000 mTPM2C0SC_MS0B: equ %00100000 mTPM2C0SC_CH0IE: equ %01000000 mTPM2C0SC_CH0F: equ %10000000 ;*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0x00000026 *** TPM2C0V: equ $00000026 ;*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0x00000026 *** ;*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0x00000026 *** TPM2C0VH: equ $00000026 ;*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0x00000026 *** ;*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0x00000027 *** TPM2C0VL: equ $00000027 ;*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0x00000027 *** ;*** ICSC1 - ICS Control Register 1; 0x00000038 *** ICSC1: equ $00000038 ;*** ICSC1 - ICS Control Register 1; 0x00000038 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSC1_IREFSTEN: equ 0 ; Internal Reference Stop Enable ICSC1_CLKS: equ 6 ; Clock Source Select ; bit position masks mICSC1_IREFSTEN: equ %00000001 mICSC1_CLKS: equ %01000000 ;*** ICSC2 - ICS Control Register 2; 0x00000039 *** ICSC2: equ $00000039 ;*** ICSC2 - ICS Control Register 2; 0x00000039 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSC2_LP: equ 3 ; Low Power Select ICSC2_BDIV0: equ 6 ; Bus Frequency Divider, bit 0 ICSC2_BDIV1: equ 7 ; Bus Frequency Divider, bit 1 ; bit position masks mICSC2_LP: equ %00001000 mICSC2_BDIV0: equ %01000000 mICSC2_BDIV1: equ %10000000 ;*** ICSTRM - ICS Trim Register; 0x0000003A *** ICSTRM: equ $0000003A ;*** ICSTRM - ICS Trim Register; 0x0000003A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSTRM_TRIM0: equ 0 ; ICS Trim Setting, bit 0 ICSTRM_TRIM1: equ 1 ; ICS Trim Setting, bit 1 ICSTRM_TRIM2: equ 2 ; ICS Trim Setting, bit 2 ICSTRM_TRIM3: equ 3 ; ICS Trim Setting, bit 3 ICSTRM_TRIM4: equ 4 ; ICS Trim Setting, bit 4 ICSTRM_TRIM5: equ 5 ; ICS Trim Setting, bit 5 ICSTRM_TRIM6: equ 6 ; ICS Trim Setting, bit 6 ICSTRM_TRIM7: equ 7 ; ICS Trim Setting, bit 7 ; bit position masks mICSTRM_TRIM0: equ %00000001 mICSTRM_TRIM1: equ %00000010 mICSTRM_TRIM2: equ %00000100 mICSTRM_TRIM3: equ %00001000 mICSTRM_TRIM4: equ %00010000 mICSTRM_TRIM5: equ %00100000 mICSTRM_TRIM6: equ %01000000 mICSTRM_TRIM7: equ %10000000 ;*** ICSSC - ICS Status and Control Register; 0x0000003B *** ICSSC: equ $0000003B ;*** ICSSC - ICS Status and Control Register; 0x0000003B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSSC_FTRIM: equ 0 ; ICS Fine Trim ICSSC_CLKST: equ 2 ; Clock Mode Status ; bit position masks mICSSC_FTRIM: equ %00000001 mICSSC_CLKST: equ %00000100 ;*** TPMSC - TPM1 Status and Control Register; 0x00000040 *** TPMSC: equ $00000040 ;*** TPMSC - TPM1 Status and Control Register; 0x00000040 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPMSC_PS0: equ 0 ; Prescale Divisor Select Bit 0 TPMSC_PS1: equ 1 ; Prescale Divisor Select Bit 1 TPMSC_PS2: equ 2 ; Prescale Divisor Select Bit 2 TPMSC_CLKSA: equ 3 ; Clock Source Select A TPMSC_CLKSB: equ 4 ; Clock Source Select B TPMSC_CPWMS: equ 5 ; Center-Aligned PWM Select TPMSC_TOIE: equ 6 ; Timer Overflow Interrupt Enable TPMSC_TOF: equ 7 ; Timer Overflow Flag ; bit position masks mTPMSC_PS0: equ %00000001 mTPMSC_PS1: equ %00000010 mTPMSC_PS2: equ %00000100 mTPMSC_CLKSA: equ %00001000 mTPMSC_CLKSB: equ %00010000 mTPMSC_CPWMS: equ %00100000 mTPMSC_TOIE: equ %01000000 mTPMSC_TOF: equ %10000000 ;*** TPMCNT - TPM1 Timer Counter Register; 0x00000041 *** TPMCNT: equ $00000041 ;*** TPMCNT - TPM1 Timer Counter Register; 0x00000041 *** ;*** TPMCNTH - TPM1 Timer Counter Register High; 0x00000041 *** TPMCNTH: equ $00000041 ;*** TPMCNTH - TPM1 Timer Counter Register High; 0x00000041 *** ;*** TPMCNTL - TPM1 Timer Counter Register Low; 0x00000042 *** TPMCNTL: equ $00000042 ;*** TPMCNTL - TPM1 Timer Counter Register Low; 0x00000042 *** ;*** TPMMOD - TPM1 Timer Counter Modulo Register; 0x00000043 *** TPMMOD: equ $00000043 ;*** TPMMOD - TPM1 Timer Counter Modulo Register; 0x00000043 *** ;*** TPMMODH - TPM1 Timer Counter Modulo Register High; 0x00000043 *** TPMMODH: equ $00000043 ;*** TPMMODH - TPM1 Timer Counter Modulo Register High; 0x00000043 *** ;*** TPMMODL - TPM1 Timer Counter Modulo Register Low; 0x00000044 *** TPMMODL: equ $00000044 ;*** TPMMODL - TPM1 Timer Counter Modulo Register Low; 0x00000044 *** ;*** TPMC0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000045 *** TPMC0SC: equ $00000045 ;*** TPMC0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000045 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPMC0SC_ELS0A: equ 2 ; Edge/Level Select Bit A TPMC0SC_ELS0B: equ 3 ; Edge/Level Select Bit B TPMC0SC_MS0A: equ 4 ; Mode Select A for TPM Channel 0 TPMC0SC_MS0B: equ 5 ; Mode Select B for TPM Channel 0 TPMC0SC_CH0IE: equ 6 ; Channel 0 Interrupt Enable TPMC0SC_CH0F: equ 7 ; Channel 0 Flag ; bit position masks mTPMC0SC_ELS0A: equ %00000100 mTPMC0SC_ELS0B: equ %00001000 mTPMC0SC_MS0A: equ %00010000 mTPMC0SC_MS0B: equ %00100000 mTPMC0SC_CH0IE: equ %01000000 mTPMC0SC_CH0F: equ %10000000 ;*** TPMC0V - TPM1 Timer Channel 0 Value Register; 0x00000046 *** TPMC0V: equ $00000046 ;*** TPMC0V - TPM1 Timer Channel 0 Value Register; 0x00000046 *** ;*** TPMC0VH - TPM1 Timer Channel 0 Value Register High; 0x00000046 *** TPMC0VH: equ $00000046 ;*** TPMC0VH - TPM1 Timer Channel 0 Value Register High; 0x00000046 *** ;*** TPMC0VL - TPM1 Timer Channel 0 Value Register Low; 0x00000047 *** TPMC0VL: equ $00000047 ;*** TPMC0VL - TPM1 Timer Channel 0 Value Register Low; 0x00000047 *** ;*** TPMC1SC - TPM1 Timer Channel 1 Status and Control Register; 0x00000048 *** TPMC1SC: equ $00000048 ;*** TPMC1SC - TPM1 Timer Channel 1 Status and Control Register; 0x00000048 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPMC1SC_ELS1A: equ 2 ; Edge/Level Select Bit A TPMC1SC_ELS1B: equ 3 ; Edge/Level Select Bit B TPMC1SC_MS1A: equ 4 ; Mode Select A for TPM Channel 1 TPMC1SC_MS1B: equ 5 ; Mode Select B for TPM Channel 1 TPMC1SC_CH1IE: equ 6 ; Channel 1 Interrupt Enable TPMC1SC_CH1F: equ 7 ; Channel 1 Flag ; bit position masks mTPMC1SC_ELS1A: equ %00000100 mTPMC1SC_ELS1B: equ %00001000 mTPMC1SC_MS1A: equ %00010000 mTPMC1SC_MS1B: equ %00100000 mTPMC1SC_CH1IE: equ %01000000 mTPMC1SC_CH1F: equ %10000000 ;*** TPMC1V - TPM1 Timer Channel 1 Value Register; 0x00000049 *** TPMC1V: equ $00000049 ;*** TPMC1V - TPM1 Timer Channel 1 Value Register; 0x00000049 *** ;*** TPMC1VH - TPM1 Timer Channel 1 Value Register High; 0x00000049 *** TPMC1VH: equ $00000049 ;*** TPMC1VH - TPM1 Timer Channel 1 Value Register High; 0x00000049 *** ;*** TPMC1VL - TPM1 Timer Channel 1 Value Register Low; 0x0000004A *** TPMC1VL: equ $0000004A ;*** TPMC1VL - TPM1 Timer Channel 1 Value Register Low; 0x0000004A *** ;*** SRS - System Reset Status Register; 0x00001800 *** SRS: equ $00001800 ;*** SRS - System Reset Status Register; 0x00001800 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRS_LVD: equ 1 ; Low Voltage Detect SRS_ILAD: equ 3 ; Illegal Address SRS_ILOP: equ 4 ; Illegal Opcode SRS_COP: equ 5 ; Computer Operating Properly (COP) Watchdog SRS_PIN: equ 6 ; External Reset Pin SRS_POR: equ 7 ; Power-On Reset ; bit position masks mSRS_LVD: equ %00000010 mSRS_ILAD: equ %00001000 mSRS_ILOP: equ %00010000 mSRS_COP: equ %00100000 mSRS_PIN: equ %01000000 mSRS_POR: equ %10000000 ;*** SBDFR - System Background Debug Force Reset Register; 0x00001801 *** SBDFR: equ $00001801 ;*** SBDFR - System Background Debug Force Reset Register; 0x00001801 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SBDFR_BDFR: equ 0 ; Background Debug Force Reset ; bit position masks mSBDFR_BDFR: equ %00000001 ;*** SOPT1 - System Options Register 1; 0x00001802 *** SOPT1: equ $00001802 ;*** SOPT1 - System Options Register 1; 0x00001802 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT1_RSTPE: equ 0 ; RESET Pin Enable SOPT1_BKGDPE: equ 1 ; Background Debug Mode Pin Enable SOPT1_STOPE: equ 5 ; Stop Mode Enable SOPT1_COPT: equ 6 ; COP Watchdog Timeout SOPT1_COPE: equ 7 ; COP Watchdog Enable ; bit position masks mSOPT1_RSTPE: equ %00000001 mSOPT1_BKGDPE: equ %00000010 mSOPT1_STOPE: equ %00100000 mSOPT1_COPT: equ %01000000 mSOPT1_COPE: equ %10000000 ;*** SOPT2 - System Options Register 2; 0x00001803 *** SOPT2: equ $00001803 ;*** SOPT2 - System Options Register 2; 0x00001803 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT2_COPCLKS: equ 7 ; COP Watchdog Clock Select ; bit position masks mSOPT2_COPCLKS: equ %10000000 ;*** SDID - System Device Identification Register; 0x00001806 *** SDID: equ $00001806 ;*** SDID - System Device Identification Register; 0x00001806 *** ;*** SDIDH - System Device Identification Register High; 0x00001806 *** SDIDH: equ $00001806 ;*** SDIDH - System Device Identification Register High; 0x00001806 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDH_ID8: equ 0 ; Part Identification Number, bit 8 SDIDH_ID9: equ 1 ; Part Identification Number, bit 9 SDIDH_ID10: equ 2 ; Part Identification Number, bit 10 SDIDH_ID11: equ 3 ; Part Identification Number, bit 11 SDIDH_REV0: equ 4 ; Revision Number, bit 0 SDIDH_REV1: equ 5 ; Revision Number, bit 1 SDIDH_REV2: equ 6 ; Revision Number, bit 2 SDIDH_REV3: equ 7 ; Revision Number, bit 3 ; bit position masks mSDIDH_ID8: equ %00000001 mSDIDH_ID9: equ %00000010 mSDIDH_ID10: equ %00000100 mSDIDH_ID11: equ %00001000 mSDIDH_REV0: equ %00010000 mSDIDH_REV1: equ %00100000 mSDIDH_REV2: equ %01000000 mSDIDH_REV3: equ %10000000 ;*** SDIDL - System Device Identification Register Low; 0x00001807 *** SDIDL: equ $00001807 ;*** SDIDL - System Device Identification Register Low; 0x00001807 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDL_ID0: equ 0 ; Part Identification Number, bit 0 SDIDL_ID1: equ 1 ; Part Identification Number, bit 1 SDIDL_ID2: equ 2 ; Part Identification Number, bit 2 SDIDL_ID3: equ 3 ; Part Identification Number, bit 3 SDIDL_ID4: equ 4 ; Part Identification Number, bit 4 SDIDL_ID5: equ 5 ; Part Identification Number, bit 5 SDIDL_ID6: equ 6 ; Part Identification Number, bit 6 SDIDL_ID7: equ 7 ; Part Identification Number, bit 7 ; bit position masks mSDIDL_ID0: equ %00000001 mSDIDL_ID1: equ %00000010 mSDIDL_ID2: equ %00000100 mSDIDL_ID3: equ %00001000 mSDIDL_ID4: equ %00010000 mSDIDL_ID5: equ %00100000 mSDIDL_ID6: equ %01000000 mSDIDL_ID7: equ %10000000 ;*** SRTISC - System Real-Time Interrupt Status and Control Register; 0x00001808 *** SRTISC: equ $00001808 ;*** SRTISC - System Real-Time Interrupt Status and Control Register; 0x00001808 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRTISC_RTIS0: equ 0 ; Real-Time Interrupt Delay Selects, bit 0 SRTISC_RTIS1: equ 1 ; Real-Time Interrupt Delay Selects, bit 1 SRTISC_RTIS2: equ 2 ; Real-Time Interrupt Delay Selects, bit 2 SRTISC_RTIE: equ 4 ; Real-Time Interrupt Enable SRTISC_RTICLKS: equ 5 ; Real-Time Interrupt Clock Select SRTISC_RTIACK: equ 6 ; Real-Time Interrupt Acknowledge SRTISC_RTIF: equ 7 ; Real-Time Interrupt Flag ; bit position masks mSRTISC_RTIS0: equ %00000001 mSRTISC_RTIS1: equ %00000010 mSRTISC_RTIS2: equ %00000100 mSRTISC_RTIE: equ %00010000 mSRTISC_RTICLKS: equ %00100000 mSRTISC_RTIACK: equ %01000000 mSRTISC_RTIF: equ %10000000 ;*** SPMSC1 - System Power Management Status and Control 1 Register; 0x00001809 *** SPMSC1: equ $00001809 ;*** SPMSC1 - System Power Management Status and Control 1 Register; 0x00001809 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC1_BGBE: equ 0 ; Bandgap Buffer Enable SPMSC1_LVDE: equ 2 ; Low-Voltage Detect Enable SPMSC1_LVDSE: equ 3 ; Low-Voltage Detect Stop Enable SPMSC1_LVDRE: equ 4 ; Low-Voltage Detect Reset Enable SPMSC1_LVDIE: equ 5 ; Low-Voltage Detect Interrupt Enable SPMSC1_LVDACK: equ 6 ; Low-Voltage Detect Acknowledge SPMSC1_LVDF: equ 7 ; Low-Voltage Detect Flag ; bit position masks mSPMSC1_BGBE: equ %00000001 mSPMSC1_LVDE: equ %00000100 mSPMSC1_LVDSE: equ %00001000 mSPMSC1_LVDRE: equ %00010000 mSPMSC1_LVDIE: equ %00100000 mSPMSC1_LVDACK: equ %01000000 mSPMSC1_LVDF: equ %10000000 ;*** SPMSC2 - System Power Management Status and Control 2 Register; 0x0000180A *** SPMSC2: equ $0000180A ;*** SPMSC2 - System Power Management Status and Control 2 Register; 0x0000180A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC2_PPDC: equ 0 ; Partial Power Down Control SPMSC2_PPDACK: equ 2 ; Partial Power Down Acknowledge SPMSC2_PPDF: equ 3 ; Partial Power Down Flag SPMSC2_LVWV: equ 4 ; Low-Voltage Warning Voltage Select SPMSC2_LVDV: equ 5 ; Low-Voltage Detect Voltage Select SPMSC2_LVWACK: equ 6 ; Low-Voltage Warning Acknowledge SPMSC2_LVWF: equ 7 ; Low-Voltage Warning Flag ; bit position masks mSPMSC2_PPDC: equ %00000001 mSPMSC2_PPDACK: equ %00000100 mSPMSC2_PPDF: equ %00001000 mSPMSC2_LVWV: equ %00010000 mSPMSC2_LVDV: equ %00100000 mSPMSC2_LVWACK: equ %01000000 mSPMSC2_LVWF: equ %10000000 ;*** FCDIV - FLASH Clock Divider Register; 0x00001820 *** FCDIV: equ $00001820 ;*** FCDIV - FLASH Clock Divider Register; 0x00001820 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCDIV_DIV0: equ 0 ; Divisor for FLASH Clock Divider, bit 0 FCDIV_DIV1: equ 1 ; Divisor for FLASH Clock Divider, bit 1 FCDIV_DIV2: equ 2 ; Divisor for FLASH Clock Divider, bit 2 FCDIV_DIV3: equ 3 ; Divisor for FLASH Clock Divider, bit 3 FCDIV_DIV4: equ 4 ; Divisor for FLASH Clock Divider, bit 4 FCDIV_DIV5: equ 5 ; Divisor for FLASH Clock Divider, bit 5 FCDIV_PRDIV8: equ 6 ; Prescale (Divide) FLASH Clock by 8 FCDIV_DIVLD: equ 7 ; Divisor Loaded Status Flag ; bit position masks mFCDIV_DIV0: equ %00000001 mFCDIV_DIV1: equ %00000010 mFCDIV_DIV2: equ %00000100 mFCDIV_DIV3: equ %00001000 mFCDIV_DIV4: equ %00010000 mFCDIV_DIV5: equ %00100000 mFCDIV_PRDIV8: equ %01000000 mFCDIV_DIVLD: equ %10000000 ;*** FOPT - FLASH Options Register; 0x00001821 *** FOPT: equ $00001821 ;*** FOPT - FLASH Options Register; 0x00001821 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FOPT_SEC00: equ 0 ; Security State Code, bit 0 FOPT_SEC01: equ 1 ; Security State Code, bit 1 FOPT_FNORED: equ 6 ; Vector Redirection Disable FOPT_KEYEN: equ 7 ; Backdoor Key Mechanism Enable ; bit position masks mFOPT_SEC00: equ %00000001 mFOPT_SEC01: equ %00000010 mFOPT_FNORED: equ %01000000 mFOPT_KEYEN: equ %10000000 ;*** FCNFG - FLASH Configuration Register; 0x00001823 *** FCNFG: equ $00001823 ;*** FCNFG - FLASH Configuration Register; 0x00001823 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCNFG_KEYACC: equ 5 ; Enable Writing of Access Key ; bit position masks mFCNFG_KEYACC: equ %00100000 ;*** FPROT - FLASH Protection Register; 0x00001824 *** FPROT: equ $00001824 ;*** FPROT - FLASH Protection Register; 0x00001824 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FPROT_FPDIS: equ 0 ; FLASH Protection Disable FPROT_FPS0: equ 1 ; FLASH Protect Select Bits, bit 0 FPROT_FPS1: equ 2 ; FLASH Protect Select Bits, bit 1 FPROT_FPS2: equ 3 ; FLASH Protect Select Bits, bit 2 FPROT_FPS3: equ 4 ; FLASH Protect Select Bits, bit 3 FPROT_FPS4: equ 5 ; FLASH Protect Select Bits, bit 4 FPROT_FPS5: equ 6 ; FLASH Protect Select Bits, bit 5 FPROT_FPS6: equ 7 ; FLASH Protect Select Bits, bit 6 ; bit position masks mFPROT_FPDIS: equ %00000001 mFPROT_FPS0: equ %00000010 mFPROT_FPS1: equ %00000100 mFPROT_FPS2: equ %00001000 mFPROT_FPS3: equ %00010000 mFPROT_FPS4: equ %00100000 mFPROT_FPS5: equ %01000000 mFPROT_FPS6: equ %10000000 ;*** FSTAT - Flash Status Register; 0x00001825 *** FSTAT: equ $00001825 ;*** FSTAT - Flash Status Register; 0x00001825 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FSTAT_FBLANK: equ 2 ; FLASH Flag Indicating the Erase Verify Operation Status FSTAT_FACCERR: equ 4 ; FLASH Access Error Flag FSTAT_FPVIOL: equ 5 ; FLASH Protection Violation Flag FSTAT_FCCF: equ 6 ; FLASH Command Complete Interrupt Flag FSTAT_FCBEF: equ 7 ; FLASH Command Buffer Empty Flag ; bit position masks mFSTAT_FBLANK: equ %00000100 mFSTAT_FACCERR: equ %00010000 mFSTAT_FPVIOL: equ %00100000 mFSTAT_FCCF: equ %01000000 mFSTAT_FCBEF: equ %10000000 ;*** FCMD - FLASH Command Register; 0x00001826 *** FCMD: equ $00001826 ;*** FCMD - FLASH Command Register; 0x00001826 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCMD_FCMD0: equ 0 ; FLASH Command Bit 0 FCMD_FCMD1: equ 1 ; FLASH Command Bit 1 FCMD_FCMD2: equ 2 ; FLASH Command Bit 2 FCMD_FCMD3: equ 3 ; FLASH Command Bit 3 FCMD_FCMD4: equ 4 ; FLASH Command Bit 4 FCMD_FCMD5: equ 5 ; FLASH Command Bit 5 FCMD_FCMD6: equ 6 ; FLASH Command Bit 6 FCMD_FCMD7: equ 7 ; FLASH Command Bit 7 ; bit position masks mFCMD_FCMD0: equ %00000001 mFCMD_FCMD1: equ %00000010 mFCMD_FCMD2: equ %00000100 mFCMD_FCMD3: equ %00001000 mFCMD_FCMD4: equ %00010000 mFCMD_FCMD5: equ %00100000 mFCMD_FCMD6: equ %01000000 mFCMD_FCMD7: equ %10000000 ;*** PTAPE - Port A Pull Enable Register; 0x00001840 *** PTAPE: equ $00001840 ;*** PTAPE - Port A Pull Enable Register; 0x00001840 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPE_PTAPE0: equ 0 ; Internal Pull Enable for Port A Bit 0 PTAPE_PTAPE1: equ 1 ; Internal Pull Enable for Port A Bit 1 PTAPE_PTAPE2: equ 2 ; Internal Pull Enable for Port A Bit 2 PTAPE_PTAPE3: equ 3 ; Internal Pull Enable for Port A Bit 3 PTAPE_PTAPE4: equ 4 ; Internal Pull Enable for Port A Bit 4 PTAPE_PTAPE5: equ 5 ; Internal Pull Enable for Port A Bit 5 ; bit position masks mPTAPE_PTAPE0: equ %00000001 mPTAPE_PTAPE1: equ %00000010 mPTAPE_PTAPE2: equ %00000100 mPTAPE_PTAPE3: equ %00001000 mPTAPE_PTAPE4: equ %00010000 mPTAPE_PTAPE5: equ %00100000 ;*** PTASE - Port A Slew Rate Enable Register; 0x00001841 *** PTASE: equ $00001841 ;*** PTASE - Port A Slew Rate Enable Register; 0x00001841 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTASE_PTASE0: equ 0 ; Output Slew Rate Enable for Port A Bit 0 PTASE_PTASE1: equ 1 ; Output Slew Rate Enable for Port A Bit 1 PTASE_PTASE2: equ 2 ; Output Slew Rate Enable for Port A Bit 2 PTASE_PTASE3: equ 3 ; Output Slew Rate Enable for Port A Bit 3 PTASE_PTASE4: equ 4 ; Output Slew Rate Enable for Port A Bit 4 PTASE_PTASE5: equ 5 ; Output Slew Rate Enable for Port A Bit 5 ; bit position masks mPTASE_PTASE0: equ %00000001 mPTASE_PTASE1: equ %00000010 mPTASE_PTASE2: equ %00000100 mPTASE_PTASE3: equ %00001000 mPTASE_PTASE4: equ %00010000 mPTASE_PTASE5: equ %00100000 ;*** PTADS - Port A Drive Strength Selection Register; 0x00001842 *** PTADS: equ $00001842 ;*** PTADS - Port A Drive Strength Selection Register; 0x00001842 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADS_PTADS0: equ 0 ; Output Drive Strength Selection for Port A Bit 0 PTADS_PTADS1: equ 1 ; Output Drive Strength Selection for Port A Bit 1 PTADS_PTADS2: equ 2 ; Output Drive Strength Selection for Port A Bit 2 PTADS_PTADS3: equ 3 ; Output Drive Strength Selection for Port A Bit 3 PTADS_PTADS4: equ 4 ; Output Drive Strength Selection for Port A Bit 4 PTADS_PTADS5: equ 5 ; Output Drive Strength Selection for Port A Bit 5 ; bit position masks mPTADS_PTADS0: equ %00000001 mPTADS_PTADS1: equ %00000010 mPTADS_PTADS2: equ %00000100 mPTADS_PTADS3: equ %00001000 mPTADS_PTADS4: equ %00010000 mPTADS_PTADS5: equ %00100000 ;*** NVFTRIM - Nonvolatile ICS Fine Trim; 0x0000FFAE *** NVFTRIM: equ $0000FFAE ;*** NVFTRIM - Nonvolatile ICS Fine Trim; 0x0000FFAE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVFTRIM_FTRIM: equ 0 ; ICS Fine Trim ; bit position masks mNVFTRIM_FTRIM: equ %00000001 ;*** NVICSTRM - Nonvolatile ICS Trim Register; 0x0000FFAF *** NVICSTRM: equ $0000FFAF ;*** NVICSTRM - Nonvolatile ICS Trim Register; 0x0000FFAF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVICSTRM_TRIM0: equ 0 ; ICS Trim Setting, bit 0 NVICSTRM_TRIM1: equ 1 ; ICS Trim Setting, bit 1 NVICSTRM_TRIM2: equ 2 ; ICS Trim Setting, bit 2 NVICSTRM_TRIM3: equ 3 ; ICS Trim Setting, bit 3 NVICSTRM_TRIM4: equ 4 ; ICS Trim Setting, bit 4 NVICSTRM_TRIM5: equ 5 ; ICS Trim Setting, bit 5 NVICSTRM_TRIM6: equ 6 ; ICS Trim Setting, bit 6 NVICSTRM_TRIM7: equ 7 ; ICS Trim Setting, bit 7 ; bit position masks mNVICSTRM_TRIM0: equ %00000001 mNVICSTRM_TRIM1: equ %00000010 mNVICSTRM_TRIM2: equ %00000100 mNVICSTRM_TRIM3: equ %00001000 mNVICSTRM_TRIM4: equ %00010000 mNVICSTRM_TRIM5: equ %00100000 mNVICSTRM_TRIM6: equ %01000000 mNVICSTRM_TRIM7: equ %10000000 ;*** NVBACKKEY0 - Backdoor Comparison Key 0; 0x0000FFB0 *** NVBACKKEY0: equ $0000FFB0 ;*** NVBACKKEY0 - Backdoor Comparison Key 0; 0x0000FFB0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY0_KEY0: equ 0 ; Backdoor Comparison Key 0 Bits, bit 0 NVBACKKEY0_KEY1: equ 1 ; Backdoor Comparison Key 0 Bits, bit 1 NVBACKKEY0_KEY2: equ 2 ; Backdoor Comparison Key 0 Bits, bit 2 NVBACKKEY0_KEY3: equ 3 ; Backdoor Comparison Key 0 Bits, bit 3 NVBACKKEY0_KEY4: equ 4 ; Backdoor Comparison Key 0 Bits, bit 4 NVBACKKEY0_KEY5: equ 5 ; Backdoor Comparison Key 0 Bits, bit 5 NVBACKKEY0_KEY6: equ 6 ; Backdoor Comparison Key 0 Bits, bit 6 NVBACKKEY0_KEY7: equ 7 ; Backdoor Comparison Key 0 Bits, bit 7 ; bit position masks mNVBACKKEY0_KEY0: equ %00000001 mNVBACKKEY0_KEY1: equ %00000010 mNVBACKKEY0_KEY2: equ %00000100 mNVBACKKEY0_KEY3: equ %00001000 mNVBACKKEY0_KEY4: equ %00010000 mNVBACKKEY0_KEY5: equ %00100000 mNVBACKKEY0_KEY6: equ %01000000 mNVBACKKEY0_KEY7: equ %10000000 ;*** NVBACKKEY1 - Backdoor Comparison Key 1; 0x0000FFB1 *** NVBACKKEY1: equ $0000FFB1 ;*** NVBACKKEY1 - Backdoor Comparison Key 1; 0x0000FFB1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY1_KEY0: equ 0 ; Backdoor Comparison Key 1 Bits, bit 0 NVBACKKEY1_KEY1: equ 1 ; Backdoor Comparison Key 1 Bits, bit 1 NVBACKKEY1_KEY2: equ 2 ; Backdoor Comparison Key 1 Bits, bit 2 NVBACKKEY1_KEY3: equ 3 ; Backdoor Comparison Key 1 Bits, bit 3 NVBACKKEY1_KEY4: equ 4 ; Backdoor Comparison Key 1 Bits, bit 4 NVBACKKEY1_KEY5: equ 5 ; Backdoor Comparison Key 1 Bits, bit 5 NVBACKKEY1_KEY6: equ 6 ; Backdoor Comparison Key 1 Bits, bit 6 NVBACKKEY1_KEY7: equ 7 ; Backdoor Comparison Key 1 Bits, bit 7 ; bit position masks mNVBACKKEY1_KEY0: equ %00000001 mNVBACKKEY1_KEY1: equ %00000010 mNVBACKKEY1_KEY2: equ %00000100 mNVBACKKEY1_KEY3: equ %00001000 mNVBACKKEY1_KEY4: equ %00010000 mNVBACKKEY1_KEY5: equ %00100000 mNVBACKKEY1_KEY6: equ %01000000 mNVBACKKEY1_KEY7: equ %10000000 ;*** NVBACKKEY2 - Backdoor Comparison Key 2; 0x0000FFB2 *** NVBACKKEY2: equ $0000FFB2 ;*** NVBACKKEY2 - Backdoor Comparison Key 2; 0x0000FFB2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY2_KEY0: equ 0 ; Backdoor Comparison Key 2 Bits, bit 0 NVBACKKEY2_KEY1: equ 1 ; Backdoor Comparison Key 2 Bits, bit 1 NVBACKKEY2_KEY2: equ 2 ; Backdoor Comparison Key 2 Bits, bit 2 NVBACKKEY2_KEY3: equ 3 ; Backdoor Comparison Key 2 Bits, bit 3 NVBACKKEY2_KEY4: equ 4 ; Backdoor Comparison Key 2 Bits, bit 4 NVBACKKEY2_KEY5: equ 5 ; Backdoor Comparison Key 2 Bits, bit 5 NVBACKKEY2_KEY6: equ 6 ; Backdoor Comparison Key 2 Bits, bit 6 NVBACKKEY2_KEY7: equ 7 ; Backdoor Comparison Key 2 Bits, bit 7 ; bit position masks mNVBACKKEY2_KEY0: equ %00000001 mNVBACKKEY2_KEY1: equ %00000010 mNVBACKKEY2_KEY2: equ %00000100 mNVBACKKEY2_KEY3: equ %00001000 mNVBACKKEY2_KEY4: equ %00010000 mNVBACKKEY2_KEY5: equ %00100000 mNVBACKKEY2_KEY6: equ %01000000 mNVBACKKEY2_KEY7: equ %10000000 ;*** NVBACKKEY3 - Backdoor Comparison Key 3; 0x0000FFB3 *** NVBACKKEY3: equ $0000FFB3 ;*** NVBACKKEY3 - Backdoor Comparison Key 3; 0x0000FFB3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY3_KEY0: equ 0 ; Backdoor Comparison Key 3 Bits, bit 0 NVBACKKEY3_KEY1: equ 1 ; Backdoor Comparison Key 3 Bits, bit 1 NVBACKKEY3_KEY2: equ 2 ; Backdoor Comparison Key 3 Bits, bit 2 NVBACKKEY3_KEY3: equ 3 ; Backdoor Comparison Key 3 Bits, bit 3 NVBACKKEY3_KEY4: equ 4 ; Backdoor Comparison Key 3 Bits, bit 4 NVBACKKEY3_KEY5: equ 5 ; Backdoor Comparison Key 3 Bits, bit 5 NVBACKKEY3_KEY6: equ 6 ; Backdoor Comparison Key 3 Bits, bit 6 NVBACKKEY3_KEY7: equ 7 ; Backdoor Comparison Key 3 Bits, bit 7 ; bit position masks mNVBACKKEY3_KEY0: equ %00000001 mNVBACKKEY3_KEY1: equ %00000010 mNVBACKKEY3_KEY2: equ %00000100 mNVBACKKEY3_KEY3: equ %00001000 mNVBACKKEY3_KEY4: equ %00010000 mNVBACKKEY3_KEY5: equ %00100000 mNVBACKKEY3_KEY6: equ %01000000 mNVBACKKEY3_KEY7: equ %10000000 ;*** NVBACKKEY4 - Backdoor Comparison Key 4; 0x0000FFB4 *** NVBACKKEY4: equ $0000FFB4 ;*** NVBACKKEY4 - Backdoor Comparison Key 4; 0x0000FFB4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY4_KEY0: equ 0 ; Backdoor Comparison Key 4 Bits, bit 0 NVBACKKEY4_KEY1: equ 1 ; Backdoor Comparison Key 4 Bits, bit 1 NVBACKKEY4_KEY2: equ 2 ; Backdoor Comparison Key 4 Bits, bit 2 NVBACKKEY4_KEY3: equ 3 ; Backdoor Comparison Key 4 Bits, bit 3 NVBACKKEY4_KEY4: equ 4 ; Backdoor Comparison Key 4 Bits, bit 4 NVBACKKEY4_KEY5: equ 5 ; Backdoor Comparison Key 4 Bits, bit 5 NVBACKKEY4_KEY6: equ 6 ; Backdoor Comparison Key 4 Bits, bit 6 NVBACKKEY4_KEY7: equ 7 ; Backdoor Comparison Key 4 Bits, bit 7 ; bit position masks mNVBACKKEY4_KEY0: equ %00000001 mNVBACKKEY4_KEY1: equ %00000010 mNVBACKKEY4_KEY2: equ %00000100 mNVBACKKEY4_KEY3: equ %00001000 mNVBACKKEY4_KEY4: equ %00010000 mNVBACKKEY4_KEY5: equ %00100000 mNVBACKKEY4_KEY6: equ %01000000 mNVBACKKEY4_KEY7: equ %10000000 ;*** NVBACKKEY5 - Backdoor Comparison Key 5; 0x0000FFB5 *** NVBACKKEY5: equ $0000FFB5 ;*** NVBACKKEY5 - Backdoor Comparison Key 5; 0x0000FFB5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY5_KEY0: equ 0 ; Backdoor Comparison Key 5 Bits, bit 0 NVBACKKEY5_KEY1: equ 1 ; Backdoor Comparison Key 5 Bits, bit 1 NVBACKKEY5_KEY2: equ 2 ; Backdoor Comparison Key 5 Bits, bit 2 NVBACKKEY5_KEY3: equ 3 ; Backdoor Comparison Key 5 Bits, bit 3 NVBACKKEY5_KEY4: equ 4 ; Backdoor Comparison Key 5 Bits, bit 4 NVBACKKEY5_KEY5: equ 5 ; Backdoor Comparison Key 5 Bits, bit 5 NVBACKKEY5_KEY6: equ 6 ; Backdoor Comparison Key 5 Bits, bit 6 NVBACKKEY5_KEY7: equ 7 ; Backdoor Comparison Key 5 Bits, bit 7 ; bit position masks mNVBACKKEY5_KEY0: equ %00000001 mNVBACKKEY5_KEY1: equ %00000010 mNVBACKKEY5_KEY2: equ %00000100 mNVBACKKEY5_KEY3: equ %00001000 mNVBACKKEY5_KEY4: equ %00010000 mNVBACKKEY5_KEY5: equ %00100000 mNVBACKKEY5_KEY6: equ %01000000 mNVBACKKEY5_KEY7: equ %10000000 ;*** NVBACKKEY6 - Backdoor Comparison Key 6; 0x0000FFB6 *** NVBACKKEY6: equ $0000FFB6 ;*** NVBACKKEY6 - Backdoor Comparison Key 6; 0x0000FFB6 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY6_KEY0: equ 0 ; Backdoor Comparison Key 6 Bits, bit 0 NVBACKKEY6_KEY1: equ 1 ; Backdoor Comparison Key 6 Bits, bit 1 NVBACKKEY6_KEY2: equ 2 ; Backdoor Comparison Key 6 Bits, bit 2 NVBACKKEY6_KEY3: equ 3 ; Backdoor Comparison Key 6 Bits, bit 3 NVBACKKEY6_KEY4: equ 4 ; Backdoor Comparison Key 6 Bits, bit 4 NVBACKKEY6_KEY5: equ 5 ; Backdoor Comparison Key 6 Bits, bit 5 NVBACKKEY6_KEY6: equ 6 ; Backdoor Comparison Key 6 Bits, bit 6 NVBACKKEY6_KEY7: equ 7 ; Backdoor Comparison Key 6 Bits, bit 7 ; bit position masks mNVBACKKEY6_KEY0: equ %00000001 mNVBACKKEY6_KEY1: equ %00000010 mNVBACKKEY6_KEY2: equ %00000100 mNVBACKKEY6_KEY3: equ %00001000 mNVBACKKEY6_KEY4: equ %00010000 mNVBACKKEY6_KEY5: equ %00100000 mNVBACKKEY6_KEY6: equ %01000000 mNVBACKKEY6_KEY7: equ %10000000 ;*** NVBACKKEY7 - Backdoor Comparison Key 7; 0x0000FFB7 *** NVBACKKEY7: equ $0000FFB7 ;*** NVBACKKEY7 - Backdoor Comparison Key 7; 0x0000FFB7 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY7_KEY0: equ 0 ; Backdoor Comparison Key 7 Bits, bit 0 NVBACKKEY7_KEY1: equ 1 ; Backdoor Comparison Key 7 Bits, bit 1 NVBACKKEY7_KEY2: equ 2 ; Backdoor Comparison Key 7 Bits, bit 2 NVBACKKEY7_KEY3: equ 3 ; Backdoor Comparison Key 7 Bits, bit 3 NVBACKKEY7_KEY4: equ 4 ; Backdoor Comparison Key 7 Bits, bit 4 NVBACKKEY7_KEY5: equ 5 ; Backdoor Comparison Key 7 Bits, bit 5 NVBACKKEY7_KEY6: equ 6 ; Backdoor Comparison Key 7 Bits, bit 6 NVBACKKEY7_KEY7: equ 7 ; Backdoor Comparison Key 7 Bits, bit 7 ; bit position masks mNVBACKKEY7_KEY0: equ %00000001 mNVBACKKEY7_KEY1: equ %00000010 mNVBACKKEY7_KEY2: equ %00000100 mNVBACKKEY7_KEY3: equ %00001000 mNVBACKKEY7_KEY4: equ %00010000 mNVBACKKEY7_KEY5: equ %00100000 mNVBACKKEY7_KEY6: equ %01000000 mNVBACKKEY7_KEY7: equ %10000000 ;*** NVPROT - Nonvolatile FLASH Protection Register; 0x0000FFBD *** NVPROT: equ $0000FFBD ;*** NVPROT - Nonvolatile FLASH Protection Register; 0x0000FFBD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVPROT_FPDIS: equ 0 ; FLASH Protection Disable NVPROT_FPS0: equ 1 ; FLASH Protect Select Bits, bit 0 NVPROT_FPS1: equ 2 ; FLASH Protect Select Bits, bit 1 NVPROT_FPS2: equ 3 ; FLASH Protect Select Bits, bit 2 NVPROT_FPS3: equ 4 ; FLASH Protect Select Bits, bit 3 NVPROT_FPS4: equ 5 ; FLASH Protect Select Bits, bit 4 NVPROT_FPS5: equ 6 ; FLASH Protect Select Bits, bit 5 NVPROT_FPS6: equ 7 ; FLASH Protect Select Bits, bit 6 ; bit position masks mNVPROT_FPDIS: equ %00000001 mNVPROT_FPS0: equ %00000010 mNVPROT_FPS1: equ %00000100 mNVPROT_FPS2: equ %00001000 mNVPROT_FPS3: equ %00010000 mNVPROT_FPS4: equ %00100000 mNVPROT_FPS5: equ %01000000 mNVPROT_FPS6: equ %10000000 ;*** NVOPT - Nonvolatile Flash Options Register; 0x0000FFBF *** NVOPT: equ $0000FFBF ;*** NVOPT - Nonvolatile Flash Options Register; 0x0000FFBF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVOPT_SEC00: equ 0 ; Security State Code, bit 0 NVOPT_SEC01: equ 1 ; Security State Code, bit 1 NVOPT_FNORED: equ 6 ; Vector Redirection Disable NVOPT_KEYEN: equ 7 ; Backdoor Key Mechanism Enable ; bit position masks mNVOPT_SEC00: equ %00000001 mNVOPT_SEC01: equ %00000010 mNVOPT_FNORED: equ %01000000 mNVOPT_KEYEN: equ %10000000 ; Flash commands mBlank: equ $05 mBurstProg: equ $25 mByteProg: equ $20 mMassErase: equ $41 mPageErase: equ $40 ;*********************************************** ;** D E P R E C I A T E D S Y M B O L S ** ;*********************************************** IFNDEF __GENERATE_APPLICATION__ ; not supported for absolute assembler XREF This_symb_has_been_depreciated ENDIF ; EOF