; Based on CPU DB MC68HC908AP64_48, version 2.89.111 (RegistersPrg V2.28) ; ################################################################### ; Filename : mc68hc908ap8.inc ; Processor : MC68HC908AP8CFA ; FileFormat: V2.28 ; DataSheet : MC68HC908AP64 Rev. 4 1/2007 / MC68HC908AP64A Rev. 3 10/2007 ; Compiler : CodeWarrior compiler ; Date/Time : 27.5.2009, 9:58 ; Abstract : ; This header implements the mapping of I/O devices. ; ; Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ; ; http : www.freescale.com ; mail : support@freescale.com ; ; CPU Registers Revisions: ; - none ; ; File-Format-Revisions: ; - 14.11.2005, V2.00 : ; - Deprecated symbols added for backward compatibility (section at the end of this file) ; - 15.11.2005, V2.01 : ; - Changes have not affected this file (because they are related to another family) ; - 17.12.2005, V2.02 : ; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ; - 16.01.2006, V2.03 : ; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ; - 08.03.2006, V2.04 : ; - Support for bit(s) names duplicated with any register name in .h header files ; - 24.03.2006, V2.05 : ; - Changes have not affected this file (because they are related to another family) ; - 26.04.2006, V2.06 : ; - Absolute assembly supported (depreciated symbols are not defined) ; - 27.04.2006, V2.07 : ; - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ; - 07.06.2006, V2.08 : ; - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ; - 03.07.2006, V2.09 : ; - Flash commands constants supported ; - 27.10.2006, V2.10 : ; - __RESET_WATCHDOG improved formating and re-definition ; - 23.11.2006, V2.11 : ; - Changes have not affected this file (because they are related to another family) ; - 22.01.2007, V2.12 : ; - Changes have not affected this file (because they are related to another family) ; - 01.03.2007, V2.13 : ; - Flash commands constants values converted to HEX format ; - 02.03.2007, V2.14 : ; - Interrupt vector numbers added into .H, see VectorNumber_* ; - 26.03.2007, V2.15 : ; - Changes have not affected this file (because they are related to another family) ; - 10.05.2007, V2.16 : ; - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ; - 05.06.2007, V2.17 : ; - Changes have not affected this file (because they are related to another family) ; - 19.07.2007, V2.18 : ; - Improved number of blanked lines inside register structures ; - 06.08.2007, V2.19 : ; - CPUDB revisions generated ahead of the file-format revisions. ; - 11.09.2007, V2.20 : ; - Added comment about initialization of unbonded pins. ; - 02.01.2008, V2.21 : ; - Changes have not affected this file (because they are related to another family) ; - 13.02.2008, V2.22 : ; - Changes have not affected this file (because they are related to another family) ; - 20.02.2008, V2.23 : ; - Changes have not affected this file (because they are related to another family) ; - 03.07.2008, V2.24 : ; - Added support for bits with name starting with number (like "1HZ") ; - 28.11.2008, V2.25 : ; - StandBy RAM array declaration for ANSI-C added ; - 1.12.2008, V2.26 : ; - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ; - 17.3.2009, V2.27 : ; - Merged bit-group is not generated, if the name matchs with anouther bit name in the register ; - 6.4.2009, V2.28 : ; - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ; ; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ; derivative device. To avoid extra current drain from floating input pins, the user’s reset ; initialization routine in the application program must either enable on-chip pull-up devices ; or change the direction of unconnected pins to outputs so the pins do not float. ; ################################################################### ;*** Memory Map and Interrupt Vectors ;****************************************** ROMStart: equ $00000860 ROMEnd: equ $0000285F Z_RAMStart: equ $00000060 Z_RAMEnd: equ $000000FF RAMStart: equ $00000100 RAMEnd: equ $0000045F ; INT_TBM: equ $0000FFD2 INT_IRSCITransmit: equ $0000FFD4 INT_IRSCIReceive: equ $0000FFD6 INT_IRSCIError: equ $0000FFD8 INT_SPITransmit: equ $0000FFDA INT_SPIReceive: equ $0000FFDC INT_ADC: equ $0000FFDE INT_KBD: equ $0000FFE0 INT_SCITransmit: equ $0000FFE2 INT_SCIReceive: equ $0000FFE4 INT_SCIError: equ $0000FFE6 INT_MMIIC: equ $0000FFE8 INT_TIM2Ovr: equ $0000FFEA INT_TIM2CH1: equ $0000FFEC INT_TIM2CH0: equ $0000FFEE INT_TIM1Ovr: equ $0000FFF0 INT_TIM1CH1: equ $0000FFF2 INT_TIM1CH0: equ $0000FFF4 INT_PLL: equ $0000FFF6 INT_IRQ2: equ $0000FFF8 INT_IRQ1: equ $0000FFFA INT_SWI: equ $0000FFFC INT_RESET: equ $0000FFFE ; ;*** PTA - Port A Data Register; 0x00000000 *** PTA: equ $00000000 ;*** PTA - Port A Data Register; 0x00000000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTA_PTA0: equ 0 ; Port A Data Bit 0 PTA_PTA1: equ 1 ; Port A Data Bit 1 PTA_PTA2: equ 2 ; Port A Data Bit 2 PTA_PTA3: equ 3 ; Port A Data Bit 3 PTA_PTA4: equ 4 ; Port A Data Bit 4 PTA_PTA5: equ 5 ; Port A Data Bit 5 PTA_PTA6: equ 6 ; Port A Data Bit 6 PTA_PTA7: equ 7 ; Port A Data Bit 7 ; bit position masks mPTA_PTA0: equ %00000001 mPTA_PTA1: equ %00000010 mPTA_PTA2: equ %00000100 mPTA_PTA3: equ %00001000 mPTA_PTA4: equ %00010000 mPTA_PTA5: equ %00100000 mPTA_PTA6: equ %01000000 mPTA_PTA7: equ %10000000 ;*** PTB - Port B Data Register; 0x00000001 *** PTB: equ $00000001 ;*** PTB - Port B Data Register; 0x00000001 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTB_PTB0: equ 0 ; Port B Data Bit 0 PTB_PTB1: equ 1 ; Port B Data Bit 1 PTB_PTB2: equ 2 ; Port B Data Bit 2 PTB_PTB3: equ 3 ; Port B Data Bit 3 PTB_PTB4: equ 4 ; Port B Data Bit 4 PTB_PTB5: equ 5 ; Port B Data Bit 5 PTB_PTB6: equ 6 ; Port B Data Bit 6 PTB_PTB7: equ 7 ; Port B Data Bit 7 ; bit position masks mPTB_PTB0: equ %00000001 mPTB_PTB1: equ %00000010 mPTB_PTB2: equ %00000100 mPTB_PTB3: equ %00001000 mPTB_PTB4: equ %00010000 mPTB_PTB5: equ %00100000 mPTB_PTB6: equ %01000000 mPTB_PTB7: equ %10000000 ;*** PTC - Port C Data Register; 0x00000002 *** PTC: equ $00000002 ;*** PTC - Port C Data Register; 0x00000002 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTC_PTC0: equ 0 ; Port C Data Bit 0 PTC_PTC1: equ 1 ; Port C Data Bit 1 PTC_PTC2: equ 2 ; Port C Data Bit 2 PTC_PTC3: equ 3 ; Port C Data Bit 3 PTC_PTC4: equ 4 ; Port C Data Bit 4 PTC_PTC5: equ 5 ; Port C Data Bit 5 PTC_PTC6: equ 6 ; Port C Data Bit 6 PTC_PTC7: equ 7 ; Port C Data Bit 7 ; bit position masks mPTC_PTC0: equ %00000001 mPTC_PTC1: equ %00000010 mPTC_PTC2: equ %00000100 mPTC_PTC3: equ %00001000 mPTC_PTC4: equ %00010000 mPTC_PTC5: equ %00100000 mPTC_PTC6: equ %01000000 mPTC_PTC7: equ %10000000 ;*** PTD - Port D Data Register; 0x00000003 *** PTD: equ $00000003 ;*** PTD - Port D Data Register; 0x00000003 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTD_PTD0: equ 0 ; Port D Data Bit 0 PTD_PTD1: equ 1 ; Port D Data Bit 1 PTD_PTD2: equ 2 ; Port D Data Bit 2 PTD_PTD3: equ 3 ; Port D Data Bit 3 PTD_PTD4: equ 4 ; Port D Data Bit 4 PTD_PTD5: equ 5 ; Port D Data Bit 5 PTD_PTD6: equ 6 ; Port D Data Bit 6 PTD_PTD7: equ 7 ; Port D Data Bit 7 ; bit position masks mPTD_PTD0: equ %00000001 mPTD_PTD1: equ %00000010 mPTD_PTD2: equ %00000100 mPTD_PTD3: equ %00001000 mPTD_PTD4: equ %00010000 mPTD_PTD5: equ %00100000 mPTD_PTD6: equ %01000000 mPTD_PTD7: equ %10000000 ;*** DDRA - Data Direction Register A; 0x00000004 *** DDRA: equ $00000004 ;*** DDRA - Data Direction Register A; 0x00000004 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DDRA_DDRA0: equ 0 ; Data Direction Register A Bit 0 DDRA_DDRA1: equ 1 ; Data Direction Register A Bit 1 DDRA_DDRA2: equ 2 ; Data Direction Register A Bit 2 DDRA_DDRA3: equ 3 ; Data Direction Register A Bit 3 DDRA_DDRA4: equ 4 ; Data Direction Register A Bit 4 DDRA_DDRA5: equ 5 ; Data Direction Register A Bit 5 DDRA_DDRA6: equ 6 ; Data Direction Register A Bit 6 DDRA_DDRA7: equ 7 ; Data Direction Register A Bit 7 ; bit position masks mDDRA_DDRA0: equ %00000001 mDDRA_DDRA1: equ %00000010 mDDRA_DDRA2: equ %00000100 mDDRA_DDRA3: equ %00001000 mDDRA_DDRA4: equ %00010000 mDDRA_DDRA5: equ %00100000 mDDRA_DDRA6: equ %01000000 mDDRA_DDRA7: equ %10000000 ;*** DDRB - Data Direction Register B; 0x00000005 *** DDRB: equ $00000005 ;*** DDRB - Data Direction Register B; 0x00000005 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DDRB_DDRB0: equ 0 ; Data Direction Register B Bit 0 DDRB_DDRB1: equ 1 ; Data Direction Register B Bit 1 DDRB_DDRB2: equ 2 ; Data Direction Register B Bit 2 DDRB_DDRB3: equ 3 ; Data Direction Register B Bit 3 DDRB_DDRB4: equ 4 ; Data Direction Register B Bit 4 DDRB_DDRB5: equ 5 ; Data Direction Register B Bit 5 DDRB_DDRB6: equ 6 ; Data Direction Register B Bit 6 DDRB_DDRB7: equ 7 ; Data Direction Register B Bit 7 ; bit position masks mDDRB_DDRB0: equ %00000001 mDDRB_DDRB1: equ %00000010 mDDRB_DDRB2: equ %00000100 mDDRB_DDRB3: equ %00001000 mDDRB_DDRB4: equ %00010000 mDDRB_DDRB5: equ %00100000 mDDRB_DDRB6: equ %01000000 mDDRB_DDRB7: equ %10000000 ;*** DDRC - Data Direction Register C; 0x00000006 *** DDRC: equ $00000006 ;*** DDRC - Data Direction Register C; 0x00000006 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DDRC_DDRC0: equ 0 ; Data Direction Register C Bit 0 DDRC_DDRC1: equ 1 ; Data Direction Register C Bit 1 DDRC_DDRC2: equ 2 ; Data Direction Register C Bit 2 DDRC_DDRC3: equ 3 ; Data Direction Register C Bit 3 DDRC_DDRC4: equ 4 ; Data Direction Register C Bit 4 DDRC_DDRC5: equ 5 ; Data Direction Register C Bit 5 DDRC_DDRC6: equ 6 ; Data Direction Register C Bit 6 DDRC_DDRC7: equ 7 ; Data Direction Register C Bit 7 ; bit position masks mDDRC_DDRC0: equ %00000001 mDDRC_DDRC1: equ %00000010 mDDRC_DDRC2: equ %00000100 mDDRC_DDRC3: equ %00001000 mDDRC_DDRC4: equ %00010000 mDDRC_DDRC5: equ %00100000 mDDRC_DDRC6: equ %01000000 mDDRC_DDRC7: equ %10000000 ;*** DDRD - Data Direction Register D; 0x00000007 *** DDRD: equ $00000007 ;*** DDRD - Data Direction Register D; 0x00000007 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DDRD_DDRD0: equ 0 ; Data Direction Register D Bit 0 DDRD_DDRD1: equ 1 ; Data Direction Register D Bit 1 DDRD_DDRD2: equ 2 ; Data Direction Register D Bit 2 DDRD_DDRD3: equ 3 ; Data Direction Register D Bit 3 DDRD_DDRD4: equ 4 ; Data Direction Register D Bit 4 DDRD_DDRD5: equ 5 ; Data Direction Register D Bit 5 DDRD_DDRD6: equ 6 ; Data Direction Register D Bit 6 DDRD_DDRD7: equ 7 ; Data Direction Register D Bit 7 ; bit position masks mDDRD_DDRD0: equ %00000001 mDDRD_DDRD1: equ %00000010 mDDRD_DDRD2: equ %00000100 mDDRD_DDRD3: equ %00001000 mDDRD_DDRD4: equ %00010000 mDDRD_DDRD5: equ %00100000 mDDRD_DDRD6: equ %01000000 mDDRD_DDRD7: equ %10000000 ;*** LEDA - Port-A LED Control; 0x0000000C *** LEDA: equ $0000000C ;*** LEDA - Port-A LED Control; 0x0000000C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET LEDA_LEDA0: equ 0 ; Port A LED Drive Enable Bit 0 LEDA_LEDA1: equ 1 ; Port A LED Drive Enable Bit 1 LEDA_LEDA2: equ 2 ; Port A LED Drive Enable Bit 2 LEDA_LEDA3: equ 3 ; Port A LED Drive Enable Bit 3 LEDA_LEDA4: equ 4 ; Port A LED Drive Enable Bit 4 LEDA_LEDA5: equ 5 ; Port A LED Drive Enable Bit 5 LEDA_LEDA6: equ 6 ; Port A LED Drive Enable Bit 6 LEDA_LEDA7: equ 7 ; Port A LED Drive Enable Bit 7 ; bit position masks mLEDA_LEDA0: equ %00000001 mLEDA_LEDA1: equ %00000010 mLEDA_LEDA2: equ %00000100 mLEDA_LEDA3: equ %00001000 mLEDA_LEDA4: equ %00010000 mLEDA_LEDA5: equ %00100000 mLEDA_LEDA6: equ %01000000 mLEDA_LEDA7: equ %10000000 ;*** SPCR - SPI Control Register; 0x00000010 *** SPCR: equ $00000010 ;*** SPCR - SPI Control Register; 0x00000010 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPCR_SPTIE: equ 0 ; SPI Transmit Interrupt Enable Bit SPCR_SPE: equ 1 ; SPI Enable Bit SPCR_SPWOM: equ 2 ; SPI Wired-OR Mode Bit SPCR_CPHA: equ 3 ; Clock Phase Bit SPCR_CPOL: equ 4 ; Clock Polarity Bit SPCR_SPMSTR: equ 5 ; SPI Master Bit SPCR_SPRIE: equ 7 ; SPI Receiver Interrupt Enable Bit ; bit position masks mSPCR_SPTIE: equ %00000001 mSPCR_SPE: equ %00000010 mSPCR_SPWOM: equ %00000100 mSPCR_CPHA: equ %00001000 mSPCR_CPOL: equ %00010000 mSPCR_SPMSTR: equ %00100000 mSPCR_SPRIE: equ %10000000 ;*** SPSCR - SPI Status and Control Register; 0x00000011 *** SPSCR: equ $00000011 ;*** SPSCR - SPI Status and Control Register; 0x00000011 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPSCR_SPR0: equ 0 ; SPI Baud Rate Select Bit 0 SPSCR_SPR1: equ 1 ; SPI Baud Rate Select Bit 1 SPSCR_MODFEN: equ 2 ; Mode Fault Enable Bit SPSCR_SPTE: equ 3 ; SPI Transmitter Empty Bit SPSCR_MODF: equ 4 ; Mode Fault Bit SPSCR_OVRF: equ 5 ; Overflow Bit SPSCR_ERRIE: equ 6 ; Error Interrupt Enable Bit SPSCR_SPRF: equ 7 ; SPI Receiver Full Bit ; bit position masks mSPSCR_SPR0: equ %00000001 mSPSCR_SPR1: equ %00000010 mSPSCR_MODFEN: equ %00000100 mSPSCR_SPTE: equ %00001000 mSPSCR_MODF: equ %00010000 mSPSCR_OVRF: equ %00100000 mSPSCR_ERRIE: equ %01000000 mSPSCR_SPRF: equ %10000000 ;*** SPDR - SPI Data Register; 0x00000012 *** SPDR: equ $00000012 ;*** SPDR - SPI Data Register; 0x00000012 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPDR_R0_T0: equ 0 ; Receive/Transmit Data Bit 0 SPDR_R1_T1: equ 1 ; Receive/Transmit Data Bit 1 SPDR_R2_T2: equ 2 ; Receive/Transmit Data Bit 2 SPDR_R3_T3: equ 3 ; Receive/Transmit Data Bit 3 SPDR_R4_T4: equ 4 ; Receive/Transmit Data Bit 4 SPDR_R5_T5: equ 5 ; Receive/Transmit Data Bit 5 SPDR_R6_T6: equ 6 ; Receive/Transmit Data Bit 6 SPDR_R7_T7: equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSPDR_R0_T0: equ %00000001 mSPDR_R1_T1: equ %00000010 mSPDR_R2_T2: equ %00000100 mSPDR_R3_T3: equ %00001000 mSPDR_R4_T4: equ %00010000 mSPDR_R5_T5: equ %00100000 mSPDR_R6_T6: equ %01000000 mSPDR_R7_T7: equ %10000000 ;*** SCC1 - SCI Control Register 1; 0x00000013 *** SCC1: equ $00000013 ;*** SCC1 - SCI Control Register 1; 0x00000013 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCC1_PTY: equ 0 ; Parity Bit SCC1_PEN: equ 1 ; Parity Enable Bit SCC1_ILTY: equ 2 ; Idle Line Type Bit SCC1_WAKE: equ 3 ; Wakeup Condition Bit SCC1_M: equ 4 ; Mode (Character Length) Bit SCC1_TXINV: equ 5 ; Transmit Inversion Bit SCC1_ENSCI: equ 6 ; Enable SCI Bit SCC1_LOOPS: equ 7 ; Loop Mode Select Bit ; bit position masks mSCC1_PTY: equ %00000001 mSCC1_PEN: equ %00000010 mSCC1_ILTY: equ %00000100 mSCC1_WAKE: equ %00001000 mSCC1_M: equ %00010000 mSCC1_TXINV: equ %00100000 mSCC1_ENSCI: equ %01000000 mSCC1_LOOPS: equ %10000000 ;*** SCC2 - SCI Control Register 2; 0x00000014 *** SCC2: equ $00000014 ;*** SCC2 - SCI Control Register 2; 0x00000014 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCC2_SBK: equ 0 ; Send Break Bit SCC2_RWU: equ 1 ; Receiver Wakeup Bit SCC2_RE: equ 2 ; Receiver Enable Bit SCC2_TE: equ 3 ; Transmitter Enable Bit SCC2_ILIE: equ 4 ; Idle Line Interrupt Enable Bit SCC2_SCRIE: equ 5 ; SCI Receive Interrupt Enable Bit SCC2_TCIE: equ 6 ; Transmission Complete Interrupt Enable Bit SCC2_SCTIE: equ 7 ; SCI Transmit Interrupt Enable Bit ; bit position masks mSCC2_SBK: equ %00000001 mSCC2_RWU: equ %00000010 mSCC2_RE: equ %00000100 mSCC2_TE: equ %00001000 mSCC2_ILIE: equ %00010000 mSCC2_SCRIE: equ %00100000 mSCC2_TCIE: equ %01000000 mSCC2_SCTIE: equ %10000000 ;*** SCC3 - SCI Control Register 3; 0x00000015 *** SCC3: equ $00000015 ;*** SCC3 - SCI Control Register 3; 0x00000015 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCC3_PEIE: equ 0 ; Receiver Parity Error Interrupt Enable Bit SCC3_FEIE: equ 1 ; Receiver Framing Error Interrupt Enable Bit SCC3_NEIE: equ 2 ; Receiver Noise Error Interrupt Enable Bit SCC3_ORIE: equ 3 ; Receiver Overrun Interrupt Enable Bit SCC3_T8: equ 6 ; Transmitted Bit 8 SCC3_R8: equ 7 ; Received Bit 8 ; bit position masks mSCC3_PEIE: equ %00000001 mSCC3_FEIE: equ %00000010 mSCC3_NEIE: equ %00000100 mSCC3_ORIE: equ %00001000 mSCC3_T8: equ %01000000 mSCC3_R8: equ %10000000 ;*** SCS1 - SCI Status Register 1; 0x00000016 *** SCS1: equ $00000016 ;*** SCS1 - SCI Status Register 1; 0x00000016 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCS1_PE: equ 0 ; Receiver Parity Error Bit SCS1_FE: equ 1 ; Receiver Framing Error Bit SCS1_NF: equ 2 ; Receiver Noise Flag Bit SCS1_OR: equ 3 ; Receiver Overrun Bit SCS1_IDLE: equ 4 ; Receiver Idle Bit SCS1_SCRF: equ 5 ; SCI Receiver Full Bit SCS1_TC: equ 6 ; Transmission Complete Bit SCS1_SCTE: equ 7 ; SCI Transmitter Empty Bit ; bit position masks mSCS1_PE: equ %00000001 mSCS1_FE: equ %00000010 mSCS1_NF: equ %00000100 mSCS1_OR: equ %00001000 mSCS1_IDLE: equ %00010000 mSCS1_SCRF: equ %00100000 mSCS1_TC: equ %01000000 mSCS1_SCTE: equ %10000000 ;*** SCS2 - SCI Status Register 2; 0x00000017 *** SCS2: equ $00000017 ;*** SCS2 - SCI Status Register 2; 0x00000017 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCS2_RPF: equ 0 ; Reception in Progress Flag Bit SCS2_BKF: equ 1 ; Break Flag Bit ; bit position masks mSCS2_RPF: equ %00000001 mSCS2_BKF: equ %00000010 ;*** SCDR - SCI Data Register; 0x00000018 *** SCDR: equ $00000018 ;*** SCDR - SCI Data Register; 0x00000018 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCDR_R0_T0: equ 0 ; Receive/Transmit Data Bit 0 SCDR_R1_T1: equ 1 ; Receive/Transmit Data Bit 1 SCDR_R2_T2: equ 2 ; Receive/Transmit Data Bit 2 SCDR_R3_T3: equ 3 ; Receive/Transmit Data Bit 3 SCDR_R4_T4: equ 4 ; Receive/Transmit Data Bit 4 SCDR_R5_T5: equ 5 ; Receive/Transmit Data Bit 5 SCDR_R6_T6: equ 6 ; Receive/Transmit Data Bit 6 SCDR_R7_T7: equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCDR_R0_T0: equ %00000001 mSCDR_R1_T1: equ %00000010 mSCDR_R2_T2: equ %00000100 mSCDR_R3_T3: equ %00001000 mSCDR_R4_T4: equ %00010000 mSCDR_R5_T5: equ %00100000 mSCDR_R6_T6: equ %01000000 mSCDR_R7_T7: equ %10000000 ;*** SCBR - SCI Baud Rate Register; 0x00000019 *** SCBR: equ $00000019 ;*** SCBR - SCI Baud Rate Register; 0x00000019 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCBR_SCR0: equ 0 ; SCI Baud Rate Select Bit 0 SCBR_SCR1: equ 1 ; SCI Baud Rate Select Bit 1 SCBR_SCR2: equ 2 ; SCI Baud Rate Select Bit 2 SCBR_SCP0: equ 4 ; SCI Baud Rate Prescaler Bit 0 SCBR_SCP1: equ 5 ; SCI Baud Rate Prescaler Bit 1 ; bit position masks mSCBR_SCR0: equ %00000001 mSCBR_SCR1: equ %00000010 mSCBR_SCR2: equ %00000100 mSCBR_SCP0: equ %00010000 mSCBR_SCP1: equ %00100000 ;*** KBSCR - Keyboard Status and Control Register; 0x0000001A *** KBSCR: equ $0000001A ;*** KBSCR - Keyboard Status and Control Register; 0x0000001A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBSCR_MODE: equ 0 ; Keyboard Triggering Sensitivity Bit KBSCR_IMASK: equ 1 ; Keyboard Interrupt Mask Bit KBSCR_ACK: equ 2 ; Keyboard Acknowledge Bit KBSCR_KEYF: equ 3 ; Keyboard Flag Bit ; bit position masks mKBSCR_MODE: equ %00000001 mKBSCR_IMASK: equ %00000010 mKBSCR_ACK: equ %00000100 mKBSCR_KEYF: equ %00001000 ;*** KBIER - Keyobard Interrupt Enable Register; 0x0000001B *** KBIER: equ $0000001B ;*** KBIER - Keyobard Interrupt Enable Register; 0x0000001B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBIER_KBIE0: equ 0 ; Keyboard Interrut Enable Bit 0 KBIER_KBIE1: equ 1 ; Keyboard Interrut Enable Bit 1 KBIER_KBIE2: equ 2 ; Keyboard Interrut Enable Bit 2 KBIER_KBIE3: equ 3 ; Keyboard Interrut Enable Bit 3 KBIER_KBIE4: equ 4 ; Keyboard Interrut Enable Bit 4 KBIER_KBIE5: equ 5 ; Keyboard Interrut Enable Bit 5 KBIER_KBIE6: equ 6 ; Keyboard Interrut Enable Bit 6 KBIER_KBIE7: equ 7 ; Keyboard Interrut Enable Bit 7 ; bit position masks mKBIER_KBIE0: equ %00000001 mKBIER_KBIE1: equ %00000010 mKBIER_KBIE2: equ %00000100 mKBIER_KBIE3: equ %00001000 mKBIER_KBIE4: equ %00010000 mKBIER_KBIE5: equ %00100000 mKBIER_KBIE6: equ %01000000 mKBIER_KBIE7: equ %10000000 ;*** INTSCR2 - IRQ2 Status and Control Register; 0x0000001C *** INTSCR2: equ $0000001C ;*** INTSCR2 - IRQ2 Status and Control Register; 0x0000001C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTSCR2_MODE2: equ 0 ; IRQ2 Edge/Level Select Bit INTSCR2_IMASK2: equ 1 ; IRQ2 Interrupt Mask Bit INTSCR2_ACK2: equ 2 ; IRQ2 Interrupt Request Acknowledge Bit INTSCR2_IRQ2F: equ 3 ; IRQ2 Flag Bit INTSCR2_PUC0ENB: equ 6 ; IRQ2 Pin Pullup Enable Bit ; bit position masks mINTSCR2_MODE2: equ %00000001 mINTSCR2_IMASK2: equ %00000010 mINTSCR2_ACK2: equ %00000100 mINTSCR2_IRQ2F: equ %00001000 mINTSCR2_PUC0ENB: equ %01000000 ;*** CONFIG2 - Configuration Register 2; 0x0000001D *** CONFIG2: equ $0000001D ;*** CONFIG2 - Configuration Register 2; 0x0000001D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CONFIG2_SCIBDSRC: equ 0 ; SCI Baud Rate Clock Source Bit CONFIG2_OSCCLK0: equ 3 ; Oscillator Output Control Bit 0 CONFIG2_OSCCLK1: equ 4 ; Oscillator Output Control Bit 1 CONFIG2_STOP_XCLKEN: equ 5 ; Crystal Oscillator Stop Mode Enable CONFIG2_STOP_RCLKEN: equ 6 ; RC Oscillator Stop Mode Enable CONFIG2_STOP_ICLKDIS: equ 7 ; Internal Oscillator Stop Mode Disable ; bit position masks mCONFIG2_SCIBDSRC: equ %00000001 mCONFIG2_OSCCLK0: equ %00001000 mCONFIG2_OSCCLK1: equ %00010000 mCONFIG2_STOP_XCLKEN: equ %00100000 mCONFIG2_STOP_RCLKEN: equ %01000000 mCONFIG2_STOP_ICLKDIS: equ %10000000 ;*** INTSCR1 - IRQ1 Status and Control Register; 0x0000001E *** INTSCR1: equ $0000001E ;*** INTSCR1 - IRQ1 Status and Control Register; 0x0000001E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTSCR1_MODE1: equ 0 ; IRQ1 Edge/Level Select Bit INTSCR1_IMASK1: equ 1 ; IRQ1 Interrupt Mask Bit INTSCR1_ACK1: equ 2 ; IRQ1 Interrupt Request Acknowledge Bit INTSCR1_IRQ1F: equ 3 ; IRQ1 Flag Bit ; bit position masks mINTSCR1_MODE1: equ %00000001 mINTSCR1_IMASK1: equ %00000010 mINTSCR1_ACK1: equ %00000100 mINTSCR1_IRQ1F: equ %00001000 ;*** CONFIG1 - Configuration Register 1; 0x0000001F *** CONFIG1: equ $0000001F ;*** CONFIG1 - Configuration Register 1; 0x0000001F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CONFIG1_COPD: equ 0 ; COP Disable Bit CONFIG1_STOP: equ 1 ; STOP Instruction Enable Bit CONFIG1_SSREC: equ 2 ; Short Stop Recovery Bit CONFIG1_LVIREGD: equ 3 ; VREG LVI Circuit Disable Bit CONFIG1_LVIPWRD: equ 4 ; LVI Power Disable Bit CONFIG1_LVIRSTD: equ 5 ; LVI Reset Disable Bit CONFIG1_LVISTOP: equ 6 ; LVI Enable in Stop Mode Bit CONFIG1_COPRS: equ 7 ; COP rate Select Bit ; bit position masks mCONFIG1_COPD: equ %00000001 mCONFIG1_STOP: equ %00000010 mCONFIG1_SSREC: equ %00000100 mCONFIG1_LVIREGD: equ %00001000 mCONFIG1_LVIPWRD: equ %00010000 mCONFIG1_LVIRSTD: equ %00100000 mCONFIG1_LVISTOP: equ %01000000 mCONFIG1_COPRS: equ %10000000 ;*** T1SC - TIM1 Status and Control Register; 0x00000020 *** T1SC: equ $00000020 ;*** T1SC - TIM1 Status and Control Register; 0x00000020 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET T1SC_PS0: equ 0 ; Prescaler Select Bit 0 T1SC_PS1: equ 1 ; Prescaler Select Bit 1 T1SC_PS2: equ 2 ; Prescaler Select Bit 2 T1SC_TRST: equ 4 ; TIM1 Reset Bit T1SC_TSTOP: equ 5 ; TIM1 Stop Bit T1SC_TOIE: equ 6 ; TIM1 Overflow Interrupt Enable Bit T1SC_TOF: equ 7 ; TIM1 Overflow Flag Bit ; bit position masks mT1SC_PS0: equ %00000001 mT1SC_PS1: equ %00000010 mT1SC_PS2: equ %00000100 mT1SC_TRST: equ %00010000 mT1SC_TSTOP: equ %00100000 mT1SC_TOIE: equ %01000000 mT1SC_TOF: equ %10000000 ;*** T1CNT - TIM1 Counter Register; 0x00000021 *** T1CNT: equ $00000021 ;*** T1CNT - TIM1 Counter Register; 0x00000021 *** ;*** T1CNTH - TIM1 Counter High Register; 0x00000021 *** T1CNTH: equ $00000021 ;*** T1CNTH - TIM1 Counter High Register; 0x00000021 *** ;*** T1CNTL - TIM1 Counter Low Register; 0x00000022 *** T1CNTL: equ $00000022 ;*** T1CNTL - TIM1 Counter Low Register; 0x00000022 *** ;*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 *** T1MOD: equ $00000023 ;*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 *** ;*** T1MODH - TIM1 Counter Modulo High Register; 0x00000023 *** T1MODH: equ $00000023 ;*** T1MODH - TIM1 Counter Modulo High Register; 0x00000023 *** ;*** T1MODL - TIM1 Counter Modulo Low Register; 0x00000024 *** T1MODL: equ $00000024 ;*** T1MODL - TIM1 Counter Modulo Low Register; 0x00000024 *** ;*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 *** T1SC0: equ $00000025 ;*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET T1SC0_CH0MAX: equ 0 ; Channel 0 Maximum Duty Cycle Bit T1SC0_TOV0: equ 1 ; Toggle-On-Overflow Bit T1SC0_ELS0A: equ 2 ; Edge/Level Select Bit A T1SC0_ELS0B: equ 3 ; Edge/Level Select Bit B T1SC0_MS0A: equ 4 ; Mode Select Bit A T1SC0_MS0B: equ 5 ; Mode Select Bit B T1SC0_CH0IE: equ 6 ; Channel 0 Interrupt Enable Bit T1SC0_CH0F: equ 7 ; Channel 0 Flag Bit ; bit position masks mT1SC0_CH0MAX: equ %00000001 mT1SC0_TOV0: equ %00000010 mT1SC0_ELS0A: equ %00000100 mT1SC0_ELS0B: equ %00001000 mT1SC0_MS0A: equ %00010000 mT1SC0_MS0B: equ %00100000 mT1SC0_CH0IE: equ %01000000 mT1SC0_CH0F: equ %10000000 ;*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 *** T1CH0: equ $00000026 ;*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 *** ;*** T1CH0H - TIM1 Channel 0 High Register; 0x00000026 *** T1CH0H: equ $00000026 ;*** T1CH0H - TIM1 Channel 0 High Register; 0x00000026 *** ;*** T1CH0L - TIM1 Channel 0 Low Register; 0x00000027 *** T1CH0L: equ $00000027 ;*** T1CH0L - TIM1 Channel 0 Low Register; 0x00000027 *** ;*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 *** T1SC1: equ $00000028 ;*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET T1SC1_CH1MAX: equ 0 ; Channel 1 Maximum Duty Cycle Bit T1SC1_TOV1: equ 1 ; Toggle-On-Overflow Bit T1SC1_ELS1A: equ 2 ; Edge/Level Select Bit A T1SC1_ELS1B: equ 3 ; Edge/Level Select Bit B T1SC1_MS1A: equ 4 ; Mode Select Bit A T1SC1_CH1IE: equ 6 ; Channel 1 Interrupt Enable Bit T1SC1_CH1F: equ 7 ; Channel 1 Flag Bit ; bit position masks mT1SC1_CH1MAX: equ %00000001 mT1SC1_TOV1: equ %00000010 mT1SC1_ELS1A: equ %00000100 mT1SC1_ELS1B: equ %00001000 mT1SC1_MS1A: equ %00010000 mT1SC1_CH1IE: equ %01000000 mT1SC1_CH1F: equ %10000000 ;*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 *** T1CH1: equ $00000029 ;*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 *** ;*** T1CH1H - TIM1 Channel 1 High Register; 0x00000029 *** T1CH1H: equ $00000029 ;*** T1CH1H - TIM1 Channel 1 High Register; 0x00000029 *** ;*** T1CH1L - TIM1 Channel 1 Low Register; 0x0000002A *** T1CH1L: equ $0000002A ;*** T1CH1L - TIM1 Channel 1 Low Register; 0x0000002A *** ;*** T2SC - TIM2 Status and Control Register; 0x0000002B *** T2SC: equ $0000002B ;*** T2SC - TIM2 Status and Control Register; 0x0000002B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET T2SC_PS0: equ 0 ; Prescaler Select Bit 0 T2SC_PS1: equ 1 ; Prescaler Select Bit 1 T2SC_PS2: equ 2 ; Prescaler Select Bit 2 T2SC_TRST: equ 4 ; TIM2 Reset Bit T2SC_TSTOP: equ 5 ; TIM2 Stop Bit T2SC_TOIE: equ 6 ; TIM2 Overflow Interrupt Enable Bit T2SC_TOF: equ 7 ; TIM2 Overflow Flag Bit ; bit position masks mT2SC_PS0: equ %00000001 mT2SC_PS1: equ %00000010 mT2SC_PS2: equ %00000100 mT2SC_TRST: equ %00010000 mT2SC_TSTOP: equ %00100000 mT2SC_TOIE: equ %01000000 mT2SC_TOF: equ %10000000 ;*** T2CNT - TIM2 Counter Register; 0x0000002C *** T2CNT: equ $0000002C ;*** T2CNT - TIM2 Counter Register; 0x0000002C *** ;*** T2CNTH - TIM2 Counter High Register; 0x0000002C *** T2CNTH: equ $0000002C ;*** T2CNTH - TIM2 Counter High Register; 0x0000002C *** ;*** T2CNTL - TIM2 Counter Low Register; 0x0000002D *** T2CNTL: equ $0000002D ;*** T2CNTL - TIM2 Counter Low Register; 0x0000002D *** ;*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E *** T2MOD: equ $0000002E ;*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E *** ;*** T2MODH - TIM2 Counter Modulo High Register; 0x0000002E *** T2MODH: equ $0000002E ;*** T2MODH - TIM2 Counter Modulo High Register; 0x0000002E *** ;*** T2MODL - TIM2 Counter Modulo Low Register; 0x0000002F *** T2MODL: equ $0000002F ;*** T2MODL - TIM2 Counter Modulo Low Register; 0x0000002F *** ;*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000030 *** T2SC0: equ $00000030 ;*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000030 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET T2SC0_CH0MAX: equ 0 ; Channel 0 Maximum Duty Cycle Bit T2SC0_TOV0: equ 1 ; Toggle-On-Overflow Bit T2SC0_ELS0A: equ 2 ; Edge/Level Select Bit A T2SC0_ELS0B: equ 3 ; Edge/Level Select Bit B T2SC0_MS0A: equ 4 ; Mode Select Bit A T2SC0_MS0B: equ 5 ; Mode Select Bit B T2SC0_CH0IE: equ 6 ; Channel 0 Interrupt Enable Bit T2SC0_CH0F: equ 7 ; Channel 0 Flag Bit ; bit position masks mT2SC0_CH0MAX: equ %00000001 mT2SC0_TOV0: equ %00000010 mT2SC0_ELS0A: equ %00000100 mT2SC0_ELS0B: equ %00001000 mT2SC0_MS0A: equ %00010000 mT2SC0_MS0B: equ %00100000 mT2SC0_CH0IE: equ %01000000 mT2SC0_CH0F: equ %10000000 ;*** T2CH0 - TIM2 Channel 0 Register; 0x00000031 *** T2CH0: equ $00000031 ;*** T2CH0 - TIM2 Channel 0 Register; 0x00000031 *** ;*** T2CH0H - TIM2 Channel 0 High Register; 0x00000031 *** T2CH0H: equ $00000031 ;*** T2CH0H - TIM2 Channel 0 High Register; 0x00000031 *** ;*** T2CH0L - TIM2 Channel 0 Low Register; 0x00000032 *** T2CH0L: equ $00000032 ;*** T2CH0L - TIM2 Channel 0 Low Register; 0x00000032 *** ;*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000033 *** T2SC1: equ $00000033 ;*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000033 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET T2SC1_CH1MAX: equ 0 ; Channel 1 Maximum Duty Cycle Bit T2SC1_TOV1: equ 1 ; Toggle-On-Overflow Bit T2SC1_ELS1A: equ 2 ; Edge/Level Select Bit A T2SC1_ELS1B: equ 3 ; Edge/Level Select Bit B T2SC1_MS1A: equ 4 ; Mode Select Bit A T2SC1_CH1IE: equ 6 ; Channel 1 Interrupt Enable Bit T2SC1_CH1F: equ 7 ; Channel 1 Flag Bit ; bit position masks mT2SC1_CH1MAX: equ %00000001 mT2SC1_TOV1: equ %00000010 mT2SC1_ELS1A: equ %00000100 mT2SC1_ELS1B: equ %00001000 mT2SC1_MS1A: equ %00010000 mT2SC1_CH1IE: equ %01000000 mT2SC1_CH1F: equ %10000000 ;*** T2CH1 - TIM2 Channel 1 Register; 0x00000034 *** T2CH1: equ $00000034 ;*** T2CH1 - TIM2 Channel 1 Register; 0x00000034 *** ;*** T2CH1H - TIM2 Channel 1 High Register; 0x00000034 *** T2CH1H: equ $00000034 ;*** T2CH1H - TIM2 Channel 1 High Register; 0x00000034 *** ;*** T2CH1L - TIM2 Channel 1 Low Register; 0x00000035 *** T2CH1L: equ $00000035 ;*** T2CH1L - TIM2 Channel 1 Low Register; 0x00000035 *** ;*** PCTL - PLL Control Register; 0x00000036 *** PCTL: equ $00000036 ;*** PCTL - PLL Control Register; 0x00000036 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PCTL_VPR0: equ 0 ; VCO Power-of-Two Range Select Bit 0 PCTL_VPR1: equ 1 ; VCO Power-of-Two Range Select Bit 1 PCTL_PRE0: equ 2 ; Prescaler Program Bit 0 PCTL_PRE1: equ 3 ; Prescaler Program Bit 1 PCTL_BCS: equ 4 ; Base Clock Select Bit PCTL_PLLON: equ 5 ; PLL On Bit PCTL_PLLF: equ 6 ; PLL Flag Bit PCTL_PLLIE: equ 7 ; PLL Interrupt Enable Bit ; bit position masks mPCTL_VPR0: equ %00000001 mPCTL_VPR1: equ %00000010 mPCTL_PRE0: equ %00000100 mPCTL_PRE1: equ %00001000 mPCTL_BCS: equ %00010000 mPCTL_PLLON: equ %00100000 mPCTL_PLLF: equ %01000000 mPCTL_PLLIE: equ %10000000 ;*** PBWC - PLL Bandwidth Control Register; 0x00000037 *** PBWC: equ $00000037 ;*** PBWC - PLL Bandwidth Control Register; 0x00000037 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PBWC_ACQ: equ 5 ; Automatic Bandwidth Control Bit PBWC_LOCK: equ 6 ; Lock Indicator Bit PBWC_AUTO: equ 7 ; Acquisiton Mode Bit ; bit position masks mPBWC_ACQ: equ %00100000 mPBWC_LOCK: equ %01000000 mPBWC_AUTO: equ %10000000 ;*** PMS - PLL Multiplier Select Register; 0x00000038 *** PMS: equ $00000038 ;*** PMS - PLL Multiplier Select Register; 0x00000038 *** ;*** PMSH - PLL Multiplier Select Register High; 0x00000038 *** PMSH: equ $00000038 ;*** PMSH - PLL Multiplier Select Register High; 0x00000038 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PMSH_MUL8: equ 0 ; PLL Multiplier Select Bit 8 PMSH_MUL9: equ 1 ; PLL Multiplier Select Bit 9 PMSH_MUL10: equ 2 ; PLL Multiplier Select Bit 10 PMSH_MUL11: equ 3 ; PLL Multiplier Select Bit 11 ; bit position masks mPMSH_MUL8: equ %00000001 mPMSH_MUL9: equ %00000010 mPMSH_MUL10: equ %00000100 mPMSH_MUL11: equ %00001000 ;*** PMSL - PLL Multiplier Select Register Low; 0x00000039 *** PMSL: equ $00000039 ;*** PMSL - PLL Multiplier Select Register Low; 0x00000039 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PMSL_MUL0: equ 0 ; PLL Multiplier Select Bit 0 PMSL_MUL1: equ 1 ; PLL Multiplier Select Bit 1 PMSL_MUL2: equ 2 ; PLL Multiplier Select Bit 2 PMSL_MUL3: equ 3 ; PLL Multiplier Select Bit 3 PMSL_MUL4: equ 4 ; PLL Multiplier Select Bit 4 PMSL_MUL5: equ 5 ; PLL Multiplier Select Bit 5 PMSL_MUL6: equ 6 ; PLL Multiplier Select Bit 6 PMSL_MUL7: equ 7 ; PLL Multiplier Select Bit 7 ; bit position masks mPMSL_MUL0: equ %00000001 mPMSL_MUL1: equ %00000010 mPMSL_MUL2: equ %00000100 mPMSL_MUL3: equ %00001000 mPMSL_MUL4: equ %00010000 mPMSL_MUL5: equ %00100000 mPMSL_MUL6: equ %01000000 mPMSL_MUL7: equ %10000000 ;*** PMRS - PLL VCO Range Select; 0x0000003A *** PMRS: equ $0000003A ;*** PMRS - PLL VCO Range Select; 0x0000003A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PMRS_VRS0: equ 0 ; VCO Range Select Bit 0 PMRS_VRS1: equ 1 ; VCO Range Select Bit 1 PMRS_VRS2: equ 2 ; VCO Range Select Bit 2 PMRS_VRS3: equ 3 ; VCO Range Select Bit 3 PMRS_VRS4: equ 4 ; VCO Range Select Bit 4 PMRS_VRS5: equ 5 ; VCO Range Select Bit 5 PMRS_VRS6: equ 6 ; VCO Range Select Bit 6 PMRS_VRS7: equ 7 ; VCO Range Select Bit 7 ; bit position masks mPMRS_VRS0: equ %00000001 mPMRS_VRS1: equ %00000010 mPMRS_VRS2: equ %00000100 mPMRS_VRS3: equ %00001000 mPMRS_VRS4: equ %00010000 mPMRS_VRS5: equ %00100000 mPMRS_VRS6: equ %01000000 mPMRS_VRS7: equ %10000000 ;*** PMDS - PLL Reference Divider Select Register; 0x0000003B *** PMDS: equ $0000003B ;*** PMDS - PLL Reference Divider Select Register; 0x0000003B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PMDS_RDS0: equ 0 ; Reference Divider Select Bit 0 PMDS_RDS1: equ 1 ; Reference Divider Select Bit 1 PMDS_RDS2: equ 2 ; Reference Divider Select Bit 2 PMDS_RDS3: equ 3 ; Reference Divider Select Bit 3 ; bit position masks mPMDS_RDS0: equ %00000001 mPMDS_RDS1: equ %00000010 mPMDS_RDS2: equ %00000100 mPMDS_RDS3: equ %00001000 ;*** IRSCC1 - IRSCI Control Register 1; 0x00000040 *** IRSCC1: equ $00000040 ;*** IRSCC1 - IRSCI Control Register 1; 0x00000040 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCC1_PTY: equ 0 ; Parity Bit IRSCC1_PEN: equ 1 ; Parity Enable Bit IRSCC1_ILTY: equ 2 ; Idle Line Type Bit IRSCC1_WAKE: equ 3 ; Wakeup Condition Bit IRSCC1_M: equ 4 ; Mode (Character Length) Bit IRSCC1_ENSCI: equ 6 ; Enable SCI Bit IRSCC1_LOOPS: equ 7 ; Loop Mode Select Bit ; bit position masks mIRSCC1_PTY: equ %00000001 mIRSCC1_PEN: equ %00000010 mIRSCC1_ILTY: equ %00000100 mIRSCC1_WAKE: equ %00001000 mIRSCC1_M: equ %00010000 mIRSCC1_ENSCI: equ %01000000 mIRSCC1_LOOPS: equ %10000000 ;*** IRSCC2 - IRSCI Control Register 2; 0x00000041 *** IRSCC2: equ $00000041 ;*** IRSCC2 - IRSCI Control Register 2; 0x00000041 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCC2_SBK: equ 0 ; Send Break Bit IRSCC2_RWU: equ 1 ; Receiver Wakeup Bit IRSCC2_RE: equ 2 ; Receiver Enable Bit IRSCC2_TE: equ 3 ; Transmitter Enable Bit IRSCC2_ILIE: equ 4 ; Idle Line Interrupt Enable Bit IRSCC2_SCRIE: equ 5 ; SCI Receive Interrupt Enable Bit IRSCC2_TCIE: equ 6 ; Transmission Complete Interrupt Enable Bit IRSCC2_SCTIE: equ 7 ; SCI Transmit Interrupt Enable Bit ; bit position masks mIRSCC2_SBK: equ %00000001 mIRSCC2_RWU: equ %00000010 mIRSCC2_RE: equ %00000100 mIRSCC2_TE: equ %00001000 mIRSCC2_ILIE: equ %00010000 mIRSCC2_SCRIE: equ %00100000 mIRSCC2_TCIE: equ %01000000 mIRSCC2_SCTIE: equ %10000000 ;*** IRSCC3 - IRSCI Control Register 3; 0x00000042 *** IRSCC3: equ $00000042 ;*** IRSCC3 - IRSCI Control Register 3; 0x00000042 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCC3_PEIE: equ 0 ; Receiver Parity Error Interrupt Enable Bit IRSCC3_FEIE: equ 1 ; Receiver Framing Error Interrupt Enable Bit IRSCC3_NEIE: equ 2 ; Receiver Noise Error Interrupt Enable Bit IRSCC3_ORIE: equ 3 ; Receiver Overrun Interrupt Enable Bit IRSCC3_T8: equ 6 ; Transmitted Bit 8 IRSCC3_R8: equ 7 ; Received Bit 8 ; bit position masks mIRSCC3_PEIE: equ %00000001 mIRSCC3_FEIE: equ %00000010 mIRSCC3_NEIE: equ %00000100 mIRSCC3_ORIE: equ %00001000 mIRSCC3_T8: equ %01000000 mIRSCC3_R8: equ %10000000 ;*** IRSCS1 - IRSCI Status Register 1; 0x00000043 *** IRSCS1: equ $00000043 ;*** IRSCS1 - IRSCI Status Register 1; 0x00000043 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCS1_PE: equ 0 ; Receiver Parity Error Bit IRSCS1_FE: equ 1 ; Receiver Framing Error Bit IRSCS1_NF: equ 2 ; Receiver Noise Flag Bit IRSCS1_OR: equ 3 ; Receiver Overrun Bit IRSCS1_IDLE: equ 4 ; Receiver Idle Bit IRSCS1_SCRF: equ 5 ; SCI Receiver Full Bit IRSCS1_TC: equ 6 ; Transmission Complete Bit IRSCS1_SCTE: equ 7 ; SCI Transmitter Empty Bit ; bit position masks mIRSCS1_PE: equ %00000001 mIRSCS1_FE: equ %00000010 mIRSCS1_NF: equ %00000100 mIRSCS1_OR: equ %00001000 mIRSCS1_IDLE: equ %00010000 mIRSCS1_SCRF: equ %00100000 mIRSCS1_TC: equ %01000000 mIRSCS1_SCTE: equ %10000000 ;*** IRSCS2 - IRSCI Status Register 2; 0x00000044 *** IRSCS2: equ $00000044 ;*** IRSCS2 - IRSCI Status Register 2; 0x00000044 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCS2_RPF: equ 0 ; Reception in Progress Flag Bit IRSCS2_BKF: equ 1 ; Break Flag Bit ; bit position masks mIRSCS2_RPF: equ %00000001 mIRSCS2_BKF: equ %00000010 ;*** IRSCDR - IRSCI Data Register; 0x00000045 *** IRSCDR: equ $00000045 ;*** IRSCDR - IRSCI Data Register; 0x00000045 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCDR_R0_T0: equ 0 ; Receive/Transmit Data Bit 0 IRSCDR_R1_T1: equ 1 ; Receive/Transmit Data Bit 1 IRSCDR_R2_T2: equ 2 ; Receive/Transmit Data Bit 2 IRSCDR_R3_T3: equ 3 ; Receive/Transmit Data Bit 3 IRSCDR_R4_T4: equ 4 ; Receive/Transmit Data Bit 4 IRSCDR_R5_T5: equ 5 ; Receive/Transmit Data Bit 5 IRSCDR_R6_T6: equ 6 ; Receive/Transmit Data Bit 6 IRSCDR_R7_T7: equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mIRSCDR_R0_T0: equ %00000001 mIRSCDR_R1_T1: equ %00000010 mIRSCDR_R2_T2: equ %00000100 mIRSCDR_R3_T3: equ %00001000 mIRSCDR_R4_T4: equ %00010000 mIRSCDR_R5_T5: equ %00100000 mIRSCDR_R6_T6: equ %01000000 mIRSCDR_R7_T7: equ %10000000 ;*** IRSCBR - IRSCI Baud Rate Register; 0x00000046 *** IRSCBR: equ $00000046 ;*** IRSCBR - IRSCI Baud Rate Register; 0x00000046 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCBR_SCR0: equ 0 ; SCI Baud Rate Select Bit 0 IRSCBR_SCR1: equ 1 ; SCI Baud Rate Select Bit 1 IRSCBR_SCR2: equ 2 ; SCI Baud Rate Select Bit 2 IRSCBR_SCP0: equ 4 ; SCI Baud Rate Prescaler Bit 0 IRSCBR_SCP1: equ 5 ; SCI Baud Rate Prescaler Bit 1 IRSCBR_CKS: equ 7 ; Baud Clock Input Select ; bit position masks mIRSCBR_SCR0: equ %00000001 mIRSCBR_SCR1: equ %00000010 mIRSCBR_SCR2: equ %00000100 mIRSCBR_SCP0: equ %00010000 mIRSCBR_SCP1: equ %00100000 mIRSCBR_CKS: equ %10000000 ;*** IRSCIRCR - IRSCI Infra-ref Control Register; 0x00000047 *** IRSCIRCR: equ $00000047 ;*** IRSCIRCR - IRSCI Infra-ref Control Register; 0x00000047 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRSCIRCR_IREN: equ 0 ; IR Enable Bit IRSCIRCR_TNP0: equ 1 ; Transmitter Narrow Pulse Bit 0 IRSCIRCR_TNP1: equ 2 ; Transmitter Narrow Pulse Bit 1 ; bit position masks mIRSCIRCR_IREN: equ %00000001 mIRSCIRCR_TNP0: equ %00000010 mIRSCIRCR_TNP1: equ %00000100 ;*** MMADR - Multi-Master IIC Address Register; 0x00000048 *** MMADR: equ $00000048 ;*** MMADR - Multi-Master IIC Address Register; 0x00000048 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMADR_MMEXTAD: equ 0 ; Multi-Master Expanded Address MMADR_MMAD1: equ 1 ; Multi-Master Address Bit 1 MMADR_MMAD2: equ 2 ; Multi-Master Address Bit 2 MMADR_MMAD3: equ 3 ; Multi-Master Address Bit 3 MMADR_MMAD4: equ 4 ; Multi-Master Address Bit 4 MMADR_MMAD5: equ 5 ; Multi-Master Address Bit 5 MMADR_MMAD6: equ 6 ; Multi-Master Address Bit 6 MMADR_MMAD7: equ 7 ; Multi-Master Address Bit 7 ; bit position masks mMMADR_MMEXTAD: equ %00000001 mMMADR_MMAD1: equ %00000010 mMMADR_MMAD2: equ %00000100 mMMADR_MMAD3: equ %00001000 mMMADR_MMAD4: equ %00010000 mMMADR_MMAD5: equ %00100000 mMMADR_MMAD6: equ %01000000 mMMADR_MMAD7: equ %10000000 ;*** MMCR1 - Multi-Master IIC Control Register 1; 0x00000049 *** MMCR1: equ $00000049 ;*** MMCR1 - Multi-Master IIC Control Register 1; 0x00000049 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMCR1_MMCRCBYTE: equ 1 ; Multi-Master IIC CRC Byte MMCR1_REPSEN: equ 2 ; Repeated Start Enable MMCR1_MMTXAK: equ 3 ; Transmit Acknowledge Enable MMCR1_MMCLRBB: equ 5 ; Multi-Master IIC Clear Busy Bit MMCR1_MMIEN: equ 6 ; Multi-Master IIC Interrupt Enable MMCR1_MMEN: equ 7 ; Multi-Master IIC Enable ; bit position masks mMMCR1_MMCRCBYTE: equ %00000010 mMMCR1_REPSEN: equ %00000100 mMMCR1_MMTXAK: equ %00001000 mMMCR1_MMCLRBB: equ %00100000 mMMCR1_MMIEN: equ %01000000 mMMCR1_MMEN: equ %10000000 ;*** MMCR2 - Multi-Master IIC Control Register 2; 0x0000004A *** MMCR2: equ $0000004A ;*** MMCR2 - Multi-Master IIC Control Register 2; 0x0000004A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMCR2_MMCRCEF: equ 0 ; Multi-Master IIC CRC Error Flag MMCR2_MMRW: equ 3 ; Multi-Master IIC Master Read/Write MMCR2_MMAST: equ 4 ; Multi-Master IIC Master Control MMCR2_MMBB: equ 5 ; Multi-Master IIC Bus Busy Flag MMCR2_MMNAKIF: equ 6 ; No Acnknowledge Interrupt Flag MMCR2_MMALIF: equ 7 ; Arbitration Loss Interrupt Flag ; bit position masks mMMCR2_MMCRCEF: equ %00000001 mMMCR2_MMRW: equ %00001000 mMMCR2_MMAST: equ %00010000 mMMCR2_MMBB: equ %00100000 mMMCR2_MMNAKIF: equ %01000000 mMMCR2_MMALIF: equ %10000000 ;*** MMSR - Multi-Master IIC Status Register; 0x0000004B *** MMSR: equ $0000004B ;*** MMSR - Multi-Master IIC Status Register; 0x0000004B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMSR_MMRXBF: equ 0 ; Multi-Master Receive Buffer Full MMSR_MMTXBE: equ 1 ; Multi-Master Transmit Buffer Empty MMSR_MMCRCBF: equ 2 ; CRC Data Buffer Full Flag MMSR_MMRXAK: equ 3 ; Multi-Master Receive Acknowledge MMSR_MMSRW: equ 4 ; Multi-Master Slave Read/Write MMSR_MMATCH: equ 5 ; Multi-Master Address Match MMSR_MMTXIF: equ 6 ; Multi-Master Transmit Interrupt Flag MMSR_MMRXIF: equ 7 ; Multi-Master IIC Receive Interrupt Flag ; bit position masks mMMSR_MMRXBF: equ %00000001 mMMSR_MMTXBE: equ %00000010 mMMSR_MMCRCBF: equ %00000100 mMMSR_MMRXAK: equ %00001000 mMMSR_MMSRW: equ %00010000 mMMSR_MMATCH: equ %00100000 mMMSR_MMTXIF: equ %01000000 mMMSR_MMRXIF: equ %10000000 ;*** MMDTR - Multi-Master IIC Data Transmit Register; 0x0000004C *** MMDTR: equ $0000004C ;*** MMDTR - Multi-Master IIC Data Transmit Register; 0x0000004C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMDTR_MMTD0: equ 0 ; Multi-Master IIC Transmit Data Bit 0 MMDTR_MMTD1: equ 1 ; Multi-Master IIC Transmit Data Bit 1 MMDTR_MMTD2: equ 2 ; Multi-Master IIC Transmit Data Bit 2 MMDTR_MMTD3: equ 3 ; Multi-Master IIC Transmit Data Bit 3 MMDTR_MMTD4: equ 4 ; Multi-Master IIC Transmit Data Bit 4 MMDTR_MMTD5: equ 5 ; Multi-Master IIC Transmit Data Bit 5 MMDTR_MMTD6: equ 6 ; Multi-Master IIC Transmit Data Bit 6 MMDTR_MMTD7: equ 7 ; Multi-Master IIC Transmit Data Bit 7 ; bit position masks mMMDTR_MMTD0: equ %00000001 mMMDTR_MMTD1: equ %00000010 mMMDTR_MMTD2: equ %00000100 mMMDTR_MMTD3: equ %00001000 mMMDTR_MMTD4: equ %00010000 mMMDTR_MMTD5: equ %00100000 mMMDTR_MMTD6: equ %01000000 mMMDTR_MMTD7: equ %10000000 ;*** MMDRR - Multi-Master IIC Data Receive Register; 0x0000004D *** MMDRR: equ $0000004D ;*** MMDRR - Multi-Master IIC Data Receive Register; 0x0000004D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMDRR_MMRD0: equ 0 ; Multi-Master IIC Receive Data Bit 0 MMDRR_MMRD1: equ 1 ; Multi-Master IIC Receive Data Bit 1 MMDRR_MMRD2: equ 2 ; Multi-Master IIC Receive Data Bit 2 MMDRR_MMRD3: equ 3 ; Multi-Master IIC Receive Data Bit 3 MMDRR_MMRD4: equ 4 ; Multi-Master IIC Receive Data Bit 4 MMDRR_MMRD5: equ 5 ; Multi-Master IIC Receive Data Bit 5 MMDRR_MMRD6: equ 6 ; Multi-Master IIC Receive Data Bit 6 MMDRR_MMRD7: equ 7 ; Multi-Master IIC Receive Data Bit 7 ; bit position masks mMMDRR_MMRD0: equ %00000001 mMMDRR_MMRD1: equ %00000010 mMMDRR_MMRD2: equ %00000100 mMMDRR_MMRD3: equ %00001000 mMMDRR_MMRD4: equ %00010000 mMMDRR_MMRD5: equ %00100000 mMMDRR_MMRD6: equ %01000000 mMMDRR_MMRD7: equ %10000000 ;*** MMCRDR - Multi-Master IIC CRC Data Register; 0x0000004E *** MMCRDR: equ $0000004E ;*** MMCRDR - Multi-Master IIC CRC Data Register; 0x0000004E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMCRDR_MMCRCD0: equ 0 ; Multi-Master IIC CRC Data Bit 0 MMCRDR_MMCRCD1: equ 1 ; Multi-Master IIC CRC Data Bit 1 MMCRDR_MMCRCD2: equ 2 ; Multi-Master IIC CRC Data Bit 2 MMCRDR_MMCRCD3: equ 3 ; Multi-Master IIC CRC Data Bit 3 MMCRDR_MMCRCD4: equ 4 ; Multi-Master IIC CRC Data Bit 4 MMCRDR_MMCRCD5: equ 5 ; Multi-Master IIC CRC Data Bit 5 MMCRDR_MMCRCD6: equ 6 ; Multi-Master IIC CRC Data Bit 6 MMCRDR_MMCRCD7: equ 7 ; Multi-Master IIC CRC Data Bit 7 ; bit position masks mMMCRDR_MMCRCD0: equ %00000001 mMMCRDR_MMCRCD1: equ %00000010 mMMCRDR_MMCRCD2: equ %00000100 mMMCRDR_MMCRCD3: equ %00001000 mMMCRDR_MMCRCD4: equ %00010000 mMMCRDR_MMCRCD5: equ %00100000 mMMCRDR_MMCRCD6: equ %01000000 mMMCRDR_MMCRCD7: equ %10000000 ;*** MMFDR - Multi-Master IIC Frequency Divider Register; 0x0000004F *** MMFDR: equ $0000004F ;*** MMFDR - Multi-Master IIC Frequency Divider Register; 0x0000004F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MMFDR_MMBR0: equ 0 ; Frequency Divider Bit 0 MMFDR_MMBR1: equ 1 ; Frequency Divider Bit 1 MMFDR_MMBR2: equ 2 ; Frequency Divider Bit 2 ; bit position masks mMMFDR_MMBR0: equ %00000001 mMMFDR_MMBR1: equ %00000010 mMMFDR_MMBR2: equ %00000100 ;*** TBCR - Timebase Control Register; 0x00000051 *** TBCR: equ $00000051 ;*** TBCR - Timebase Control Register; 0x00000051 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TBCR_TBON: equ 1 ; Timebase Enabled TBCR_TBIE: equ 2 ; Timebase Interrupt Enable TBCR_TACK: equ 3 ; Timebase ACKnowledge TBCR_TBR0: equ 4 ; Timebase Rate Selection Bit 0 TBCR_TBR1: equ 5 ; Timebase Rate Selection Bit 1 TBCR_TBR2: equ 6 ; Timebase Rate Selection Bit 2 TBCR_TBIF: equ 7 ; Timebase Interrupt Flag ; bit position masks mTBCR_TBON: equ %00000010 mTBCR_TBIE: equ %00000100 mTBCR_TACK: equ %00001000 mTBCR_TBR0: equ %00010000 mTBCR_TBR1: equ %00100000 mTBCR_TBR2: equ %01000000 mTBCR_TBIF: equ %10000000 ;*** ADSCR - ADC Status and Control Register; 0x00000057 *** ADSCR: equ $00000057 ;*** ADSCR - ADC Status and Control Register; 0x00000057 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADSCR_ADCH0: equ 0 ; ADC Channel Select Bit 0 ADSCR_ADCH1: equ 1 ; ADC Channel Select Bit 1 ADSCR_ADCH2: equ 2 ; ADC Channel Select Bit 2 ADSCR_ADCH3: equ 3 ; ADC Channel Select Bit 3 ADSCR_ADCH4: equ 4 ; ADC Channel Select Bit 4 ADSCR_ADCO: equ 5 ; ADC Continuous Conversion Bit ADSCR_AIEN: equ 6 ; ADC Interrupt Enable Bit ADSCR_COCO: equ 7 ; Conversions Complete Bit ; bit position masks mADSCR_ADCH0: equ %00000001 mADSCR_ADCH1: equ %00000010 mADSCR_ADCH2: equ %00000100 mADSCR_ADCH3: equ %00001000 mADSCR_ADCH4: equ %00010000 mADSCR_ADCO: equ %00100000 mADSCR_AIEN: equ %01000000 mADSCR_COCO: equ %10000000 ;*** ADICLK - ADC Input Clock Register; 0x00000058 *** ADICLK: equ $00000058 ;*** ADICLK - ADC Input Clock Register; 0x00000058 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADICLK_MODE0: equ 2 ; Mode of Result Justification Bit 0 ADICLK_MODE1: equ 3 ; Mode of Result Justification Bit 1 ADICLK_ADICLK_BIT: equ 4 ; ADC Input Clock Register Bit ADICLK_ADIV0: equ 5 ; ADC Clock Prescaler Bit 0 ADICLK_ADIV1: equ 6 ; ADC Clock Prescaler Bit 1 ADICLK_ADIV2: equ 7 ; ADC Clock Prescaler Bit 2 ; bit position masks mADICLK_MODE0: equ %00000100 mADICLK_MODE1: equ %00001000 mADICLK_ADICLK_BIT: equ %00010000 mADICLK_ADIV0: equ %00100000 mADICLK_ADIV1: equ %01000000 mADICLK_ADIV2: equ %10000000 ;*** ADR0 - ADC Data Register High; 0x00000059 *** ADR0: equ $00000059 ;*** ADR0 - ADC Data Register High; 0x00000059 *** ;*** ADR0H - ADC Data Register High 0; 0x00000059 *** ADR0H: equ $00000059 ;*** ADR0H - ADC Data Register High 0; 0x00000059 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADR0H_AD8: equ 0 ; ADC Data Bit 8 ADR0H_AD9: equ 1 ; ADC Data Bit 9 ; bit position masks mADR0H_AD8: equ %00000001 mADR0H_AD9: equ %00000010 ;*** ADR0L - ADC Data Register Low 0; 0x0000005A *** ADR0L: equ $0000005A ;*** ADR0L - ADC Data Register Low 0; 0x0000005A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADR0L_AD0: equ 0 ; ADC Data Bit 0 ADR0L_AD1: equ 1 ; ADC Data Bit 1 ADR0L_AD2: equ 2 ; ADC Data Bit 2 ADR0L_AD3: equ 3 ; ADC Data Bit 3 ADR0L_AD4: equ 4 ; ADC Data Bit 4 ADR0L_AD5: equ 5 ; ADC Data Bit 5 ADR0L_AD6: equ 6 ; ADC Data Bit 6 ADR0L_AD7: equ 7 ; ADC Data Bit 7 ; bit position masks mADR0L_AD0: equ %00000001 mADR0L_AD1: equ %00000010 mADR0L_AD2: equ %00000100 mADR0L_AD3: equ %00001000 mADR0L_AD4: equ %00010000 mADR0L_AD5: equ %00100000 mADR0L_AD6: equ %01000000 mADR0L_AD7: equ %10000000 ;*** ADR1L - ADC Data Register Low 1; 0x0000005B *** ADR1L: equ $0000005B ;*** ADR1L - ADC Data Register Low 1; 0x0000005B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADR1L_AD0: equ 0 ; ADC Data Bit 0 ADR1L_AD1: equ 1 ; ADC Data Bit 1 ADR1L_AD2: equ 2 ; ADC Data Bit 2 ADR1L_AD3: equ 3 ; ADC Data Bit 3 ADR1L_AD4: equ 4 ; ADC Data Bit 4 ADR1L_AD5: equ 5 ; ADC Data Bit 5 ADR1L_AD6: equ 6 ; ADC Data Bit 6 ADR1L_AD7: equ 7 ; ADC Data Bit 7 ; bit position masks mADR1L_AD0: equ %00000001 mADR1L_AD1: equ %00000010 mADR1L_AD2: equ %00000100 mADR1L_AD3: equ %00001000 mADR1L_AD4: equ %00010000 mADR1L_AD5: equ %00100000 mADR1L_AD6: equ %01000000 mADR1L_AD7: equ %10000000 ;*** ADR2L - ADC Data Register Low 2; 0x0000005C *** ADR2L: equ $0000005C ;*** ADR2L - ADC Data Register Low 2; 0x0000005C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADR2L_AD0: equ 0 ; ADC Data Bit 0 ADR2L_AD1: equ 1 ; ADC Data Bit 1 ADR2L_AD2: equ 2 ; ADC Data Bit 2 ADR2L_AD3: equ 3 ; ADC Data Bit 3 ADR2L_AD4: equ 4 ; ADC Data Bit 4 ADR2L_AD5: equ 5 ; ADC Data Bit 5 ADR2L_AD6: equ 6 ; ADC Data Bit 6 ADR2L_AD7: equ 7 ; ADC Data Bit 7 ; bit position masks mADR2L_AD0: equ %00000001 mADR2L_AD1: equ %00000010 mADR2L_AD2: equ %00000100 mADR2L_AD3: equ %00001000 mADR2L_AD4: equ %00010000 mADR2L_AD5: equ %00100000 mADR2L_AD6: equ %01000000 mADR2L_AD7: equ %10000000 ;*** ADR3L - ADC Data Register Low 3; 0x0000005D *** ADR3L: equ $0000005D ;*** ADR3L - ADC Data Register Low 3; 0x0000005D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADR3L_AD0: equ 0 ; ADC Data Bit 0 ADR3L_AD1: equ 1 ; ADC Data Bit 1 ADR3L_AD2: equ 2 ; ADC Data Bit 2 ADR3L_AD3: equ 3 ; ADC Data Bit 3 ADR3L_AD4: equ 4 ; ADC Data Bit 4 ADR3L_AD5: equ 5 ; ADC Data Bit 5 ADR3L_AD6: equ 6 ; ADC Data Bit 6 ADR3L_AD7: equ 7 ; ADC Data Bit 7 ; bit position masks mADR3L_AD0: equ %00000001 mADR3L_AD1: equ %00000010 mADR3L_AD2: equ %00000100 mADR3L_AD3: equ %00001000 mADR3L_AD4: equ %00010000 mADR3L_AD5: equ %00100000 mADR3L_AD6: equ %01000000 mADR3L_AD7: equ %10000000 ;*** ADASCR - ADC Auto-Scan Control Register; 0x0000005E *** ADASCR: equ $0000005E ;*** ADASCR - ADC Auto-Scan Control Register; 0x0000005E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADASCR_ASCAN: equ 0 ; Auto-Scan Mode Enable ADASCR_AUTO0: equ 1 ; Auto-Scan Mode Channel Select Bit 0 ADASCR_AUTO1: equ 2 ; Auto-Scan Mode Channel Select Bit 1 ; bit position masks mADASCR_ASCAN: equ %00000001 mADASCR_AUTO0: equ %00000010 mADASCR_AUTO1: equ %00000100 ;*** SBSR - SIM Break Status Register; 0x0000FE00 *** SBSR: equ $0000FE00 ;*** SBSR - SIM Break Status Register; 0x0000FE00 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SBSR_SBSW: equ 1 ; SIM Break Stop/Wait ; bit position masks mSBSR_SBSW: equ %00000010 ;*** SRSR - SIM Reset Status Register; 0x0000FE01 *** SRSR: equ $0000FE01 ;*** SRSR - SIM Reset Status Register; 0x0000FE01 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRSR_LVI: equ 1 ; Low-Voltage Inhibit Reset Bit SRSR_MODRST: equ 2 ; Monitor Mode Entry Module Reset Bit SRSR_ILAD: equ 3 ; Illegal Address Reset Bit SRSR_ILOP: equ 4 ; Illegal Opcode Reset Bit SRSR_COP: equ 5 ; Computer Operating Properly Reset Bit SRSR_PIN: equ 6 ; External Reset Bit SRSR_POR: equ 7 ; Power-On Reset Bit ; bit position masks mSRSR_LVI: equ %00000010 mSRSR_MODRST: equ %00000100 mSRSR_ILAD: equ %00001000 mSRSR_ILOP: equ %00010000 mSRSR_COP: equ %00100000 mSRSR_PIN: equ %01000000 mSRSR_POR: equ %10000000 ;*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 *** SBFCR: equ $0000FE03 ;*** SBFCR - SIM Break Flag Control Register; 0x0000FE03 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SBFCR_BCFE: equ 7 ; Break Clear Flag Enable Bit ; bit position masks mSBFCR_BCFE: equ %10000000 ;*** INT1 - Interrupt Status Register 1; 0x0000FE04 *** INT1: equ $0000FE04 ;*** INT1 - Interrupt Status Register 1; 0x0000FE04 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INT1_IF1: equ 2 ; Interrupt Flag 1 INT1_IF2: equ 3 ; Interrupt Flag 2 INT1_IF3: equ 4 ; Interrupt Flag 3 INT1_IF4: equ 5 ; Interrupt Flag 4 INT1_IF5: equ 6 ; Interrupt Flag 5 INT1_IF6: equ 7 ; Interrupt Flag 6 ; bit position masks mINT1_IF1: equ %00000100 mINT1_IF2: equ %00001000 mINT1_IF3: equ %00010000 mINT1_IF4: equ %00100000 mINT1_IF5: equ %01000000 mINT1_IF6: equ %10000000 ;*** INT2 - Interrupt Status Register 2; 0x0000FE05 *** INT2: equ $0000FE05 ;*** INT2 - Interrupt Status Register 2; 0x0000FE05 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INT2_IF7: equ 0 ; Interrupt Flag 7 INT2_IF8: equ 1 ; Interrupt Flag 8 INT2_IF9: equ 2 ; Interrupt Flag 9 INT2_IF10: equ 3 ; Interrupt Flag 10 INT2_IF11: equ 4 ; Interrupt Flag 11 INT2_IF12: equ 5 ; Interrupt Flag 12 INT2_IF13: equ 6 ; Interrupt Flag 13 INT2_IF14: equ 7 ; Interrupt Flag 14 ; bit position masks mINT2_IF7: equ %00000001 mINT2_IF8: equ %00000010 mINT2_IF9: equ %00000100 mINT2_IF10: equ %00001000 mINT2_IF11: equ %00010000 mINT2_IF12: equ %00100000 mINT2_IF13: equ %01000000 mINT2_IF14: equ %10000000 ;*** INT3 - Interrupt Status Register 3; 0x0000FE06 *** INT3: equ $0000FE06 ;*** INT3 - Interrupt Status Register 3; 0x0000FE06 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INT3_IF15: equ 0 ; Interrupt Flag 15 INT3_IF16: equ 1 ; Interrupt Flag 16 INT3_IF17: equ 2 ; Interrupt Flag 17 INT3_IF18: equ 3 ; Interrupt Flag 18 INT3_IF19: equ 4 ; Interrupt Flag 19 INT3_IF20: equ 5 ; Interrupt Flag 20 INT3_IF21: equ 6 ; Interrupt Flag 21 ; bit position masks mINT3_IF15: equ %00000001 mINT3_IF16: equ %00000010 mINT3_IF17: equ %00000100 mINT3_IF18: equ %00001000 mINT3_IF19: equ %00010000 mINT3_IF20: equ %00100000 mINT3_IF21: equ %01000000 ;*** FLCR - FLASH Control Register; 0x0000FE08 *** FLCR: equ $0000FE08 ;*** FLCR - FLASH Control Register; 0x0000FE08 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FLCR_PGM: equ 0 ; Program Control Bit FLCR_ERASE: equ 1 ; Erase Control Bit FLCR_MASS: equ 2 ; Mass Erase Control Bit FLCR_HVEN: equ 3 ; High-Voltage Enable Bit ; bit position masks mFLCR_PGM: equ %00000001 mFLCR_ERASE: equ %00000010 mFLCR_MASS: equ %00000100 mFLCR_HVEN: equ %00001000 ;*** FLBPR - FLASH Block Protect Register; 0x0000FE09 *** FLBPR: equ $0000FE09 ;*** FLBPR - FLASH Block Protect Register; 0x0000FE09 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FLBPR_BPR0: equ 0 ; FLASH Block Protect Bit 0 FLBPR_BPR1: equ 1 ; FLASH Block Protect Bit 1 FLBPR_BPR2: equ 2 ; FLASH Block Protect Bit 2 FLBPR_BPR3: equ 3 ; FLASH Block Protect Bit 3 FLBPR_BPR4: equ 4 ; FLASH Block Protect Bit 4 FLBPR_BPR5: equ 5 ; FLASH Block Protect Bit 5 FLBPR_BPR6: equ 6 ; FLASH Block Protect Bit 6 FLBPR_BPR7: equ 7 ; FLASH Block Protect Bit 7 ; bit position masks mFLBPR_BPR0: equ %00000001 mFLBPR_BPR1: equ %00000010 mFLBPR_BPR2: equ %00000100 mFLBPR_BPR3: equ %00001000 mFLBPR_BPR4: equ %00010000 mFLBPR_BPR5: equ %00100000 mFLBPR_BPR6: equ %01000000 mFLBPR_BPR7: equ %10000000 ;*** BRK - Break Address Register; 0x0000FE0C *** BRK: equ $0000FE0C ;*** BRK - Break Address Register; 0x0000FE0C *** ;*** BRKH - Break Address High Register; 0x0000FE0C *** BRKH: equ $0000FE0C ;*** BRKH - Break Address High Register; 0x0000FE0C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BRKH_MUL8: equ 0 ; Break Address Register Bit 8 BRKH_MUL9: equ 1 ; Break Address Register Bit 9 BRKH_MUL10: equ 2 ; Break Address Register Bit 10 BRKH_MUL11: equ 3 ; Break Address Register Bit 11 BRKH_MUL12: equ 4 ; Break Address Register Bit 12 BRKH_MUL13: equ 5 ; Break Address Register Bit 13 BRKH_MUL14: equ 6 ; Break Address Register Bit 14 BRKH_MUL15: equ 7 ; Break Address Register Bit 15 ; bit position masks mBRKH_MUL8: equ %00000001 mBRKH_MUL9: equ %00000010 mBRKH_MUL10: equ %00000100 mBRKH_MUL11: equ %00001000 mBRKH_MUL12: equ %00010000 mBRKH_MUL13: equ %00100000 mBRKH_MUL14: equ %01000000 mBRKH_MUL15: equ %10000000 ;*** BRKL - Break Address Low Register; 0x0000FE0D *** BRKL: equ $0000FE0D ;*** BRKL - Break Address Low Register; 0x0000FE0D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BRKL_MUL0: equ 0 ; Break Address Register Bit 0 BRKL_MUL1: equ 1 ; Break Address Register Bit 1 BRKL_MUL2: equ 2 ; Break Address Register Bit 2 BRKL_MUL3: equ 3 ; Break Address Register Bit 3 BRKL_MUL4: equ 4 ; Break Address Register Bit 4 BRKL_MUL5: equ 5 ; Break Address Register Bit 5 BRKL_MUL6: equ 6 ; Break Address Register Bit 6 BRKL_MUL7: equ 7 ; Break Address Register Bit 7 ; bit position masks mBRKL_MUL0: equ %00000001 mBRKL_MUL1: equ %00000010 mBRKL_MUL2: equ %00000100 mBRKL_MUL3: equ %00001000 mBRKL_MUL4: equ %00010000 mBRKL_MUL5: equ %00100000 mBRKL_MUL6: equ %01000000 mBRKL_MUL7: equ %10000000 ;*** BRKSCR - Break Status and Control Register; 0x0000FE0E *** BRKSCR: equ $0000FE0E ;*** BRKSCR - Break Status and Control Register; 0x0000FE0E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BRKSCR_BRKA: equ 6 ; Break Active Bit BRKSCR_BRKE: equ 7 ; Break Enable Bit ; bit position masks mBRKSCR_BRKA: equ %01000000 mBRKSCR_BRKE: equ %10000000 ;*** LVISR - LVI Status Register; 0x0000FE0F *** LVISR: equ $0000FE0F ;*** LVISR - LVI Status Register; 0x0000FE0F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET LVISR_LVIOUT: equ 7 ; LVI Output Bit ; bit position masks mLVISR_LVIOUT: equ %10000000 ;*** MOR - Mask Option Register; 0x0000FFCF *** MOR: equ $0000FFCF ;*** MOR - Mask Option Register; 0x0000FFCF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MOR_OSCSEL0: equ 6 ; Oscillator Selection Bit 0 MOR_OSCSEL1: equ 7 ; Oscillator Selection Bit 1 ; bit position masks mMOR_OSCSEL0: equ %01000000 mMOR_OSCSEL1: equ %10000000 ;*** COPCTL - COP Control Register; 0x0000FFFF *** COPCTL: equ $0000FFFF ;*** COPCTL - COP Control Register; 0x0000FFFF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET COPCTL_BIT0: equ 0 ; Bit 0 COPCTL_BIT1: equ 1 ; Bit 1 COPCTL_BIT2: equ 2 ; Bit 2 COPCTL_BIT3: equ 3 ; Bit 3 COPCTL_BIT4: equ 4 ; Bit 4 COPCTL_BIT5: equ 5 ; Bit 5 COPCTL_BIT6: equ 6 ; Bit 6 COPCTL_BIT7: equ 7 ; Bit 7 ; bit position masks mCOPCTL_BIT0: equ %00000001 mCOPCTL_BIT1: equ %00000010 mCOPCTL_BIT2: equ %00000100 mCOPCTL_BIT3: equ %00001000 mCOPCTL_BIT4: equ %00010000 mCOPCTL_BIT5: equ %00100000 mCOPCTL_BIT6: equ %01000000 mCOPCTL_BIT7: equ %10000000 ;*********************************************** ;** D E P R E C I A T E D S Y M B O L S ** ;*********************************************** IFNDEF __GENERATE_APPLICATION__ ; not supported for absolute assembler XREF This_symb_has_been_depreciated ENDIF ; --------------------------------------------------------------------------- ; The following symbols were removed, because they were invalid or irrelevant ; --------------------------------------------------------------------------- ; EOF