; Based on CPU DB MC13214, version 2.87.130 (RegistersPrg V2.28) ; ################################################################### ; Filename : mc13212.inc ; Processor : MC13212 ; FileFormat: V2.28 ; DataSheet : MC1321xRM Rev. 1.1 10/2006 ; Compiler : CodeWarrior compiler ; Date/Time : 27.5.2009, 10:14 ; Abstract : ; This header implements the mapping of I/O devices. ; ; Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ; ; http : www.freescale.com ; mail : support@freescale.com ; ; CPU Registers Revisions: ; - 11.04.2006, V2.87.092: ; - Renamed bits IICA_ADDR0..6 ==> IICA_ADDR1..7 REASON: Bug-fix (#3047 in Issue Manager) ; - 27.11.2006, V2.87.107: ; - Renamed registers SPIx ==> SPI1x, IICx ==> IIC1x, KBIx ==> KBI1x, ATDx ==> ATD1x, Renamed interrupt vector Viic ==> Viic1, Vatd ==> Vatd1, Vkeyboard ==> Vkeyboard1, Vspi ==> Vspi1, Added bit ICGC1_HGO, Added bit ICGC1_LOCD, Renamed bit ICGFLTx_FILTx ==> ICGFLTx_FLTx, Added register DBGCBL. REASON: Bug-fix (#3976 in Issue Manager) ; - 04.01.2007, V2.87.115: ; - Added register s for TPM10, TPM11, TPM20 channels, Added port F registers/ REASON: Bug-fix (#4107 in Issue Manager) ; ; File-Format-Revisions: ; - 14.11.2005, V2.00 : ; - Deprecated symbols added for backward compatibility (section at the end of this file) ; - 15.11.2005, V2.01 : ; - Changes have not affected this file (because they are related to another family) ; - 17.12.2005, V2.02 : ; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 ; - 16.01.2006, V2.03 : ; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. ; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") ; - 08.03.2006, V2.04 : ; - Support for bit(s) names duplicated with any register name in .h header files ; - 24.03.2006, V2.05 : ; - Changes have not affected this file (because they are related to another family) ; - 26.04.2006, V2.06 : ; - Absolute assembly supported (depreciated symbols are not defined) ; - 27.04.2006, V2.07 : ; - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). ; - 07.06.2006, V2.08 : ; - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM. ; - 03.07.2006, V2.09 : ; - Flash commands constants supported ; - 27.10.2006, V2.10 : ; - __RESET_WATCHDOG improved formating and re-definition ; - 23.11.2006, V2.11 : ; - Changes have not affected this file (because they are related to another family) ; - 22.01.2007, V2.12 : ; - Changes have not affected this file (because they are related to another family) ; - 01.03.2007, V2.13 : ; - Flash commands constants values converted to HEX format ; - 02.03.2007, V2.14 : ; - Interrupt vector numbers added into .H, see VectorNumber_* ; - 26.03.2007, V2.15 : ; - Changes have not affected this file (because they are related to another family) ; - 10.05.2007, V2.16 : ; - Fixed flash commands definition for ColdFireV1 assembler (equ -> .equ) ; - 05.06.2007, V2.17 : ; - Changes have not affected this file (because they are related to another family) ; - 19.07.2007, V2.18 : ; - Improved number of blanked lines inside register structures ; - 06.08.2007, V2.19 : ; - CPUDB revisions generated ahead of the file-format revisions. ; - 11.09.2007, V2.20 : ; - Added comment about initialization of unbonded pins. ; - 02.01.2008, V2.21 : ; - Changes have not affected this file (because they are related to another family) ; - 13.02.2008, V2.22 : ; - Changes have not affected this file (because they are related to another family) ; - 20.02.2008, V2.23 : ; - Changes have not affected this file (because they are related to another family) ; - 03.07.2008, V2.24 : ; - Added support for bits with name starting with number (like "1HZ") ; - 28.11.2008, V2.25 : ; - StandBy RAM array declaration for ANSI-C added ; - 1.12.2008, V2.26 : ; - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ; - 17.3.2009, V2.27 : ; - Merged bit-group is not generated, if the name matchs with anouther bit name in the register ; - 6.4.2009, V2.28 : ; - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ; ; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ; derivative device. To avoid extra current drain from floating input pins, the user’s reset ; initialization routine in the application program must either enable on-chip pull-up devices ; or change the direction of unconnected pins to outputs so the pins do not float. ; ################################################################### ;*** Memory Map and Interrupt Vectors ;****************************************** ROMStart: equ $00008000 ROMEnd: equ $0000FFAF Z_RAMStart: equ $00000080 Z_RAMEnd: equ $000000FF RAMStart: equ $00000100 RAMEnd: equ $0000087F ROM1Start: equ $0000FFC0 ROM1End: equ $0000FFCB ; Vrti: equ $0000FFCC Viic1: equ $0000FFCE Vatd1: equ $0000FFD0 Vkeyboard1: equ $0000FFD2 Vsci2tx: equ $0000FFD4 Vsci2rx: equ $0000FFD6 Vsci2err: equ $0000FFD8 Vsci1tx: equ $0000FFDA Vsci1rx: equ $0000FFDC Vsci1err: equ $0000FFDE Vspi1: equ $0000FFE0 Vtpm2ovf: equ $0000FFE2 Vtpm2ch4: equ $0000FFE4 Vtpm2ch3: equ $0000FFE6 Vtpm2ch2: equ $0000FFE8 Vtpm2ch1: equ $0000FFEA Vtpm2ch0: equ $0000FFEC Vtpm1ovf: equ $0000FFEE Vtpm1ch2: equ $0000FFF0 Vtpm1ch1: equ $0000FFF2 Vtpm1ch0: equ $0000FFF4 Vicg: equ $0000FFF6 Vlvd: equ $0000FFF8 Virq: equ $0000FFFA Vswi: equ $0000FFFC Vreset: equ $0000FFFE ; ;*** PTAD - Port A Data Register; 0x00000000 *** PTAD: equ $00000000 ;*** PTAD - Port A Data Register; 0x00000000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0 PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1 PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2 PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3 PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4 PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5 PTAD_PTAD6: equ 6 ; Port A Data Register Bit 6 PTAD_PTAD7: equ 7 ; Port A Data Register Bit 7 ; bit position masks mPTAD_PTAD0: equ %00000001 mPTAD_PTAD1: equ %00000010 mPTAD_PTAD2: equ %00000100 mPTAD_PTAD3: equ %00001000 mPTAD_PTAD4: equ %00010000 mPTAD_PTAD5: equ %00100000 mPTAD_PTAD6: equ %01000000 mPTAD_PTAD7: equ %10000000 ;*** PTAPE - Pullup Enable for Port A; 0x00000001 *** PTAPE: equ $00000001 ;*** PTAPE - Pullup Enable for Port A; 0x00000001 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPE_PTAPE0: equ 0 ; Pullup Enable for Port A Bit 0 PTAPE_PTAPE1: equ 1 ; Pullup Enable for Port A Bit 1 PTAPE_PTAPE2: equ 2 ; Pullup Enable for Port A Bit 2 PTAPE_PTAPE3: equ 3 ; Pullup Enable for Port A Bit 3 PTAPE_PTAPE4: equ 4 ; Pullup Enable for Port A Bit 4 PTAPE_PTAPE5: equ 5 ; Pullup Enable for Port A Bit 5 PTAPE_PTAPE6: equ 6 ; Pullup Enable for Port A Bit 6 PTAPE_PTAPE7: equ 7 ; Pullup Enable for Port A Bit 7 ; bit position masks mPTAPE_PTAPE0: equ %00000001 mPTAPE_PTAPE1: equ %00000010 mPTAPE_PTAPE2: equ %00000100 mPTAPE_PTAPE3: equ %00001000 mPTAPE_PTAPE4: equ %00010000 mPTAPE_PTAPE5: equ %00100000 mPTAPE_PTAPE6: equ %01000000 mPTAPE_PTAPE7: equ %10000000 ;*** PTASE - Slew Rate Control Enable for Port A; 0x00000002 *** PTASE: equ $00000002 ;*** PTASE - Slew Rate Control Enable for Port A; 0x00000002 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTASE_PTASE0: equ 0 ; Slew Rate Control Enable for Port A Bit 0 PTASE_PTASE1: equ 1 ; Slew Rate Control Enable for Port A Bit 1 PTASE_PTASE2: equ 2 ; Slew Rate Control Enable for Port A Bit 2 PTASE_PTASE3: equ 3 ; Slew Rate Control Enable for Port A Bit 3 PTASE_PTASE4: equ 4 ; Slew Rate Control Enable for Port A Bit 4 PTASE_PTASE5: equ 5 ; Slew Rate Control Enable for Port A Bit 5 PTASE_PTASE6: equ 6 ; Slew Rate Control Enable for Port A Bit 6 PTASE_PTASE7: equ 7 ; Slew Rate Control Enable for Port A Bit 7 ; bit position masks mPTASE_PTASE0: equ %00000001 mPTASE_PTASE1: equ %00000010 mPTASE_PTASE2: equ %00000100 mPTASE_PTASE3: equ %00001000 mPTASE_PTASE4: equ %00010000 mPTASE_PTASE5: equ %00100000 mPTASE_PTASE6: equ %01000000 mPTASE_PTASE7: equ %10000000 ;*** PTADD - Data Direction Register A; 0x00000003 *** PTADD: equ $00000003 ;*** PTADD - Data Direction Register A; 0x00000003 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0 PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1 PTADD_PTADD2: equ 2 ; Data Direction for Port A Bit 2 PTADD_PTADD3: equ 3 ; Data Direction for Port A Bit 3 PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4 PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5 PTADD_PTADD6: equ 6 ; Data Direction for Port A Bit 6 PTADD_PTADD7: equ 7 ; Data Direction for Port A Bit 7 ; bit position masks mPTADD_PTADD0: equ %00000001 mPTADD_PTADD1: equ %00000010 mPTADD_PTADD2: equ %00000100 mPTADD_PTADD3: equ %00001000 mPTADD_PTADD4: equ %00010000 mPTADD_PTADD5: equ %00100000 mPTADD_PTADD6: equ %01000000 mPTADD_PTADD7: equ %10000000 ;*** PTBD - Port B Data Register; 0x00000004 *** PTBD: equ $00000004 ;*** PTBD - Port B Data Register; 0x00000004 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBD_PTBD0: equ 0 ; Port B Data Register Bit 0 PTBD_PTBD1: equ 1 ; Port B Data Register Bit 1 PTBD_PTBD2: equ 2 ; Port B Data Register Bit 2 PTBD_PTBD3: equ 3 ; Port B Data Register Bit 3 PTBD_PTBD4: equ 4 ; Port B Data Register Bit 4 PTBD_PTBD5: equ 5 ; Port B Data Register Bit 5 PTBD_PTBD6: equ 6 ; Port B Data Register Bit 6 PTBD_PTBD7: equ 7 ; Port B Data Register Bit 7 ; bit position masks mPTBD_PTBD0: equ %00000001 mPTBD_PTBD1: equ %00000010 mPTBD_PTBD2: equ %00000100 mPTBD_PTBD3: equ %00001000 mPTBD_PTBD4: equ %00010000 mPTBD_PTBD5: equ %00100000 mPTBD_PTBD6: equ %01000000 mPTBD_PTBD7: equ %10000000 ;*** PTBPE - Pullup Enable for Port B; 0x00000005 *** PTBPE: equ $00000005 ;*** PTBPE - Pullup Enable for Port B; 0x00000005 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBPE_PTBPE0: equ 0 ; Pullup Enable for Port B Bit 0 PTBPE_PTBPE1: equ 1 ; Pullup Enable for Port B Bit 1 PTBPE_PTBPE2: equ 2 ; Pullup Enable for Port B Bit 2 PTBPE_PTBPE3: equ 3 ; Pullup Enable for Port B Bit 3 PTBPE_PTBPE4: equ 4 ; Pullup Enable for Port B Bit 4 PTBPE_PTBPE5: equ 5 ; Pullup Enable for Port B Bit 5 PTBPE_PTBPE6: equ 6 ; Pullup Enable for Port B Bit 6 PTBPE_PTBPE7: equ 7 ; Pullup Enable for Port B Bit 7 ; bit position masks mPTBPE_PTBPE0: equ %00000001 mPTBPE_PTBPE1: equ %00000010 mPTBPE_PTBPE2: equ %00000100 mPTBPE_PTBPE3: equ %00001000 mPTBPE_PTBPE4: equ %00010000 mPTBPE_PTBPE5: equ %00100000 mPTBPE_PTBPE6: equ %01000000 mPTBPE_PTBPE7: equ %10000000 ;*** PTBSE - Slew Rate Control Enable for Port B; 0x00000006 *** PTBSE: equ $00000006 ;*** PTBSE - Slew Rate Control Enable for Port B; 0x00000006 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBSE_PTBSE0: equ 0 ; Slew Rate Control Enable for Port B Bit 0 PTBSE_PTBSE1: equ 1 ; Slew Rate Control Enable for Port B Bit 1 PTBSE_PTBSE2: equ 2 ; Slew Rate Control Enable for Port B Bit 2 PTBSE_PTBSE3: equ 3 ; Slew Rate Control Enable for Port B Bit 3 PTBSE_PTBSE4: equ 4 ; Slew Rate Control Enable for Port B Bit 4 PTBSE_PTBSE5: equ 5 ; Slew Rate Control Enable for Port B Bit 5 PTBSE_PTBSE6: equ 6 ; Slew Rate Control Enable for Port B Bit 6 PTBSE_PTBSE7: equ 7 ; Slew Rate Control Enable for Port B Bit 7 ; bit position masks mPTBSE_PTBSE0: equ %00000001 mPTBSE_PTBSE1: equ %00000010 mPTBSE_PTBSE2: equ %00000100 mPTBSE_PTBSE3: equ %00001000 mPTBSE_PTBSE4: equ %00010000 mPTBSE_PTBSE5: equ %00100000 mPTBSE_PTBSE6: equ %01000000 mPTBSE_PTBSE7: equ %10000000 ;*** PTBDD - Data Direction Register B; 0x00000007 *** PTBDD: equ $00000007 ;*** PTBDD - Data Direction Register B; 0x00000007 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDD_PTBDD0: equ 0 ; Data Direction for Port B Bit 0 PTBDD_PTBDD1: equ 1 ; Data Direction for Port B Bit 1 PTBDD_PTBDD2: equ 2 ; Data Direction for Port B Bit 2 PTBDD_PTBDD3: equ 3 ; Data Direction for Port B Bit 3 PTBDD_PTBDD4: equ 4 ; Data Direction for Port B Bit 4 PTBDD_PTBDD5: equ 5 ; Data Direction for Port B Bit 5 PTBDD_PTBDD6: equ 6 ; Data Direction for Port B Bit 6 PTBDD_PTBDD7: equ 7 ; Data Direction for Port B Bit 7 ; bit position masks mPTBDD_PTBDD0: equ %00000001 mPTBDD_PTBDD1: equ %00000010 mPTBDD_PTBDD2: equ %00000100 mPTBDD_PTBDD3: equ %00001000 mPTBDD_PTBDD4: equ %00010000 mPTBDD_PTBDD5: equ %00100000 mPTBDD_PTBDD6: equ %01000000 mPTBDD_PTBDD7: equ %10000000 ;*** PTCD - Port C Data Register; 0x00000008 *** PTCD: equ $00000008 ;*** PTCD - Port C Data Register; 0x00000008 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCD_PTCD0: equ 0 ; Port C Data Register Bit 0 PTCD_PTCD1: equ 1 ; Port C Data Register Bit 1 PTCD_PTCD2: equ 2 ; Port C Data Register Bit 2 PTCD_PTCD3: equ 3 ; Port C Data Register Bit 3 PTCD_PTCD4: equ 4 ; Port C Data Register Bit 4 PTCD_PTCD5: equ 5 ; Port C Data Register Bit 5 PTCD_PTCD6: equ 6 ; Port C Data Register Bit 6 PTCD_PTCD7: equ 7 ; Port C Data Register Bit 7 ; bit position masks mPTCD_PTCD0: equ %00000001 mPTCD_PTCD1: equ %00000010 mPTCD_PTCD2: equ %00000100 mPTCD_PTCD3: equ %00001000 mPTCD_PTCD4: equ %00010000 mPTCD_PTCD5: equ %00100000 mPTCD_PTCD6: equ %01000000 mPTCD_PTCD7: equ %10000000 ;*** PTCPE - Pullup Enable for Port C; 0x00000009 *** PTCPE: equ $00000009 ;*** PTCPE - Pullup Enable for Port C; 0x00000009 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCPE_PTCPE0: equ 0 ; Pullup Enable for Port C Bit 0 PTCPE_PTCPE1: equ 1 ; Pullup Enable for Port C Bit 1 PTCPE_PTCPE2: equ 2 ; Pullup Enable for Port C Bit 2 PTCPE_PTCPE3: equ 3 ; Pullup Enable for Port C Bit 3 PTCPE_PTCPE4: equ 4 ; Pullup Enable for Port C Bit 4 PTCPE_PTCPE5: equ 5 ; Pullup Enable for Port C Bit 5 PTCPE_PTCPE6: equ 6 ; Pullup Enable for Port C Bit 6 PTCPE_PTCPE7: equ 7 ; Pullup Enable for Port C Bit 7 ; bit position masks mPTCPE_PTCPE0: equ %00000001 mPTCPE_PTCPE1: equ %00000010 mPTCPE_PTCPE2: equ %00000100 mPTCPE_PTCPE3: equ %00001000 mPTCPE_PTCPE4: equ %00010000 mPTCPE_PTCPE5: equ %00100000 mPTCPE_PTCPE6: equ %01000000 mPTCPE_PTCPE7: equ %10000000 ;*** PTCSE - Slew Rate Control Enable for Port C; 0x0000000A *** PTCSE: equ $0000000A ;*** PTCSE - Slew Rate Control Enable for Port C; 0x0000000A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCSE_PTCSE0: equ 0 ; Slew Rate Control Enable for Port C Bit 0 PTCSE_PTCSE1: equ 1 ; Slew Rate Control Enable for Port C Bit 1 PTCSE_PTCSE2: equ 2 ; Slew Rate Control Enable for Port C Bit 2 PTCSE_PTCSE3: equ 3 ; Slew Rate Control Enable for Port C Bit 3 PTCSE_PTCSE4: equ 4 ; Slew Rate Control Enable for Port C Bit 4 PTCSE_PTCSE5: equ 5 ; Slew Rate Control Enable for Port C Bit 5 PTCSE_PTCSE6: equ 6 ; Slew Rate Control Enable for Port C Bit 6 PTCSE_PTCSE7: equ 7 ; Slew Rate Control Enable for Port C Bit 7 ; bit position masks mPTCSE_PTCSE0: equ %00000001 mPTCSE_PTCSE1: equ %00000010 mPTCSE_PTCSE2: equ %00000100 mPTCSE_PTCSE3: equ %00001000 mPTCSE_PTCSE4: equ %00010000 mPTCSE_PTCSE5: equ %00100000 mPTCSE_PTCSE6: equ %01000000 mPTCSE_PTCSE7: equ %10000000 ;*** PTCDD - Data Direction Register C; 0x0000000B *** PTCDD: equ $0000000B ;*** PTCDD - Data Direction Register C; 0x0000000B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDD_PTCDD0: equ 0 ; Data Direction for Port C Bit 0 PTCDD_PTCDD1: equ 1 ; Data Direction for Port C Bit 1 PTCDD_PTCDD2: equ 2 ; Data Direction for Port C Bit 2 PTCDD_PTCDD3: equ 3 ; Data Direction for Port C Bit 3 PTCDD_PTCDD4: equ 4 ; Data Direction for Port C Bit 4 PTCDD_PTCDD5: equ 5 ; Data Direction for Port C Bit 5 PTCDD_PTCDD6: equ 6 ; Data Direction for Port C Bit 6 PTCDD_PTCDD7: equ 7 ; Data Direction for Port C Bit 7 ; bit position masks mPTCDD_PTCDD0: equ %00000001 mPTCDD_PTCDD1: equ %00000010 mPTCDD_PTCDD2: equ %00000100 mPTCDD_PTCDD3: equ %00001000 mPTCDD_PTCDD4: equ %00010000 mPTCDD_PTCDD5: equ %00100000 mPTCDD_PTCDD6: equ %01000000 mPTCDD_PTCDD7: equ %10000000 ;*** PTDD - Port D Data Register; 0x0000000C *** PTDD: equ $0000000C ;*** PTDD - Port D Data Register; 0x0000000C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDD_PTDD0: equ 0 ; Port D Data Register Bit 0 PTDD_PTDD1: equ 1 ; Port D Data Register Bit 1 PTDD_PTDD2: equ 2 ; Port D Data Register Bit 2 PTDD_PTDD3: equ 3 ; Port D Data Register Bit 3 PTDD_PTDD4: equ 4 ; Port D Data Register Bit 4 PTDD_PTDD5: equ 5 ; Port D Data Register Bit 5 PTDD_PTDD6: equ 6 ; Port D Data Register Bit 6 PTDD_PTDD7: equ 7 ; Port D Data Register Bit 7 ; bit position masks mPTDD_PTDD0: equ %00000001 mPTDD_PTDD1: equ %00000010 mPTDD_PTDD2: equ %00000100 mPTDD_PTDD3: equ %00001000 mPTDD_PTDD4: equ %00010000 mPTDD_PTDD5: equ %00100000 mPTDD_PTDD6: equ %01000000 mPTDD_PTDD7: equ %10000000 ;*** PTDPE - Pullup Enable for Port D; 0x0000000D *** PTDPE: equ $0000000D ;*** PTDPE - Pullup Enable for Port D; 0x0000000D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDPE_PTDPE0: equ 0 ; Pullup Enable for Port D Bit 0 PTDPE_PTDPE1: equ 1 ; Pullup Enable for Port D Bit 1 PTDPE_PTDPE2: equ 2 ; Pullup Enable for Port D Bit 2 PTDPE_PTDPE3: equ 3 ; Pullup Enable for Port D Bit 3 PTDPE_PTDPE4: equ 4 ; Pullup Enable for Port D Bit 4 PTDPE_PTDPE5: equ 5 ; Pullup Enable for Port D Bit 5 PTDPE_PTDPE6: equ 6 ; Pullup Enable for Port D Bit 6 PTDPE_PTDPE7: equ 7 ; Pullup Enable for Port D Bit 7 ; bit position masks mPTDPE_PTDPE0: equ %00000001 mPTDPE_PTDPE1: equ %00000010 mPTDPE_PTDPE2: equ %00000100 mPTDPE_PTDPE3: equ %00001000 mPTDPE_PTDPE4: equ %00010000 mPTDPE_PTDPE5: equ %00100000 mPTDPE_PTDPE6: equ %01000000 mPTDPE_PTDPE7: equ %10000000 ;*** PTDSE - Slew Rate Control Enable for Port D; 0x0000000E *** PTDSE: equ $0000000E ;*** PTDSE - Slew Rate Control Enable for Port D; 0x0000000E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDSE_PTDSE0: equ 0 ; Slew Rate Control Enable for Port D Bit 0 PTDSE_PTDSE1: equ 1 ; Slew Rate Control Enable for Port D Bit 1 PTDSE_PTDSE2: equ 2 ; Slew Rate Control Enable for Port D Bit 2 PTDSE_PTDSE3: equ 3 ; Slew Rate Control Enable for Port D Bit 3 PTDSE_PTDSE4: equ 4 ; Slew Rate Control Enable for Port D Bit 4 PTDSE_PTDSE5: equ 5 ; Slew Rate Control Enable for Port D Bit 5 PTDSE_PTDSE6: equ 6 ; Slew Rate Control Enable for Port D Bit 6 PTDSE_PTDSE7: equ 7 ; Slew Rate Control Enable for Port D Bit 7 ; bit position masks mPTDSE_PTDSE0: equ %00000001 mPTDSE_PTDSE1: equ %00000010 mPTDSE_PTDSE2: equ %00000100 mPTDSE_PTDSE3: equ %00001000 mPTDSE_PTDSE4: equ %00010000 mPTDSE_PTDSE5: equ %00100000 mPTDSE_PTDSE6: equ %01000000 mPTDSE_PTDSE7: equ %10000000 ;*** PTDDD - Data Direction Register D; 0x0000000F *** PTDDD: equ $0000000F ;*** PTDDD - Data Direction Register D; 0x0000000F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDD_PTDDD0: equ 0 ; Data Direction for Port D Bit 0 PTDDD_PTDDD1: equ 1 ; Data Direction for Port D Bit 1 PTDDD_PTDDD2: equ 2 ; Data Direction for Port D Bit 2 PTDDD_PTDDD3: equ 3 ; Data Direction for Port D Bit 3 PTDDD_PTDDD4: equ 4 ; Data Direction for Port D Bit 4 PTDDD_PTDDD5: equ 5 ; Data Direction for Port D Bit 5 PTDDD_PTDDD6: equ 6 ; Data Direction for Port D Bit 6 PTDDD_PTDDD7: equ 7 ; Data Direction for Port D Bit 7 ; bit position masks mPTDDD_PTDDD0: equ %00000001 mPTDDD_PTDDD1: equ %00000010 mPTDDD_PTDDD2: equ %00000100 mPTDDD_PTDDD3: equ %00001000 mPTDDD_PTDDD4: equ %00010000 mPTDDD_PTDDD5: equ %00100000 mPTDDD_PTDDD6: equ %01000000 mPTDDD_PTDDD7: equ %10000000 ;*** PTED - Port E Data Register; 0x00000010 *** PTED: equ $00000010 ;*** PTED - Port E Data Register; 0x00000010 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTED_PTED0: equ 0 ; Port E Data Register Bit 0 PTED_PTED1: equ 1 ; Port E Data Register Bit 1 PTED_PTED2: equ 2 ; Port E Data Register Bit 2 PTED_PTED3: equ 3 ; Port E Data Register Bit 3 PTED_PTED4: equ 4 ; Port E Data Register Bit 4 PTED_PTED5: equ 5 ; Port E Data Register Bit 5 PTED_PTED6: equ 6 ; Port E Data Register Bit 6 PTED_PTED7: equ 7 ; Port E Data Register Bit 7 ; bit position masks mPTED_PTED0: equ %00000001 mPTED_PTED1: equ %00000010 mPTED_PTED2: equ %00000100 mPTED_PTED3: equ %00001000 mPTED_PTED4: equ %00010000 mPTED_PTED5: equ %00100000 mPTED_PTED6: equ %01000000 mPTED_PTED7: equ %10000000 ;*** PTEPE - Pullup Enable for Port E; 0x00000011 *** PTEPE: equ $00000011 ;*** PTEPE - Pullup Enable for Port E; 0x00000011 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEPE_PTEPE0: equ 0 ; Pullup Enable for Port E Bit 0 PTEPE_PTEPE1: equ 1 ; Pullup Enable for Port E Bit 1 PTEPE_PTEPE2: equ 2 ; Pullup Enable for Port E Bit 2 PTEPE_PTEPE3: equ 3 ; Pullup Enable for Port E Bit 3 PTEPE_PTEPE4: equ 4 ; Pullup Enable for Port E Bit 4 PTEPE_PTEPE5: equ 5 ; Pullup Enable for Port E Bit 5 PTEPE_PTEPE6: equ 6 ; Pullup Enable for Port E Bit 6 PTEPE_PTEPE7: equ 7 ; Pullup Enable for Port E Bit 7 ; bit position masks mPTEPE_PTEPE0: equ %00000001 mPTEPE_PTEPE1: equ %00000010 mPTEPE_PTEPE2: equ %00000100 mPTEPE_PTEPE3: equ %00001000 mPTEPE_PTEPE4: equ %00010000 mPTEPE_PTEPE5: equ %00100000 mPTEPE_PTEPE6: equ %01000000 mPTEPE_PTEPE7: equ %10000000 ;*** PTESE - Slew Rate Control Enable for Port E; 0x00000012 *** PTESE: equ $00000012 ;*** PTESE - Slew Rate Control Enable for Port E; 0x00000012 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTESE_PTESE0: equ 0 ; Slew Rate Control Enable for Port E Bit 0 PTESE_PTESE1: equ 1 ; Slew Rate Control Enable for Port E Bit 1 PTESE_PTESE2: equ 2 ; Slew Rate Control Enable for Port E Bit 2 PTESE_PTESE3: equ 3 ; Slew Rate Control Enable for Port E Bit 3 PTESE_PTESE4: equ 4 ; Slew Rate Control Enable for Port E Bit 4 PTESE_PTESE5: equ 5 ; Slew Rate Control Enable for Port E Bit 5 PTESE_PTESE6: equ 6 ; Slew Rate Control Enable for Port E Bit 6 PTESE_PTESE7: equ 7 ; Slew Rate Control Enable for Port E Bit 7 ; bit position masks mPTESE_PTESE0: equ %00000001 mPTESE_PTESE1: equ %00000010 mPTESE_PTESE2: equ %00000100 mPTESE_PTESE3: equ %00001000 mPTESE_PTESE4: equ %00010000 mPTESE_PTESE5: equ %00100000 mPTESE_PTESE6: equ %01000000 mPTESE_PTESE7: equ %10000000 ;*** PTEDD - Data Direction Register E; 0x00000013 *** PTEDD: equ $00000013 ;*** PTEDD - Data Direction Register E; 0x00000013 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDD_PTEDD0: equ 0 ; Data Direction for Port E Bit 0 PTEDD_PTEDD1: equ 1 ; Data Direction for Port E Bit 1 PTEDD_PTEDD2: equ 2 ; Data Direction for Port E Bit 2 PTEDD_PTEDD3: equ 3 ; Data Direction for Port E Bit 3 PTEDD_PTEDD4: equ 4 ; Data Direction for Port E Bit 4 PTEDD_PTEDD5: equ 5 ; Data Direction for Port E Bit 5 PTEDD_PTEDD6: equ 6 ; Data Direction for Port E Bit 6 PTEDD_PTEDD7: equ 7 ; Data Direction for Port E Bit 7 ; bit position masks mPTEDD_PTEDD0: equ %00000001 mPTEDD_PTEDD1: equ %00000010 mPTEDD_PTEDD2: equ %00000100 mPTEDD_PTEDD3: equ %00001000 mPTEDD_PTEDD4: equ %00010000 mPTEDD_PTEDD5: equ %00100000 mPTEDD_PTEDD6: equ %01000000 mPTEDD_PTEDD7: equ %10000000 ;*** IRQSC - Interrupt Request Status and Control Register; 0x00000014 *** IRQSC: equ $00000014 ;*** IRQSC - Interrupt Request Status and Control Register; 0x00000014 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRQSC_IRQMOD: equ 0 ; IRQ Detection Mode IRQSC_IRQIE: equ 1 ; IRQ Interrupt Enable IRQSC_IRQACK: equ 2 ; IRQ Acknowledge IRQSC_IRQF: equ 3 ; IRQ Flag IRQSC_IRQPE: equ 4 ; IRQ Pin Enable IRQSC_IRQEDG: equ 5 ; Interrupt Request (IRQ) Edge Select ; bit position masks mIRQSC_IRQMOD: equ %00000001 mIRQSC_IRQIE: equ %00000010 mIRQSC_IRQACK: equ %00000100 mIRQSC_IRQF: equ %00001000 mIRQSC_IRQPE: equ %00010000 mIRQSC_IRQEDG: equ %00100000 ;*** KBI1SC - KBI Status and Control; 0x00000016 *** KBI1SC: equ $00000016 ;*** KBI1SC - KBI Status and Control; 0x00000016 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI1SC_KBIMOD: equ 0 ; Keyboard Detection Mode KBI1SC_KBIE: equ 1 ; Keyboard Interrupt Enable KBI1SC_KBACK: equ 2 ; Keyboard Interrupt Acknowledge KBI1SC_KBF: equ 3 ; Keyboard Interrupt Flag KBI1SC_KBEDG4: equ 4 ; Keyboard Edge Select for Port A Bit 4 KBI1SC_KBEDG5: equ 5 ; Keyboard Edge Select for Port A Bit 5 KBI1SC_KBEDG6: equ 6 ; Keyboard Edge Select for Port A Bit 6 KBI1SC_KBEDG7: equ 7 ; Keyboard Edge Select for Port A Bit 7 ; bit position masks mKBI1SC_KBIMOD: equ %00000001 mKBI1SC_KBIE: equ %00000010 mKBI1SC_KBACK: equ %00000100 mKBI1SC_KBF: equ %00001000 mKBI1SC_KBEDG4: equ %00010000 mKBI1SC_KBEDG5: equ %00100000 mKBI1SC_KBEDG6: equ %01000000 mKBI1SC_KBEDG7: equ %10000000 ;*** KBI1PE - KBI Pin Enable Register; 0x00000017 *** KBI1PE: equ $00000017 ;*** KBI1PE - KBI Pin Enable Register; 0x00000017 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI1PE_KBIPE0: equ 0 ; Keyboard Pin Enable for Port A Bit 0 KBI1PE_KBIPE1: equ 1 ; Keyboard Pin Enable for Port A Bit 1 KBI1PE_KBIPE2: equ 2 ; Keyboard Pin Enable for Port A Bit 2 KBI1PE_KBIPE3: equ 3 ; Keyboard Pin Enable for Port A Bit 3 KBI1PE_KBIPE4: equ 4 ; Keyboard Pin Enable for Port A Bit 4 KBI1PE_KBIPE5: equ 5 ; Keyboard Pin Enable for Port A Bit 5 KBI1PE_KBIPE6: equ 6 ; Keyboard Pin Enable for Port A Bit 6 KBI1PE_KBIPE7: equ 7 ; Keyboard Pin Enable for Port A Bit 7 ; bit position masks mKBI1PE_KBIPE0: equ %00000001 mKBI1PE_KBIPE1: equ %00000010 mKBI1PE_KBIPE2: equ %00000100 mKBI1PE_KBIPE3: equ %00001000 mKBI1PE_KBIPE4: equ %00010000 mKBI1PE_KBIPE5: equ %00100000 mKBI1PE_KBIPE6: equ %01000000 mKBI1PE_KBIPE7: equ %10000000 ;*** SCI1BD - SCI1 Baud Rate Register; 0x00000018 *** SCI1BD: equ $00000018 ;*** SCI1BD - SCI1 Baud Rate Register; 0x00000018 *** ;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000018 *** SCI1BDH: equ $00000018 ;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000018 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BDH_SBR8: equ 0 ; Baud Rate Modulo Divisor Bit 8 SCI1BDH_SBR9: equ 1 ; Baud Rate Modulo Divisor Bit 9 SCI1BDH_SBR10: equ 2 ; Baud Rate Modulo Divisor Bit 10 SCI1BDH_SBR11: equ 3 ; Baud Rate Modulo Divisor Bit 11 SCI1BDH_SBR12: equ 4 ; Baud Rate Modulo Divisor Bit 12 ; bit position masks mSCI1BDH_SBR8: equ %00000001 mSCI1BDH_SBR9: equ %00000010 mSCI1BDH_SBR10: equ %00000100 mSCI1BDH_SBR11: equ %00001000 mSCI1BDH_SBR12: equ %00010000 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000019 *** SCI1BDL: equ $00000019 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000019 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BDL_SBR0: equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI1BDL_SBR1: equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI1BDL_SBR2: equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI1BDL_SBR3: equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI1BDL_SBR4: equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI1BDL_SBR5: equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI1BDL_SBR6: equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI1BDL_SBR7: equ 7 ; Baud Rate Modulo Divisor Bit 7 ; bit position masks mSCI1BDL_SBR0: equ %00000001 mSCI1BDL_SBR1: equ %00000010 mSCI1BDL_SBR2: equ %00000100 mSCI1BDL_SBR3: equ %00001000 mSCI1BDL_SBR4: equ %00010000 mSCI1BDL_SBR5: equ %00100000 mSCI1BDL_SBR6: equ %01000000 mSCI1BDL_SBR7: equ %10000000 ;*** SCI1C1 - SCI1 Control Register 1; 0x0000001A *** SCI1C1: equ $0000001A ;*** SCI1C1 - SCI1 Control Register 1; 0x0000001A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C1_PT: equ 0 ; Parity Type SCI1C1_PE: equ 1 ; Parity Enable SCI1C1_ILT: equ 2 ; Idle Line Type Select SCI1C1_WAKE: equ 3 ; Receiver Wakeup Method Select SCI1C1_M: equ 4 ; 9-Bit or 8-Bit Mode Select SCI1C1_RSRC: equ 5 ; Receiver Source Select SCI1C1_SCISWAI: equ 6 ; SCI Stops in Wait Mode SCI1C1_LOOPS: equ 7 ; Loop Mode Select ; bit position masks mSCI1C1_PT: equ %00000001 mSCI1C1_PE: equ %00000010 mSCI1C1_ILT: equ %00000100 mSCI1C1_WAKE: equ %00001000 mSCI1C1_M: equ %00010000 mSCI1C1_RSRC: equ %00100000 mSCI1C1_SCISWAI: equ %01000000 mSCI1C1_LOOPS: equ %10000000 ;*** SCI1C2 - SCI1 Control Register 2; 0x0000001B *** SCI1C2: equ $0000001B ;*** SCI1C2 - SCI1 Control Register 2; 0x0000001B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C2_SBK: equ 0 ; Send Break SCI1C2_RWU: equ 1 ; Receiver Wakeup Control SCI1C2_RE: equ 2 ; Receiver Enable SCI1C2_TE: equ 3 ; Transmitter Enable SCI1C2_ILIE: equ 4 ; Idle Line Interrupt Enable (for IDLE) SCI1C2_RIE: equ 5 ; Receiver Interrupt Enable (for RDRF) SCI1C2_TCIE: equ 6 ; Transmission Complete Interrupt Enable (for TC) SCI1C2_TIE: equ 7 ; Transmit Interrupt Enable (for TDRE) ; bit position masks mSCI1C2_SBK: equ %00000001 mSCI1C2_RWU: equ %00000010 mSCI1C2_RE: equ %00000100 mSCI1C2_TE: equ %00001000 mSCI1C2_ILIE: equ %00010000 mSCI1C2_RIE: equ %00100000 mSCI1C2_TCIE: equ %01000000 mSCI1C2_TIE: equ %10000000 ;*** SCI1S1 - SCI1 Status Register 1; 0x0000001C *** SCI1S1: equ $0000001C ;*** SCI1S1 - SCI1 Status Register 1; 0x0000001C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1S1_PF: equ 0 ; Parity Error Flag SCI1S1_FE: equ 1 ; Framing Error Flag SCI1S1_NF: equ 2 ; Noise Flag SCI1S1_OR: equ 3 ; Receiver Overrun Flag SCI1S1_IDLE: equ 4 ; Idle Line Flag SCI1S1_RDRF: equ 5 ; Receive Data Register Full Flag SCI1S1_TC: equ 6 ; Transmission Complete Flag SCI1S1_TDRE: equ 7 ; Transmit Data Register Empty Flag ; bit position masks mSCI1S1_PF: equ %00000001 mSCI1S1_FE: equ %00000010 mSCI1S1_NF: equ %00000100 mSCI1S1_OR: equ %00001000 mSCI1S1_IDLE: equ %00010000 mSCI1S1_RDRF: equ %00100000 mSCI1S1_TC: equ %01000000 mSCI1S1_TDRE: equ %10000000 ;*** SCI1S2 - SCI1 Status Register 2; 0x0000001D *** SCI1S2: equ $0000001D ;*** SCI1S2 - SCI1 Status Register 2; 0x0000001D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1S2_RAF: equ 0 ; Receiver Active Flag ; bit position masks mSCI1S2_RAF: equ %00000001 ;*** SCI1C3 - SCI1 Control Register 3; 0x0000001E *** SCI1C3: equ $0000001E ;*** SCI1C3 - SCI1 Control Register 3; 0x0000001E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C3_PEIE: equ 0 ; Parity Error Interrupt Enable SCI1C3_FEIE: equ 1 ; Framing Error Interrupt Enable SCI1C3_NEIE: equ 2 ; Noise Error Interrupt Enable SCI1C3_ORIE: equ 3 ; Overrun Interrupt Enable SCI1C3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode SCI1C3_T8: equ 6 ; Ninth Data Bit for Transmitter SCI1C3_R8: equ 7 ; Ninth Data Bit for Receiver ; bit position masks mSCI1C3_PEIE: equ %00000001 mSCI1C3_FEIE: equ %00000010 mSCI1C3_NEIE: equ %00000100 mSCI1C3_ORIE: equ %00001000 mSCI1C3_TXDIR: equ %00100000 mSCI1C3_T8: equ %01000000 mSCI1C3_R8: equ %10000000 ;*** SCI1D - SCI1 Data Register; 0x0000001F *** SCI1D: equ $0000001F ;*** SCI1D - SCI1 Data Register; 0x0000001F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1D_R0_T0: equ 0 ; Receive/Transmit Data Bit 0 SCI1D_R1_T1: equ 1 ; Receive/Transmit Data Bit 1 SCI1D_R2_T2: equ 2 ; Receive/Transmit Data Bit 2 SCI1D_R3_T3: equ 3 ; Receive/Transmit Data Bit 3 SCI1D_R4_T4: equ 4 ; Receive/Transmit Data Bit 4 SCI1D_R5_T5: equ 5 ; Receive/Transmit Data Bit 5 SCI1D_R6_T6: equ 6 ; Receive/Transmit Data Bit 6 SCI1D_R7_T7: equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCI1D_R0_T0: equ %00000001 mSCI1D_R1_T1: equ %00000010 mSCI1D_R2_T2: equ %00000100 mSCI1D_R3_T3: equ %00001000 mSCI1D_R4_T4: equ %00010000 mSCI1D_R5_T5: equ %00100000 mSCI1D_R6_T6: equ %01000000 mSCI1D_R7_T7: equ %10000000 ;*** SCI2BD - SCI2 Baud Rate Register; 0x00000020 *** SCI2BD: equ $00000020 ;*** SCI2BD - SCI2 Baud Rate Register; 0x00000020 *** ;*** SCI2BDH - SCI2 Baud Rate Register High; 0x00000020 *** SCI2BDH: equ $00000020 ;*** SCI2BDH - SCI2 Baud Rate Register High; 0x00000020 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BDH_SBR8: equ 0 ; Baud Rate Modulo Divisor Bit 8 SCI2BDH_SBR9: equ 1 ; Baud Rate Modulo Divisor Bit 9 SCI2BDH_SBR10: equ 2 ; Baud Rate Modulo Divisor Bit 10 SCI2BDH_SBR11: equ 3 ; Baud Rate Modulo Divisor Bit 11 SCI2BDH_SBR12: equ 4 ; Baud Rate Modulo Divisor Bit 12 ; bit position masks mSCI2BDH_SBR8: equ %00000001 mSCI2BDH_SBR9: equ %00000010 mSCI2BDH_SBR10: equ %00000100 mSCI2BDH_SBR11: equ %00001000 mSCI2BDH_SBR12: equ %00010000 ;*** SCI2BDL - SCI2 Baud Rate Register Low; 0x00000021 *** SCI2BDL: equ $00000021 ;*** SCI2BDL - SCI2 Baud Rate Register Low; 0x00000021 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BDL_SBR0: equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI2BDL_SBR1: equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI2BDL_SBR2: equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI2BDL_SBR3: equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI2BDL_SBR4: equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI2BDL_SBR5: equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI2BDL_SBR6: equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI2BDL_SBR7: equ 7 ; Baud Rate Modulo Divisor Bit 7 ; bit position masks mSCI2BDL_SBR0: equ %00000001 mSCI2BDL_SBR1: equ %00000010 mSCI2BDL_SBR2: equ %00000100 mSCI2BDL_SBR3: equ %00001000 mSCI2BDL_SBR4: equ %00010000 mSCI2BDL_SBR5: equ %00100000 mSCI2BDL_SBR6: equ %01000000 mSCI2BDL_SBR7: equ %10000000 ;*** SCI2C1 - SCI1 Control Register 1; 0x00000022 *** SCI2C1: equ $00000022 ;*** SCI2C1 - SCI1 Control Register 1; 0x00000022 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C1_PT: equ 0 ; Parity Type SCI2C1_PE: equ 1 ; Parity Enable SCI2C1_ILT: equ 2 ; Idle Line Type Select SCI2C1_WAKE: equ 3 ; Receiver Wakeup Method Select SCI2C1_M: equ 4 ; 9-Bit or 8-Bit Mode Select SCI2C1_RSRC: equ 5 ; Receiver Source Select SCI2C1_SCISWAI: equ 6 ; SCI Stops in Wait Mode SCI2C1_LOOPS: equ 7 ; Loop Mode Select ; bit position masks mSCI2C1_PT: equ %00000001 mSCI2C1_PE: equ %00000010 mSCI2C1_ILT: equ %00000100 mSCI2C1_WAKE: equ %00001000 mSCI2C1_M: equ %00010000 mSCI2C1_RSRC: equ %00100000 mSCI2C1_SCISWAI: equ %01000000 mSCI2C1_LOOPS: equ %10000000 ;*** SCI2C2 - SCI2 Control Register 2; 0x00000023 *** SCI2C2: equ $00000023 ;*** SCI2C2 - SCI2 Control Register 2; 0x00000023 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C2_SBK: equ 0 ; Send Break SCI2C2_RWU: equ 1 ; Receiver Wakeup Control SCI2C2_RE: equ 2 ; Receiver Enable SCI2C2_TE: equ 3 ; Transmitter Enable SCI2C2_ILIE: equ 4 ; Idle Line Interrupt Enable (for IDLE) SCI2C2_RIE: equ 5 ; Receiver Interrupt Enable (for RDRF) SCI2C2_TCIE: equ 6 ; Transmission Complete Interrupt Enable (for TC) SCI2C2_TIE: equ 7 ; Transmit Interrupt Enable (for TDRE) ; bit position masks mSCI2C2_SBK: equ %00000001 mSCI2C2_RWU: equ %00000010 mSCI2C2_RE: equ %00000100 mSCI2C2_TE: equ %00001000 mSCI2C2_ILIE: equ %00010000 mSCI2C2_RIE: equ %00100000 mSCI2C2_TCIE: equ %01000000 mSCI2C2_TIE: equ %10000000 ;*** SCI2S1 - SCI2 Status Register 1; 0x00000024 *** SCI2S1: equ $00000024 ;*** SCI2S1 - SCI2 Status Register 1; 0x00000024 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2S1_PF: equ 0 ; Parity Error Flag SCI2S1_FE: equ 1 ; Framing Error Flag SCI2S1_NF: equ 2 ; Noise Flag SCI2S1_OR: equ 3 ; Receiver Overrun Flag SCI2S1_IDLE: equ 4 ; Idle Line Flag SCI2S1_RDRF: equ 5 ; Receive Data Register Full Flag SCI2S1_TC: equ 6 ; Transmission Complete Flag SCI2S1_TDRE: equ 7 ; Transmit Data Register Empty Flag ; bit position masks mSCI2S1_PF: equ %00000001 mSCI2S1_FE: equ %00000010 mSCI2S1_NF: equ %00000100 mSCI2S1_OR: equ %00001000 mSCI2S1_IDLE: equ %00010000 mSCI2S1_RDRF: equ %00100000 mSCI2S1_TC: equ %01000000 mSCI2S1_TDRE: equ %10000000 ;*** SCI2S2 - SCI2 Status Register 2; 0x00000025 *** SCI2S2: equ $00000025 ;*** SCI2S2 - SCI2 Status Register 2; 0x00000025 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2S2_RAF: equ 0 ; Receiver Active Flag ; bit position masks mSCI2S2_RAF: equ %00000001 ;*** SCI2C3 - SCI2 Control Register 3; 0x00000026 *** SCI2C3: equ $00000026 ;*** SCI2C3 - SCI2 Control Register 3; 0x00000026 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C3_PEIE: equ 0 ; Parity Error Interrupt Enable SCI2C3_FEIE: equ 1 ; Framing Error Interrupt Enable SCI2C3_NEIE: equ 2 ; Noise Error Interrupt Enable SCI2C3_ORIE: equ 3 ; Overrun Interrupt Enable SCI2C3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode SCI2C3_T8: equ 6 ; Ninth Data Bit for Transmitter SCI2C3_R8: equ 7 ; Ninth Data Bit for Receiver ; bit position masks mSCI2C3_PEIE: equ %00000001 mSCI2C3_FEIE: equ %00000010 mSCI2C3_NEIE: equ %00000100 mSCI2C3_ORIE: equ %00001000 mSCI2C3_TXDIR: equ %00100000 mSCI2C3_T8: equ %01000000 mSCI2C3_R8: equ %10000000 ;*** SCI2D - SCI2 Data Register; 0x00000027 *** SCI2D: equ $00000027 ;*** SCI2D - SCI2 Data Register; 0x00000027 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2D_R0_T0: equ 0 ; Receive/Transmit Data Bit 0 SCI2D_R1_T1: equ 1 ; Receive/Transmit Data Bit 1 SCI2D_R2_T2: equ 2 ; Receive/Transmit Data Bit 2 SCI2D_R3_T3: equ 3 ; Receive/Transmit Data Bit 3 SCI2D_R4_T4: equ 4 ; Receive/Transmit Data Bit 4 SCI2D_R5_T5: equ 5 ; Receive/Transmit Data Bit 5 SCI2D_R6_T6: equ 6 ; Receive/Transmit Data Bit 6 SCI2D_R7_T7: equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCI2D_R0_T0: equ %00000001 mSCI2D_R1_T1: equ %00000010 mSCI2D_R2_T2: equ %00000100 mSCI2D_R3_T3: equ %00001000 mSCI2D_R4_T4: equ %00010000 mSCI2D_R5_T5: equ %00100000 mSCI2D_R6_T6: equ %01000000 mSCI2D_R7_T7: equ %10000000 ;*** SPI1C1 - SPI Control Register 1; 0x00000028 *** SPI1C1: equ $00000028 ;*** SPI1C1 - SPI Control Register 1; 0x00000028 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C1_LSBFE: equ 0 ; LSB First (shifter direction) SPI1C1_SSOE: equ 1 ; Slave Select Output Enable SPI1C1_CPHA: equ 2 ; Clock Phase SPI1C1_CPOL: equ 3 ; Clock Polarity SPI1C1_MSTR: equ 4 ; Master/Slave Mode Select SPI1C1_SPTIE: equ 5 ; SPI Transmit Interrupt Enable SPI1C1_SPE: equ 6 ; SPI System Enable SPI1C1_SPIE: equ 7 ; SPI Interrupt Enable ; bit position masks mSPI1C1_LSBFE: equ %00000001 mSPI1C1_SSOE: equ %00000010 mSPI1C1_CPHA: equ %00000100 mSPI1C1_CPOL: equ %00001000 mSPI1C1_MSTR: equ %00010000 mSPI1C1_SPTIE: equ %00100000 mSPI1C1_SPE: equ %01000000 mSPI1C1_SPIE: equ %10000000 ;*** SPI1C2 - SPI Control Register 2; 0x00000029 *** SPI1C2: equ $00000029 ;*** SPI1C2 - SPI Control Register 2; 0x00000029 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C2_SPC0: equ 0 ; SPI Pin Control 0 SPI1C2_SPISWAI: equ 1 ; SPI Stop in Wait Mode SPI1C2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable SPI1C2_MODFEN: equ 4 ; Master Mode-Fault Function Enable ; bit position masks mSPI1C2_SPC0: equ %00000001 mSPI1C2_SPISWAI: equ %00000010 mSPI1C2_BIDIROE: equ %00001000 mSPI1C2_MODFEN: equ %00010000 ;*** SPI1BR - SPI Baud Rate Register; 0x0000002A *** SPI1BR: equ $0000002A ;*** SPI1BR - SPI Baud Rate Register; 0x0000002A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1BR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0 SPI1BR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1 SPI1BR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2 SPI1BR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0 SPI1BR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1 SPI1BR_SPPR2: equ 6 ; SPI Baud Rate Prescale Divisor Bit 2 ; bit position masks mSPI1BR_SPR0: equ %00000001 mSPI1BR_SPR1: equ %00000010 mSPI1BR_SPR2: equ %00000100 mSPI1BR_SPPR0: equ %00010000 mSPI1BR_SPPR1: equ %00100000 mSPI1BR_SPPR2: equ %01000000 ;*** SPI1S - SPI Status Register; 0x0000002B *** SPI1S: equ $0000002B ;*** SPI1S - SPI Status Register; 0x0000002B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1S_MODF: equ 4 ; Master Mode Fault Flag SPI1S_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag SPI1S_SPRF: equ 7 ; SPI Read Buffer Full Flag ; bit position masks mSPI1S_MODF: equ %00010000 mSPI1S_SPTEF: equ %00100000 mSPI1S_SPRF: equ %10000000 ;*** SPI1D - SPI Data Register; 0x0000002D *** SPI1D: equ $0000002D ;*** SPI1D - SPI Data Register; 0x0000002D *** ;*** TPM1SC - TPM 1 Status and Control Register; 0x00000030 *** TPM1SC: equ $00000030 ;*** TPM1SC - TPM 1 Status and Control Register; 0x00000030 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1SC_PS0: equ 0 ; Prescale Divisor Select Bit 0 TPM1SC_PS1: equ 1 ; Prescale Divisor Select Bit 1 TPM1SC_PS2: equ 2 ; Prescale Divisor Select Bit 2 TPM1SC_CLKSA: equ 3 ; Clock Source Select A TPM1SC_CLKSB: equ 4 ; Clock Source Select B TPM1SC_CPWMS: equ 5 ; Center-Aligned PWM Select TPM1SC_TOIE: equ 6 ; Timer Overflow Interrupt Enable TPM1SC_TOF: equ 7 ; Timer Overflow Flag ; bit position masks mTPM1SC_PS0: equ %00000001 mTPM1SC_PS1: equ %00000010 mTPM1SC_PS2: equ %00000100 mTPM1SC_CLKSA: equ %00001000 mTPM1SC_CLKSB: equ %00010000 mTPM1SC_CPWMS: equ %00100000 mTPM1SC_TOIE: equ %01000000 mTPM1SC_TOF: equ %10000000 ;*** TPM1CNT - TPM 1 Counter Register; 0x00000031 *** TPM1CNT: equ $00000031 ;*** TPM1CNT - TPM 1 Counter Register; 0x00000031 *** ;*** TPM1CNTH - TPM 1 Counter Register High; 0x00000031 *** TPM1CNTH: equ $00000031 ;*** TPM1CNTH - TPM 1 Counter Register High; 0x00000031 *** ;*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000032 *** TPM1CNTL: equ $00000032 ;*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000032 *** ;*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000033 *** TPM1MOD: equ $00000033 ;*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000033 *** ;*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000033 *** TPM1MODH: equ $00000033 ;*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000033 *** ;*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000034 *** TPM1MODL: equ $00000034 ;*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000034 *** ;*** TPM1C0SC - TPM 1 Timer Channel 0 Status and Control Register; 0x00000035 *** TPM1C0SC: equ $00000035 ;*** TPM1C0SC - TPM 1 Timer Channel 0 Status and Control Register; 0x00000035 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C0SC_ELS0A: equ 2 ; Edge/Level Select Bit A TPM1C0SC_ELS0B: equ 3 ; Edge/Level Select Bit B TPM1C0SC_MS0A: equ 4 ; Mode Select A for TPM Channel 0 TPM1C0SC_MS0B: equ 5 ; Mode Select B for TPM Channel 0 TPM1C0SC_CH0IE: equ 6 ; Channel 0 Interrupt Enable TPM1C0SC_CH0F: equ 7 ; Channel 0 Flag ; bit position masks mTPM1C0SC_ELS0A: equ %00000100 mTPM1C0SC_ELS0B: equ %00001000 mTPM1C0SC_MS0A: equ %00010000 mTPM1C0SC_MS0B: equ %00100000 mTPM1C0SC_CH0IE: equ %01000000 mTPM1C0SC_CH0F: equ %10000000 ;*** TPM1C0V - TPM 1 Timer Channel 0 Value Register; 0x00000036 *** TPM1C0V: equ $00000036 ;*** TPM1C0V - TPM 1 Timer Channel 0 Value Register; 0x00000036 *** ;*** TPM1C0VH - TPM 1 Timer Channel 0 Value Register High; 0x00000036 *** TPM1C0VH: equ $00000036 ;*** TPM1C0VH - TPM 1 Timer Channel 0 Value Register High; 0x00000036 *** ;*** TPM1C0VL - TPM 1 Timer Channel 0 Value Register Low; 0x00000037 *** TPM1C0VL: equ $00000037 ;*** TPM1C0VL - TPM 1 Timer Channel 0 Value Register Low; 0x00000037 *** ;*** TPM1C1SC - TPM 1 Timer Channel 1 Status and Control Register; 0x00000038 *** TPM1C1SC: equ $00000038 ;*** TPM1C1SC - TPM 1 Timer Channel 1 Status and Control Register; 0x00000038 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C1SC_ELS1A: equ 2 ; Edge/Level Select Bit A TPM1C1SC_ELS1B: equ 3 ; Edge/Level Select Bit B TPM1C1SC_MS1A: equ 4 ; Mode Select A for TPM Channel 1 TPM1C1SC_MS1B: equ 5 ; Mode Select B for TPM Channel 1 TPM1C1SC_CH1IE: equ 6 ; Channel 1 Interrupt Enable TPM1C1SC_CH1F: equ 7 ; Channel 1 Flag ; bit position masks mTPM1C1SC_ELS1A: equ %00000100 mTPM1C1SC_ELS1B: equ %00001000 mTPM1C1SC_MS1A: equ %00010000 mTPM1C1SC_MS1B: equ %00100000 mTPM1C1SC_CH1IE: equ %01000000 mTPM1C1SC_CH1F: equ %10000000 ;*** TPM1C1V - TPM 1 Timer Channel 1 Value Register; 0x00000039 *** TPM1C1V: equ $00000039 ;*** TPM1C1V - TPM 1 Timer Channel 1 Value Register; 0x00000039 *** ;*** TPM1C1VH - TPM 1 Timer Channel 1 Value Register High; 0x00000039 *** TPM1C1VH: equ $00000039 ;*** TPM1C1VH - TPM 1 Timer Channel 1 Value Register High; 0x00000039 *** ;*** TPM1C1VL - TPM 1 Timer Channel 1 Value Register Low; 0x0000003A *** TPM1C1VL: equ $0000003A ;*** TPM1C1VL - TPM 1 Timer Channel 1 Value Register Low; 0x0000003A *** ;*** TPM1C2SC - TPM 1 Timer Channel 2 Status and Control Register; 0x0000003B *** TPM1C2SC: equ $0000003B ;*** TPM1C2SC - TPM 1 Timer Channel 2 Status and Control Register; 0x0000003B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C2SC_ELS2A: equ 2 ; Edge/Level Select Bit A TPM1C2SC_ELS2B: equ 3 ; Edge/Level Select Bit B TPM1C2SC_MS2A: equ 4 ; Mode Select A for TPM Channel 2 TPM1C2SC_MS2B: equ 5 ; Mode Select B for TPM Channel 2 TPM1C2SC_CH2IE: equ 6 ; Channel 2 Interrupt Enable TPM1C2SC_CH2F: equ 7 ; Channel 2 Flag ; bit position masks mTPM1C2SC_ELS2A: equ %00000100 mTPM1C2SC_ELS2B: equ %00001000 mTPM1C2SC_MS2A: equ %00010000 mTPM1C2SC_MS2B: equ %00100000 mTPM1C2SC_CH2IE: equ %01000000 mTPM1C2SC_CH2F: equ %10000000 ;*** TPM1C2V - TPM 1 Timer Channel 2 Value Register; 0x0000003C *** TPM1C2V: equ $0000003C ;*** TPM1C2V - TPM 1 Timer Channel 2 Value Register; 0x0000003C *** ;*** TPM1C2VH - TPM 1 Timer Channel 2 Value Register High; 0x0000003C *** TPM1C2VH: equ $0000003C ;*** TPM1C2VH - TPM 1 Timer Channel 2 Value Register High; 0x0000003C *** ;*** TPM1C2VL - TPM 1 Timer Channel 2 Value Register Low; 0x0000003D *** TPM1C2VL: equ $0000003D ;*** TPM1C2VL - TPM 1 Timer Channel 2 Value Register Low; 0x0000003D *** ;*** PTFD - Port F Data Register; 0x00000040 *** PTFD: equ $00000040 ;*** PTFD - Port F Data Register; 0x00000040 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFD_PTFD0: equ 0 ; Port F Data Register Bit 0 PTFD_PTFD1: equ 1 ; Port F Data Register Bit 1 PTFD_PTFD2: equ 2 ; Port F Data Register Bit 2 PTFD_PTFD3: equ 3 ; Port F Data Register Bit 3 PTFD_PTFD4: equ 4 ; Port F Data Register Bit 4 PTFD_PTFD5: equ 5 ; Port F Data Register Bit 5 PTFD_PTFD6: equ 6 ; Port F Data Register Bit 6 PTFD_PTFD7: equ 7 ; Port F Data Register Bit 7 ; bit position masks mPTFD_PTFD0: equ %00000001 mPTFD_PTFD1: equ %00000010 mPTFD_PTFD2: equ %00000100 mPTFD_PTFD3: equ %00001000 mPTFD_PTFD4: equ %00010000 mPTFD_PTFD5: equ %00100000 mPTFD_PTFD6: equ %01000000 mPTFD_PTFD7: equ %10000000 ;*** PTFPE - Pullup Enable for Port F; 0x00000041 *** PTFPE: equ $00000041 ;*** PTFPE - Pullup Enable for Port F; 0x00000041 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFPE_PTFPE0: equ 0 ; Pullup Enable for Port F Bit 0 PTFPE_PTFPE1: equ 1 ; Pullup Enable for Port F Bit 1 PTFPE_PTFPE2: equ 2 ; Pullup Enable for Port F Bit 2 PTFPE_PTFPE3: equ 3 ; Pullup Enable for Port F Bit 3 PTFPE_PTFPE4: equ 4 ; Pullup Enable for Port F Bit 4 PTFPE_PTFPE5: equ 5 ; Pullup Enable for Port F Bit 5 PTFPE_PTFPE6: equ 6 ; Pullup Enable for Port F Bit 6 PTFPE_PTFPE7: equ 7 ; Pullup Enable for Port F Bit 7 ; bit position masks mPTFPE_PTFPE0: equ %00000001 mPTFPE_PTFPE1: equ %00000010 mPTFPE_PTFPE2: equ %00000100 mPTFPE_PTFPE3: equ %00001000 mPTFPE_PTFPE4: equ %00010000 mPTFPE_PTFPE5: equ %00100000 mPTFPE_PTFPE6: equ %01000000 mPTFPE_PTFPE7: equ %10000000 ;*** PTFSE - Slew Rate Control Enable for Port F; 0x00000042 *** PTFSE: equ $00000042 ;*** PTFSE - Slew Rate Control Enable for Port F; 0x00000042 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFSE_PTFSE0: equ 0 ; Slew Rate Control Enable for Port F Bit 0 PTFSE_PTFSE1: equ 1 ; Slew Rate Control Enable for Port F Bit 1 PTFSE_PTFSE2: equ 2 ; Slew Rate Control Enable for Port F Bit 2 PTFSE_PTFSE3: equ 3 ; Slew Rate Control Enable for Port F Bit 3 PTFSE_PTFSE4: equ 4 ; Slew Rate Control Enable for Port F Bit 4 PTFSE_PTFSE5: equ 5 ; Slew Rate Control Enable for Port F Bit 5 PTFSE_PTFSE6: equ 6 ; Slew Rate Control Enable for Port F Bit 6 PTFSE_PTFSE7: equ 7 ; Slew Rate Control Enable for Port F Bit 7 ; bit position masks mPTFSE_PTFSE0: equ %00000001 mPTFSE_PTFSE1: equ %00000010 mPTFSE_PTFSE2: equ %00000100 mPTFSE_PTFSE3: equ %00001000 mPTFSE_PTFSE4: equ %00010000 mPTFSE_PTFSE5: equ %00100000 mPTFSE_PTFSE6: equ %01000000 mPTFSE_PTFSE7: equ %10000000 ;*** PTFDD - Data Direction Register G; 0x00000043 *** PTFDD: equ $00000043 ;*** PTFDD - Data Direction Register G; 0x00000043 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDD_PTFDD0: equ 0 ; Data Direction for Port F Bit 0 PTFDD_PTFDD1: equ 1 ; Data Direction for Port F Bit 1 PTFDD_PTFDD2: equ 2 ; Data Direction for Port F Bit 2 PTFDD_PTFDD3: equ 3 ; Data Direction for Port F Bit 3 PTFDD_PTFDD4: equ 4 ; Data Direction for Port F Bit 4 PTFDD_PTFDD5: equ 5 ; Data Direction for Port F Bit 5 PTFDD_PTFDD6: equ 6 ; Data Direction for Port F Bit 6 PTFDD_PTFDD7: equ 7 ; Data Direction for Port F Bit 7 ; bit position masks mPTFDD_PTFDD0: equ %00000001 mPTFDD_PTFDD1: equ %00000010 mPTFDD_PTFDD2: equ %00000100 mPTFDD_PTFDD3: equ %00001000 mPTFDD_PTFDD4: equ %00010000 mPTFDD_PTFDD5: equ %00100000 mPTFDD_PTFDD6: equ %01000000 mPTFDD_PTFDD7: equ %10000000 ;*** PTGD - Port G Data Register; 0x00000044 *** PTGD: equ $00000044 ;*** PTGD - Port G Data Register; 0x00000044 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGD_PTGD0: equ 0 ; Port G Data Register Bit 0 PTGD_PTGD1: equ 1 ; Port G Data Register Bit 1 PTGD_PTGD2: equ 2 ; Port G Data Register Bit 2 ; bit position masks mPTGD_PTGD0: equ %00000001 mPTGD_PTGD1: equ %00000010 mPTGD_PTGD2: equ %00000100 ;*** PTGPE - Pullup Enable for Port G; 0x00000045 *** PTGPE: equ $00000045 ;*** PTGPE - Pullup Enable for Port G; 0x00000045 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGPE_PTGPE0: equ 0 ; Pullup Enable for Port G Bit 0 PTGPE_PTGPE1: equ 1 ; Pullup Enable for Port G Bit 1 PTGPE_PTGPE2: equ 2 ; Pullup Enable for Port G Bit 2 ; bit position masks mPTGPE_PTGPE0: equ %00000001 mPTGPE_PTGPE1: equ %00000010 mPTGPE_PTGPE2: equ %00000100 ;*** PTGSE - Slew Rate Control Enable for Port G; 0x00000046 *** PTGSE: equ $00000046 ;*** PTGSE - Slew Rate Control Enable for Port G; 0x00000046 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGSE_PTGSE0: equ 0 ; Slew Rate Control Enable for Port G Bit 0 PTGSE_PTGSE1: equ 1 ; Slew Rate Control Enable for Port G Bit 1 PTGSE_PTGSE2: equ 2 ; Slew Rate Control Enable for Port G Bit 2 ; bit position masks mPTGSE_PTGSE0: equ %00000001 mPTGSE_PTGSE1: equ %00000010 mPTGSE_PTGSE2: equ %00000100 ;*** PTGDD - Data Direction Register G; 0x00000047 *** PTGDD: equ $00000047 ;*** PTGDD - Data Direction Register G; 0x00000047 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDD_PTGDD0: equ 0 ; Data Direction for Port G Bit 0 PTGDD_PTGDD1: equ 1 ; Data Direction for Port G Bit 1 PTGDD_PTGDD2: equ 2 ; Data Direction for Port G Bit 2 ; bit position masks mPTGDD_PTGDD0: equ %00000001 mPTGDD_PTGDD1: equ %00000010 mPTGDD_PTGDD2: equ %00000100 ;*** ICGC1 - ICG Control Register 1; 0x00000048 *** ICGC1: equ $00000048 ;*** ICGC1 - ICG Control Register 1; 0x00000048 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGC1_LOCD: equ 1 ; Loss of Clock Disable ICGC1_OSCSTEN: equ 2 ; Enable Oscillator in Off Mode ICGC1_CLKS0: equ 3 ; Clock Mode Select Bit 0 ICGC1_CLKS1: equ 4 ; Clock Mode Select Bit 1 ICGC1_REFS: equ 5 ; External Reference Select ICGC1_RANGE: equ 6 ; Frequency Range Select ICGC1_HGO: equ 7 ; High Gain Oscillator Select ; bit position masks mICGC1_LOCD: equ %00000010 mICGC1_OSCSTEN: equ %00000100 mICGC1_CLKS0: equ %00001000 mICGC1_CLKS1: equ %00010000 mICGC1_REFS: equ %00100000 mICGC1_RANGE: equ %01000000 mICGC1_HGO: equ %10000000 ;*** ICGC2 - ICG Control Register 2; 0x00000049 *** ICGC2: equ $00000049 ;*** ICGC2 - ICG Control Register 2; 0x00000049 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGC2_RFD0: equ 0 ; Reduced Frequency Divider Bit 0 ICGC2_RFD1: equ 1 ; Reduced Frequency Divider Bit 1 ICGC2_RFD2: equ 2 ; Reduced Frequency Divider Bit 2 ICGC2_LOCRE: equ 3 ; Loss of Clock Reset Enable ICGC2_MFD0: equ 4 ; Multiplication Factor Bit 0 ICGC2_MFD1: equ 5 ; Multiplication Factor Bit 1 ICGC2_MFD2: equ 6 ; Multiplication Factor Bit 2 ICGC2_LOLRE: equ 7 ; Loss of Lock Reset Enable ; bit position masks mICGC2_RFD0: equ %00000001 mICGC2_RFD1: equ %00000010 mICGC2_RFD2: equ %00000100 mICGC2_LOCRE: equ %00001000 mICGC2_MFD0: equ %00010000 mICGC2_MFD1: equ %00100000 mICGC2_MFD2: equ %01000000 mICGC2_LOLRE: equ %10000000 ;*** ICGS1 - ICG Status Register 1; 0x0000004A *** ICGS1: equ $0000004A ;*** ICGS1 - ICG Status Register 1; 0x0000004A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGS1_ICGIF: equ 0 ; ICG Interrupt Flag ICGS1_ERCS: equ 1 ; External Reference Clock Status ICGS1_LOCS: equ 2 ; Loss Of Clock Status ICGS1_LOCK: equ 3 ; FLL Lock Status ICGS1_LOLS: equ 4 ; FLL Loss of Lock Status ICGS1_REFST: equ 5 ; Reference Clock Status ICGS1_CLKST0: equ 6 ; Clock Mode Status Bit 0 ICGS1_CLKST1: equ 7 ; Clock Mode Status Bit 1 ; bit position masks mICGS1_ICGIF: equ %00000001 mICGS1_ERCS: equ %00000010 mICGS1_LOCS: equ %00000100 mICGS1_LOCK: equ %00001000 mICGS1_LOLS: equ %00010000 mICGS1_REFST: equ %00100000 mICGS1_CLKST0: equ %01000000 mICGS1_CLKST1: equ %10000000 ;*** ICGS2 - ICG Status Register 2; 0x0000004B *** ICGS2: equ $0000004B ;*** ICGS2 - ICG Status Register 2; 0x0000004B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGS2_DCOS: equ 0 ; DCO Clock Stable ; bit position masks mICGS2_DCOS: equ %00000001 ;*** ICGFLT - ICG Filter Register; 0x0000004C *** ICGFLT: equ $0000004C ;*** ICGFLT - ICG Filter Register; 0x0000004C *** ;*** ICGFLTU - ICG Upper Filter Register; 0x0000004C *** ICGFLTU: equ $0000004C ;*** ICGFLTU - ICG Upper Filter Register; 0x0000004C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGFLTU_FLT8: equ 0 ; ICG Filter Bit 8 ICGFLTU_FLT9: equ 1 ; ICG Filter Bit 9 ICGFLTU_FLT10: equ 2 ; ICG Filter Bit 10 ICGFLTU_FLT11: equ 3 ; ICG Filter Bit 11 ; bit position masks mICGFLTU_FLT8: equ %00000001 mICGFLTU_FLT9: equ %00000010 mICGFLTU_FLT10: equ %00000100 mICGFLTU_FLT11: equ %00001000 ;*** ICGFLTL - ICG Lower Filter Register; 0x0000004D *** ICGFLTL: equ $0000004D ;*** ICGFLTL - ICG Lower Filter Register; 0x0000004D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGFLTL_FLT0: equ 0 ; ICG Filter Bit 0 ICGFLTL_FLT1: equ 1 ; ICG Filter Bit 1 ICGFLTL_FLT2: equ 2 ; ICG Filter Bit 2 ICGFLTL_FLT3: equ 3 ; ICG Filter Bit 3 ICGFLTL_FLT4: equ 4 ; ICG Filter Bit 4 ICGFLTL_FLT5: equ 5 ; ICG Filter Bit 5 ICGFLTL_FLT6: equ 6 ; ICG Filter Bit 6 ICGFLTL_FLT7: equ 7 ; ICG Filter Bit 7 ; bit position masks mICGFLTL_FLT0: equ %00000001 mICGFLTL_FLT1: equ %00000010 mICGFLTL_FLT2: equ %00000100 mICGFLTL_FLT3: equ %00001000 mICGFLTL_FLT4: equ %00010000 mICGFLTL_FLT5: equ %00100000 mICGFLTL_FLT6: equ %01000000 mICGFLTL_FLT7: equ %10000000 ;*** ICGTRM - ICG Trim Register; 0x0000004E *** ICGTRM: equ $0000004E ;*** ICGTRM - ICG Trim Register; 0x0000004E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICGTRM_TRIM0: equ 0 ; ICG Trim Bit 0 ICGTRM_TRIM1: equ 1 ; ICG Trim Bit 1 ICGTRM_TRIM2: equ 2 ; ICG Trim Bit 2 ICGTRM_TRIM3: equ 3 ; ICG Trim Bit 3 ICGTRM_TRIM4: equ 4 ; ICG Trim Bit 4 ICGTRM_TRIM5: equ 5 ; ICG Trim Bit 5 ICGTRM_TRIM6: equ 6 ; ICG Trim Bit 6 ICGTRM_TRIM7: equ 7 ; ICG Trim Bit 7 ; bit position masks mICGTRM_TRIM0: equ %00000001 mICGTRM_TRIM1: equ %00000010 mICGTRM_TRIM2: equ %00000100 mICGTRM_TRIM3: equ %00001000 mICGTRM_TRIM4: equ %00010000 mICGTRM_TRIM5: equ %00100000 mICGTRM_TRIM6: equ %01000000 mICGTRM_TRIM7: equ %10000000 ;*** ATD1C - ATD Control Register; 0x00000050 *** ATD1C: equ $00000050 ;*** ATD1C - ATD Control Register; 0x00000050 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ATD1C_PRS0: equ 0 ; Prescaler Rate Select Bit 0 ATD1C_PRS1: equ 1 ; Prescaler Rate Select Bit 1 ATD1C_PRS2: equ 2 ; Prescaler Rate Select Bit 2 ATD1C_PRS3: equ 3 ; Prescaler Rate Select Bit 3 ATD1C_SGN: equ 4 ; Signed Result Select ATD1C_RES8: equ 5 ; ATD Resolution Select ATD1C_DJM: equ 6 ; Data Justification Mode ATD1C_ATDPU: equ 7 ; ATD Power Up ; bit position masks mATD1C_PRS0: equ %00000001 mATD1C_PRS1: equ %00000010 mATD1C_PRS2: equ %00000100 mATD1C_PRS3: equ %00001000 mATD1C_SGN: equ %00010000 mATD1C_RES8: equ %00100000 mATD1C_DJM: equ %01000000 mATD1C_ATDPU: equ %10000000 ;*** ATD1SC - ATD Status and Control Register; 0x00000051 *** ATD1SC: equ $00000051 ;*** ATD1SC - ATD Status and Control Register; 0x00000051 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ATD1SC_ATDCH0: equ 0 ; Analog Input Channel Select Bit 0 ATD1SC_ATDCH1: equ 1 ; Analog Input Channel Select Bit 1 ATD1SC_ATDCH2: equ 2 ; Analog Input Channel Select Bit 2 ATD1SC_ATDCH3: equ 3 ; Analog Input Channel Select Bit 3 ATD1SC_ATDCH4: equ 4 ; Analog Input Channel Select Bit 4 ATD1SC_ATDCO: equ 5 ; ATD Continuous Conversion ATD1SC_ATDIE: equ 6 ; ATD Interrupt Enabled ATD1SC_CCF: equ 7 ; Conversion Complete Flag ; bit position masks mATD1SC_ATDCH0: equ %00000001 mATD1SC_ATDCH1: equ %00000010 mATD1SC_ATDCH2: equ %00000100 mATD1SC_ATDCH3: equ %00001000 mATD1SC_ATDCH4: equ %00010000 mATD1SC_ATDCO: equ %00100000 mATD1SC_ATDIE: equ %01000000 mATD1SC_CCF: equ %10000000 ;*** ATD1R - ATD Result Data; 0x00000052 *** ATD1R: equ $00000052 ;*** ATD1R - ATD Result Data; 0x00000052 *** ;*** ATD1RH - ATD Result Data High Right Justified; 0x00000052 *** ATD1RH: equ $00000052 ;*** ATD1RH - ATD Result Data High Right Justified; 0x00000052 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ATD1RH_BIT8: equ 0 ; ATD Result Data Bit 8 ATD1RH_BIT9: equ 1 ; ATD Result Data Bit 9 ; bit position masks mATD1RH_BIT8: equ %00000001 mATD1RH_BIT9: equ %00000010 ;*** ATD1RL - ATD Result Data Low Right Justified; 0x00000053 *** ATD1RL: equ $00000053 ;*** ATD1RL - ATD Result Data Low Right Justified; 0x00000053 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ATD1RL_BIT0: equ 0 ; ATD Result Data Bit 0 ATD1RL_BIT1: equ 1 ; ATD Result Data Bit 1 ATD1RL_BIT2: equ 2 ; ATD Result Data Bit 2 ATD1RL_BIT3: equ 3 ; ATD Result Data Bit 3 ATD1RL_BIT4: equ 4 ; ATD Result Data Bit 4 ATD1RL_BIT5: equ 5 ; ATD Result Data Bit 5 ATD1RL_BIT6: equ 6 ; ATD Result Data Bit 6 ATD1RL_BIT7: equ 7 ; ATD Result Data Bit 7 ; bit position masks mATD1RL_BIT0: equ %00000001 mATD1RL_BIT1: equ %00000010 mATD1RL_BIT2: equ %00000100 mATD1RL_BIT3: equ %00001000 mATD1RL_BIT4: equ %00010000 mATD1RL_BIT5: equ %00100000 mATD1RL_BIT6: equ %01000000 mATD1RL_BIT7: equ %10000000 ;*** ATD1PE - ATD Pin Enable; 0x00000054 *** ATD1PE: equ $00000054 ;*** ATD1PE - ATD Pin Enable; 0x00000054 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ATD1PE_ATDPE0: equ 0 ; ATD Pin Enable Bit 0 ATD1PE_ATDPE1: equ 1 ; ATD Pin Enable Bit 1 ATD1PE_ATDPE2: equ 2 ; ATD Pin Enable Bit 2 ATD1PE_ATDPE3: equ 3 ; ATD Pin Enable Bit 3 ATD1PE_ATDPE4: equ 4 ; ATD Pin Enable Bit 4 ATD1PE_ATDPE5: equ 5 ; ATD Pin Enable Bit 5 ATD1PE_ATDPE6: equ 6 ; ATD Pin Enable Bit 6 ATD1PE_ATDPE7: equ 7 ; ATD Pin Enable Bit 7 ; bit position masks mATD1PE_ATDPE0: equ %00000001 mATD1PE_ATDPE1: equ %00000010 mATD1PE_ATDPE2: equ %00000100 mATD1PE_ATDPE3: equ %00001000 mATD1PE_ATDPE4: equ %00010000 mATD1PE_ATDPE5: equ %00100000 mATD1PE_ATDPE6: equ %01000000 mATD1PE_ATDPE7: equ %10000000 ;*** IIC1A - IIC Address Register; 0x00000058 *** IIC1A: equ $00000058 ;*** IIC1A - IIC Address Register; 0x00000058 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IIC1A_ADDR1: equ 1 ; IIC Address Bit 1 IIC1A_ADDR2: equ 2 ; IIC Address Bit 2 IIC1A_ADDR3: equ 3 ; IIC Address Bit 3 IIC1A_ADDR4: equ 4 ; IIC Address Bit 4 IIC1A_ADDR5: equ 5 ; IIC Address Bit 5 IIC1A_ADDR6: equ 6 ; IIC Address Bit 6 IIC1A_ADDR7: equ 7 ; IIC Address Bit 7 ; bit position masks mIIC1A_ADDR1: equ %00000010 mIIC1A_ADDR2: equ %00000100 mIIC1A_ADDR3: equ %00001000 mIIC1A_ADDR4: equ %00010000 mIIC1A_ADDR5: equ %00100000 mIIC1A_ADDR6: equ %01000000 mIIC1A_ADDR7: equ %10000000 ;*** IIC1F - IIC Frequency Divider Register; 0x00000059 *** IIC1F: equ $00000059 ;*** IIC1F - IIC Frequency Divider Register; 0x00000059 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IIC1F_ICR0: equ 0 ; IIC Clock Rate Bit 0 IIC1F_ICR1: equ 1 ; IIC Clock Rate Bit 1 IIC1F_ICR2: equ 2 ; IIC Clock Rate Bit 2 IIC1F_ICR3: equ 3 ; IIC Clock Rate Bit 3 IIC1F_ICR4: equ 4 ; IIC Clock Rate Bit 4 IIC1F_ICR5: equ 5 ; IIC Clock Rate Bit 5 IIC1F_MULT0: equ 6 ; Multiplier Factor Bit 0 IIC1F_MULT1: equ 7 ; Multiplier Factor Bit 1 ; bit position masks mIIC1F_ICR0: equ %00000001 mIIC1F_ICR1: equ %00000010 mIIC1F_ICR2: equ %00000100 mIIC1F_ICR3: equ %00001000 mIIC1F_ICR4: equ %00010000 mIIC1F_ICR5: equ %00100000 mIIC1F_MULT0: equ %01000000 mIIC1F_MULT1: equ %10000000 ;*** IIC1C - IIC Control Register; 0x0000005A *** IIC1C: equ $0000005A ;*** IIC1C - IIC Control Register; 0x0000005A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IIC1C_RSTA: equ 2 ; Repeat START Bit IIC1C_TXAK: equ 3 ; Transmit Acknowledge Enable Bit IIC1C_TX: equ 4 ; Transmit Mode Select Bit IIC1C_MST: equ 5 ; Master Mode Select Bit IIC1C_IICIE: equ 6 ; IIC Interrupt Enable Bit IIC1C_IICEN: equ 7 ; IIC Enable Bit ; bit position masks mIIC1C_RSTA: equ %00000100 mIIC1C_TXAK: equ %00001000 mIIC1C_TX: equ %00010000 mIIC1C_MST: equ %00100000 mIIC1C_IICIE: equ %01000000 mIIC1C_IICEN: equ %10000000 ;*** IIC1S - IIC Status Register; 0x0000005B *** IIC1S: equ $0000005B ;*** IIC1S - IIC Status Register; 0x0000005B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IIC1S_RXAK: equ 0 ; Receive Acknowledge IIC1S_IICIF: equ 1 ; IIC Interrupt Flag IIC1S_SRW: equ 2 ; Slave Read/Write IIC1S_ARBL: equ 4 ; Arbitration Lost IIC1S_BUSY: equ 5 ; Bus Busy bit IIC1S_IAAS: equ 6 ; Addressed as a Slave Bit IIC1S_TCF: equ 7 ; Transfer Complete Flag ; bit position masks mIIC1S_RXAK: equ %00000001 mIIC1S_IICIF: equ %00000010 mIIC1S_SRW: equ %00000100 mIIC1S_ARBL: equ %00010000 mIIC1S_BUSY: equ %00100000 mIIC1S_IAAS: equ %01000000 mIIC1S_TCF: equ %10000000 ;*** IIC1D - IIC Data I/O Register; 0x0000005C *** IIC1D: equ $0000005C ;*** IIC1D - IIC Data I/O Register; 0x0000005C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IIC1D_DATA0: equ 0 ; IIC Data Bit 0 IIC1D_DATA1: equ 1 ; IIC Data Bit 1 IIC1D_DATA2: equ 2 ; IIC Data Bit 2 IIC1D_DATA3: equ 3 ; IIC Data Bit 3 IIC1D_DATA4: equ 4 ; IIC Data Bit 4 IIC1D_DATA5: equ 5 ; IIC Data Bit 5 IIC1D_DATA6: equ 6 ; IIC Data Bit 6 IIC1D_DATA7: equ 7 ; IIC Data Bit 7 ; bit position masks mIIC1D_DATA0: equ %00000001 mIIC1D_DATA1: equ %00000010 mIIC1D_DATA2: equ %00000100 mIIC1D_DATA3: equ %00001000 mIIC1D_DATA4: equ %00010000 mIIC1D_DATA5: equ %00100000 mIIC1D_DATA6: equ %01000000 mIIC1D_DATA7: equ %10000000 ;*** TPM2SC - TPM 2 Status and Control Register; 0x00000060 *** TPM2SC: equ $00000060 ;*** TPM2SC - TPM 2 Status and Control Register; 0x00000060 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2SC_PS0: equ 0 ; Prescale Divisor Select Bit 0 TPM2SC_PS1: equ 1 ; Prescale Divisor Select Bit 1 TPM2SC_PS2: equ 2 ; Prescale Divisor Select Bit 2 TPM2SC_CLKSA: equ 3 ; Clock Source Select A TPM2SC_CLKSB: equ 4 ; Clock Source Select B TPM2SC_CPWMS: equ 5 ; Center-Aligned PWM Select TPM2SC_TOIE: equ 6 ; Timer Overflow Interrupt Enable TPM2SC_TOF: equ 7 ; Timer Overflow Flag ; bit position masks mTPM2SC_PS0: equ %00000001 mTPM2SC_PS1: equ %00000010 mTPM2SC_PS2: equ %00000100 mTPM2SC_CLKSA: equ %00001000 mTPM2SC_CLKSB: equ %00010000 mTPM2SC_CPWMS: equ %00100000 mTPM2SC_TOIE: equ %01000000 mTPM2SC_TOF: equ %10000000 ;*** TPM2CNT - TPM 2 Counter Register; 0x00000061 *** TPM2CNT: equ $00000061 ;*** TPM2CNT - TPM 2 Counter Register; 0x00000061 *** ;*** TPM2CNTH - TPM 2 Counter Register High; 0x00000061 *** TPM2CNTH: equ $00000061 ;*** TPM2CNTH - TPM 2 Counter Register High; 0x00000061 *** ;*** TPM2CNTL - TPM 2 Counter Register Low; 0x00000062 *** TPM2CNTL: equ $00000062 ;*** TPM2CNTL - TPM 2 Counter Register Low; 0x00000062 *** ;*** TPM2MOD - TPM 2 Timer Counter Modulo Register; 0x00000063 *** TPM2MOD: equ $00000063 ;*** TPM2MOD - TPM 2 Timer Counter Modulo Register; 0x00000063 *** ;*** TPM2MODH - TPM 2 Timer Counter Modulo Register High; 0x00000063 *** TPM2MODH: equ $00000063 ;*** TPM2MODH - TPM 2 Timer Counter Modulo Register High; 0x00000063 *** ;*** TPM2MODL - TPM 2 Timer Counter Modulo Register Low; 0x00000064 *** TPM2MODL: equ $00000064 ;*** TPM2MODL - TPM 2 Timer Counter Modulo Register Low; 0x00000064 *** ;*** TPM2C0SC - TPM 2 Timer Channel 0 Status and Control Register; 0x00000065 *** TPM2C0SC: equ $00000065 ;*** TPM2C0SC - TPM 2 Timer Channel 0 Status and Control Register; 0x00000065 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C0SC_ELS0A: equ 2 ; Edge/Level Select Bit A TPM2C0SC_ELS0B: equ 3 ; Edge/Level Select Bit B TPM2C0SC_MS0A: equ 4 ; Mode Select A for TPM Channel 0 TPM2C0SC_MS0B: equ 5 ; Mode Select B for TPM Channel 0 TPM2C0SC_CH0IE: equ 6 ; Channel 0 Interrupt Enable TPM2C0SC_CH0F: equ 7 ; Channel 0 Flag ; bit position masks mTPM2C0SC_ELS0A: equ %00000100 mTPM2C0SC_ELS0B: equ %00001000 mTPM2C0SC_MS0A: equ %00010000 mTPM2C0SC_MS0B: equ %00100000 mTPM2C0SC_CH0IE: equ %01000000 mTPM2C0SC_CH0F: equ %10000000 ;*** TPM2C0V - TPM 2 Timer Channel 0 Value Register; 0x00000066 *** TPM2C0V: equ $00000066 ;*** TPM2C0V - TPM 2 Timer Channel 0 Value Register; 0x00000066 *** ;*** TPM2C0VH - TPM 2 Timer Channel 0 Value Register High; 0x00000066 *** TPM2C0VH: equ $00000066 ;*** TPM2C0VH - TPM 2 Timer Channel 0 Value Register High; 0x00000066 *** ;*** TPM2C0VL - TPM 2 Timer Channel 0 Value Register Low; 0x00000067 *** TPM2C0VL: equ $00000067 ;*** TPM2C0VL - TPM 2 Timer Channel 0 Value Register Low; 0x00000067 *** ;*** TPM2C1SC - TPM 2 Timer Channel 1 Status and Control Register; 0x00000068 *** TPM2C1SC: equ $00000068 ;*** TPM2C1SC - TPM 2 Timer Channel 1 Status and Control Register; 0x00000068 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C1SC_ELS1A: equ 2 ; Edge/Level Select Bit A TPM2C1SC_ELS1B: equ 3 ; Edge/Level Select Bit B TPM2C1SC_MS1A: equ 4 ; Mode Select A for TPM Channel 1 TPM2C1SC_MS1B: equ 5 ; Mode Select B for TPM Channel 1 TPM2C1SC_CH1IE: equ 6 ; Channel 1 Interrupt Enable TPM2C1SC_CH1F: equ 7 ; Channel 1 Flag ; bit position masks mTPM2C1SC_ELS1A: equ %00000100 mTPM2C1SC_ELS1B: equ %00001000 mTPM2C1SC_MS1A: equ %00010000 mTPM2C1SC_MS1B: equ %00100000 mTPM2C1SC_CH1IE: equ %01000000 mTPM2C1SC_CH1F: equ %10000000 ;*** TPM2C1V - TPM 2 Timer Channel 1 Value Register; 0x00000069 *** TPM2C1V: equ $00000069 ;*** TPM2C1V - TPM 2 Timer Channel 1 Value Register; 0x00000069 *** ;*** TPM2C1VH - TPM 2 Timer Channel 1 Value Register High; 0x00000069 *** TPM2C1VH: equ $00000069 ;*** TPM2C1VH - TPM 2 Timer Channel 1 Value Register High; 0x00000069 *** ;*** TPM2C1VL - TPM 2 Timer Channel 1 Value Register Low; 0x0000006A *** TPM2C1VL: equ $0000006A ;*** TPM2C1VL - TPM 2 Timer Channel 1 Value Register Low; 0x0000006A *** ;*** TPM2C2SC - TPM 2 Timer Channel 2 Status and Control Register; 0x0000006B *** TPM2C2SC: equ $0000006B ;*** TPM2C2SC - TPM 2 Timer Channel 2 Status and Control Register; 0x0000006B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C2SC_ELS2A: equ 2 ; Edge/Level Select Bit A TPM2C2SC_ELS2B: equ 3 ; Edge/Level Select Bit B TPM2C2SC_MS2A: equ 4 ; Mode Select A for TPM Channel 2 TPM2C2SC_MS2B: equ 5 ; Mode Select B for TPM Channel 2 TPM2C2SC_CH2IE: equ 6 ; Channel 2 Interrupt Enable TPM2C2SC_CH2F: equ 7 ; Channel 2 Flag ; bit position masks mTPM2C2SC_ELS2A: equ %00000100 mTPM2C2SC_ELS2B: equ %00001000 mTPM2C2SC_MS2A: equ %00010000 mTPM2C2SC_MS2B: equ %00100000 mTPM2C2SC_CH2IE: equ %01000000 mTPM2C2SC_CH2F: equ %10000000 ;*** TPM2C2V - TPM 2 Timer Channel 2 Value Register; 0x0000006C *** TPM2C2V: equ $0000006C ;*** TPM2C2V - TPM 2 Timer Channel 2 Value Register; 0x0000006C *** ;*** TPM2C2VH - TPM 2 Timer Channel 2 Value Register High; 0x0000006C *** TPM2C2VH: equ $0000006C ;*** TPM2C2VH - TPM 2 Timer Channel 2 Value Register High; 0x0000006C *** ;*** TPM2C2VL - TPM 2 Timer Channel 2 Value Register Low; 0x0000006D *** TPM2C2VL: equ $0000006D ;*** TPM2C2VL - TPM 2 Timer Channel 2 Value Register Low; 0x0000006D *** ;*** TPM2C3SC - TPM 2 Timer Channel 3 Status and Control Register; 0x0000006E *** TPM2C3SC: equ $0000006E ;*** TPM2C3SC - TPM 2 Timer Channel 3 Status and Control Register; 0x0000006E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C3SC_ELS3A: equ 2 ; Edge/Level Select Bit A TPM2C3SC_ELS3B: equ 3 ; Edge/Level Select Bit B TPM2C3SC_MS3A: equ 4 ; Mode Select A for TPM Channel 3 TPM2C3SC_MS3B: equ 5 ; Mode Select B for TPM Channel 3 TPM2C3SC_CH3IE: equ 6 ; Channel 3 Interrupt Enable TPM2C3SC_CH3F: equ 7 ; Channel 3 Flag ; bit position masks mTPM2C3SC_ELS3A: equ %00000100 mTPM2C3SC_ELS3B: equ %00001000 mTPM2C3SC_MS3A: equ %00010000 mTPM2C3SC_MS3B: equ %00100000 mTPM2C3SC_CH3IE: equ %01000000 mTPM2C3SC_CH3F: equ %10000000 ;*** TPM2C3V - TPM 2 Timer Channel 3 Value Register; 0x0000006F *** TPM2C3V: equ $0000006F ;*** TPM2C3V - TPM 2 Timer Channel 3 Value Register; 0x0000006F *** ;*** TPM2C3VH - TPM 2 Timer Channel 3 Value Register High; 0x0000006F *** TPM2C3VH: equ $0000006F ;*** TPM2C3VH - TPM 2 Timer Channel 3 Value Register High; 0x0000006F *** ;*** TPM2C3VL - TPM 2 Timer Channel 3 Value Register Low; 0x00000070 *** TPM2C3VL: equ $00000070 ;*** TPM2C3VL - TPM 2 Timer Channel 3 Value Register Low; 0x00000070 *** ;*** TPM2C4SC - TPM 2 Timer Channel 4 Status and Control Register; 0x00000071 *** TPM2C4SC: equ $00000071 ;*** TPM2C4SC - TPM 2 Timer Channel 4 Status and Control Register; 0x00000071 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C4SC_ELS4A: equ 2 ; Edge/Level Select Bit A TPM2C4SC_ELS4B: equ 3 ; Edge/Level Select Bit B TPM2C4SC_MS4A: equ 4 ; Mode Select A for TPM Channel 4 TPM2C4SC_MS4B: equ 5 ; Mode Select B for TPM Channel 4 TPM2C4SC_CH4IE: equ 6 ; Channel 4 Interrupt Enable TPM2C4SC_CH4F: equ 7 ; Channel 4 Flag ; bit position masks mTPM2C4SC_ELS4A: equ %00000100 mTPM2C4SC_ELS4B: equ %00001000 mTPM2C4SC_MS4A: equ %00010000 mTPM2C4SC_MS4B: equ %00100000 mTPM2C4SC_CH4IE: equ %01000000 mTPM2C4SC_CH4F: equ %10000000 ;*** TPM2C4V - TPM 2 Timer Channel 4 Value Register; 0x00000072 *** TPM2C4V: equ $00000072 ;*** TPM2C4V - TPM 2 Timer Channel 4 Value Register; 0x00000072 *** ;*** TPM2C4VH - TPM 2 Timer Channel 4 Value Register High; 0x00000072 *** TPM2C4VH: equ $00000072 ;*** TPM2C4VH - TPM 2 Timer Channel 4 Value Register High; 0x00000072 *** ;*** TPM2C4VL - TPM 2 Timer Channel 4 Value Register Low; 0x00000073 *** TPM2C4VL: equ $00000073 ;*** TPM2C4VL - TPM 2 Timer Channel 4 Value Register Low; 0x00000073 *** ;*** SRS - System Reset Status; 0x00001800 *** SRS: equ $00001800 ;*** SRS - System Reset Status; 0x00001800 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRS_LVD: equ 1 ; Low Voltage Detect SRS_ICG: equ 2 ; Internal Clock Generation Module Reset SRS_ILOP: equ 4 ; Illegal Opcode SRS_COP: equ 5 ; Computer Operating Properly (COP) Watchdog SRS_PIN: equ 6 ; External Reset Pin SRS_POR: equ 7 ; Power-On Reset ; bit position masks mSRS_LVD: equ %00000010 mSRS_ICG: equ %00000100 mSRS_ILOP: equ %00010000 mSRS_COP: equ %00100000 mSRS_PIN: equ %01000000 mSRS_POR: equ %10000000 ;*** SBDFR - System Background Debug Force Reset Register; 0x00001801 *** SBDFR: equ $00001801 ;*** SBDFR - System Background Debug Force Reset Register; 0x00001801 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SBDFR_BDFR: equ 0 ; Background Debug Force Reset ; bit position masks mSBDFR_BDFR: equ %00000001 ;*** SOPT - System Options Register; 0x00001802 *** SOPT: equ $00001802 ;*** SOPT - System Options Register; 0x00001802 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT_BKGDPE: equ 1 ; Background Debug Mode Pin Enable SOPT_STOPE: equ 5 ; Stop Mode Enable SOPT_COPT: equ 6 ; COP Watchdog Timeout SOPT_COPE: equ 7 ; COP Watchdog Enable ; bit position masks mSOPT_BKGDPE: equ %00000010 mSOPT_STOPE: equ %00100000 mSOPT_COPT: equ %01000000 mSOPT_COPE: equ %10000000 ;*** SDID - System Integration Module Part ID Register; 0x00001806 *** SDID: equ $00001806 ;*** SDID - System Integration Module Part ID Register; 0x00001806 *** ;*** SDIDH - System Integration Module Part ID Register High; 0x00001806 *** SDIDH: equ $00001806 ;*** SDIDH - System Integration Module Part ID Register High; 0x00001806 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDH_ID8: equ 0 ; Part Identification Number 8 SDIDH_ID9: equ 1 ; Part Identification Number 9 SDIDH_ID10: equ 2 ; Part Identification Number 10 SDIDH_ID11: equ 3 ; Part Identification Number 11 SDIDH_REV0: equ 4 ; Revision Number 0 SDIDH_REV1: equ 5 ; Revision Number 1 SDIDH_REV2: equ 6 ; Revision Number 2 SDIDH_REV3: equ 7 ; Revision Number 3 ; bit position masks mSDIDH_ID8: equ %00000001 mSDIDH_ID9: equ %00000010 mSDIDH_ID10: equ %00000100 mSDIDH_ID11: equ %00001000 mSDIDH_REV0: equ %00010000 mSDIDH_REV1: equ %00100000 mSDIDH_REV2: equ %01000000 mSDIDH_REV3: equ %10000000 ;*** SDIDL - System Integration Module Part ID Register Low; 0x00001807 *** SDIDL: equ $00001807 ;*** SDIDL - System Integration Module Part ID Register Low; 0x00001807 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDL_ID0: equ 0 ; Part Identification Number 0 SDIDL_ID1: equ 1 ; Part Identification Number 1 SDIDL_ID2: equ 2 ; Part Identification Number 2 SDIDL_ID3: equ 3 ; Part Identification Number 3 SDIDL_ID4: equ 4 ; Part Identification Number 4 SDIDL_ID5: equ 5 ; Part Identification Number 5 SDIDL_ID6: equ 6 ; Part Identification Number 6 SDIDL_ID7: equ 7 ; Part Identification Number 7 ; bit position masks mSDIDL_ID0: equ %00000001 mSDIDL_ID1: equ %00000010 mSDIDL_ID2: equ %00000100 mSDIDL_ID3: equ %00001000 mSDIDL_ID4: equ %00010000 mSDIDL_ID5: equ %00100000 mSDIDL_ID6: equ %01000000 mSDIDL_ID7: equ %10000000 ;*** SRTISC - System RTI Status and Control Register; 0x00001808 *** SRTISC: equ $00001808 ;*** SRTISC - System RTI Status and Control Register; 0x00001808 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRTISC_RTIS0: equ 0 ; Real-Time Interrupt Delay Select Bit 0 SRTISC_RTIS1: equ 1 ; Real-Time Interrupt Delay Select Bit 1 SRTISC_RTIS2: equ 2 ; Real-Time Interrupt Delay Select Bit 2 SRTISC_RTIE: equ 4 ; Real-Time Interrupt Enable SRTISC_RTICLKS: equ 5 ; Real-Time Interrupt Clock Select SRTISC_RTIACK: equ 6 ; Real-Time Interrupt Acknowledge SRTISC_RTIF: equ 7 ; Real-Time Interrupt Flag ; bit position masks mSRTISC_RTIS0: equ %00000001 mSRTISC_RTIS1: equ %00000010 mSRTISC_RTIS2: equ %00000100 mSRTISC_RTIE: equ %00010000 mSRTISC_RTICLKS: equ %00100000 mSRTISC_RTIACK: equ %01000000 mSRTISC_RTIF: equ %10000000 ;*** SPMSC1 - PM Status and Control 1 Register; 0x00001809 *** SPMSC1: equ $00001809 ;*** SPMSC1 - PM Status and Control 1 Register; 0x00001809 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC1_LVDE: equ 2 ; Low-Voltage Detect Enable SPMSC1_LVDSE: equ 3 ; Low-Voltage Detect Stop Enable SPMSC1_LVDRE: equ 4 ; Low-Voltage Detect Reset Enable SPMSC1_LVDIE: equ 5 ; Low-Voltage Detect Interrrupt Enable SPMSC1_LVDACK: equ 6 ; Low-Voltage Detect Acknowledge SPMSC1_LVDF: equ 7 ; Low-Voltage Detect Flag ; bit position masks mSPMSC1_LVDE: equ %00000100 mSPMSC1_LVDSE: equ %00001000 mSPMSC1_LVDRE: equ %00010000 mSPMSC1_LVDIE: equ %00100000 mSPMSC1_LVDACK: equ %01000000 mSPMSC1_LVDF: equ %10000000 ;*** SPMSC2 - PM Status and Control 2 Register; 0x0000180A *** SPMSC2: equ $0000180A ;*** SPMSC2 - PM Status and Control 2 Register; 0x0000180A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC2_PPDC: equ 0 ; Partial Power Down Control SPMSC2_PDC: equ 1 ; Power Down Control SPMSC2_PPDACK: equ 2 ; Partial Power Down Acknowlege SPMSC2_PPDF: equ 3 ; Partial Power Down Flag SPMSC2_LVWV: equ 4 ; Low-Voltage Warning Voltage Select SPMSC2_LVDV: equ 5 ; Low-Voltage Detect Voltage Select SPMSC2_LVWACK: equ 6 ; Low-Voltage Warning Acknowlege SPMSC2_LVWF: equ 7 ; Low-Voltage Warning Flag ; bit position masks mSPMSC2_PPDC: equ %00000001 mSPMSC2_PDC: equ %00000010 mSPMSC2_PPDACK: equ %00000100 mSPMSC2_PPDF: equ %00001000 mSPMSC2_LVWV: equ %00010000 mSPMSC2_LVDV: equ %00100000 mSPMSC2_LVWACK: equ %01000000 mSPMSC2_LVWF: equ %10000000 ;*** DBGCAH - Debug Comparator A High Register; 0x00001810 *** DBGCAH: equ $00001810 ;*** DBGCAH - Debug Comparator A High Register; 0x00001810 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGCAH_Bit8: equ 0 ; Debug Comparator A Bit 8 DBGCAH_Bit9: equ 1 ; Debug Comparator A Bit 9 DBGCAH_Bit10: equ 2 ; Debug Comparator A Bit 10 DBGCAH_Bit11: equ 3 ; Debug Comparator A Bit 11 DBGCAH_Bit12: equ 4 ; Debug Comparator A Bit 12 DBGCAH_Bit13: equ 5 ; Debug Comparator A Bit 13 DBGCAH_Bit14: equ 6 ; Debug Comparator A Bit 14 DBGCAH_Bit15: equ 7 ; Debug Comparator A Bit 15 ; bit position masks mDBGCAH_Bit8: equ %00000001 mDBGCAH_Bit9: equ %00000010 mDBGCAH_Bit10: equ %00000100 mDBGCAH_Bit11: equ %00001000 mDBGCAH_Bit12: equ %00010000 mDBGCAH_Bit13: equ %00100000 mDBGCAH_Bit14: equ %01000000 mDBGCAH_Bit15: equ %10000000 ;*** DBGCAL - Debug Comparator A Low Register; 0x00001811 *** DBGCAL: equ $00001811 ;*** DBGCAL - Debug Comparator A Low Register; 0x00001811 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGCAL_Bit0: equ 0 ; Debug Comparator A Bit 0 DBGCAL_Bit1: equ 1 ; Debug Comparator A Bit 1 DBGCAL_Bit2: equ 2 ; Debug Comparator A Bit 2 DBGCAL_Bit3: equ 3 ; Debug Comparator A Bit 3 DBGCAL_Bit4: equ 4 ; Debug Comparator A Bit 4 DBGCAL_Bit5: equ 5 ; Debug Comparator A Bit 5 DBGCAL_Bit6: equ 6 ; Debug Comparator A Bit 6 DBGCAL_Bit7: equ 7 ; Debug Comparator A Bit 7 ; bit position masks mDBGCAL_Bit0: equ %00000001 mDBGCAL_Bit1: equ %00000010 mDBGCAL_Bit2: equ %00000100 mDBGCAL_Bit3: equ %00001000 mDBGCAL_Bit4: equ %00010000 mDBGCAL_Bit5: equ %00100000 mDBGCAL_Bit6: equ %01000000 mDBGCAL_Bit7: equ %10000000 ;*** DBGCBH - Debug Comparator B High Register; 0x00001812 *** DBGCBH: equ $00001812 ;*** DBGCBH - Debug Comparator B High Register; 0x00001812 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGCBH_Bit8: equ 0 ; Debug Comparator B Bit 8 DBGCBH_Bit9: equ 1 ; Debug Comparator B Bit 9 DBGCBH_Bit10: equ 2 ; Debug Comparator B Bit 10 DBGCBH_Bit11: equ 3 ; Debug Comparator B Bit 11 DBGCBH_Bit12: equ 4 ; Debug Comparator B Bit 12 DBGCBH_Bit13: equ 5 ; Debug Comparator B Bit 13 DBGCBH_Bit14: equ 6 ; Debug Comparator B Bit 14 DBGCBH_Bit15: equ 7 ; Debug Comparator B Bit 15 ; bit position masks mDBGCBH_Bit8: equ %00000001 mDBGCBH_Bit9: equ %00000010 mDBGCBH_Bit10: equ %00000100 mDBGCBH_Bit11: equ %00001000 mDBGCBH_Bit12: equ %00010000 mDBGCBH_Bit13: equ %00100000 mDBGCBH_Bit14: equ %01000000 mDBGCBH_Bit15: equ %10000000 ;*** DBGCBL - Debug Comparator B Low Register; 0x00001813 *** DBGCBL: equ $00001813 ;*** DBGCBL - Debug Comparator B Low Register; 0x00001813 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGCBL_Bit0: equ 0 ; Debug Comparator B Bit 0 DBGCBL_Bit1: equ 1 ; Debug Comparator B Bit 1 DBGCBL_Bit2: equ 2 ; Debug Comparator B Bit 2 DBGCBL_Bit3: equ 3 ; Debug Comparator B Bit 3 DBGCBL_Bit4: equ 4 ; Debug Comparator B Bit 4 DBGCBL_Bit5: equ 5 ; Debug Comparator B Bit 5 DBGCBL_Bit6: equ 6 ; Debug Comparator B Bit 6 DBGCBL_Bit7: equ 7 ; Debug Comparator B Bit 7 ; bit position masks mDBGCBL_Bit0: equ %00000001 mDBGCBL_Bit1: equ %00000010 mDBGCBL_Bit2: equ %00000100 mDBGCBL_Bit3: equ %00001000 mDBGCBL_Bit4: equ %00010000 mDBGCBL_Bit5: equ %00100000 mDBGCBL_Bit6: equ %01000000 mDBGCBL_Bit7: equ %10000000 ;*** DBGF - Debug FIFO Register; 0x00001814 *** DBGF: equ $00001814 ;*** DBGF - Debug FIFO Register; 0x00001814 *** ;*** DBGFH - Debug FIFO High Register; 0x00001814 *** DBGFH: equ $00001814 ;*** DBGFH - Debug FIFO High Register; 0x00001814 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGFH_Bit8: equ 0 ; Debug FIFO Bit 8 DBGFH_Bit9: equ 1 ; Debug FIFO Bit 9 DBGFH_Bit10: equ 2 ; Debug FIFO Bit 10 DBGFH_Bit11: equ 3 ; Debug FIFO Bit 11 DBGFH_Bit12: equ 4 ; Debug FIFO Bit 12 DBGFH_Bit13: equ 5 ; Debug FIFO Bit 13 DBGFH_Bit14: equ 6 ; Debug FIFO Bit 14 DBGFH_Bit15: equ 7 ; Debug FIFO Bit 15 ; bit position masks mDBGFH_Bit8: equ %00000001 mDBGFH_Bit9: equ %00000010 mDBGFH_Bit10: equ %00000100 mDBGFH_Bit11: equ %00001000 mDBGFH_Bit12: equ %00010000 mDBGFH_Bit13: equ %00100000 mDBGFH_Bit14: equ %01000000 mDBGFH_Bit15: equ %10000000 ;*** DBGFL - Debug FIFO Low Register; 0x00001815 *** DBGFL: equ $00001815 ;*** DBGFL - Debug FIFO Low Register; 0x00001815 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGFL_Bit0: equ 0 ; Debug FIFO Bit 0 DBGFL_Bit1: equ 1 ; Debug FIFO Bit 1 DBGFL_Bit2: equ 2 ; Debug FIFO Bit 2 DBGFL_Bit3: equ 3 ; Debug FIFO Bit 3 DBGFL_Bit4: equ 4 ; Debug FIFO Bit 4 DBGFL_Bit5: equ 5 ; Debug FIFO Bit 5 DBGFL_Bit6: equ 6 ; Debug FIFO Bit 6 DBGFL_Bit7: equ 7 ; Debug FIFO Bit 7 ; bit position masks mDBGFL_Bit0: equ %00000001 mDBGFL_Bit1: equ %00000010 mDBGFL_Bit2: equ %00000100 mDBGFL_Bit3: equ %00001000 mDBGFL_Bit4: equ %00010000 mDBGFL_Bit5: equ %00100000 mDBGFL_Bit6: equ %01000000 mDBGFL_Bit7: equ %10000000 ;*** DBGC - Debug Control Register; 0x00001816 *** DBGC: equ $00001816 ;*** DBGC - Debug Control Register; 0x00001816 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGC_RWBEN: equ 0 ; Enable R/W for Comparator B DBGC_RWB: equ 1 ; R/W Comparison Value for Comparator B DBGC_RWAEN: equ 2 ; Enable R/W for Comparator A DBGC_RWA: equ 3 ; R/W Comparison Value for Comparator A DBGC_BRKEN: equ 4 ; Break Enable DBGC_TAG: equ 5 ; Tag/Force Select DBGC_ARM: equ 6 ; Arm Control DBGC_DBGEN: equ 7 ; Debug Module Enable ; bit position masks mDBGC_RWBEN: equ %00000001 mDBGC_RWB: equ %00000010 mDBGC_RWAEN: equ %00000100 mDBGC_RWA: equ %00001000 mDBGC_BRKEN: equ %00010000 mDBGC_TAG: equ %00100000 mDBGC_ARM: equ %01000000 mDBGC_DBGEN: equ %10000000 ;*** DBGT - Debug Trigger Register; 0x00001817 *** DBGT: equ $00001817 ;*** DBGT - Debug Trigger Register; 0x00001817 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGT_TRG0: equ 0 ; Select Trigger Mode Bit 0 DBGT_TRG1: equ 1 ; Select Trigger Mode Bit 1 DBGT_TRG2: equ 2 ; Select Trigger Mode Bit 2 DBGT_TRG3: equ 3 ; Select Trigger Mode Bit 3 DBGT_BEGIN: equ 6 ; Begin/End Trigger Select DBGT_TRGSEL: equ 7 ; Trigger Type ; bit position masks mDBGT_TRG0: equ %00000001 mDBGT_TRG1: equ %00000010 mDBGT_TRG2: equ %00000100 mDBGT_TRG3: equ %00001000 mDBGT_BEGIN: equ %01000000 mDBGT_TRGSEL: equ %10000000 ;*** DBGS - Debug Status Register; 0x00001818 *** DBGS: equ $00001818 ;*** DBGS - Debug Status Register; 0x00001818 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DBGS_CNT0: equ 0 ; FIFO Valid Count Bit 0 DBGS_CNT1: equ 1 ; FIFO Valid Count Bit 1 DBGS_CNT2: equ 2 ; FIFO Valid Count Bit 2 DBGS_CNT3: equ 3 ; FIFO Valid Count Bit 3 DBGS_ARMF: equ 5 ; Arm Flag DBGS_BF: equ 6 ; Trigger Match B Flag DBGS_AF: equ 7 ; Trigger Match A Flag ; bit position masks mDBGS_CNT0: equ %00000001 mDBGS_CNT1: equ %00000010 mDBGS_CNT2: equ %00000100 mDBGS_CNT3: equ %00001000 mDBGS_ARMF: equ %00100000 mDBGS_BF: equ %01000000 mDBGS_AF: equ %10000000 ;*** FCDIV - FLASH Clock Divider Register; 0x00001820 *** FCDIV: equ $00001820 ;*** FCDIV - FLASH Clock Divider Register; 0x00001820 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCDIV_DIV0: equ 0 ; Divisor for FLASH Clock Divider Bit 0 FCDIV_DIV1: equ 1 ; Divisor for FLASH Clock Divider Bit 1 FCDIV_DIV2: equ 2 ; Divisor for FLASH Clock Divider Bit 2 FCDIV_DIV3: equ 3 ; Divisor for FLASH Clock Divider Bit 3 FCDIV_DIV4: equ 4 ; Divisor for FLASH Clock Divider Bit 4 FCDIV_DIV5: equ 5 ; Divisor for FLASH Clock Divider Bit 5 FCDIV_PRDIV8: equ 6 ; Prescale (Divide) FLASH Clock by 8 FCDIV_DIVLD: equ 7 ; Divisor Loaded Status Flag ; bit position masks mFCDIV_DIV0: equ %00000001 mFCDIV_DIV1: equ %00000010 mFCDIV_DIV2: equ %00000100 mFCDIV_DIV3: equ %00001000 mFCDIV_DIV4: equ %00010000 mFCDIV_DIV5: equ %00100000 mFCDIV_PRDIV8: equ %01000000 mFCDIV_DIVLD: equ %10000000 ;*** FOPT - FLASH Options Register; 0x00001821 *** FOPT: equ $00001821 ;*** FOPT - FLASH Options Register; 0x00001821 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FOPT_SEC00: equ 0 ; Security State Code Bit 0 FOPT_SEC01: equ 1 ; Security State Code Bit 1 FOPT_FNORED: equ 6 ; Vector Redirection Disable FOPT_KEYEN: equ 7 ; Backdoor Key Mechanism Enable ; bit position masks mFOPT_SEC00: equ %00000001 mFOPT_SEC01: equ %00000010 mFOPT_FNORED: equ %01000000 mFOPT_KEYEN: equ %10000000 ;*** FCNFG - FLASH Configuration Register; 0x00001823 *** FCNFG: equ $00001823 ;*** FCNFG - FLASH Configuration Register; 0x00001823 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCNFG_KEYACC: equ 5 ; Enable Writing of Access Key ; bit position masks mFCNFG_KEYACC: equ %00100000 ;*** FPROT - FLASH Protection Register; 0x00001824 *** FPROT: equ $00001824 ;*** FPROT - FLASH Protection Register; 0x00001824 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FPROT_FPS0: equ 3 ; FLASH Protect Size Select Bit 0 FPROT_FPS1: equ 4 ; FLASH Protect Size Select Bit 1 FPROT_FPS2: equ 5 ; FLASH Protect Size Select Bit 2 FPROT_FPDIS: equ 6 ; FLASH Protection Disable FPROT_FPOPEN: equ 7 ; Open Unprotected FLASH for Program/Erase ; bit position masks mFPROT_FPS0: equ %00001000 mFPROT_FPS1: equ %00010000 mFPROT_FPS2: equ %00100000 mFPROT_FPDIS: equ %01000000 mFPROT_FPOPEN: equ %10000000 ;*** FSTAT - FLASH Status Register; 0x00001825 *** FSTAT: equ $00001825 ;*** FSTAT - FLASH Status Register; 0x00001825 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FSTAT_FBLANK: equ 2 ; FLASH Verified as All Blank (erased) Flag FSTAT_FACCERR: equ 4 ; Access Error Flag FSTAT_FPVIOL: equ 5 ; Protection Violation Flag FSTAT_FCCF: equ 6 ; FLASH Command Complete Flag FSTAT_FCBEF: equ 7 ; FLASH Command Buffer Empty Flag ; bit position masks mFSTAT_FBLANK: equ %00000100 mFSTAT_FACCERR: equ %00010000 mFSTAT_FPVIOL: equ %00100000 mFSTAT_FCCF: equ %01000000 mFSTAT_FCBEF: equ %10000000 ;*** FCMD - FLASH Command Register; 0x00001826 *** FCMD: equ $00001826 ;*** FCMD - FLASH Command Register; 0x00001826 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCMD_FCMD0: equ 0 ; FLASH Command Bit 0 FCMD_FCMD1: equ 1 ; FLASH Command Bit 1 FCMD_FCMD2: equ 2 ; FLASH Command Bit 2 FCMD_FCMD3: equ 3 ; FLASH Command Bit 3 FCMD_FCMD4: equ 4 ; FLASH Command Bit 4 FCMD_FCMD5: equ 5 ; FLASH Command Bit 5 FCMD_FCMD6: equ 6 ; FLASH Command Bit 6 FCMD_FCMD7: equ 7 ; FLASH Command Bit 7 ; bit position masks mFCMD_FCMD0: equ %00000001 mFCMD_FCMD1: equ %00000010 mFCMD_FCMD2: equ %00000100 mFCMD_FCMD3: equ %00001000 mFCMD_FCMD4: equ %00010000 mFCMD_FCMD5: equ %00100000 mFCMD_FCMD6: equ %01000000 mFCMD_FCMD7: equ %10000000 ;*** NVBACKKEY0 - Backdoor Comparison Key 0; 0x0000FFB0 *** NVBACKKEY0: equ $0000FFB0 ;*** NVBACKKEY0 - Backdoor Comparison Key 0; 0x0000FFB0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY0_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY0_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY0_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY0_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY0_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY0_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY0_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY0_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY0_KEY0: equ %00000001 mNVBACKKEY0_KEY1: equ %00000010 mNVBACKKEY0_KEY2: equ %00000100 mNVBACKKEY0_KEY3: equ %00001000 mNVBACKKEY0_KEY4: equ %00010000 mNVBACKKEY0_KEY5: equ %00100000 mNVBACKKEY0_KEY6: equ %01000000 mNVBACKKEY0_KEY7: equ %10000000 ;*** NVBACKKEY1 - Backdoor Comparison Key 1; 0x0000FFB1 *** NVBACKKEY1: equ $0000FFB1 ;*** NVBACKKEY1 - Backdoor Comparison Key 1; 0x0000FFB1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY1_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY1_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY1_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY1_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY1_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY1_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY1_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY1_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY1_KEY0: equ %00000001 mNVBACKKEY1_KEY1: equ %00000010 mNVBACKKEY1_KEY2: equ %00000100 mNVBACKKEY1_KEY3: equ %00001000 mNVBACKKEY1_KEY4: equ %00010000 mNVBACKKEY1_KEY5: equ %00100000 mNVBACKKEY1_KEY6: equ %01000000 mNVBACKKEY1_KEY7: equ %10000000 ;*** NVBACKKEY2 - Backdoor Comparison Key 2; 0x0000FFB2 *** NVBACKKEY2: equ $0000FFB2 ;*** NVBACKKEY2 - Backdoor Comparison Key 2; 0x0000FFB2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY2_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY2_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY2_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY2_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY2_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY2_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY2_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY2_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY2_KEY0: equ %00000001 mNVBACKKEY2_KEY1: equ %00000010 mNVBACKKEY2_KEY2: equ %00000100 mNVBACKKEY2_KEY3: equ %00001000 mNVBACKKEY2_KEY4: equ %00010000 mNVBACKKEY2_KEY5: equ %00100000 mNVBACKKEY2_KEY6: equ %01000000 mNVBACKKEY2_KEY7: equ %10000000 ;*** NVBACKKEY3 - Backdoor Comparison Key 3; 0x0000FFB3 *** NVBACKKEY3: equ $0000FFB3 ;*** NVBACKKEY3 - Backdoor Comparison Key 3; 0x0000FFB3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY3_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY3_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY3_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY3_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY3_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY3_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY3_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY3_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY3_KEY0: equ %00000001 mNVBACKKEY3_KEY1: equ %00000010 mNVBACKKEY3_KEY2: equ %00000100 mNVBACKKEY3_KEY3: equ %00001000 mNVBACKKEY3_KEY4: equ %00010000 mNVBACKKEY3_KEY5: equ %00100000 mNVBACKKEY3_KEY6: equ %01000000 mNVBACKKEY3_KEY7: equ %10000000 ;*** NVBACKKEY4 - Backdoor Comparison Key 4; 0x0000FFB4 *** NVBACKKEY4: equ $0000FFB4 ;*** NVBACKKEY4 - Backdoor Comparison Key 4; 0x0000FFB4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY4_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY4_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY4_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY4_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY4_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY4_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY4_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY4_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY4_KEY0: equ %00000001 mNVBACKKEY4_KEY1: equ %00000010 mNVBACKKEY4_KEY2: equ %00000100 mNVBACKKEY4_KEY3: equ %00001000 mNVBACKKEY4_KEY4: equ %00010000 mNVBACKKEY4_KEY5: equ %00100000 mNVBACKKEY4_KEY6: equ %01000000 mNVBACKKEY4_KEY7: equ %10000000 ;*** NVBACKKEY5 - Backdoor Comparison Key 5; 0x0000FFB5 *** NVBACKKEY5: equ $0000FFB5 ;*** NVBACKKEY5 - Backdoor Comparison Key 5; 0x0000FFB5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY5_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY5_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY5_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY5_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY5_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY5_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY5_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY5_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY5_KEY0: equ %00000001 mNVBACKKEY5_KEY1: equ %00000010 mNVBACKKEY5_KEY2: equ %00000100 mNVBACKKEY5_KEY3: equ %00001000 mNVBACKKEY5_KEY4: equ %00010000 mNVBACKKEY5_KEY5: equ %00100000 mNVBACKKEY5_KEY6: equ %01000000 mNVBACKKEY5_KEY7: equ %10000000 ;*** NVBACKKEY6 - Backdoor Comparison Key 6; 0x0000FFB6 *** NVBACKKEY6: equ $0000FFB6 ;*** NVBACKKEY6 - Backdoor Comparison Key 6; 0x0000FFB6 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY6_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY6_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY6_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY6_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY6_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY6_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY6_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY6_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY6_KEY0: equ %00000001 mNVBACKKEY6_KEY1: equ %00000010 mNVBACKKEY6_KEY2: equ %00000100 mNVBACKKEY6_KEY3: equ %00001000 mNVBACKKEY6_KEY4: equ %00010000 mNVBACKKEY6_KEY5: equ %00100000 mNVBACKKEY6_KEY6: equ %01000000 mNVBACKKEY6_KEY7: equ %10000000 ;*** NVBACKKEY7 - Backdoor Comparison Key 7; 0x0000FFB7 *** NVBACKKEY7: equ $0000FFB7 ;*** NVBACKKEY7 - Backdoor Comparison Key 7; 0x0000FFB7 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY7_KEY0: equ 0 ; Backdoor Comparison Key bits, bit 0 NVBACKKEY7_KEY1: equ 1 ; Backdoor Comparison Key bits, bit 1 NVBACKKEY7_KEY2: equ 2 ; Backdoor Comparison Key bits, bit 2 NVBACKKEY7_KEY3: equ 3 ; Backdoor Comparison Key bits, bit 3 NVBACKKEY7_KEY4: equ 4 ; Backdoor Comparison Key bits, bit 4 NVBACKKEY7_KEY5: equ 5 ; Backdoor Comparison Key bits, bit 5 NVBACKKEY7_KEY6: equ 6 ; Backdoor Comparison Key bits, bit 6 NVBACKKEY7_KEY7: equ 7 ; Backdoor Comparison Key bits, bit 7 ; bit position masks mNVBACKKEY7_KEY0: equ %00000001 mNVBACKKEY7_KEY1: equ %00000010 mNVBACKKEY7_KEY2: equ %00000100 mNVBACKKEY7_KEY3: equ %00001000 mNVBACKKEY7_KEY4: equ %00010000 mNVBACKKEY7_KEY5: equ %00100000 mNVBACKKEY7_KEY6: equ %01000000 mNVBACKKEY7_KEY7: equ %10000000 ;*** NVPROT - Nonvolatile FLASH Protection Register; 0x0000FFBD *** NVPROT: equ $0000FFBD ;*** NVPROT - Nonvolatile FLASH Protection Register; 0x0000FFBD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVPROT_FPS0: equ 3 ; FLASH Protect Size Select Bit 0 NVPROT_FPS1: equ 4 ; FLASH Protect Size Select Bit 1 NVPROT_FPS2: equ 5 ; FLASH Protect Size Select Bit 2 NVPROT_FPDIS: equ 6 ; FLASH Protection Disable NVPROT_FPOPEN: equ 7 ; Open Unprotected FLASH for Program/Erase ; bit position masks mNVPROT_FPS0: equ %00001000 mNVPROT_FPS1: equ %00010000 mNVPROT_FPS2: equ %00100000 mNVPROT_FPDIS: equ %01000000 mNVPROT_FPOPEN: equ %10000000 ;*** NVOPT - Nonvolatile FLASH Options Register; 0x0000FFBF *** NVOPT: equ $0000FFBF ;*** NVOPT - Nonvolatile FLASH Options Register; 0x0000FFBF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVOPT_SEC00: equ 0 ; Security State Code Bit 0 NVOPT_SEC01: equ 1 ; Security State Code Bit 1 NVOPT_FNORED: equ 6 ; Vector Redirection Disable NVOPT_KEYEN: equ 7 ; Backdoor Key Mechanism Enable ; bit position masks mNVOPT_SEC00: equ %00000001 mNVOPT_SEC01: equ %00000010 mNVOPT_FNORED: equ %01000000 mNVOPT_KEYEN: equ %10000000 ; Flash commands mBlank: equ $05 mByteProg: equ $20 mBurstProg: equ $25 mMassErase: equ $41 mPageErase: equ $40 ;*********************************************** ;** D E P R E C I A T E D S Y M B O L S ** ;*********************************************** IFNDEF __GENERATE_APPLICATION__ ; not supported for absolute assembler XREF This_symb_has_been_depreciated ENDIF ; --------------------------------------------------------------------------- ; The following symbols were removed, because they were invalid or irrelevant ; --------------------------------------------------------------------------- ; ; Follows changes from the database 2.87.167 version IFNDEF __GENERATE_APPLICATION__ mIIC1A_ADDR0 EQU This_symb_has_been_depreciated IIC1A_ADDR0 EQU This_symb_has_been_depreciated ENDIF ; ; Follows changes from the database 2.87.106 version ATDC EQU ATD1C ATDC_PRS0 EQU ATD1C_PRS0 mATDC_PRS0 EQU mATD1C_PRS0 ATDC_PRS1 EQU ATD1C_PRS1 mATDC_PRS1 EQU mATD1C_PRS1 ATDC_PRS2 EQU ATD1C_PRS2 mATDC_PRS2 EQU mATD1C_PRS2 ATDC_PRS3 EQU ATD1C_PRS3 mATDC_PRS3 EQU mATD1C_PRS3 ATDC_SGN EQU ATD1C_SGN mATDC_SGN EQU mATD1C_SGN ATDC_RES8 EQU ATD1C_RES8 mATDC_RES8 EQU mATD1C_RES8 ATDC_DJM EQU ATD1C_DJM mATDC_DJM EQU mATD1C_DJM ATDC_ATDPU EQU ATD1C_ATDPU mATDC_ATDPU EQU mATD1C_ATDPU ATDSC EQU ATD1SC ATDSC_ATDCH0 EQU ATD1SC_ATDCH0 mATDSC_ATDCH0 EQU mATD1SC_ATDCH0 ATDSC_ATDCH1 EQU ATD1SC_ATDCH1 mATDSC_ATDCH1 EQU mATD1SC_ATDCH1 ATDSC_ATDCH2 EQU ATD1SC_ATDCH2 mATDSC_ATDCH2 EQU mATD1SC_ATDCH2 ATDSC_ATDCH3 EQU ATD1SC_ATDCH3 mATDSC_ATDCH3 EQU mATD1SC_ATDCH3 ATDSC_ATDCH4 EQU ATD1SC_ATDCH4 mATDSC_ATDCH4 EQU mATD1SC_ATDCH4 ATDSC_ATDCO EQU ATD1SC_ATDCO mATDSC_ATDCO EQU mATD1SC_ATDCO ATDSC_ATDIE EQU ATD1SC_ATDIE mATDSC_ATDIE EQU mATD1SC_ATDIE ATDSC_CCF EQU ATD1SC_CCF mATDSC_CCF EQU mATD1SC_CCF ATDR EQU ATD1R ATDRH EQU ATD1RH ATDRH_BIT8 EQU ATD1RH_BIT8 mATDRH_BIT8 EQU mATD1RH_BIT8 ATDRH_BIT9 EQU ATD1RH_BIT9 mATDRH_BIT9 EQU mATD1RH_BIT9 ATDRL EQU ATD1RL ATDRL_BIT0 EQU ATD1RL_BIT0 mATDRL_BIT0 EQU mATD1RL_BIT0 ATDRL_BIT1 EQU ATD1RL_BIT1 mATDRL_BIT1 EQU mATD1RL_BIT1 ATDRL_BIT2 EQU ATD1RL_BIT2 mATDRL_BIT2 EQU mATD1RL_BIT2 ATDRL_BIT3 EQU ATD1RL_BIT3 mATDRL_BIT3 EQU mATD1RL_BIT3 ATDRL_BIT4 EQU ATD1RL_BIT4 mATDRL_BIT4 EQU mATD1RL_BIT4 ATDRL_BIT5 EQU ATD1RL_BIT5 mATDRL_BIT5 EQU mATD1RL_BIT5 ATDRL_BIT6 EQU ATD1RL_BIT6 mATDRL_BIT6 EQU mATD1RL_BIT6 ATDRL_BIT7 EQU ATD1RL_BIT7 mATDRL_BIT7 EQU mATD1RL_BIT7 ATDPE EQU ATD1PE ATDPE_ATDPE0 EQU ATD1PE_ATDPE0 mATDPE_ATDPE0 EQU mATD1PE_ATDPE0 ATDPE_ATDPE1 EQU ATD1PE_ATDPE1 mATDPE_ATDPE1 EQU mATD1PE_ATDPE1 ATDPE_ATDPE2 EQU ATD1PE_ATDPE2 mATDPE_ATDPE2 EQU mATD1PE_ATDPE2 ATDPE_ATDPE3 EQU ATD1PE_ATDPE3 mATDPE_ATDPE3 EQU mATD1PE_ATDPE3 ATDPE_ATDPE4 EQU ATD1PE_ATDPE4 mATDPE_ATDPE4 EQU mATD1PE_ATDPE4 ATDPE_ATDPE5 EQU ATD1PE_ATDPE5 mATDPE_ATDPE5 EQU mATD1PE_ATDPE5 ATDPE_ATDPE6 EQU ATD1PE_ATDPE6 mATDPE_ATDPE6 EQU mATD1PE_ATDPE6 ATDPE_ATDPE7 EQU ATD1PE_ATDPE7 mATDPE_ATDPE7 EQU mATD1PE_ATDPE7 IICA EQU IIC1A IICA_ADDR1 EQU IIC1A_ADDR1 mIICA_ADDR1 EQU mIIC1A_ADDR1 IICA_ADDR2 EQU IIC1A_ADDR2 mIICA_ADDR2 EQU mIIC1A_ADDR2 IICA_ADDR3 EQU IIC1A_ADDR3 mIICA_ADDR3 EQU mIIC1A_ADDR3 IICA_ADDR4 EQU IIC1A_ADDR4 mIICA_ADDR4 EQU mIIC1A_ADDR4 IICA_ADDR5 EQU IIC1A_ADDR5 mIICA_ADDR5 EQU mIIC1A_ADDR5 IICA_ADDR6 EQU IIC1A_ADDR6 mIICA_ADDR6 EQU mIIC1A_ADDR6 IICA_ADDR7 EQU IIC1A_ADDR7 mIICA_ADDR7 EQU mIIC1A_ADDR7 IICF EQU IIC1F IICF_ICR0 EQU IIC1F_ICR0 mIICF_ICR0 EQU mIIC1F_ICR0 IICF_ICR1 EQU IIC1F_ICR1 mIICF_ICR1 EQU mIIC1F_ICR1 IICF_ICR2 EQU IIC1F_ICR2 mIICF_ICR2 EQU mIIC1F_ICR2 IICF_ICR3 EQU IIC1F_ICR3 mIICF_ICR3 EQU mIIC1F_ICR3 IICF_ICR4 EQU IIC1F_ICR4 mIICF_ICR4 EQU mIIC1F_ICR4 IICF_ICR5 EQU IIC1F_ICR5 mIICF_ICR5 EQU mIIC1F_ICR5 IICF_MULT0 EQU IIC1F_MULT0 mIICF_MULT0 EQU mIIC1F_MULT0 IICF_MULT1 EQU IIC1F_MULT1 mIICF_MULT1 EQU mIIC1F_MULT1 IICC EQU IIC1C IICC_RSTA EQU IIC1C_RSTA mIICC_RSTA EQU mIIC1C_RSTA IICC_TXAK EQU IIC1C_TXAK mIICC_TXAK EQU mIIC1C_TXAK IICC_TX EQU IIC1C_TX mIICC_TX EQU mIIC1C_TX IICC_MST EQU IIC1C_MST mIICC_MST EQU mIIC1C_MST IICC_IICIE EQU IIC1C_IICIE mIICC_IICIE EQU mIIC1C_IICIE IICC_IICEN EQU IIC1C_IICEN mIICC_IICEN EQU mIIC1C_IICEN IICS EQU IIC1S IICS_RXAK EQU IIC1S_RXAK mIICS_RXAK EQU mIIC1S_RXAK IICS_IICIF EQU IIC1S_IICIF mIICS_IICIF EQU mIIC1S_IICIF IICS_SRW EQU IIC1S_SRW mIICS_SRW EQU mIIC1S_SRW IICS_ARBL EQU IIC1S_ARBL mIICS_ARBL EQU mIIC1S_ARBL IICS_BUSY EQU IIC1S_BUSY mIICS_BUSY EQU mIIC1S_BUSY IICS_IAAS EQU IIC1S_IAAS mIICS_IAAS EQU mIIC1S_IAAS IICS_TCF EQU IIC1S_TCF mIICS_TCF EQU mIIC1S_TCF IICD EQU IIC1D IICD_DATA0 EQU IIC1D_DATA0 mIICD_DATA0 EQU mIIC1D_DATA0 IICD_DATA1 EQU IIC1D_DATA1 mIICD_DATA1 EQU mIIC1D_DATA1 IICD_DATA2 EQU IIC1D_DATA2 mIICD_DATA2 EQU mIIC1D_DATA2 IICD_DATA3 EQU IIC1D_DATA3 mIICD_DATA3 EQU mIIC1D_DATA3 IICD_DATA4 EQU IIC1D_DATA4 mIICD_DATA4 EQU mIIC1D_DATA4 IICD_DATA5 EQU IIC1D_DATA5 mIICD_DATA5 EQU mIIC1D_DATA5 IICD_DATA6 EQU IIC1D_DATA6 mIICD_DATA6 EQU mIIC1D_DATA6 IICD_DATA7 EQU IIC1D_DATA7 mIICD_DATA7 EQU mIIC1D_DATA7 SPIBR EQU SPI1BR SPIBR_SPR0 EQU SPI1BR_SPR0 mSPIBR_SPR0 EQU mSPI1BR_SPR0 SPIBR_SPR1 EQU SPI1BR_SPR1 mSPIBR_SPR1 EQU mSPI1BR_SPR1 SPIBR_SPR2 EQU SPI1BR_SPR2 mSPIBR_SPR2 EQU mSPI1BR_SPR2 SPIBR_SPPR0 EQU SPI1BR_SPPR0 mSPIBR_SPPR0 EQU mSPI1BR_SPPR0 SPIBR_SPPR1 EQU SPI1BR_SPPR1 mSPIBR_SPPR1 EQU mSPI1BR_SPPR1 SPIBR_SPPR2 EQU SPI1BR_SPPR2 mSPIBR_SPPR2 EQU mSPI1BR_SPPR2 SPIS EQU SPI1S SPIS_MODF EQU SPI1S_MODF mSPIS_MODF EQU mSPI1S_MODF SPIS_SPTEF EQU SPI1S_SPTEF mSPIS_SPTEF EQU mSPI1S_SPTEF SPIS_SPRF EQU SPI1S_SPRF mSPIS_SPRF EQU mSPI1S_SPRF SPID EQU SPI1D Viic EQU Viic1 Vatd EQU Vatd1 Vkeyboard EQU Vkeyboard1 Vspi EQU Vspi1 KBISC EQU KBI1SC KBISC_KBIMOD EQU KBI1SC_KBIMOD mKBISC_KBIMOD EQU mKBI1SC_KBIMOD KBISC_KBIE EQU KBI1SC_KBIE mKBISC_KBIE EQU mKBI1SC_KBIE KBISC_KBACK EQU KBI1SC_KBACK mKBISC_KBACK EQU mKBI1SC_KBACK KBISC_KBF EQU KBI1SC_KBF mKBISC_KBF EQU mKBI1SC_KBF KBISC_KBEDG4 EQU KBI1SC_KBEDG4 mKBISC_KBEDG4 EQU mKBI1SC_KBEDG4 KBISC_KBEDG5 EQU KBI1SC_KBEDG5 mKBISC_KBEDG5 EQU mKBI1SC_KBEDG5 KBISC_KBEDG6 EQU KBI1SC_KBEDG6 mKBISC_KBEDG6 EQU mKBI1SC_KBEDG6 KBISC_KBEDG7 EQU KBI1SC_KBEDG7 mKBISC_KBEDG7 EQU mKBI1SC_KBEDG7 KBIPE EQU KBI1PE KBIPE_KBIPE0 EQU KBI1PE_KBIPE0 mKBIPE_KBIPE0 EQU mKBI1PE_KBIPE0 KBIPE_KBIPE1 EQU KBI1PE_KBIPE1 mKBIPE_KBIPE1 EQU mKBI1PE_KBIPE1 KBIPE_KBIPE2 EQU KBI1PE_KBIPE2 mKBIPE_KBIPE2 EQU mKBI1PE_KBIPE2 KBIPE_KBIPE3 EQU KBI1PE_KBIPE3 mKBIPE_KBIPE3 EQU mKBI1PE_KBIPE3 KBIPE_KBIPE4 EQU KBI1PE_KBIPE4 mKBIPE_KBIPE4 EQU mKBI1PE_KBIPE4 KBIPE_KBIPE5 EQU KBI1PE_KBIPE5 mKBIPE_KBIPE5 EQU mKBI1PE_KBIPE5 KBIPE_KBIPE6 EQU KBI1PE_KBIPE6 mKBIPE_KBIPE6 EQU mKBI1PE_KBIPE6 KBIPE_KBIPE7 EQU KBI1PE_KBIPE7 mKBIPE_KBIPE7 EQU mKBI1PE_KBIPE7 ; ; Follows changes from the database 2.87.109 version ICGFLTU_FILT8 EQU ICGFLTU_FLT8 mICGFLTU_FILT8 EQU mICGFLTU_FLT8 ICGFLTU_FILT9 EQU ICGFLTU_FLT9 mICGFLTU_FILT9 EQU mICGFLTU_FLT9 ICGFLTU_FILT10 EQU ICGFLTU_FLT10 mICGFLTU_FILT10 EQU mICGFLTU_FLT10 ICGFLTU_FILT11 EQU ICGFLTU_FLT11 mICGFLTU_FILT11 EQU mICGFLTU_FLT11 ICGFLTL_FILT0 EQU ICGFLTL_FLT0 mICGFLTL_FILT0 EQU mICGFLTL_FLT0 ICGFLTL_FILT1 EQU ICGFLTL_FLT1 mICGFLTL_FILT1 EQU mICGFLTL_FLT1 ICGFLTL_FILT2 EQU ICGFLTL_FLT2 mICGFLTL_FILT2 EQU mICGFLTL_FLT2 ICGFLTL_FILT3 EQU ICGFLTL_FLT3 mICGFLTL_FILT3 EQU mICGFLTL_FLT3 ICGFLTL_FILT4 EQU ICGFLTL_FLT4 mICGFLTL_FILT4 EQU mICGFLTL_FLT4 ICGFLTL_FILT5 EQU ICGFLTL_FLT5 mICGFLTL_FILT5 EQU mICGFLTL_FLT5 ICGFLTL_FILT6 EQU ICGFLTL_FLT6 mICGFLTL_FILT6 EQU mICGFLTL_FLT6 ICGFLTL_FILT7 EQU ICGFLTL_FLT7 mICGFLTL_FILT7 EQU mICGFLTL_FLT7 ; ; Follows changes from the database 2.87.113 version SPIC1 EQU SPI1C1 SPIC1_LSBFE EQU SPI1C1_LSBFE mSPIC1_LSBFE EQU mSPI1C1_LSBFE SPIC1_SSOE EQU SPI1C1_SSOE mSPIC1_SSOE EQU mSPI1C1_SSOE SPIC1_CPHA EQU SPI1C1_CPHA mSPIC1_CPHA EQU mSPI1C1_CPHA SPIC1_CPOL EQU SPI1C1_CPOL mSPIC1_CPOL EQU mSPI1C1_CPOL SPIC1_MSTR EQU SPI1C1_MSTR mSPIC1_MSTR EQU mSPI1C1_MSTR SPIC1_SPTIE EQU SPI1C1_SPTIE mSPIC1_SPTIE EQU mSPI1C1_SPTIE SPIC1_SPE EQU SPI1C1_SPE mSPIC1_SPE EQU mSPI1C1_SPE SPIC1_SPIE EQU SPI1C1_SPIE mSPIC1_SPIE EQU mSPI1C1_SPIE SPIC2 EQU SPI1C2 SPIC2_SPC0 EQU SPI1C2_SPC0 mSPIC2_SPC0 EQU mSPI1C2_SPC0 SPIC2_SPISWAI EQU SPI1C2_SPISWAI mSPIC2_SPISWAI EQU mSPI1C2_SPISWAI SPIC2_BIDIROE EQU SPI1C2_BIDIROE mSPIC2_BIDIROE EQU mSPI1C2_BIDIROE SPIC2_MODFEN EQU SPI1C2_MODFEN mSPIC2_MODFEN EQU mSPI1C2_MODFEN ; EOF