SC9S08IA4_8
 
General Info



CPU beans



CPU icon
Component icon
CPU SC9S08IA4_8
Freescale HCS08 family : SC9S08IA4 in 8 pin SOIC package
Device Initialization
(Description of the CPU component parameters.)
  • Clock settings - MCU clock settings.
    • Internal clock - If this property is enabled, an internal clock is allowed for MCU timing.
      • Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 31.25 kHz. It is responsibility of the user to provide correct trim value (see 'Initialize trim value' property), which will adjust the frequency of the internal oscillator to the required value.
      • Initialize trim value - This property enables to generate code for initialization of the trim register (ICGTR) by the value from a non-volatile memory location.
        The following items are available only if the group is enabled (the value is "yes"):
    • Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source.
    • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock.
      If all dividers/multiplier are set manually by the user (none of them is set to 'Auto select value'), the bus frequency is calculated by Processor Expert and cannot be modified.
    • Fixed freq. clock clk src. - Fixed frequency clock source (for information only). This clock source is selected by the HW. It is set to Bus Clock when Bus clock is two times greater the divided FLL reference clock otherwise it is set to divided FLL reference clock.
    • Fixed frequency clock - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock is either Bus clock or Divided FLL ref. clock divided by two.
    • FLL mode - FLL mode (Engaged/Bypassed/Bypassed Low Power).
      There are 3 modes:
      • Engaged - In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal of external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
      • Bypassed - In FLL bypassed mode, the bus clock is derived from the internal or external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See Engaged mode for items available in this mode.
      • Bypassed Low Power - In FLL bypassed low power mode, the bus clock is derived from the internal or external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. See Engaged mode for items available in this mode.
    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - This property enables the STOP instruction.
        There are 2 modes:
        • yes - The following items are displayed in this mode:
          • Power down control - This property sets power down control bits that determine which power-down mode will be invoked when the STOP instruction is executed.

            There are 2 options:
            • STOP2 - Partial power down mode: Partial power down mode
            • STOP3 - Standby mode: Standby mode

          • Internal clock in stop mode - This property controls whether or not the internal reference clock remains enabled when the ICS enters stop mode.
        • no - There are no items in this mode.
  • Initialization interrupt priority - Initialization interrupt priority value.
  • Internal resource mapping - Internal resource mapping setting
    • Interrupt vector table - This group contains settings for placement of interrupt vector table.
      • Address - This property defines address of definition of interrupt vector table. For a bootloader support the definition of the interrupt vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of interrupt vector to a valid source. The setting of the interrupt vector table address doesn't affect any HW resources.
        When the Vector redirection property is available and is enabled the user is offered automatic adjustment of the address of the interrupt vector table according to the current setting of FLASH memory protection (see property group Internal peripherals/FLASH).
      • Size - Size of the exception vector table. (For information only)
    • Reset vector - This group contains settings for placement of reset vector.
      • Address - This property defines address of definition of reset vector. For a bootloader support the definition of the reset vector can be placed on a user defined address. In this case the user has to ensure correct redirection of the reset vector to a valid source. The setting of the reset vector address doesn't affect any HW resources.
      • Size - Size of the reset vector. (For information only)
  • Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
    • ADC - Settings of the ADC module
      • Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. This item modifies the BGBE bit in the SPMSC1 register.
    • BDM pin support - Enables/disables the background debug mode pin support.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • BDM pin - Background Debug Mode pin name (for information only)
    • FLASH - The FLASH memory options.
      • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
        There are 2 modes:
        • Enabled - The following items are displayed in this mode:
          • SEC01:SEC00 bits value - This property specifies value for enabled security state (useful if it must be set exactly for debugger).
            This item modifies SEC00:SEC01 bits in the NVOPT register.
          • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
            The following items are available only if the group is enabled (the value is "Enabled"):
        • Disabled - There are no items in this mode.
      • Protection - Protection of the selected memory block. If a block of the FLASH memory is protected a bootloader cannot erase the protected block of memory.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Boundary address - This boundary defines the last address within Flash memory that is unprotected. The rest of the Flash memory is protected up to address $FFFF. The size of the protected area shall be a multiple of 512 bytes block. The inserted value is adjusted by Processor Expert to meet this requirement.
      • Vector redirection - If the protection is enabled the vector interrupts can be redirected to the unprotected area by setting of this vector redirection property.
    • I/O module - I/O ports' settings
      • PORT A - Slew rate control for all pins of PORT A
    • LVD module - Low Voltage Detect module settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • LVD operation - This property defines operation performed upon detection of a low voltage condition.
        There are 3 modes:
        • Reset - Reset is generated upon detection of a low voltage condition. There are no items in this mode.
        • Interrupt - Interrupt is generated when LVI detector state is changed. The following items are displayed in this mode:
          • Interrupt name - Interrupt vector that is invoked from the Low Voltage Detect interrupt (for information only).
          • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
            The user code of the routine should handle all respective interrupt flags correctly.
        • Polling mode - No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output. There are no items in this mode.
      • Enable in stop mode - Enables the low-voltage detection during stop mode.
      • Low-voltage detect voltage - Low-voltage detect trip point selection (low or high).
      • Low-voltage warning voltage - Low-voltage warning trip point selection (low or high).
    • Reset pin support - Reset pin support
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Reset pin - Reset pin name (for information only)
  • CPU interrupts - Internal peripherals setting
    • Reset vector - Reset vector settings.
      • Interrupt - Interrupt associated with the reset
      • ISR name - Name of the reset vector - routine, that initializes CPU after reset.
    • SWI - This property enables/disables generation of SWI interrupt service routine.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Software Interrupt (for information only)
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.

PROCESSOR EXPERT is trademark of Freescale Semiconductor, Inc.
Copyright 1997 - 2010 Freescale Semiconductor, Inc.