MCF51MM256_100
 
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CPU Component MCF51MM256_100
Freescale ColdFireV1 family : MCF51MM256 in 100 pin LQFP package
Component Level: High
Category: CPU-Freescale-ColdFireV1-JE/MM
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • CPU type - CPU variant
  • Clock settings - MCU clock settings
    • Internal clock - Internal clock settings.
      • Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 32.7 kHz. It is responsibility of the user to provide correct trim value (see ' Initialize trim value value' property), which will adjust the frequency of the internal oscillator to the required value.
      • Internal ref. clock for peripherals - This property enables the internal reference clock for use as MCGIRCLK for peripherals.
      • Initialize trim value - This property enables to generate code for initialization of the trim register (MCGTRM, MCGSC) by the value from a non-volatile memory location.
        The following items are available only if the group is enabled (the value is "yes"):
    • External Clock XOSC1 - Settings of the external clock source 1. This clock can be used as the reference clock to the MCG or the TOD.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Clock source - Possible external clock sources (external crystal or external clock).
        There are 2 modes:
        • External crystal - The following items are displayed in this mode:
          • Clock input pin - Clock input properties.
            • Pin name - XOSC1 Clock input pin name (for information only).
            • Pin signal - XOSC1 Clock input signal name.
          • Clock output pin - Clock output properties.
            • Pin name - XOSC1 Clock output pin name (for information only).
            • Pin signal - XOSC1 Clock output signal name.
          • Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 32-38.4kHz or 1-16MHz and the external clock should be in the range of 0.0001-40MHz but this limits may be further restricted by other MCG module settings (Oscillator operating mode, FLL/PLL mode).
          • Clock range - This property selects the frequency range for the external oscillator or external clock source.

            There are 2 options:
            • High frequency: selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source)
            • Low frequency: selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source)

            The property is set automatically by Processor expert if clock frequency is in the vendor recommended range otherwise can by changed manually.
          • Oscillator operating mode - The operating mode of the oscillator module. It provides the high gain for improving of noise immunity or the low power consumption This property also influences allowed frequency range of external crystal.

            There are 2 options:
            • High gain: This mode provides a higher amplitude output for the improved noise immunity.
            • Low power: This mode provides the lower power consumption.

          • External ref. clock for peripherals - This property enables the external reference clock provided by XOSC1 for use as MCGERCLK for peripherals.
        • External oscillator - The following items are displayed in this mode:
          • Clock input pin - Clock input properties.
            • The content is the same as in previous modes.
          • Clock frequency [MHz] - See previous modes for more details
          • Clock range - See previous modes for more details
          • External ref. clock for peripherals - See previous modes for more details
    • External Clock XOSC2 - Settings of the external clock source 2. This clock can be used as the reference clock to the MCG.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Clock source - Possible external clock sources (external crystal or external clock).
        There are 2 modes:
        • External crystal - The following items are displayed in this mode:
          • Clock input pin - Clock input properties.
            • Pin name - XOSC1 Clock input pin name (for information only).
            • Pin signal - XOSC1 Clock input signal name.
          • Clock output pin - Clock output properties.
            • Pin name - XOSC1 Clock output pin name (for information only).
            • Pin signal - XOSC1 Clock output signal name.
          • Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 32-38.4kHz or 1-16MHz and the external clock should be in the range of 0.0001-40MHz but this limits may be further restricted by other MCG module settings (Oscillator operating mode, FLL/PLL mode).
          • Clock range - This property selects the frequency range for the external oscillator or external clock source.

            There are 2 options:
            • High frequency: selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source)
            • Low frequency: selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source)

            The property is set automatically by Processor expert if clock frequency is in the vendor recommended range otherwise can by changed manually.
          • Oscillator operating mode - The operating mode of the oscillator module. It provides the high gain for improving of noise immunity or the low power consumption This property also influences allowed frequency range of external crystal.

            There are 2 options:
            • High gain: This mode provides a higher amplitude output for the improved noise immunity.
            • Low power: This mode provides the lower power consumption.

        • External oscillator - The following items are displayed in this mode:
    • External clock for MCG - This property selects external clock source for MCG module. The value is set by Processor Expert unless both XOSC1 and XOSC2 are enabled.

      There are 2 options:
      • XOSC1: XOSC1 is used as an external clock source
      • XOSC2: XOSC2 is used as an external clock source

    • External ref. clock for peripherals - This property enables the external reference clock for use as MCGERCLK for peripherals. This property has an effect only when External Clock is used as a reference clock for MCG.
    • External clock - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
      • Clock source - Possible external clock sources (external crystal or external clock).
        There are 2 modes:
        • External crystal - The following items are displayed in this mode:
          • Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 32-38.4kHz or 1-16MHz and the external clock should be in the range of 0.0001-40MHz but this limits may be further restricted by other MCG module settings (Oscillator operating mode, FLL/PLL mode).
          • Clock range - This property selects the frequency range for the external oscillator or external clock source.

            There are 2 options:
            • High frequency: selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source)
            • Low frequency: selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source)

            The property is set automatically by Processor expert if clock frequency is in the vendor recommended range otherwise can by changed manually.
          • Oscillator operating mode - The operating mode of the oscillator module. It provides the high gain for improving of noise immunity or the low power consumption This property also influences allowed frequency range of external crystal.

            There are 2 options:
            • High gain: This mode provides a higher amplitude output for the improved noise immunity.
            • Low power: This mode provides the lower power consumption.

          • External ref. clock for peripherals - This property enables the external reference clock for use as MCGERCLK for peripherals.
        • External oscillator - The following items are displayed in this mode:
          • Clock frequency [MHz] - See previous modes for more details
          • Clock range - See previous modes for more details
          • External ref. clock for peripherals - See previous modes for more details
    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - This property enables the STOP instruction.
        The following items are available only if the group is enabled (the value is "yes"):
      • Force exit on interrupt - This property enables to force exit from STOP or WAIT mode on interrupt. When enabled, the combinational wake-up signal may be asserted to the clock generation logic when an interrupt occurs.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Wakeup interrupt level - Defines the interrupt mask level during wait or stop mode. Once an interrupt request of a level higher than selected value is asserted, the wake-up signal to the clock generation logic is asserted.

          There are 7 options:
          • 0: All interrupts will assert wake-up.
          • 1: Interrupts with level 2 and higher will assert wake-up.
          • 2: Interrupts with level 3 and higher will assert wake-up.
          • 3: Interrupts with level 4 and higher will assert wake-up.
          • 4: Interrupts with level 5 and higher will assert wake-up.
          • 5: Interrupts with level 6 and higher will assert wake-up.
          • 6: Only interrupts with level 7 (non-maskable interrupts) will assert wake-up.

  • Internal resource mapping - Internal resource mapping setting
    • Exception vector table - This group contains settings for placement of exception vector table.
      • Fetch vectors from RAM - When set to 'yes' the cpu fetches exception vectors from RAM (base address of the vector table is 0x80_0000). When set to 'no' exception vectors are fetched from flash (base address of the vector table is 0x00_0000).
      • Address - This property defines address of definition of exception vectors table - the default address is 0x00_0000. For a bootloader support the definition of the exception vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of exception vectors to a valid source. The setting of the exception vector table address doesn't affect any HW resources.
      • Size - Size of the exception vector table. (For information only)
  • Initialization priority - Initialization interrupt priority value of the CPU bean.
  • Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
    • ADC - Settings of the ADC module
      • Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference. It can be used by an ADC module on one of its internal channels or by an analog comparator module (if available). This item modifies the BGBE bit in the SPMSC1 register.
    • BDM pin support - Enables/disables the background debug mode pin support. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • BDM pin - Background Debug Mode pin name (for information only)
      • BDM pin signal - Signal name of the Background Debug Mode pin
    • Clock output - This property controls operation of the clock output (CLKOUT) pin. The various clock sources must be enabled/disabled via the appropriate controls elsewhere in the device.
      There are 8 modes:
    • Bootloader - The FLASH memory options.
      • Flash Block 1 - Flash block 1 settings
        • Checksum - This property controls condition to enter bootloader code.

          There are 3 options:
          • Calculate: Upon reset and BLMS=1 the flash checksum is calculated and verified against a stored value. If the checksum does not match the cpu jumps to the bootloadet.
          • Bypass, jump to user code: No checksum is calculated, the cpu jumps directly to the user code.
          • Bypass, jump to bootloader: No checksum is calculated, the cpu jumps directly to the bootloader code.

      • Flash Block 2 - Flash block 2 settings
        • Checksum - This property controls condition to enter bootloader code.

          There are 3 options:
          • Calculate: Upon reset and BLMS=1 the flash checksum is calculated and verified against a stored value. If the checksum does not match the cpu jumps to the bootloadet.
          • Bypass, jump to user code: No checksum is calculated, the cpu jumps directly to the user code.
          • Bypass, jump to bootloader: No checksum is calculated, the cpu jumps directly to the bootloader code.

    • CPU configuration - Configuration of specific CPu core functionality.
      • Interrupt mask - When enabled, the processor raises the interrupt level mask (SR[I]) to 7 during every interrupt. This disables all level 1-6 interrupt requests but allows recognition of the edge-sensitive level 7 requests.
        When disabled, the processor sets SR[I] to the level of the interrupt being serviced.
        This capability is provided to assist when porting S08 application code to ColdFire.
      • Interrupt acknowledge (IACK) - When enabled, forces the processor to generate an IACK read cycle from the interrupt controller during exception processing to retrieve the vector number of the interrupt request being acknowledged. The processor’s execution time for an interrupt exception is slightly improved when this property is disabled. This item modifies bit IAE of the CPUCR register.
      • Buffered peripheral bus write - This property controls buffered peripheral bus write access.
        When enabled, peripheral bus writes are buffered and the bus cycle is terminated immediately and does not wait for the peripheral bus termination status. Any peripheral bus error status is lost.
        When disabled, peripheral bus writes are not buffered and bus cycle is not terminated until a registered version of the peripheral bus termination is received.
        This item modifies the BWD bit of CPUCR register.
      • Flash speculation - This property controls certain performance-enhancing features related to address speculation in the FSD flash memory controller. When enabled, the flash controller tries to speculate on read accesses to improve processor performance by minimizing the exposed flash memory access time. Recall the basic flash access time is two processor cycles.
        This item modifies the FSD bit of the CPUCR register.
    • FLASH - The FLASH memory options.
      • Flash Block 1 - Flash block 1 settings
        • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
          There are 2 modes:
          • Enabled - The following items are displayed in this mode:
            • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
              The following items are available only if the group is enabled (the value is "Enabled"):
          • Disabled - There are no items in this mode.
        • Protection - Protection of the selected FLASH memory block. Trying to alter data in any protected area in the flash memory will result in a flash protection violation error.
          There are 3 modes:
          • Disabled - The protection of the FLASH memory is disabled. There are no items in this mode.
          • User defined - The size of the protected area is defined by user. The following items are displayed in this mode:
            • Protected area [kB] - Size of protected are in kB. The inserted value will be automatically adjusted to the nearest allowed value. The address range of protected flash is shown in the third column of this property.
          • Entire FLASH - The entire FLASH memory is protected. There are no items in this mode.
      • Flash Block 2 - Flash block 2 settings
        • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
          There are 2 modes:
          • Enabled - The following items are displayed in this mode:
            • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
              The following items are available only if the group is enabled (the value is "Enabled"):
          • Disabled - There are no items in this mode.
        • Protection - Protection of the selected FLASH memory block. Trying to alter data in any protected area in the flash memory will result in a flash protection violation error.
          There are 3 modes:
          • Disabled - The protection of the FLASH memory is disabled. There are no items in this mode.
          • User defined - The size of the protected area is defined by user. The following items are displayed in this mode:
            • Protected area [kB] - Size of protected are in kB. The inserted value will be automatically adjusted to the nearest allowed value. The address range of protected flash is shown in the third column of this property.
          • Entire FLASH - The entire FLASH memory is protected. There are no items in this mode.
    • I/O module - I/O ports' settings
      • Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
        This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
        There are 3 modes:
        • no initialization - There are no items in this mode.
        • input - The following items are displayed in this mode:
          • Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
          • Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
        • output - See input mode for items available in this mode.
      • Initialize not-bonded I/O pins - Initialization for all not-bonded I/O pins.
        This property specifies initialization direction for all not-bonded pins . If the given not-bonded pin doesn't support the preferred direction then the pin direction is left in it's default state.
        There are 3 modes:
        • no initialization - There are no items in this mode.
        • input - The following items are displayed in this mode:
          • Pull resistor - Default initialization of pull resistors for all not-bonded I/O pins. Pull resistor is initialized only if the given not-bonded pin is set to input direction and supports selected pull resistor type.
          • Output value - Default initialization of output value for all not-bonded I/O pins. Output value is initialized only if the given not-bonded pin is set to output direction.
        • output - See input mode for items available in this mode.
      • PORT A - Slew rate control, Drive strength, Input filter setting for pins of PORT A
      • PORT B - Slew rate control, Drive strength, Input filter setting for pins of PORT B
      • PORT C - Slew rate control, Drive strength, Input filter setting for pins of PORT C
      • PORT D - Slew rate control, Drive strength, Input filter setting for pins of PORT D
      • PORT E - Slew rate control, Drive strength, Input filter setting for pins of PORT E
      • PORT F - Slew rate control, Drive strength, Input filter setting for pins of PORT F
      • PORT G - Slew rate control, Drive strength, Input filter setting for pins of PORT G
      • PORT H - Slew rate control, Drive strength, Input filter setting for pins of PORT H
      • PORT J - Slew rate control, Drive strength, Input filter setting for pins of PORT J
    • System Clock Gating - Clock gating control settings. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait currents.
      • SCI1 Clock Gate - This property sets the SCI1 Clock Gate Control.
        This item modifies the SCI1 bit in the SCGC1 register
        Enabled - Bus clock to the SCI1 module is enabled.
        Disabled - Bus clock to the SCI1 module is disabled.
      • SCI2 Clock Gate - This property sets the SCI2 Clock Gate Control.
        This item modifies the SCI2 bit in the SCGC1 register
        Enabled - Bus clock to the SCI2 module is enabled.
        Disabled - Bus clock to the SCI2 module is disabled.
      • IIC Clock Gate - This property sets the IIC Clock Gate Control.
        This item modifies the IIC bit in the SCGC1 register
        Enabled - Bus clock to the IIC module is enabled.
        Disabled - Bus clock to the IIC module is disabled.
      • DAC Clock Gate - This property sets the DAC Clock Gate Control.
        This item modifies the DAC bit in the SCGC1 register
        Enabled - Bus clock to the DAC module is enabled.
        Disabled - Bus clock to the DAC module is disabled.
      • ADC Clock Gate - This property sets the ADC Clock Gate Control.
        This item modifies the ADC bit in the SCGC1 register
        Enabled - Bus clock to the ADC module is enabled.
        Disabled - Bus clock to the ADC module is disabled.
      • TPM1 Clock Gate - This property sets the TPM1 Clock Gate Control.
        This item modifies the TPM1 bit in the SCGC1 register
        Enabled - Bus clock to the TPM1 module is enabled.
        Disabled - Bus clock to the TPM1 module is disabled.
      • TPM2 Clock Gate - This property sets the TPM2 Clock Gate Control.
        This item modifies the TPM2 bit in the SCGC1 register
        Enabled - Bus clock to the TPM2 module is enabled.
        Disabled - Bus clock to the TPM2 module is disabled.
      • CMT Clock Gate - This property sets the CMT Clock Gate Control
        This item modifies the CMT bit in the SCGC1 register.
        Enabled - Bus clock to the CMT module is enabled.
        Disabled - Bus clock to the CMT module is disabled.
      • SPI1 Clock Gate - This property sets the SPI1 Clock Gate Control.
        This item modifies the SPI1 bit in the SCGC2 register
        Enabled - Bus clock to the SPI1 module is enabled.
        Disabled - Bus clock to the SPI1 module is disabled.
      • SPI2 Clock Gate - This property sets the SPI2 Clock Gate Control.
        This item modifies the SPI2 bit in the SCGC2 register
        Enabled - Bus clock to the SPI2 module is enabled.
        Disabled - Bus clock to the SPI2 module is disabled.
      • MFB Clock Gate - This property sets the MFB Clock Gate Control.
        This item modifies the MFB bit in the SCGC2 register
        Enabled - Bus clock to the MFB module is enabled.
        Disabled - Bus clock to the MFB module is disabled.
      • PRACMP Clock Gate - This property sets the PRACMP Clock Gate Control.
        This item modifies the PRACMP bit in the SCGC2 register
        Enabled - Bus clock to the PRACMP modules is enabled.
        Disabled - Bus clock to the PRACMP modules is disabled.
      • KBI Clock Gate - This property sets the KBI Clock Gate Control.
        This item modifies the KBI bit in the SCGC2 register
        Enabled - Bus clock to the KBI modules is enabled.
        Disabled - Bus clock to the KBI modules is disabled.
      • IRQ Clock Gate - This property sets the IRQ Clock Gate Control.
        This item modifies the IRQ bit in the SCGC2 register
        Enabled - Bus clock to the IRQ module is enabled.
        Disabled - Bus clock to the IRQ module is disabled.
      • PDB Register Clock Gate - This property sets the PDB Register Clock Gate Control.
        This item modifies the PDB bit in the SCGC2 register
        Enabled - Bus clock to the PDB registers is enabled.
        Disabled - Bus clock to the PDB registers is disabled.
      • USB Clock Gate - This property sets the USB Clock Gate Control.
        This item modifies the USB bit in the SCGC2 register
        Enabled - Bus clock to the USB module is enabled.
        Disabled - Bus clock to the USB module is disabled.
      • GPOA1 Clock Gate - This property sets the GPOA1 Clock Gate Control.
        This item modifies the GPOA1 bit in the SCGC3 register
        Enabled - Bus clock to the GPOA1 module is enabled.
        Disabled - Bus clock to the GPOA1 module is disabled.
      • GPOA2 Clock Gate - This property sets the GPOA2 Clock Gate Control.
        This item modifies the GPOA2 bit in the SCGC3 register
        Enabled - Bus clock to the GPOA2 module is enabled.
        Disabled - Bus clock to the GPOA2 module is disabled.
      • TRIAMP1 Clock Gate - This property sets the TRIAMP1 Clock Gate Control.
        This item modifies the TRIAMP1 bit in the SCGC3 register
        Enabled - Bus clock to the TRIAMP1 module is enabled.
        Disabled - Bus clock to the TRIAMP1 module is disabled.
      • TRIAMP2 Clock Gate - This property sets the TRIAMP2 Clock Gate Control.
        This item modifies the TRIAMP2 bit in the SCGC3 register
        Enabled - Bus clock to the TRIAMP2 module is enabled.
        Disabled - Bus clock to the TRIAMP2 module is disabled.
      • FLS1 Clock Gate - This property sets the FLS1 Clock Gate Control.
        This item modifies the FLS1 bit in the SCGC3 register
        Enabled - Bus clock to the FLS1 module is enabled.
        Disabled - Bus clock to the FLS1 module is disabled.
      • FLS2 Clock Gate - This property sets the FLS2 Clock Gate Control.
        This item modifies the FLS2 bit in the SCGC3 register
        Enabled - Bus clock to the FLS2 module is enabled.
        Disabled - Bus clock to the FLS2 module is disabled.
      • CRC Clock Gate - This property sets the CRC Clock Gate Control
        This item modifies the CRC bit in the SCGC3 register.
        Enabled - Bus clock to the CRC module is enabled.
        Disabled - Bus clock to the CRC module is disabled
      • VREF Clock Gate - This property sets the VREF Clock Gate Control.
        This item modifies the VREF bit in the SCGC3 register
        Enabled - Bus clock to the VREF module is enabled.
        Disabled - Bus clock to the VREF module is disabled
    • LVD module - Low Voltage Detect module settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • LVD operation - This property defines operation performed upon detection of a low voltage condition.

        There are 3 options:
        • Reset: Reset is generated upon detection of a low voltage condition.
        • Interrupt: Interrupt is generated when LVI detector state is changed.
        • Polling mode: No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output.

      • LVW interrupt - This property enables to generate hardware interrupt requests upon a detection of the Low-voltage warning condition.
      • LVD module interrupt - Low Voltage Detect module interrupt vector (for information only). This property is set automatically by Processor Expert and depends on the setting of LVD operation and LVW interrupt.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt name - Interrupt vector that is invoked from the Low-voltage warning interrupt (for information only).
        • Interrupt priority - Priority of the LVD module interrupt (for information only).
      • Enable in stop mode - Enables the Low-voltage detection during the stop mode.
      • Wake-up on Interupt - This property controls whether or not the voltage regulator exits standby when any active MCU interrupt occurs.
      • Low-voltage detect voltage - Low-voltage detect trip point selection (low or high).
      • Low-voltage warning voltage - Low-voltage warning trip point selection (low or high).
    • TPM modules - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
      • Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
      • Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
    • Reset pin support - Enables/disables the reset pin to function as RESET. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
  • CPU interrupts/resets - Interrupts/Resets vectors allocated by the CPU component.
    • Instruction related exceptions - Settings of instruction related exceptions.
      • Instruction related reset - This property enables/disables the generation of an "illegal opcode" reset event in response to a processor exception caused by the attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal line F instructions, or a privilege violation.
      • Illegal Instruction Exception - This property enables/disables generation of Illegal Instruction Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Illegal Instruction Exception.
      • Unimplemented Line-A Opcode - This property enables/disables generation of Unimplemented Line-A Opcode interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Unimplemented Line-A Opcode exception.
      • Unimplemented Line-F Opcode - This property enables/disables generation of Unimplemented Line-F Opcode interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Unimplemented Line-F Opcode exception.
      • Privilege Violation - This property enables/disables generation of Privilege Violation interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Privilege Violation exception.
    • Address related exceptions - Settings of address related exceptions.
      • Address related reset - This property enables/disables the generation of an "illegal address" reset event in response to a processor exception caused by an address error, a bus error (access error), an RTE format error, or a fault-on-fault halt condition.
      • Access Error Exception - This property enables/disables generation of Access Error Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Access Error Exception.
      • Address Error Exception - This property enables/disables generation of Address Error Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Address Error Exception.
      • RTE Format Error Exception - This property enables/disables generation of RTE Format Error Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the RTE Format Error Exception.
    • Unsupported Instruction - This property enables/disables generation of Unssuported Instruction interrupt service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Interrupt associated with the Unsupported Instruction exception.
    • Trap exceptions - Settings of Trap exceptions.
      One Item of the list looks like:
      Trap 0 - This property enables/disables generation of selected TRAP exception service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Exception vector associated with the TRAP exception.
    • Software Interrupts - Settings of software interrupts.
      One Item of the list looks like:
      Software Interrupt Level 1 - This property enables/disables generation of the selected software interrupt service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Interrupt associated with the selected software interrupt.
      • Interrupt priority - Interrupt level of associated software interrupt(for information only).
    • Loss of lock - Loss of lock interrupt settings. This property is set by Processor expert and depends on the setting of Loss of lock interrupt property. (For information only)
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Loss of lock interrupt. (for information only)
  • ExternalBus - External bus interface
    • Chip selects - Chip selects settings.
      • CS0 - Enables/Disable the chip select 0.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Base address - Specifies the upper 16 bits of base address for memory dedicated to chip-select CS0. This value is then compared to bits 31-16 on the internal address bus to determine if chip-select memory is being accessed.
        • Base address mask - Specifies the chip-select block size by masking address bits. Setting a mask bit causes the corresponding bits of the Base address to be a don't care in the decode.
          0 - Corresponding address bit is used in chip-select decode.
          1 - Corresponding address bit is a don't care in chip-select decode.
        • Write protect - Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip select not being selected, as well as a bus error sent to the interrupt controller

          There are 2 options:
          • Disabled: Read and write accesses are allowed.
          • Enabled: Only read accesses are allowed.

        • Wait states - The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states).
        • Address setup - Controls the assertion of the chip-select with respect to assertion of a valid address and attributes. The address and attributes are considered valid at the same time FB_ALE asserts.

          There are 4 options:
          • FB_CSn on first rising clock edge: Assert FB_CSn on first rising clock edge after address is asserted.
          • FB_CSn on second rising clock edge: Assert FB_CSn on second rising clock edge after address is asserted.
          • FB_CSn on third rising clock edge: Assert FB_CSn on third rising clock edge after address is asserted.
          • FB_CSn on fourth rising clock edge: Assert FB_CSn on fourth rising clock edge after address is asserted.

        • Read address hold or deselect - Controls the address and attribute hold time after the termination during a read cycle that hits in the chip-select address space. The hold time applies only at the end of a transfer. Therefore, the hold time is only added after the last bus cycle, during a burst transfer or a transfer to a port size smaller than the transfer size.

          There are 4 options:
          • Zero cycles after FB_CSn: Hold address and attributes zero cycles after FB_CSn negates on reads.
          • One cycles after FB_CSn: Hold address and attributes one cycle after FB_CSn negates on reads.
          • Two cycles after FB_CSn: Hold address and attributes two cycles after FB_CSn negates on reads.
          • Three cycles after FB_CSn: Hold address and attributes three cycles after FB_CSn negates on reads.

        • Write address hold or deselect - Controls the address, data, and attribute hold time after the termination of a write cycle that hits in the chip-select address space.The hold time applies only at the end of a transfer.Therefore, the hold time is only added after the last bus cycle, during a burst transfer or a transfer to a port size smaller than the transfer size.

          There are 4 options:
          • One cycle after FB_CSn: Hold address and attributes one cycle after FB_CSn negates on writes.
          • Two cycles after FB_CSn: Hold address and attributes two cycles after FB_CSn negates on writes.
          • Three cycles after FB_CSn: Hold address and attributes three cycles after FB_CSn negates on writes.
          • Four cycles after FB_CSn: Hold address and attributes four cycles after FB_CSn negates on writes.

        • Multiplexed mode - Selects between multiplexed and non-multiplexed address/data bus.

          There are 2 options:
          • Disabled: Non-multiplexed A/D bus.
          • Enabled: Multiplexed A/D bus

        • Port size - Specifies the data port width associated with each chip-select. It determines where data is driven during write cycles and where data is sampled during read cycles.

          There are 2 options:
          • 8-bit port size: Valid data sampled and driven on FB_D[31:24].
          • 16-bit port size: Valid data sampled and driven on FB_D[31:16].

        • CS0 pin - Chip select 0 pin.
        • CS0 pin signal - Signal name of CS0 pin
      • CS1 - Enables/Disable the chip select 1.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Base address - Specifies the upper 16 bits of base address for memory dedicated to chip-select CS1. This value is then compared to bits 31-16 on the internal address bus to determine if chip-select memory is being accessed.
        • Base address mask - Specifies the chip-select block size by masking address bits. Setting a mask bit causes the corresponding bits of the Base address to be a don't care in the decode.
          0 - Corresponding address bit is used in chip-select decode.
          1 - Corresponding address bit is a don't care in chip-select decode.
        • Write protect - Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip select not being selected, as well as a bus error sent to the interrupt controller

          There are 2 options:
          • Disabled: Read and write accesses are allowed.
          • Enabled: Only read accesses are allowed.

        • Wait states - The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states).
        • Address setup - Controls the assertion of the chip-select with respect to assertion of a valid address and attributes. The address and attributes are considered valid at the same time FB_ALE asserts.

          There are 4 options:
          • FB_CSn on first rising clock edge: Assert FB_CSn on first rising clock edge after address is asserted.
          • FB_CSn on second rising clock edge: Assert FB_CSn on second rising clock edge after address is asserted.
          • FB_CSn on third rising clock edge: Assert FB_CSn on third rising clock edge after address is asserted.
          • FB_CSn on fourth rising clock edge: Assert FB_CSn on fourth rising clock edge after address is asserted.

        • Read address hold or deselect - Controls the address and attribute hold time after the termination during a read cycle that hits in the chip-select address space. The hold time applies only at the end of a transfer. Therefore, the hold time is only added after the last bus cycle, during a burst transfer or a transfer to a port size smaller than the transfer size.

          There are 4 options:
          • Zero cycles after FB_CSn: Hold address and attributes zero cycles after FB_CSn negates on reads.
          • One cycles after FB_CSn: Hold address and attributes one cycle after FB_CSn negates on reads.
          • Two cycles after FB_CSn: Hold address and attributes two cycles after FB_CSn negates on reads.
          • Three cycles after FB_CSn: Hold address and attributes three cycles after FB_CSn negates on reads.

        • Write address hold or deselect - Controls the address, data, and attribute hold time after the termination of a write cycle that hits in the chip-select address space.The hold time applies only at the end of a transfer.Therefore, the hold time is only added after the last bus cycle, during a burst transfer or a transfer to a port size smaller than the transfer size.

          There are 4 options:
          • One cycle after FB_CSn: Hold address and attributes one cycle after FB_CSn negates on writes.
          • Two cycles after FB_CSn: Hold address and attributes two cycles after FB_CSn negates on writes.
          • Three cycles after FB_CSn: Hold address and attributes three cycles after FB_CSn negates on writes.
          • Four cycles after FB_CSn: Hold address and attributes four cycles after FB_CSn negates on writes.

        • Multiplexed mode - Selects between multiplexed and non-multiplexed address/data bus.

          There are 2 options:
          • Disabled: Non-multiplexed A/D bus.
          • Enabled: Multiplexed A/D bus

        • Port size - Specifies the data port width associated with each chip-select. It determines where data is driven during write cycles and where data is sampled during read cycles.

          There are 2 options:
          • 8-bit port size: Valid data sampled and driven on FB_D[31:24].
          • 16-bit port size: Valid data sampled and driven on FB_D[31:16].

        • CS1 pin - Chip select 1 pin.
        • CS1 pin signal - Signal name of CS1 pin
    • Address pins - Address pins/signals settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • A0 pin - Address pin 0 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A1 pin - Address pin 1 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A2 pin - Address pin 2 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A3 pin - Address pin 3 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A4 pin - Address pin 4 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A5 pin - Address pin 5 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A6 pin - Address pin 6 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A7 pin - Address pin 7 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A8 pin - Address pin 8 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A9 pin - Address pin 9 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A10 pin - Address pin 10 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A11 pin - Address pin 11 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A12 pin - Address pin 12 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A13 pin - Address pin 13 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A14 pin - Address pin 14 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A15 pin - Address pin 15 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A16 pin - Address pin 16 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A17 pin - Address pin 17 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A18 pin - Address pin 18 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • A19 pin - Address pin 19 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
    • Data pins - Data pins/signals settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • D0 pin - Data pin 0 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D1 pin - Data pin 1 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D2 pin - Data pin 2 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D3 pin - Data pin 3 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D4 pin - Data pin 4 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D5 pin - Data pin 5 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D6 pin - Data pin 6 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • D7 pin - Data pin 7 settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
    • Control pins - Control pins/signals settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • OE pin - Control pin OE settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • RW pin - Control pin RW settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
      • ALE pin - Control pin ALE settings.
        The following items are available only if the group is enabled (the value is "Enabled"):
    • External memory - External memory block definitions.
      One Item of the list looks like:
      Memory block0 - External memory block
  • Enabled speed modes - Enabled speed modes.
    • High speed mode - High speed mode support (always enabled)
      The following items are available only if the group is enabled (the value is "Enabled"):
      • High speed clock - The clock source for the internal bus clock.
        Internal Clock - Internal reference clock 31.25kHz - 39.0625kHz.
        External Clock - External clock source (external crystal or external reference clock, if available and enabled).
        See Clock settings to set the current value of a clock source.
      • Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source.
      • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock. If all dividers/multiplier are set manually by the user (none of them is set to 'Auto select value'), the bus frequency is calculated by Processor Expert and cannot be modified. Possible bus clock frequency is limited by the selected reference clock source and are limited by its value. See Clock settings to set the current value of a clock source.
      • Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock source is derived from the MCG Divided ref.clock freq. [MHz]. It is valid only when the reference clock is no more than 1/4 of the output frequency of the MCG module.
      • Clock monitor - This property determines if a reset request is made following a loss of external clock indication. Clock monitor should only be enabled when either the MCG is in an operation mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference clock for peripherals is enabled.

        There are 2 options:
        • Disabled: Clock monitor is disabled.
        • Force reset: Generate a reset request on loss of external clock.

      • FLL/PLL mode - FLL/PLL mode (Engaged/Bypassed/Bypassed Low Power).
        There are 6 modes:
        • FLL Engaged - In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal of external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
          • Loss of lock interrupt - This property enables to generate an interrupt request after a loss of lock condition is detected. This property is not available in Bypassed Low-power modes.
          • Ref. clock source - FLL or PLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
            There are 2 modes:
            • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
              • Ref. clock freq. [MHz] - Frequency of the FLL/PLL reference clock [MHz]
                When either an Engaged or a Bypassed FLL mode is selected then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
                When either Engaged of bypassed PLL mode is selected then the reference clock frequency shall be in range <1 MHz, 2 MHz>.
                The source of the reference clock is selected by the Ref. clock source property:
                When 'Internal Clock' is selected: When 'External Clock' is selected:
                • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                  When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                  If an external Bypassed Low-power mode is selected and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
            • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
              • Ref. clock source freq. [MHz] - Frequency of FLL/PLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
              • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
              • Ref. clock freq. [MHz] - See previous modes for more details
          • DCO mode - This property defines, which DCO mode will be used.
            When set to 'Auto select' the PE selects optimal DCO mode according to the requested Internal bus clock (in FLL Engaged mode) or the requested FLL output clock freq. [MHz] (in FLL Bypassed mode).
            There are 3 modes:
            • Auto select - DCO mode will be automatically selected by PE There are no items in this mode.
            • Default - DCO has default range of 25%. The following items are displayed in this mode:
              • FLL mult. factor - Selects the FLL factor. This value establishes the DCO range (Low range, Mid range). This property cannot be modified in FLL Engaged mode. If 'Auto select' value is used you can enter the requested FLL output clock frequency into the FLL output clock freq. [MHz] property and PE will select the most suitable value.
            • Fine tuned 32kHz - DCO is fined tuned for maximum frequency with 32.768 kHz reference. The following items are displayed in this mode:
          • FLL output clock freq. [MHz] - FLL output clock frequency [MHz] (for information only).
        • FLL Bypassed - In FLL bypassed mode, the bus clock is derived from the internal or external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See FLL Engaged mode for items available in this mode.
        • FLL Bypassed Low Power - In FLL bypassed low power mode, the bus clock is derived from the internal or external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. The following items are displayed in this mode:
          • Ref. clock source - FLL or PLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
            There are 2 modes:
            • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
              • Ref. clock freq. [MHz] - Frequency of the FLL/PLL reference clock [MHz]
                When either an Engaged or a Bypassed FLL mode is selected then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
                When either Engaged of bypassed PLL mode is selected then the reference clock frequency shall be in range <1 MHz, 2 MHz>.
                The source of the reference clock is selected by the Ref. clock source property:
                When 'Internal Clock' is selected: When 'External Clock' is selected:
                • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                  When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                  If an external Bypassed Low-power mode is selected and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
            • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
              • Ref. clock source freq. [MHz] - Frequency of FLL/PLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
              • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
              • Ref. clock freq. [MHz] - See previous modes for more details
        • PLL Engaged - In PLL engaged mode, the bus clock is derived from the FLL which is controlled by the external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
          • Loss of lock interrupt - See previous modes for more details
          • Ref. clock source - FLL or PLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
            There are 2 modes:
            • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
              • Ref. clock freq. [MHz] - Frequency of the FLL/PLL reference clock [MHz]
                When either an Engaged or a Bypassed FLL mode is selected then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
                When either Engaged of bypassed PLL mode is selected then the reference clock frequency shall be in range <1 MHz, 2 MHz>.
                The source of the reference clock is selected by the Ref. clock source property:
                When 'Internal Clock' is selected: When 'External Clock' is selected:
                • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                  When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                  If an external Bypassed Low-power mode is selected and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
            • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
              • Ref. clock source freq. [MHz] - Frequency of FLL/PLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
              • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
              • Ref. clock freq. [MHz] - See previous modes for more details
          • PLL mult. factor - Selects the amount to divide down the VCO output of PLL. This value establish the multiplication factor (M) applied to the reference clock frequency. This property can be modified only in PLL bypassed mode(PBE). If 'Auto select' value is used you can try to write requested PLL output clock frequency into the PLL output clock freq. property and PE will try to calculate best multiplication factor for you.
          • PLL output clock freq. [MHz] - PLL output clock frequency [MHz]. If the PLL mult. factor property is set to 'Auto select' value you can write here requested frequency and PE will try to calculate best multiplication factor for you. Otherwise this property is set by PE according to the selected PLL mult. factor and cannot be modified.
        • PLL Bypassed - In PLL bypassed mode, the bus clock is derived from external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See PLL Engaged mode for items available in this mode.
        • PLL Bypassed Low Power - In PLL bypassed low power mode, the bus clock is derived external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. See FLL Bypassed Low Power mode for items available in this mode.
    • Low speed mode - See High speed mode description.
    • Slow speed mode - See High speed mode description.

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