MCF51EM256_80
 
General Info



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CPU MCF51EM256_80
Freescale ColdFireV1 family : MCF51EM256 in 80 pin LQFP package
Device Initialization
(Description of the CPU component parameters.)
  • Clock settings - MCU clock settings
    • Source CPU clock - The clock source for the internal bus clock.
      Internal Clock - Internal reference clock 31.25kHz - 39.0625kHz.
      External Clock - External clock source (external crystal or external reference clock, if available and enabled).
      See Clock settings to set the current value of a clock source.
    • Internal clock - Internal clock settings.
      • Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 32.7 kHz.
      • Internal ref. clock for peripherals - This property enables the internal reference clock for use as ICSIRCLK for peripherals.
      • Initialize trim value - This property enables to generate code for initialization of the trim registers (ICSTRM, ICSSC) with a value from a non-volatile memory location.
        The following items are available only if the group is enabled (the value is "yes"):
    • External clock - If this property is enabled, an external clock is allowed for MCU timing.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • XOSC1 Clock input pin - Clock input properties.
        • Pin name - XOSC1 Clock input pin name (for information only).
      • XOSC1 Clock output pin - Clock output properties.
        • Pin name - XOSC1 Clock output pin name (for information only).
      • Clock source - Possible external clock sources (external crystal or external clock).
        There are 3 modes:
        • XOSC2 External crystal - External crystal connected to the XOSC2 module The following items are displayed in this mode:
          • Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 32-38.4kHz or 1-16MHz and the external clock should be in the range of 0.0001-40MHz but this limits may be further restricted by other settings of the ICS module (Oscillator operating mode, FLL/PLL mode).
          • Clock range - This property selects the frequency range for the external oscillator or external clock source.

            There are 2 options:
            • High frequency: selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source)
            • Low frequency: selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source)

            The property is set automatically by Processor expert if clock frequency is in the vendor recommended range otherwise can by changed manually.
          • Oscillator operating mode - The operating mode of the oscillator module. It provides the high gain for improving of noise immunity or the low power consumption This property also influences allowed frequency range of external crystal.

            There are 2 options:
            • High gain: This mode provides a higher amplitude output for the improved noise immunity.
            • Low power: This mode provides the lower power consumption.

          • External ref. clock for peripherals - This property enables the external reference clock for use as ICSERCLK for peripherals.
          • XOSC2 Clock input pin - Clock input properties.
            • Pin name - Clock input pin name (for information only).
          • XOSC2 Clock output pin - Clock output properties.
            • Pin name - Clock output pin name (for information only).
        • XOSC2 External oscillator - External oscillator connected to the XOSC2 module The following items are displayed in this mode:
          • Clock frequency [MHz] - See previous modes for more details
          • Clock range - See previous modes for more details
          • External ref. clock for peripherals - See previous modes for more details
          • XOSC2 Clock input pin - Clock input properties.
            • The content is the same as in previous modes.
        • XOSC1 External crystal - External crystal of the independent real time clock module The following items are displayed in this mode:
          • Clock frequency [MHz] - See previous modes for more details
          • Clock range - See previous modes for more details
          • External ref. clock for peripherals - See previous modes for more details
    • Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source.
    • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock. If all dividers/multiplier are set manually by the user (none of them is set to 'Auto select value'), the bus frequency is calculated by Processor Expert and cannot be modified. Possible bus clock frequency is limited by the selected reference clock source and are limited by its value. See Clock settings to set the current value of a clock source.
    • Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock source is derived from the ICS Ref. clock freq. [MHz]. It is valid only when the reference clock is no more than 1/4 of the output frequency of the ICS module.
    • FLL mode - FLL mode (Engaged/Bypassed/Bypassed Low Power).
      There are 3 modes:
      • Engaged - In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal of external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
        • Ref. clock source - FLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
          There are 2 modes:
          • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
            • Ref. clock freq. [MHz] - Frequency of the FLL reference clock [MHz]
              If FLL is enabled (Engaged and Bypassed modes) then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
              The source of the reference clock is selected by the Ref. clock source property:
              When 'Internal Clock' is selected: When 'External Clock' is selected:
              • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                If FLL is disabled (Bypassed Low-power modes) and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
          • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
            • Ref. clock source freq. [MHz] - Frequency of FLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
            • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
            • Ref. clock freq. [MHz] - See previous modes for more details
        • DCO mode - This property defines, which DCO mode will be used.
          When set to 'Auto select' the PE selects optimal DCO mode according to the requested Internal bus clock (in FLL Engaged mode) or the requested FLL output clock freq. [MHz] (in FLL Bypassed mode).
          There are 3 modes:
          • Auto select - DCO mode will be automatically selected by PE There are no items in this mode.
          • Default - DCO has default range of 25%. The following items are displayed in this mode:
            • FLL mult. factor - Selects the FLL factor. This value establishes the range DCO range (Low range, Mid range, High range). This property cannot be modified in FLL Engaged mode. If 'Auto select' value is used you can enter the requested FLL output clock frequency into the FLL output clock freq. [MHz] property and PE will select the most suitable value.
          • Fine tuned 32kHz - DCO is fined tuned for maximum frequency with 32.768 kHz reference. The following items are displayed in this mode:
        • FLL output clock freq. [MHz] - FLL output clock frequency [MHz] (for information only).
      • Bypassed - In FLL bypassed mode, the bus clock is derived from the internal or external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See Engaged mode for items available in this mode.
      • Bypassed Low Power - In FLL bypassed low power mode, the bus clock is derived from the internal or external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. The following items are displayed in this mode:
        • Ref. clock source - FLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
          There are 2 modes:
          • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
            • Ref. clock freq. [MHz] - Frequency of the FLL reference clock [MHz]
              If FLL is enabled (Engaged and Bypassed modes) then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
              The source of the reference clock is selected by the Ref. clock source property:
              When 'Internal Clock' is selected: When 'External Clock' is selected:
              • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                If FLL is disabled (Bypassed Low-power modes) and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
          • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
            • Ref. clock source freq. [MHz] - Frequency of FLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
            • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
            • Ref. clock freq. [MHz] - See previous modes for more details
    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - This property enables the STOP instruction.
        The following items are available only if the group is enabled (the value is "yes"):
      • Force exit on interrupt - This property enables to force exit from STOP or WAIT mode on interrupt. When enabled, the combinational wake-up signal may be asserted to the clock generation logic when an interrupt occurs.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Wakeup interrupt level - Defines the interrupt mask level during wait or stop mode. Once an interrupt request of a level higher than selected value is asserted, the wake-up signal to the clock generation logic is asserted.

          There are 7 options:
          • 0: All interrupts will assert wake-up.
          • 1: Interrupts with level 2 and higher will assert wake-up.
          • 2: Interrupts with level 3 and higher will assert wake-up.
          • 3: Interrupts with level 4 and higher will assert wake-up.
          • 4: Interrupts with level 5 and higher will assert wake-up.
          • 5: Interrupts with level 6 and higher will assert wake-up.
          • 6: Only interrupts with level 7 (non-maskable interrupts) will assert wake-up.

  • Internal resource mapping - Internal resource mapping setting
    • Exception vector table - This group contains settings for placement of exception vector table.
      • Fetch vectors from RAM - When set to 'yes' the cpu fetches exception vectors from RAM (base address of the vector table is 0x80_0000). When set to 'no' exception vectors are fetched from flash (base address of the vector table is 0x00_0000).
      • Address - This property defines address of definition of exception vectors table - the default address is 0x00_0000. For a bootloader support the definition of the exception vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of exception vectors to a valid source. The setting of the exception vector table address doesn't affect any HW resources.
      • Size - Size of the exception vector table. (For information only)
  • Initialization priority - Initialization interrupt priority value of the CPU bean.
  • Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
    • Internal bandgap - Settings of the Internal bandgap
      • Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. This item modifies the BGBE bit in the SPMSC1 register.
      • Internal bandgap buffer drive - This property select the drive mode of the bandgap buffer. This item modifies the BGDS bit in the SPMSC1 register.

        There are 2 options:
        • Low drive mode: Bandgap buffer enabled in low drive mode
        • High drive mode: Bandgap buffer enabled in high drive mode

    • BDM pin support - Enables/disables the background debug mode pin support. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • BDM pin - Background Debug Mode pin name (for information only)
    • Clock output - This property controls operation of the clock output (CLKOUT) pin. The various clock sources must be enabled/disabled via the appropriate controls elsewhere in the device.
      There are 12 modes:
    • CPU configuration - Configuration of specific CPu core functionality.
      • Interrupt mask - When enabled, the processor raises the interrupt level mask (SR[I]) to 7 during every interrupt. This disables all level 1-6 interrupt requests but allows recognition of the edge-sensitive level 7 requests.
        When disabled, the processor sets SR[I] to the level of the interrupt being serviced.
        This capability is provided to assist when porting S08 application code to ColdFire.
      • Interrupt acknowledge (IACK) - When enabled, forces the processor to generate an IACK read cycle from the interrupt controller during exception processing to retrieve the vector number of the interrupt request being acknowledged. The processor’s execution time for an interrupt exception is slightly improved when this property is disabled. This item modifies bit IAE of the CPUCR register.
      • Buffered peripheral bus write - This property controls buffered peripheral bus write access.
        When enabled, peripheral bus writes are buffered and the bus cycle is terminated immediately and does not wait for the peripheral bus termination status. Any peripheral bus error status is lost.
        When disabled, peripheral bus writes are not buffered and bus cycle is not terminated until a registered version of the peripheral bus termination is received.
        This item modifies the BWD bit of CPUCR register.
      • Flash speculation - This property controls certain performance-enhancing features related to address speculation in the FSD flash memory controller. When enabled, the flash controller tries to speculate on read accesses to improve processor performance by minimizing the exposed flash memory access time. Recall the basic flash access time is two processor cycles.
        This item modifies the FSD bit of the CPUCR register.
    • FLASH - The FLASH memory options.
      • Flash Block 1 - Flash block 1 settings
        • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
          There are 2 modes:
          • Enabled - The following items are displayed in this mode:
            • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
              The following items are available only if the group is enabled (the value is "Enabled"):
          • Disabled - There are no items in this mode.
        • Protection - Protection of the selected FLASH memory block. Trying to alter data in any protected area in the flash memory will result in a flash protection violation error.
          There are 3 modes:
          • Disabled - The protection of the FLASH memory is disabled. There are no items in this mode.
          • User defined - The size of the protected area is defined by user. The following items are displayed in this mode:
            • Protected area [kB] - Size of protected are in kB. The inserted value will be automatically adjusted to the nearest allowed value. The address range of protected flash is shown in the third column of this property.
          • Entire FLASH - The entire FLASH memory is protected. There are no items in this mode.
      • Flash Block 2 - Flash block 2 settings
        • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
          There are 2 modes:
          • Enabled - The following items are displayed in this mode:
            • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
              The following items are available only if the group is enabled (the value is "Enabled"):
          • Disabled - There are no items in this mode.
        • Protection - Protection of the selected FLASH memory block. Trying to alter data in any protected area in the flash memory will result in a flash protection violation error.
          There are 3 modes:
          • Disabled - The protection of the FLASH memory is disabled. There are no items in this mode.
          • User defined - The size of the protected area is defined by user. The following items are displayed in this mode:
            • Protected area [kB] - Size of protected are in kB. The inserted value will be automatically adjusted to the nearest allowed value. The address range of protected flash is shown in the third column of this property.
          • Entire FLASH - The entire FLASH memory is protected. There are no items in this mode.
    • I/O module - I/O ports' settings
      • Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
        This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
        There are 3 modes:
        • no initialization - There are no items in this mode.
        • input - The following items are displayed in this mode:
          • Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
          • Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
        • output - See input mode for items available in this mode.
      • PORT A - Slew rate control, Drive strength, Input filter setting for pins of PORT A
      • PORT B - Slew rate control, Drive strength, Input filter setting for pins of PORT B
      • PORT C - Slew rate control, Drive strength, Input filter setting for pins of PORT C
      • PORT D - Slew rate control, Drive strength, Input filter setting for pins of PORT D
      • PORT E - Slew rate control, Drive strength, Input filter setting for pins of PORT E
      • PORT F - Slew rate control, Drive strength, Input filter setting for pins of PORT F
    • System Clock Gating - Clock gating control settings. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait currents.
      • SCI1 Clock Gate - This property sets the SCI1 Clock Gate Control.
        This item modifies the SCI1 bit in the SCGC1 register
        Enabled - Bus clock to the SCI1 module is enabled.
        Disabled - Bus clock to the SCI1 module is disabled.
      • SCI2 Clock Gate - This property sets the SCI2 Clock Gate Control.
        This item modifies the SCI2 bit in the SCGC1 register
        Enabled - Bus clock to the SCI2 module is enabled.
        Disabled - Bus clock to the SCI2 module is disabled.
      • SCI3 Clock Gate - This property sets the SCI3 Clock Gate Control.
        This item modifies the SCI3 bit in the SCGC1 register
        Enabled - Bus clock to the SCI3 module is enabled.
        Disabled - Bus clock to the SCI3 module is disabled.
      • IIC Clock Gate - This property sets the IIC Clock Gate Control.
        This item modifies the IIC bit in the SCGC1 register
        Enabled - Bus clock to the IIC module is enabled.
        Disabled - Bus clock to the IIC module is disabled.
      • ADC 1 Clock Gate - This property sets the ADC 1 Clock Gate Control
        This item modifies the ADC1 bit in the SCGC1 register.
        Enabled - Bus clock to the ADC 1 module is enabled.
        Disabled - Bus clock to the ADC 1 module is disabled.
      • ADC 2 Clock Gate - This property sets the ADC 2 Clock Gate Control
        This item modifies the ADC2 bit in the SCGC1 register.
        Enabled - Bus clock to the ADC 2 module is enabled.
        Disabled - Bus clock to the ADC 2 module is disabled.
      • ADC 3 Clock Gate - This property sets the ADC 3 Clock Gate Control
        This item modifies the ADC3 bit in the SCGC1 register.
        Enabled - Bus clock to the ADC 3 module is enabled.
        Disabled - Bus clock to the ADC 3 module is disabled.
      • ADC 4 Clock Gate - This property sets the ADC 4 Clock Gate Control
        This item modifies the ADC4 bit in the SCGC1 register.
        Enabled - Bus clock to the ADC 4 module is enabled.
        Disabled - Bus clock to the ADC 4 module is disabled.
      • SPI1 Clock Gate - This property sets the SPI1 Clock Gate Control.
        This item modifies the SPI1 bit in the SCGC2 register
        Enabled - Bus clock to the SPI1 module is enabled.
        Disabled - Bus clock to the SPI1 module is disabled.
      • SPI2 Clock Gate - This property sets the SPI2 Clock Gate Control.
        This item modifies the SPI2 bit in the SCGC2 register
        Enabled - Bus clock to the SPI2 module is enabled.
        Disabled - Bus clock to the SPI2 module is disabled.
      • SPI3 Clock Gate - This property sets the SPI3 Clock Gate Control.
        This item modifies the SPI3 bit in the SCGC2 register
        Enabled - Bus clock to the SPI3 module is enabled.
        Disabled - Bus clock to the SPI3 module is disabled.
      • LCD Clock Gate - This property sets the LCD Clock Gate Control.
        This item modifies the LCD bit in the SCGC2 register
        Enabled - Bus clock to the LCD module is enabled.
        Disabled - Bus clock to the LCD module is disabled.
      • IRQ Clock Gate - This property sets the IRQ Clock Gate Control.
        This item modifies the IRQ bit in the SCGC2 register
        Enabled - Bus clock to the IRQ module is enabled.
        Disabled - Bus clock to the IRQ module is disabled.
      • VREF Clock Gate - This property sets the VREF Clock Gate Control.
        This item modifies the VREF bit in the SCGC2 register
        Enabled - Bus clock to the VREF module is enabled.
        Disabled - Bus clock to the VREF module is disabled.
      • CMP1 Clock Gate - This property sets the CMP1 Clock Gate Control.
        This item modifies the CMP1 bit in the SCGC2 register
        Enabled - Bus clock to the CMP1 module is enabled.
        Disabled - Bus clock to the CMP1 module is disabled.
      • CMP2 Clock Gate - This property sets the CMP2 Clock Gate Control.
        This item modifies the CMP2 bit in the SCGC2 register
        Enabled - Bus clock to the CMP2 module is enabled.
        Disabled - Bus clock to the CMP2 module is disabled.
      • PTA Clock Gate - This property sets the PTA Clock Gate Control.
        This item modifies the PTA bit in the SCGC3 register
        Enabled - Bus clock to the PTA module is enabled.
        Disabled - Bus clock to the PTA module is disabled.
      • PTB Clock Gate - This property sets the PTB Clock Gate Control.
        This item modifies the PTB bit in the SCGC3 register
        Enabled - Bus clock to the PTB module is enabled.
        Disabled - Bus clock to the PTB module is disabled.
      • PTC Clock Gate - This property sets the PTC Clock Gate Control.
        This item modifies the PTC bit in the SCGC3 register
        Enabled - Bus clock to the PTC module is enabled.
        Disabled - Bus clock to the PTC module is disabled.
      • PTD Clock Gate - This property sets the PTD Clock Gate Control.
        This item modifies the PTD bit in the SCGC3 register
        Enabled - Bus clock to the PTD module is enabled.
        Disabled - Bus clock to the PTD module is disabled.
      • PTE Clock Gate - This property sets the PTE Clock Gate Control.
        This item modifies the PTE bit in the SCGC3 register
        Enabled - Bus clock to the PTE module is enabled.
        Disabled - Bus clock to the PTE module is disabled.
      • PTF Clock Gate - This property sets the PTF Clock Gate Control.
        This item modifies the PTF bit in the SCGC3 register
        Enabled - Bus clock to the PTF module is enabled.
        Disabled - Bus clock to the PTF module is disabled.
      • KBI1 Clock Gate - This property sets the KBI1 Clock Gate Control
        This item modifies the KBI1 bit in the SCGC3 register.
        Enabled - Bus clock to the KBI1 module is enabled.
        Disabled - Bus clock to the KBI1 module is disabled.
      • KBI2 Clock Gate - This property sets the KBI2 Clock Gate Control
        This item modifies the KBI2 bit in the SCGC3 register.
        Enabled - Bus clock to the KBI2 module is enabled.
        Disabled - Bus clock to the KBI2 module is disabled.
      • MTIM1 Clock Gate - This property sets the MTIM1 Clock Gate Control.
        This item modifies the MTIM1 bit in the SCGC4 register
        Enabled - Bus clock to the MTIM1 module is enabled.
        Disabled - Bus clock to the MTIM1 module is disabled.
      • MTIM2 Clock Gate - This property sets the MTIM2 Clock Gate Control.
        This item modifies the MTIM2 bit in the SCGC4 register
        Enabled - Bus clock to the MTIM2 module is enabled.
        Disabled - Bus clock to the MTIM2 module is disabled.
      • MTIM3 Clock Gate - This property sets the MTIM3 Clock Gate Control.
        This item modifies the MTIM3 bit in the SCGC4 register
        Enabled - Bus clock to the MTIM3 module is enabled.
        Disabled - Bus clock to the MTIM3 module is disabled.
      • PDB Clock Gate - This property sets the PDB Clock Gate Control
        This item modifies the PDB bit in the SCGC4 register.
        Enabled - Bus clock to the PDB module is enabled.
        Disabled - Bus clock to the PDB module is disabled.
      • TPM Clock Gate - This property sets the TPM Clock Gate Control
        This item modifies the TPM bit in the SCGC4 register.
        Enabled - Bus clock to the TPM module is enabled.
        Disabled - Bus clock to the TPM module is disabled.
      • CRC Clock Gate - This property sets the CRC Clock Gate Control
        This item modifies the CRC bit in the SCGC4 register.
        Enabled - Bus clock to the CRC module is enabled.
        Disabled - Bus clock to the CRC module is disabled.
      • Port Mux - This property sets the Port Mux Control
        This item modifies the PM bit in the SCGC4 register.
        Enabled - Bus clock to the Port Mux Control module is enabled
        Disabled - Bus clock to the Port Mux Control module is disabled
      • FTSR1 Clock Gate - This property sets the FTSR1 Clock Gate Control
        This item modifies the FTSR1 bit in the SCGC5 register.
        Enabled - Bus clock to flash registers is enabled.
        Disabled - Bus clock to flash registers is disabled
      • FTSR2 Clock Gate - This property sets the FTSR2 Clock Gate Control
        This item modifies the FTSR2 bit in the SCGC5 register.
        Enabled - Bus clock to flash registers is enabled.
        Disabled - Bus clock to flash registers is disabled
    • LVD module - Low Voltage Detect module settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • LVD operation - This property defines operation performed upon detection of a low voltage condition.

        There are 3 options:
        • Reset: Reset is generated upon detection of a low voltage condition.
        • Interrupt: Interrupt is generated when LVI detector state is changed.
        • Polling mode: No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output.

      • LVW interrupt - This property enables to generate hardware interrupt requests upon a detection of the Low-voltage warning condition.
      • LVD module interrupt - Low Voltage Detect module interrupt vector (for information only). This property is set automatically by Processor Expert and depends on the setting of LVD operation and LVW interrupt.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt name - Interrupt vector that is invoked from the Low-voltage warning interrupt (for information only).
        • Interrupt priority - Priority of the LVD module interrupt (for information only).
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
      • Enable in stop mode - Enables the Low-voltage detection during the stop mode.
      • Wake-up on Interupt - This property controls whether or not the voltage regulator exits standby when any active MCU interrupt occurs.
      • Low-voltage detect voltage - Low-voltage detect trip point selection (low or high).
      • Low-voltage warning voltage - Low-voltage warning trip point selection (low or high).
    • Reset pin - Reset pin
      • Reset pin - Reset pin name (for information only)
  • CPU interrupts/resets - Interrupts/Resets vectors allocated by the CPU component.
    • Reset vector - Reset vector settings.
      • Interrupt - Interrupt associated with the reset vector (for information only)
      • ISR name - Name of the reset vector - routine, that initializes CPU after reset.
    • Instruction related exceptions - Settings of instruction related exceptions.
      • Instruction related reset - This property enables/disables the generation of an "illegal opcode" reset event in response to a processor exception caused by the attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal line F instructions, or a privilege violation.
      • Illegal Instruction Exception - This property enables/disables generation of Illegal Instruction Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Illegal Instruction Exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
      • Unimplemented Line-A Opcode - This property enables/disables generation of Unimplemented Line-A Opcode interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Unimplemented Line-A Opcode exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
      • Unimplemented Line-F Opcode - This property enables/disables generation of Unimplemented Line-F Opcode interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Unimplemented Line-F Opcode exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
      • Privilege Violation - This property enables/disables generation of Privilege Violation interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Privilege Violation exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
    • Address related exceptions - Settings of address related exceptions.
      • Address related reset - This property enables/disables the generation of an "illegal address" reset event in response to a processor exception caused by an address error, a bus error (access error), an RTE format error, or a fault-on-fault halt condition.
      • Access Error Exception - This property enables/disables generation of Access Error Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Access Error Exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
      • Address Error Exception - This property enables/disables generation of Address Error Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the Address Error Exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
      • RTE Format Error Exception - This property enables/disables generation of RTE Format Error Exception interrupt service routine. If disabled, the default ISR will be used instead.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt - Interrupt associated with the RTE Format Error Exception.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly.
    • Unsupported Instruction - This property enables/disables generation of Unssuported Instruction interrupt service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Interrupt associated with the Unsupported Instruction exception.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.
    • Trap exceptions - Settings of Trap exceptions.
      One Item of the list looks like:
      Trap 0 - This property enables/disables generation of selected TRAP exception service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Exception vector associated with the TRAP exception.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this exception vector.
        The user code of the routine should handle all respective interrupt flags correctly.
    • Software Interrupts - Settings of software interrupts.
      One Item of the list looks like:
      Software Interrupt Level 1 - This property enables/disables generation of the selected software interrupt service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Interrupt associated with the selected software interrupt.
      • Interrupt priority - Interrupt level of associated software interrupt(for information only).
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.
    • Trace Exception - This property enables/disables generation of Trace Exception interrupt service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Interrupt associated with the Trace Exception.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.
    • Debug Interrupt - This property enables/disables generation of Debug Interrupt service routine. If disabled, the default ISR will be used instead.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Interrupt associated with the Debug Interrupt.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.

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