MC9S08RG60_32
 
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CPU Component MC9S08RG60_32
Freescale HCS08 family: MC9S08RG60 in 32 pin package
Component Level: High
Category: CPU-Freescale-HCS08-RG/RE/RD/RC
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • CPU type - CPU variant
  • Clock settings - MCU Clock settings
    • Oscillator frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 1-16MHz and the external clock should be in the range of 0.0001-16MHz.
    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - This property enables the STOP instruction.
        There are 2 modes:
        • yes - The following items are displayed in this mode:
          • Power down control - This property sets power down control bits that determine which power-down mode will be invoked when the STOP instruction is executed.

            There are 3 options:
            • STOP1 - Power down mode: Power down mode
            • STOP2 - Partial power down mode: Partial power down mode
            • STOP3 - Standby mode: Standby mode

        • no - There are no items in this mode.
  • Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.
  • Internal resource mapping - Internal resource mapping setting
    • Interrupt vector table - This group contains settings for placement of interrupt vector table.
      • Address - This property defines address of definition of interrupt vector table. For a bootloader support the definition of the interrupt vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of interrupt vector to a valid source. The setting of the interrupt vector table address doesn't affect any HW resources.
        When the Vector redirection property is available and is enabled the user is offered automatic adjustment of the address of the interrupt vector table according to the current setting of FLASH memory protection (see property group Internal peripherals/FLASH).
      • Size - Size of the exception vector table. (For information only)
    • Reset vector - This group contains settings for placement of reset vector.
      • Address - This property defines address of definition of reset vector. For a bootloader support the definition of the reset vector can be placed on a user defined address. In this case the user has to ensure correct redirection of the reset vector to a valid source. The setting of the reset vector address doesn't affect any HW resources.
      • Size - Size of the reset vector. (For information only)
  • Internal peripherals - Internal peripherals setting
    • Reset pin support - Reset pin support
      The following items are available only if the group is enabled (the value is "Enabled"):
    • BDM pin support - Enables/disables the background debug mode pin support.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • BDM pin - Background Debug Mode pin name (for information only)
      • BDM pin signal - Signal name of the Background Debug Mode pin
    • LVD module - Low Voltage Detect module settings.
      • LVD operation - This property defines operation performed upon detection of a low voltage condition.
        There are 3 modes:
        • Reset - Reset is generated upon detection of a low voltage condition. There are no items in this mode.
        • Interrupt - Interrupt is generated when LVI detector state is changed. The following items are displayed in this mode:
          • Interrupt name - Interrupt vector that is invoked from the Low Voltage Detect interrupt (for information only).
        • Polling mode - No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output. There are no items in this mode.
      • SAFE system interrupts - If the SAFE system interrupts mode is enabled the interrupts are blocked while supply voltage is below the re-arm voltage.
    • FLASH - The FLASH memory options.
      • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
        There are 2 modes:
        • Enabled - The following items are displayed in this mode:
          • SEC01:SEC00 bits value - This property specifies value for enabled security state (useful if it must be set exactly for debugger).
            This item modifies SEC00:SEC01 bits in the NVOPT register.
          • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
            The following items are available only if the group is enabled (the value is "Enabled"):
        • Disabled - There are no items in this mode.
      • Protection - Protection of the selected memory block. If a block of the FLASH memory is protected a bootloader cannot erase the protected block of memory.

        There are 7 options:
        • Disabled: Protection is disabled.
        • 512 bytes: Protected address range is $FE00 - $FFFF
        • 1 Kbytes: Protected address range is $FC00 - $FFFF
        • 2 Kbytes: Protected address range is $F800 - $FFFF
        • 4 Kbytes: Protected address range is $F000 - $FFFF
        • 8 Kbytes: Protected address range is $E000 - $FFFF
        • Entire FLASH: Entire FLASH is protected

      • Vector redirection - If the protection is enabled the vector interrupts can be redirected to the unprotected area by setting of this vector redirection property.
    • TPM module - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
      • Aligned - The PWM timer provides the choice of two types of outputs, Left Aligned or Center Aligned outputs. Note: If the align mode is switched to the Center align mode then the real lengths of the Period and Starting pulse width signals will be equal two times of what is being displayed in the Component Inspector.
  • CPU interrupts - Interrupts allocated by CPU bean
    • SWI - This property enables/disables generation of SWI interrupt service routine.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Software Interrupt (for information only)
  • Enabled speed modes - Enabled speed modes
    • High speed mode - High speed mode support (always enabled)
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock.
      • Clock source selections in high speed mode - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    • Low speed mode - Low speed mode support
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock.
      • Clock source selections in low speed mode - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    • Slow speed mode - Slow speed mode support
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock.
      • Clock source selections in slow speed mode - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.

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