MC9S08LL36_64
 
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CPU Component MC9S08LL36_64
Freescale HCS08 family : MC9S08LL36 in 64 pin LQFP package
Component Level: High
Category: CPU-Freescale-HCS08-LH/LL
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • CPU type - CPU variant
  • Clock settings - MCU clock settings
    • Internal clock - Internal clock settings.
      • Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 32.7 kHz.
      • Internal ref. clock for peripherals - This property enables the internal reference clock for use as ICSIRCLK for peripherals.
      • Initialize trim value - This property enables to generate code for initialization of the trim registers (ICSTRM, ICSSC) with a value from a non-volatile memory location.
        The following items are available only if the group is enabled (the value is "yes"):
    • External clock - If this property is enabled, an external clock is allowed for MCU timing.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Clock source - Possible external clock sources (external crystal or external clock).
        There are 2 modes:
        • External crystal - The following items are displayed in this mode:
          • Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 32-38.4kHz or 1-16MHz and the external clock should be in the range of 0.0001-40MHz but this limits may be further restricted by other settings of the ICS module (Oscillator operating mode, FLL/PLL mode).
          • Clock input pin - Clock input properties.
          • Clock output pin - Clock output properties.
          • Clock range - This property selects the frequency range for the external oscillator or external clock source.

            There are 2 options:
            • High frequency: selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source)
            • Low frequency: selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source)

            The property is set automatically by Processor expert if clock frequency is in the vendor recommended range otherwise can by changed manually.
          • Oscillator operating mode - The operating mode of the oscillator module. It provides the high gain for improving of noise immunity or the low power consumption This property also influences allowed frequency range of external crystal.

            There are 2 options:
            • High gain: This mode provides a higher amplitude output for the improved noise immunity.
            • Low power: This mode provides the lower power consumption.

          • External ref. clock for peripherals - This property enables the external reference clock for use as ICSERCLK for peripherals.
        • External oscillator - The following items are displayed in this mode:
          • Clock frequency [MHz] - See previous modes for more details
          • Clock input pin - Clock input properties.
            • The content is the same as in previous modes.
          • Clock range - See previous modes for more details
          • External ref. clock for peripherals - See previous modes for more details
    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - This property enables the STOP instruction.
        The following items are available only if the group is enabled (the value is "yes"):
  • Initialization interrupt priority - Initialization interrupt priority value.
  • Internal resource mapping - Internal resource mapping setting
    • Interrupt vector table - This group contains settings for placement of interrupt vector table.
      • Address - This property defines address of definition of interrupt vector table. For a bootloader support the definition of the interrupt vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of interrupt vector to a valid source. The setting of the interrupt vector table address doesn't affect any HW resources.
        When the Vector redirection property is available and is enabled the user is offered automatic adjustment of the address of the interrupt vector table according to the current setting of FLASH memory protection (see property group Internal peripherals/FLASH).
      • Size - Size of the exception vector table. (For information only)
    • Reset vector - This group contains settings for placement of reset vector.
      • Address - This property defines address of definition of reset vector. For a bootloader support the definition of the reset vector can be placed on a user defined address. In this case the user has to ensure correct redirection of the reset vector to a valid source. The setting of the reset vector address doesn't affect any HW resources.
      • Size - Size of the reset vector. (For information only)
  • Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
      This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    • TOD clock output prescaler in high speed mode - TOD clock output prescaler in the high speed mode.
    • TOD clock source in high speed mode - TOD clock source in the high speed mode.
    • TOD clock output prescaler in low speed mode - TOD clock output prescaler in the low speed mode.
    • TOD clock source in low speed mode - TOD clock source in the low speed mode.
    • TOD clock output prescaler in slow speed mode - TOD clock output prescaler in the slow speed mode.
    • TOD clock source in slow speed mode - TOD clock source in the slow speed mode.
    • Internal bandgap - Settings of the Internal bandgap
      • Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. This item modifies the BGBE bit in the SPMSC1 register.
      • Internal bandgap buffer drive - This property select the drive mode of the bandgap buffer. This item modifies the BGDS bit in the SPMSC1 register.

        There are 2 options:
        • low-drive mode: Bandgap Buffer is in low-drive mode when enabled
        • high-drive mode: Bandgap Buffer is in high-drive mode when enabled

      • This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    • BDM pin support - Enables/disables the background debug mode pin support. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • BDM pin - Background Debug Mode pin name (for information only)
      • BDM pin signal - Signal name of the Background Debug Mode pin
    • FLASH - The FLASH memory options.
      • Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
        There are 2 modes:
        • Enabled - The following items are displayed in this mode:
          • SEC01:SEC00 bits value - This property specifies value for enabled security state (useful if it must be set exactly for debugger).
            This item modifies SEC00:SEC01 bits in the NVOPT register.
          • Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
            The following items are available only if the group is enabled (the value is "Enabled"):
        • Disabled - There are no items in this mode.
      • Protection - Protection of the selected FLASH memory block. Trying to alter data in any protected area in the flash memory will result in a flash protection violation error.
        There are 3 modes:
        • Disabled - The protection of the FLASH memory is disabled. There are no items in this mode.
        • User defined - The size of the protected area is defined by user. The following items are displayed in this mode:
          • Protected area [kB] - Size of protected are in kB. The inserted value will be automatically adjusted to the nearest allowed value. The address range of protected flash is shown in the third column of this property.
        • Entire FLASH - The entire FLASH memory is protected. There are no items in this mode.
      • Vector redirection - If the protection is enabled the vector interrupts can be redirected to the unprotected area by setting of this vector redirection property.
    • I/O module - I/O ports' settings
      • Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
        This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
        There are 3 modes:
        • no initialization - There are no items in this mode.
        • input - The following items are displayed in this mode:
          • Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
          • Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
        • output - See input mode for items available in this mode.
      • PORT A - Slew rate control and Drive strength setting for pins of PORT A
      • PORT B - Slew rate control and Drive strength setting for pins of PORT B
      • PORT C - Slew rate control and Drive strength setting for pins of PORT C
      • PORT D - Slew rate control and Drive strength setting for pins of PORT D
      • PORT E - Slew rate control and Drive strength setting for pins of PORT E
    • System Clock Gating - Clock gating control settings. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait currents.
      • SCI1 Clock Gate - This property sets the SCI1 Clock Gate Control.
        This item modifies the SCI1 bit in the SCGC1 register
        Enabled - Bus clock to the SCI1 module is enabled.
        Disabled - Bus clock to the SCI1 module is disabled.
      • SCI2 Clock Gate - This property sets the SCI2 Clock Gate Control
        This item modifies the SCI2 bit in the SCGC1 register.
        Enabled - Bus clock to the SCI2 module is enabled.
        Disabled - Bus clock to the SCI2 module is disabled.
      • IIC Clock Gate - This property sets the IIC Clock Gate Control.
        This item modifies the IIC bit in the SCGC1 register
        Enabled - Bus clock to the IIC module is enabled.
        Disabled - Bus clock to the IIC module is disabled.
      • VREF1 Clock Gate - This property sets the VREF1 Clock Gate Control
        This item modifies the VREF1 bit in the SCGC1 register.
        Enabled - Bus clock to the VREF1 module is enabled
        Disabled - Bus clock to the VREF1 module is disabled
      • ADC Clock Gate - This property sets the ADC Clock Gate Control.
        This item modifies the ADC bit in the SCGC1 register
        Enabled - Bus clock to the ADC module is enabled.
        Disabled - Bus clock to the ADC module is disabled.
      • TPM1 Clock Gate - This property sets the TPM1 Clock Gate Control.
        This item modifies the TPM1 bit in the SCGC1 register
        Enabled - Bus clock to the TPM1 module is enabled.
        Disabled - Bus clock to the TPM1 module is disabled.
      • TPM2 Clock Gate - This property sets the TPM2 Clock Gate Control.
        This item modifies the TPM2 bit in the SCGC1 register
        Enabled - Bus clock to the TPM2 module is enabled.
        Disabled - Bus clock to the TPM2 module is disabled.
      • VREF2 Clock Gate - This property sets the VREF2 Clock Gate Control
        This item modifies the VREF2 bit in the SCGC1 register.
        Enabled - Bus clock to the VREF2 module is enabled
        Disabled - Bus clock to the VREF2 module is disabled
      • SPI Clock Gate - This property sets the SPI Clock Gate Control.
        This item modifies the SPI bit in the SCGC2 register
        Enabled - Bus clock to the SPI module is enabled.
        Disabled - Bus clock to the SPI module is disabled.
      • LCD Clock Gate - This property sets the LCD Clock Gate Control
        This item modifies the LCD bit in the SCGC2 register.
        Enabled - Bus clock to the LCD module is enabled
        Disabled - Bus clock to the LCD module is disabled
      • TOD Clock Gate - This property sets the TOD Clock Gate Control
        This item modifies the TOD bit in the SCGC2 register.
        Enabled - Bus clock to the TOD module is enabled
        Disabled - Bus clock to the TOD module is disabled
      • ACMP Clock Gate - This property sets the ACMP Clock Gate Control.
        This item modifies the ACMP bit in the SCGC2 register
        Enabled - Bus clock to the ACMP modules is enabled.
        Disabled - Bus clock to the ACMP modules is disabled.
      • KBI Clock Gate - This property sets the KBI Clock Gate Control.
        This item modifies the KBI bit in the SCGC2 register
        Enabled - Bus clock to the KBI module is enabled.
        Disabled - Bus clock to the KBI module is disabled.
      • IRQ Clock Gate - This property sets the IRQ Clock Gate Control.
        This item modifies the IRQ bit in the SCGC2 register
        Enabled - Bus clock to the IRQ module is enabled.
        Disabled - Bus clock to the IRQ module is disabled.
      • FLASH Register Clock Gate - This property sets the FLASH Register Clock Gate Control.
        This item modifies the FLS bit in the SCGC2 register
        Enabled - Bus clock to the FLASH registers is enabled.
        Disabled - Bus clock to the FLASH registers is disabled.
      • DBG Clock Gate - This property sets the DBG Clock Gate Control.
        This item modifies the DBG bit in the SCGC2 register
        Enabled - Bus clock to the DBG module is enabled.
        Disabled - Bus clock to the DBG module is disabled.
    • LVD module - Low Voltage Detect module settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • LVD operation - This property defines operation performed upon detection of a low voltage condition.

        There are 3 options:
        • Reset: Reset is generated upon detection of a low voltage condition.
        • Interrupt: Interrupt is generated when LVI detector state is changed.
        • Polling mode: No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output.

      • LVW interrupt - This property enables to generate hardware interrupt requests upon a detection of the Low-voltage warning condition.
      • LVD module interrupt - Low Voltage Detect module interrupt vector (for information only). This property is set automatically by Processor Expert and depends on the setting of LVD operation and LVW interrupt.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Interrupt name - Interrupt vector that is invoked from the Low-voltage warning interrupt (for information only).
      • Enable in stop mode - Enables the Low-voltage detection during the stop mode.
      • Wake-up on Interupt - This property controls whether or not the voltage regulator exits standby when any active MCU interrupt occurs.
    • TPM modules - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
      • Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
      • Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
    • Reset pin support - Enables/disables the reset pin to function as RESET. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
  • CPU interrupts - Internal peripherals setting
    • SWI - This property enables/disables generation of SWI interrupt service routine.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Software Interrupt (for information only)
  • Enabled speed modes - Enabled speed modes.
    • High speed mode - High speed mode support (always enabled)
      The following items are available only if the group is enabled (the value is "Enabled"):
      • High speed clock - The clock source for the internal bus clock.
        Internal Clock - Internal reference clock 31.25kHz - 39.0625kHz.
        External Clock - External clock source (external crystal or external reference clock, if available and enabled).
        See Clock settings to set the current value of a clock source.
      • Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source.
      • Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock. If all dividers/multiplier are set manually by the user (none of them is set to 'Auto select value'), the bus frequency is calculated by Processor Expert and cannot be modified. Possible bus clock frequency is limited by the selected reference clock source and are limited by its value. See Clock settings to set the current value of a clock source.
      • Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock source is derived from the ICS Ref. clock freq. [MHz]. It is valid only when the reference clock is no more than 1/4 of the output frequency of the ICS module.
      • FLL mode - FLL mode (Engaged/Bypassed/Bypassed Low Power).
        There are 3 modes:
        • Engaged - In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal of external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
          • Ref. clock source - FLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
            There are 2 modes:
            • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
              • Ref. clock freq. [MHz] - Frequency of the FLL reference clock [MHz]
                If FLL is enabled (Engaged and Bypassed modes) then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
                The source of the reference clock is selected by the Ref. clock source property:
                When 'Internal Clock' is selected: When 'External Clock' is selected:
                • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                  When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                  If FLL is disabled (Bypassed Low-power modes) and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
            • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
              • Ref. clock source freq. [MHz] - Frequency of FLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
              • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
              • Ref. clock freq. [MHz] - See previous modes for more details
          • DCO mode - This property defines, which DCO mode will be used.
            When set to 'Auto select' the PE selects optimal DCO mode according to the requested Internal bus clock (in FLL Engaged mode) or the requested FLL output clock freq. [MHz] (in FLL Bypassed mode).
            There are 3 modes:
            • Auto select - DCO mode will be automatically selected by PE There are no items in this mode.
            • Default - DCO has default range of 25%. The following items are displayed in this mode:
              • FLL mult. factor - Selects the FLL factor. This value establishes the range DCO range (Low range, Mid range, High range). This property cannot be modified in FLL Engaged mode. If 'Auto select' value is used you can enter the requested FLL output clock frequency into the FLL output clock freq. [MHz] property and PE will select the most suitable value.
            • Fine tuned 32kHz - DCO is fined tuned for maximum frequency with 32.768 kHz reference. The following items are displayed in this mode:
          • FLL output clock freq. [MHz] - FLL output clock frequency [MHz] (for information only).
        • Bypassed - In FLL bypassed mode, the bus clock is derived from the internal or external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See Engaged mode for items available in this mode.
        • Bypassed Low Power - In FLL bypassed low power mode, the bus clock is derived from the internal or external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. The following items are displayed in this mode:
          • Ref. clock source - FLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
            There are 2 modes:
            • Internal Clock - FLL is controlled by the internal reference clock. The following items are displayed in this mode:
              • Ref. clock freq. [MHz] - Frequency of the FLL reference clock [MHz]
                If FLL is enabled (Engaged and Bypassed modes) then for Default DCO mode the reference clock frequency shall be in range <31.25 kHz, 39.0625 kHz> and for the Fine tuned DCO mode the reference clock frequency shall be 32.768 kHz.
                The source of the reference clock is selected by the Ref. clock source property:
                When 'Internal Clock' is selected: When 'External Clock' is selected:
                • The reference clock is derived from divided (see Ref. clock divider) external clock source.
                  When the Ref. clock divider is set to 'Auto select' value PE will try to select the best value of the divider. If no possible setting of the divider results in a valid value of the reference clock then PE will select reference clock with minimal deviation from a valid value and a warning will be issued.
                  If FLL is disabled (Bypassed Low-power modes) and the Ref. clock divider is set to 'Auto select' value it is possible to write requested frequency into this property and PE will try to select the reference clock divider. Otherwise the frequency cannot be directly modified.
            • External Clock - FLL is controlled by the external reference clock. The following items are displayed in this mode:
              • Ref. clock source freq. [MHz] - Frequency of FLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
              • Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL external reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
              • Ref. clock freq. [MHz] - See previous modes for more details
    • Low speed mode - See High speed mode description.
    • Slow speed mode - See High speed mode description.

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