CPU Component documentation

Component name - Name of the component.
CPU type - CPU variant

Clock settings - MCU clock settings
- Internal clock - Internal clock settings.
  - Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 32.7 kHz. It is responsibility of the user to provide correct trim value (see ' Initialize trim value value' property), which will adjust the frequency of the internal oscillator to the required value.
  - Internal ref. clock for peripherals - This property enables the internal reference clock for use as MCGIRCLK for peripherals.
  - Initialize trim value - This property enables to generate code for initialization of the trim register (MCGTRM, MCGSC) by the value from a non-volatile memory location.
    The following items are available only if the group is enabled (the value is "yes"):
    - Trim value address - The location where the trim value is stored in the non-volatile memory.
    - Fine trim value address - The location where the fine trim value is stored in the non-volatile memory.
- External clock - If this property is enabled, an external clock is allowed for MCU timing.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Clock source - Possible external clock sources (external crystal or external clock).
    There are 2 modes:
    - External crystal - The following items are displayed in this mode:
      - Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 32-38.4kHz or 1-16MHz and the external clock should be in the range of 0.0001-40MHz but this limits may be further restricted by other MCG module settings (Oscillator operating mode, FLL/PLL mode).
      - Clock input pin - Clock input properties.
        
        Pin name - Clock input pin name (for information only).
        
        Pin signal - Clock input signal name.
      - Clock output pin - Clock output properties.
        
        Pin name - Clock output pin name (for information only).
        
        Pin signal - Clock output signal name.
      - Clock range - This property selects the frequency range for the external oscillator or external clock source.
        
        There are 2 options:
        
        High frequency: selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external clock source)
        
        Low frequency: selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external clock source)
        
        The property is set automatically by Processor expert if clock frequency is in the vendor recommended range otherwise can by changed manually.
      - Oscillator operating mode - The operating mode of the oscillator module. It provides the high gain for improving of noise immunity or the low power consumption This property also influences allowed frequency range of external crystal.
        
        There are 2 options:
        
        High gain: This mode provides a higher amplitude output for the improved noise immunity.
        
        Low power: This mode provides the lower power consumption.
      - External ref. clock for peripherals - This property enables the external reference clock for use as MCGERCLK for peripherals.
    - External oscillator - The following items are displayed in this mode:
      - Clock frequency [MHz] - See previous modes for more details
      - Clock input pin - Clock input properties.
        
        The content is the same as in previous modes.
      - Clock range - See previous modes for more details
      - External ref. clock for peripherals - See previous modes for more details
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - This property enables the STOP instruction.
    The following items are available only if the group is enabled (the value is "yes"):
    - Power down control - This property sets power down control bits that determine which power-down mode will be invoked when the STOP instruction is executed.
      
      There are 2 options:
      - STOP2 - Partial power down mode: Partial power down mode
      - STOP3 - Standby mode: Standby mode
    - Internal clock in stop mode - This property controls whether or not the internal reference clock remains enabled when the ICS enters stop mode.
    - External clock in stop mode - This property controls whether or not the external reference clock remains enabled when the ICS enters stop mode.
Initialization interrupt priority - Initialization interrupt priority value.

Internal resource mapping - Internal resource mapping setting
- Interrupt vector table - This group contains settings for placement of interrupt vector table.
  - Address - This property defines address of definition of interrupt vector table. For a bootloader support the definition of the interrupt vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of interrupt vector to a valid source. The setting of the interrupt vector table address doesn't affect any HW resources.
    When the Vector redirection property is available and is enabled the user is offered automatic adjustment of the address of the interrupt vector table according to the current setting of FLASH memory protection (see property group Internal peripherals/FLASH).
  - Size - Size of the exception vector table. (For information only)
- Reset vector - This group contains settings for placement of reset vector.
  - Address - This property defines address of definition of reset vector. For a bootloader support the definition of the reset vector can be placed on a user defined address. In this case the user has to ensure correct redirection of the reset vector to a valid source. The setting of the reset vector address doesn't affect any HW resources.
  - Size - Size of the reset vector. (For information only)
Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
- ADC - Settings of the ADC module
  - Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. This item modifies the BGBE bit in the SPMSC1 register.
- BDM pin support - The Background debug mode pin.
  - BDM pin - Background Debug Mode pin name (for information only)
  - BDM pin signal - Signal name of the Background Debug Mode pin
- Bus clock output - Bus clock output pin.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Bus clock output pin - Bus clock output pin name (for information only)
  - Bus clock output pin signal - Signal name of the Bus clock output pin
  - Clock output divider - The divide ratio of the output bus clock of the pin.
    
    There are 7 options:
    - 2: Bus clock frequency divided by 2.
    - 4: Bus clock frequency divided by 4.
    - 6: Bus clock frequency divided by 6.
    - 8: Bus clock frequency divided by 8.
    - 10: Bus clock frequency divided by 10.
    - 12: Bus clock frequency divided by 12.
    - 14: Bus clock frequency divided by 14.
- FLASH - The FLASH memory options.
  - Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
    There are 2 modes:
    - Enabled - The following items are displayed in this mode:
      - SEC01:SEC00 bits value - This property specifies value for enabled security state (useful if it must be set exactly for debugger).
        This item modifies SEC00:SEC01 bits in the NVOPT register.
      - Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
        The following items are available only if the group is enabled (the value is "Enabled"):
        
        Backdoor key 0 - 7 Backdoor key value of the register 0-7.
    - Disabled - There are no items in this mode.
  - Protected area - Protected area
  - Vector redirection - If the protection is enabled the vector interrupts can be redirected to the unprotected area by setting of this vector redirection property.
- I/O module - I/O ports' settings
  - Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
    This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
    There are 3 modes:
    - no initialization - There are no items in this mode.
    - input - The following items are displayed in this mode:
      - Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
      - Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
    - output - See input mode for items available in this mode.
  - PORT A - Slew rate control and Drive strength setting for pins of PORT A
  - PORT B - Slew rate control and Drive strength setting for pins of PORT B
  - PORT D - Slew rate control and Drive strength setting for pins of PORT D
  - PORT E - Slew rate control and Drive strength setting for pins of PORT E
  - PORT F - Slew rate control and Drive strength setting for pins of PORT F
  - PORT G - Slew rate control and Drive strength setting for pins of PORT G
- LVD module - Low Voltage Detect module settings.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - LVD reset - This property enables to generate a hardware reset upon a detection of the Low-voltage condition.
  - LVW interrupt - This property enables to generate hardware interrupt requests upon detection of the Low-voltage warning condition.
    The following items are available only if the group is enabled (the value is "Enabled"):
    - Interrupt name - Interrupt vector that is invoked from the Low-voltage warning interrupt (for information only).
  - Enable in stop mode - Enables the Low-voltage detection during the stop mode.
  - Low-voltage detect voltage - Low-voltage detect trip point selection (low or high).
  - Low-voltage warning voltage - Low-voltage warning trip point selection (low or high).
- TPM1 module - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
  - Aligned - The PWM timer provides the choice of two types of outputs, Left Aligned or Center Aligned outputs.
- Reset pin - Reset pin
  - Reset pin - Reset pin name (for information only)
  - Reset pin signal - Signal name of the Reset pin

CPU interrupts - Internal peripherals setting
- Loss of lock - Loss of lock interrupt settings. This property is set by Processor expert and depends on the setting of Loss of lock interrupt property. (For information only)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Loss of lock interrupt. (for information only)
- SWI - This property enables/disables generation of SWI interrupt service routine.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Software Interrupt (for information only)

Enabled speed modes - Enabled speed modes.
- High speed mode - High speed mode support (always enabled)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - High speed clock - The clock source for the internal bus clock.
    Internal Clock - Internal reference clock 31.25kHz - 39.0625kHz.
    External Clock - External clock source (external crystal or external reference clock, if available and enabled).
    See Clock settings to set the current value of a clock source.
  - Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source.
  - Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock. If all dividers/multiplier are set manually by the user (none of them is set to 'Auto select value'), the bus frequency is calculated by Processor Expert and cannot be modified. Possible bus clock frequency is limited by the selected reference clock source and are limited by its value. See Clock settings to set the current value of a clock source.
  - Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock source is derived from the MCG Divided ref.clock freq. [MHz]. It is valid only when the reference clock is no more than 1/4 of the output frequency of the MCG module.
  - Clock monitor - This property determines if a reset request is made following a loss of external clock indication. Clock monitor should only be enabled when either the MCG is in an operation mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled.
    
    There are 2 options:
    - Disabled: Clock monitor is disabled.
    - Force reset: Generate a reset request on loss of external clock.
  - FLL/PLL mode - FLL/PLL mode (Engaged/Bypassed/Bypassed Low Power).
    There are 6 modes:
    - FLL Engaged - In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal of external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
      - Loss of lock interrupt - This property enables to generate an interrupt request after a loss of lock condition is detected. This property is not available in Bypassed Low-power modes.
      - Ref.clock source - FLL or PLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
        
        There are 2 options:
        
        Internal Clock: FLL is controlled by the internal reference clock.
        
        External Clock: FLL is controlled by the external reference clock.
      - Ref.clock freq. [MHz] - Frequency of FLL/PLL reference clock (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
      - Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL/PLL reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
      - Divided ref.clock freq. [MHz] - Divided ref. clock frequency [MHz] (Frdiv).
        This frequency is calculated according to the formula:
        Frdiv = Reference clock frequency/Reference clock divider
        If FLL/PLL is disabled (Bypassed Low-power modes) and Ref. clock divider is set to 'Auto select' value you can write requested frequency into this property and PE will try to calculate best reference clock divider for you. Otherwise the frequency cannot be directly modified.
        If FLL or PLL is enabled (Engaged and Bypassed modes) this frequency shall be in range <31.25 kHz, 39.0625 kHz> or <1 MHz, 2 MHz> respectively. If the Ref. clock divider is set to 'Auto select' value Processor Expert select the best reference divider and will try to recalculate it if reference clock is changed.
      - FLL output clock freq. [MHz] - FLL output clock frequency [MHz] (for information only).
    - FLL Bypassed - In FLL bypassed mode, the bus clock is derived from the internal or external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See FLL Engaged mode for items available in this mode.
    - FLL Bypassed Low Power - In FLL bypassed low power mode, the bus clock is derived from the internal or external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. The following items are displayed in this mode:
      - Ref.clock source - See previous modes for more details
      - Ref.clock freq. [MHz] - See previous modes for more details
      - Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL/PLL reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
      - Divided ref.clock freq. [MHz] - See previous modes for more details
    - PLL Engaged - In PLL engaged mode, the bus clock is derived from the FLL which is controlled by the external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
      - Loss of lock interrupt - See previous modes for more details
      - Ref.clock source - See previous modes for more details
      - Ref.clock freq. [MHz] - See previous modes for more details
      - Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL/PLL reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
      - Divided ref.clock freq. [MHz] - See previous modes for more details
      - PLL mult. factor - Selects the amount to divide down the VCO output of PLL. This value establish the multiplication factor (M) applied to the reference clock frequency. This property can be modified only in PLL bypassed mode(PBE). If 'Auto select' value is used you can try to write requested PLL output clock frequency into the PLL output clock freq. property and PE will try to calculate best multiplication factor for you.
      - PLL output clock freq. [MHz] - PLL output clock frequency [MHz]. If the PLL mult. factor property is set to 'Auto select' value you can write here requested frequency and PE will try to calculate best multiplication factor for you. Otherwise this property is set by PE according to the selected PLL mult. factor and cannot be modified.
    - PLL Bypassed - In PLL bypassed mode, the bus clock is derived from external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See PLL Engaged mode for items available in this mode.
    - PLL Bypassed Low Power - In PLL bypassed low power mode, the bus clock is derived external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. See FLL Bypassed Low Power mode for items available in this mode.
- Low speed mode - See High speed mode description.
- Slow speed mode - See High speed mode description.

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