CPU Component documentation

Component name - Name of the component.
CPU type - CPU variant
Clock settings - MCU Clock settings
- Internal Clock - Internal clock oscillator settings.
  - Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 243 kHz. It is responsibility of the user to provide correct trim value (see 'Initialize trim value' property), which will adjust the frequency of the internal oscillator to the required value.
  - Initialize trim value - This property enables to generate code for initialization of the trim register (ICGTR) by the value from a non-volatile memory location.
    The following items are available only if the group is enabled (the value is "yes"):
    - Trim value address - The location where the trim value is stored in the non-volatile memory.
- External clock - If this property is enabled, an external clock is allowed for the MCU timing.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Clock source - Possible external clock sources (external crystal or external oscillator).
    There are 2 modes:
    - External crystal - The following items are displayed in this mode:
      - Clock frequency [MHz] - Frequency of the external clock (external crystal or the external oscillator). The following properties may restrict the valid range of the external clock: The Clock source, Clock range, Operating mode and the FLL clock. The valid frequency range of the external clock for current CPU component settings is shown in the third column of the Clock range property in the Component Inspector. For details see the MCU specification.
      - Clock range - This property selects one of two reference frequency ranges for the ICG (High frequency and Low frequency range). The property controls the oscillator, reference divider, and FLL loop prescaler multiplication factor (P). The property has only an effect in FLL engaged external and FLL bypassed external modes. The valid frequency range of the external clock for current CPU component settings is shown in the third column of the Component Inspector.
      - Operating mode - The operating mode of the oscillator module. It provides a high gain for the noise immunity improvement or the low power consumption. This property also affects the valid range of an external crystal.
        
        There are 2 options:
        
        High gain: This mode provides a higher amplitude output for the improved noise immunity.
        
        Low power: This mode provides the lower power consumption.
      - Clock input pin - Clock input properties.
        
        Pin name - Clock input pin name (for information only).
        
        Pin signal - Clock input signal name.
      - Clock output pin - Clock output properties.
        
        Pin name - Clock output pin name (for information only).
        
        Pin signal - Clock output signal name.
    - External oscillator - The following items are displayed in this mode:
      - Clock frequency [MHz] - See previous modes for more details
      - Clock range - See previous modes for more details
      - Clock input pin - Clock input properties.
        
        The content is the same as in previous modes.
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - This property enables the STOP instruction.
    The following items are available only if the group is enabled (the value is "yes"):
    - Power down control - This property sets power down control bits that determine which power-down mode will be invoked when the STOP instruction is executed.
      
      There are 2 options:
      - STOP2 - Partial power down mode: Partial power down mode
      - STOP3 - Standby mode: Standby mode
    - Enable oscillator in ICG off mode - Enables/disables the external oscillator in the ICG off mode.
Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.

Internal resource mapping - Internal resource mapping setting
- Interrupt vector table - This group contains settings for placement of interrupt vector table.
  - Address - This property defines address of definition of interrupt vector table. For a bootloader support the definition of the interrupt vector table can be placed on a user defined address. In this case the user has to ensure correct redirection of interrupt vector to a valid source. The setting of the interrupt vector table address doesn't affect any HW resources.
    When the Vector redirection property is available and is enabled the user is offered automatic adjustment of the address of the interrupt vector table according to the current setting of FLASH memory protection (see property group Internal peripherals/FLASH).
  - Size - Size of the exception vector table. (For information only)
- Reset vector - This group contains settings for placement of reset vector.
  - Address - This property defines address of definition of reset vector. For a bootloader support the definition of the reset vector can be placed on a user defined address. In this case the user has to ensure correct redirection of the reset vector to a valid source. The setting of the reset vector address doesn't affect any HW resources.
  - Size - Size of the reset vector. (For information only)
Internal peripherals - Internal peripherals settings.
- ADC - Settings of the ADC module
  - Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference. It can be used by an ADC module on one of its internal channels or by an analog comparator module (if available). This item modifies the BGBE bit in the SPMSC1 register.
- BDM pin support - The Background debug mode pin.
  - BDM pin - Background Debug Mode pin name (for information only)
  - BDM pin signal - Signal name of the Background Debug Mode pin
- Bus clock output - Bus clock output pin.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Bus clock output pin - Bus clock output pin name (for information only)
  - Bus clock output pin signal - Signal name of the Bus clock output pin
  - Clock output divider - The divide ratio of the output bus clock of the pin.
    
    There are 8 options:
    - driven low: The output pin is driven low.
    - 2: Bus clock frequency divided by 2.
    - 4: Bus clock frequency divided by 4.
    - 6: Bus clock frequency divided by 6.
    - 8: Bus clock frequency divided by 8.
    - 10: Bus clock frequency divided by 10.
    - 12: Bus clock frequency divided by 12.
    - 14: Bus clock frequency divided by 14.
- FLASH - The FLASH memory options.
  - Security state - If the security state is enabled the content of the memory cannot be read by an instruction from any unsecured source including the background debug interface. Security state can be temporary disabled by the Backdoor key mechanism property.
    There are 2 modes:
    - Enabled - The following items are displayed in this mode:
      - SEC01:SEC00 bits value - This property specifies value for enabled security state (useful if it must be set exactly for debugger).
        This item modifies SEC00:SEC01 bits in the NVOPT register.
      - Backdoor key mechanism - This property enables/disables security unlocking mechanism. This mechanism uses an 8-byte backdoor security key to unsecure the MCU. You can use SetBackdoorKey() method to unsecure the MCU (Not available in Device Initialization tool).
        The following items are available only if the group is enabled (the value is "Enabled"):
        
        Backdoor key 0 - 7 Backdoor key value of the register 0-7.
    - Disabled - There are no items in this mode.
  - Protection - Protection of the selected memory block. If a block of the FLASH memory is protected a bootloader cannot erase the protected block of memory.
    The following items are available only if the group is enabled (the value is "Enabled"):
    - Boundary address - This boundary defines the last address within Flash memory that is unprotected. The rest of the Flash memory is protected up to address $FFFF. The size of the protected area shall be a multiple of 512 bytes block. The inserted value is adjusted by Processor Expert to meet this requirement.
  - Vector redirection - If the protection is enabled the vector interrupts can be redirected to the unprotected area by setting of this vector redirection property.
- I/O module - I/O ports' settings
  - Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
    This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
    There are 3 modes:
    - no initialization - There are no items in this mode.
    - input - The following items are displayed in this mode:
      - Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
      - Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
    - output - See input mode for items available in this mode.
  - Initialize not-bonded I/O pins - Initialization for all not-bonded I/O pins.
    This property specifies initialization direction for all not-bonded pins . If the given not-bonded pin doesn't support the preferred direction then the pin direction is left in it's default state.
    There are 3 modes:
    - no initialization - There are no items in this mode.
    - input - The following items are displayed in this mode:
      - Pull resistor - Default initialization of pull resistors for all not-bonded I/O pins. Pull resistor is initialized only if the given not-bonded pin is set to input direction and supports selected pull resistor type.
      - Output value - Default initialization of output value for all not-bonded I/O pins. Output value is initialized only if the given not-bonded pin is set to output direction.
    - output - See input mode for items available in this mode.
  - PORT A - Slew rate control and Drive strength setting for pins of PORT A
  - PORT B - Slew rate control and Drive strength setting for pins of PORT B
  - PORT C - Slew rate control and Drive strength setting for pins of PORT C
  - PORT D - Slew rate control and Drive strength setting for pins of PORT D
  - PORT E - Slew rate control and Drive strength setting for pins of PORT E
  - PORT F - Slew rate control and Drive strength setting for pins of PORT F
  - PORT G - Slew rate control and Drive strength setting for pins of PORT G
- LVD module - Low Voltage Detect module settings.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - LVD operation - This property defines operation performed upon detection of a low voltage condition.
    There are 3 modes:
    - Reset - Reset is generated upon detection of a low voltage condition. The following items are displayed in this mode:
    - Interrupt - Interrupt is generated when LVI detector state is changed. The following items are displayed in this mode:
      - Interrupt name - Interrupt vector that is invoked from the Low Voltage Detect interrupt (for information only).
    - Polling mode - No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output. See Reset mode for items available in this mode.
  - Enable in stop mode - Enables the low-voltage detection during stop mode.
  - Low-voltage detect voltage - Low-voltage detect trip point selection (low or high).
  - Low-voltage warning voltage - Low-voltage warning trip point selection (low or high).
- TPM modules - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
  - Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
  - Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
  - Aligned - The PWM timer provides the choice of two types of outputs, Edge Aligned or Center Aligned outputs.
- Reset pin - Reset pin
  - Reset pin - Reset pin name (for information only)
  - Reset pin signal - Signal name of the Reset pin
CPU interrupts - Interrupts allocated by CPU bean
- Clock monitor - Clock monitor interrupt settings. This property is set by Processor expert and depends on the setting of 'Loss of FLL lock' and 'Loss of clock' properties. (For information only)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Clock monitor interrupt. (for information only)
- SWI - This property enables/disables generation of SWI interrupt service routine.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Software Interrupt (for information only)

Enabled speed modes - Enabled speed modes.
- High speed mode - High speed mode support (always enabled)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - High speed clock - The clock source for the internal bus clock.
  - Clock divider - The reduced frequency divider of the internal clock generator module.
  - Internal bus clock - The internal bus clock [MHz]. The maximum bus frequency is 20MHz.
  - Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock is valid only when External clock is selected as a clock source (FEE or FBE ICG modes). In this case, depending on the ICG settings, it is either equal to bus clock or external reference clock divided by 2.
  - Loss of clock - Determines what type of request is made when the FLL loses the clock.
  - FLL clock - FLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - FLL clock frequency - FLL clock frequency [MHz]. This property is for information only and is set by PE according to the selected clock source. The value of the FLL clock frequency depends on the bus clock frequency.
    - Loss of FLL lock - Determines what type of request is made when the FLL loses the lock indication.
- Low speed mode - Low speed mode support
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Low speed clock - The clock source for the internal bus clock.
  - Clock divider - The reduced frequency divider of the internal clock generator module.
  - Internal bus clock - The internal bus clock [MHz]. The maximum bus frequency is 20MHz.
  - Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock is valid only when External clock is selected as a clock source (FEE or FBE ICG modes). In this case, depending on the ICG settings, it is either equal to bus clock or external reference clock divided by 2.
  - Loss of clock - Determines what type of request is made when the FLL loses the clock.
  - FLL clock - FLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - FLL clock frequency - FLL clock frequency [MHz]. This property is for information only and is set by PE according to the selected clock source. The value of the FLL clock frequency depends on the bus clock frequency.
    - Loss of FLL lock - Determines what type of request is made when the FLL loses the lock indication.
- Slow speed mode - Slow speed mode support
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Slow speed clock - The clock source for the internal bus clock.
  - Clock divider - The reduced frequency divider of the internal clock generator module.
  - Internal bus clock - The internal bus clock [MHz]. The maximum bus frequency is 20MHz.
  - Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock is valid only when External clock is selected as a clock source (FEE or FBE ICG modes). In this case, depending on the ICG settings, it is either equal to bus clock or external reference clock divided by 2.
  - Loss of clock - Determines what type of request is made when the FLL loses the clock.
  - FLL clock - FLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - FLL clock frequency - FLL clock frequency [MHz]. This property is for information only and is set by PE according to the selected clock source. The value of the FLL clock frequency depends on the bus clock frequency.
    - Loss of FLL lock - Determines what type of request is made when the FLL loses the lock indication.

PROCESSOR EXPERT is trademark of Freescale Semiconductor, Inc.
Copyright 1997 - 2010 Freescale Semiconductor, Inc.