CPU documentation - General info

Clock settings - MCU clock settings
- Source CPU clock - The clock source for the internal bus clock.
  Internal Clock - Internal reference clock 31.25kHz - 39.0625kHz.
  External Clock - External clock source (external crystal or external reference clock, if available and enabled).
  See Clock settings to set the current value of a clock source.
- Internal clock - Internal clock settings.
  - Internal oscillator frequency [kHz] - Frequency of the internal oscillator. Typical recommended value is 32.7 kHz.
  - Internal ref. clock for peripherals - This property enables the internal reference clock for use as ICSIRCLK for peripherals.
  - Initialize trim value - This property enables to generate code for initialization of the trim register (ICSTRM, ICSSC) by the value from a non-volatile memory location.
    The following items are available only if the group is enabled (the value is "yes"):
    - Trim value address - The location where the trim value is stored in the non-volatile memory.
    - Fine trim value address - The location where the fine trim value is stored in the non-volatile memory.
- Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source.
- Internal bus clock - The internal bus clock frequency [MHz] for timing of internal peripherals. The CPU clock is twice the internal bus clock. If all dividers/multiplier are set manually by the user (none of them is set to 'Auto select value'), the bus frequency is calculated by Processor Expert and cannot be modified. Possible bus clock frequency is limited by the selected reference clock source and are limited by its value. See Clock settings to set the current value of a clock source.
- Fixed frequency clock [MHz] - Fixed frequency clock for internal timer peripherals [MHz] (for information only). This clock is derived from the ICS divided reference clock. It is valid only when the divided reference clock is no more than 1/4 of the output frequency of the ICS module.
- FLL mode - FLL mode (Engaged/Bypassed/Bypassed Low Power).
  There are 3 modes:
  - Engaged - In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal of external reference clock. The Background Debug Controller (BDC) clock is supplied from the FLL. The following items are displayed in this mode:
    - Ref.clock source - FLL reference clock. This property can by changed only in 'Low-power' modes. In the 'Engaged' and 'Bypassed' modes this property is set by PE and cannot be modified by the user.
      
      There are 2 options:
      - Internal Clock: FLL is controlled by the internal reference clock.
      - External Clock: FLL is controlled by the external reference clock.
    - Ref. clock source freq. [MHz] - Frequency of FLL reference clock source (for information only). This property is set by PE according to the selected clock source. It is either Internal clock frequency or external crystal/external clock frequency.
    - Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
    - Divided ref.clock freq. [MHz] - Divided ref. clock frequency [MHz] (Frdiv).
      This frequency is calculated according to the formula:
      Frdiv = Reference clock frequency/Reference clock divider
      If FLL is disabled (Bypassed Low-power mode) and Ref. clock divider is set to 'Auto select' value you can write requested frequency into this property and PE will try to calculate best reference clock divider for you. Otherwise the frequency cannot be directly modified.
      If FLL is enabled (Engaged and Bypassed modes) this frequency shall be in range <31.25 kHz, 39.0625 kHz>. If the Ref. clock divider is set to 'Auto select' value Processor Expert select the best reference divider and will try to recalculate it if reference clock is changed.
    - FLL output clock freq. [MHz] - FLL output clock frequency [MHz] (for information only).
  - Bypassed - In FLL bypassed mode, the bus clock is derived from the internal or external reference clock. The FLL is enabled and controlled by the internal or external reference clock, but is bypassed. The Background Debug Controller (BDC) clock is supplied from the FLL. See Engaged mode for items available in this mode.
  - Bypassed Low Power - In FLL bypassed low power mode, the bus clock is derived from the internal or external reference clock. The FLL is disabled and bypassed. The Background Debug Controller (BDC) clock is not available. The following items are displayed in this mode:
    - Ref.clock source - See previous modes for more details
    - Ref. clock source freq. [MHz] - See previous modes for more details
    - Ref. clock divider - Reference clock divider (R). Selects the amount to divide down the FLL reference clock. Processor Expert selects the best value for the desired Bus clock and the Ref.clock frequency if the 'Auto select' value is used.
    - Divided ref.clock freq. [MHz] - See previous modes for more details
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - This property enables the STOP instruction.
    The following items are available only if the group is enabled (the value is "yes"):
    - Internal clock in stop mode - This property controls whether or not the internal reference clock remains enabled when the ICS enters stop mode.
Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.

Internal resource mapping - Internal resource mapping setting
- Reset vector - This group contains settings for placement of reset vector.
  - Address - This property defines address of definition of reset vector (for information only).
  - Size - Size of the reset vector. (For information only)
Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
- ADC - Settings of the ADC module
  - Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference. It can be used by an ADC module on one of its internal channels or by an analog comparator module (if available). This item modifies the BGBE bit in the SPMSC1 register.
- BDM pin support - Enables/disables the background debug mode pin support. When Disabled, the pin functions as one of its alternative functions.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - BDM pin - Background Debug Mode pin name (for information only)
- FLASH - The FLASH module settings.
  - Security state - If the security state is enabled, FLASH is considered a secure resource. The RAM, direct-page registers, and background debug controller are considered unsecured resources. Attempts to access a secure memory location through the background debug interface, or whenever BKGDPE is set, are blocked (reads return all 0s).
- I/O module - I/O ports' settings
  - Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
    This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
    There are 3 modes:
    - no initialization - There are no items in this mode.
    - input - The following items are displayed in this mode:
      - Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
      - Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
    - output - See input mode for items available in this mode.
  - Initialize not-bonded I/O pins - Initialization for all not-bonded I/O pins.
    This property specifies initialization direction for all not-bonded pins . If the given not-bonded pin doesn't support the preferred direction then the pin direction is left in it's default state.
    There are 3 modes:
    - no initialization - There are no items in this mode.
    - input - The following items are displayed in this mode:
      - Pull resistor - Default initialization of pull resistors for all not-bonded I/O pins. Pull resistor is initialized only if the given not-bonded pin is set to input direction and supports selected pull resistor type.
      - Output value - Default initialization of output value for all not-bonded I/O pins. Output value is initialized only if the given not-bonded pin is set to output direction.
    - output - See input mode for items available in this mode.
  - PORT A - Slew rate control and Drive strength setting for pins of PORT A
- LVD module - Low Voltage Detect module settings.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - LVD operation - This property defines operation performed upon detection of a low voltage condition.
    There are 3 modes:
    - Reset - Reset is generated upon detection of a low voltage condition. The following items are displayed in this mode:
    - Interrupt - Interrupt is generated when LVI detector state is changed. The following items are displayed in this mode:
      - Interrupt name - Interrupt vector that is invoked from the Low Voltage Detect interrupt (for information only).
      - Priority - Interrupt Priority
      - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.
    - Polling mode - No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output. See Reset mode for items available in this mode.
  - Enable in stop mode - Enables the low-voltage detection during stop mode.
- Reset pin support - Enables/disables the reset pin to function as RESET. When Disabled, the pin functions as one of its alternative functions.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Reset pin - Reset pin name (for information only)

Reset vector - Reset vector settings.
- ISR name - Name of the reset vector - routine, that initializes CPU after reset.
Interrupt vector - Interrupt vector settings (for information only)
- ISR name - Name of the interrupt vector routine (for information only).

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