MC9RS08KA2_6
 
General Info



CPU beans



CPU icon
Component icon
CPU MC9RS08KA2_6
Freescale RS08 family : MC9RS08KA2 in 6 pin package
Device Initialization
(Description of the CPU component parameters.)
  • Clock settings - MCU clock settings
    • Internal clock - Internal clock settings
      • Internal oscillator frequency [kHz] - Frequency of the internal reference clock. Typical recommended value is 31.25 kHz. It is responsibility of the user to provide correct trim value (see 'Initialize trim value' property), which will adjust the frequency of the internal oscillator to the required value.
      • Initialize trim value - This property enables to generate code for initialization of the trim (TRIM) and fine trim (FTRIM) bits by the value from a non-volatile memory location.
        The following items are available only if the group is enabled (the value is "yes"):
    • Bus freq. divider - This property controls the bus frequency. It selects the amount to divide down the clock source (BDIV). If the 'Auto select' value is selected the 'Internal bus clock' property can be used to input requested bus clock otherwise the 'Internal bus clock' is calculated by Processor Expert and can not be modified.
    • Internal bus clock - The internal bus clock frequency [MHz]. This property can by modified only if the 'Bus freq. divider' property is set to 'Auto select' value.
    • FLL mode - FLL mode (Engaged/Bypassed/Bypassed Low Power).

      There are 3 options:
      • Engaged: In FLL engaged mode, the bus clock is derived from the FLL which is controlled by the internal reference clock.
      • Bypassed: In FLL bypassed mode, the bus clock is derived from internal reference clock. The FLL is enabled and controlled by the internal reference clock, but is bypassed.
      • Bypassed Low Power: In FLL bypassed low power mode, the bus clock is derived from internal reference clock. The FLL is disabled and bypassed.

    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - This property enables the STOP instruction.
        The following items are available only if the group is enabled (the value is "yes"):
        • Internal clock in stop mode - This property controls whether or not the internal reference clock remains enabled when the ICS enters stop mode.
  • Internal resource mapping - Internal resource mapping setting
    • Reset vector - This group contains settings for placement of reset vector.
      • Address - This property defines address of definition of reset vector (for information only).
      • Size - Size of the reset vector. (For information only)
  • Internal peripherals - This group contains peripheral settings that are not supported by separate beans (such as for example LVI) and peripheral settings shareable between several beans.
    • ACMP - ACMP (analog comparator) module settings
      • Internal bandgap buffer - Enables/disables an internal buffer for the bandgap voltage reference for use by the
        ACMP module on one of its internal channels. This item modifies the BGBE bit in the SPMSC1 register.
    • BDM pin support - Enables/disables the background debug mode pin support. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • BDM pin - Background Debug Mode pin name (for information only)
    • FLASH - The FLASH module settings.
      • Security state - If the security state is enabled, FLASH is considered a secure resource. The RAM, direct-page registers, and background debug controller are considered unsecured resources. Attempts to access a secure memory location through the background debug interface, or whenever BKGDPE is set, are blocked (reads return all 0s).
    • I/O module - I/O ports' settings
      • Initialize unused I/O pins - Initialization for all unused I/O pins ( I/O pins neither used by any component nor reserved in the 'Used' tab of the cpu component).
        This property specifies initialization direction for all unused pins . If the given unused pin doesn't support the preferred direction then the pin direction is left in it's default state. Note: Initial state of the unused pins is displayed in Target CPU package window.
        There are 3 modes:
        • no initialization - There are no items in this mode.
        • input - The following items are displayed in this mode:
          • Pull resistor - Default initialization of pull resistors for all unused I/O pins. Pull resistor is initialized only if the given unused pin is set to input direction and supports selected pull resistor type.
          • Output value - Default initialization of output value for all unused I/O pins. Output value is initialized only if the given unused pin is set to output direction.
        • output - See input mode for items available in this mode.
      • Initialize not-bonded I/O pins - Initialization for all not-bonded I/O pins.
        This property specifies initialization direction for all not-bonded pins . If the given not-bonded pin doesn't support the preferred direction then the pin direction is left in it's default state.
        There are 3 modes:
        • no initialization - There are no items in this mode.
        • input - The following items are displayed in this mode:
          • Pull resistor - Default initialization of pull resistors for all not-bonded I/O pins. Pull resistor is initialized only if the given not-bonded pin is set to input direction and supports selected pull resistor type.
          • Output value - Default initialization of output value for all not-bonded I/O pins. Output value is initialized only if the given not-bonded pin is set to output direction.
        • output - See input mode for items available in this mode.
      • PORT A - Slew rate control setting for pins of PORT A
    • LVD module - Low Voltage Detect module settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • LVD operation - This property defines operation performed upon detection of a low voltage condition.

        There are 3 options:
        • Reset: Reset is generated upon detection of a low voltage condition.
        • Interrupt: Interrupt is generated when LVI detector state is changed.
        • Polling mode: No operation is done after detection of low voltage condition.

      • Enable in stop mode - Enables the low-voltage detection during stop mode.
    • Reset pin support - Enables/disables the reset pin to function as RESET. When Disabled, the pin functions as one of its alternative functions.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Reset pin - Reset pin name (for information only)
  • Reset vector - Reset vector settings.
    • ISR name - Name of the reset vector - routine, that initializes CPU after reset.

PROCESSOR EXPERT is trademark of Freescale Semiconductor, Inc.
Copyright 1997 - 2010 Freescale Semiconductor, Inc.